SKIP CLAMPING CIRCUIT FOR DC / DC POWER CONVERTER
Patent Information
- Application Number
- DE112023001379
- Authority / Receiving Office
- DE · DE
- Patent Type
- Applications
- Current Assignee / Owner
- Priority Date
- 2023-02-16
- Filing Date
- 2023-03-03
- Publication Date
- 2025-02-27
Smart Images
Figure 00000000_0000_ABST
Abstract
Description
BACKGROUND
[0001] This description refers to DC / DC voltage converters, and more specifically, to skip clamp circuits in DC / DC voltage converters. Skip clamp circuits can improve the performance of a voltage converter while it is in a power-saving mode. When powered by a DC power source, a switching DC / DC voltage converter delivers power at a regulated voltage to a load connected to its output. An inductor may be coupled to a switching terminal of the DC / DC voltage converter to store energy during converter operation. In a buck or boost DC / DC converter, the output voltage delivered to the load is regulated to be less than or greater than the input DC power source voltage, respectively.
[0002] Some DC / DC converters include a feedback loop with an error amplifier for providing a feedback voltage proportional to a current through an inductor coupled to the output. A current feedback loop may be designed so that the voltage at the error amplifier output exceeds a current-limiting clamp voltage when the DC / DC converter enters an overcurrent condition. A voltage feedback loop may be designed so that the voltage at the error amplifier output neither exceeds nor falls below a skip clamp when the DC / DC converter is in skip mode. SUMMARY
[0003] In a first example, a circuit includes a first amplifier having first and second amplifier inputs and a first amplifier output. The first amplifier input is coupled to a reference voltage terminal, and the second amplifier input is coupled to a voltage feedback terminal. A second amplifier has third and fourth amplifier inputs and second and third amplifier outputs, the third amplifier input coupled to the first amplifier output. A first switch has first and second switch terminals, and the second switch terminal is coupled to the fourth amplifier input. A resistor is coupled between the first amplifier output and the first switch terminal.
[0004] A third amplifier has a fifth and a sixth amplifier input and a fourth amplifier output. The fifth amplifier input is coupled to the second amplifier output, and the sixth amplifier input is coupled to the third amplifier output. A second switch has a third and a fourth switch terminal. The third switch terminal is coupled to the fourth amplifier output, and the fourth switch terminal is coupled to the first amplifier output.
[0005] In a second example, a voltage regulator circuit includes an integrator having first and second integrator inputs and an integrator output. The first integrator input is coupled to a reference voltage terminal, and the second integrator input is coupled to a feedback voltage terminal. A comparator has first and second comparator inputs and first and second comparator outputs. The first comparator input is coupled to the integrator output, and the second comparator input is coupled to an internal feedback terminal.
[0006] A transconductance amplifier has first and second transconductance inputs and a transconductance output. The first transconductance input is coupled to the first comparator output, the second transconductance input is coupled to the second comparator output, and the transconductance output is coupled to the first comparator input. A gate driver circuit has first and second gate drive outputs and a gate drive input. The gate drive input is coupled to the control output.
[0007] A high-side transistor has a high-side control terminal. The high-side transistor is coupled between an input voltage terminal and a switch terminal, and the high-side control terminal is coupled to the first gate drive output. A low-side transistor has a low-side control terminal. The low-side transistor is coupled between the switch terminal and a ground terminal, and the low-side control terminal is coupled to the second gate drive output. BRIEF DESCRIPTION OF THE DRAWINGS Fig. Figure 1 shows a circuit diagram for an example voltage regulator with a skip clamp circuit. Fig. Figure 2 shows a circuit diagram for an example voltage regulator control loop with a skip clamp circuit. Fig. Figure 3 shows a circuit diagram for an example voltage regulator with an active skip terminal in combination with a passive terminal. Fig. 4 shows a circuit diagram for an exemplary circuit including a comparator preamplifier circuit, a comparator circuit, a transconductance circuit, and a current extractor. DETAILED DESCRIPTION OF EMBODIMENTS
[0008] Throughout this description, the same reference numerals (functional and / or structural) represent the same or similar features. The drawings are not necessarily to scale.
[0009] In some DC / DC voltage converters, the output voltage can be regulated by a circuit with a feedback loop. The feedback loop may include an error amplifier that compares a feedback voltage proportional to the output voltage with a reference voltage. When the voltage regulator is operating in a power-saving mode, the error amplifier's output can benefit from clamping the error amplifier's output voltage within a specific voltage range. The circuitry that keeps the amplifier's output voltage within this specific voltage range is a skip clamp.
[0010] Fig. Figure 1 shows a circuit diagram for an example voltage regulator 100 with a skip clamp circuit. The input voltage terminal for the voltage regulator 100 is V IN 136 and the output voltage terminal is V OUT150. An integrating error amplifier 104 has a first input connected to V REF 102 and a second input connected to V FB 106. The output 112 of the error amplifier 104, REF_INNER, is coupled to a first input of the comparator 116. A capacitor Cc 108 is coupled between REF_INNER and a ground terminal. In at least one case, the comparator 116 is a hysteresis comparator. However, in other cases, the comparator 116 may be a comparator without hysteresis.
[0011] The second input of comparator 116 is coupled to an inner feedback terminal FB_INNER 114. Skip clamp circuit 110 is coupled between the first and second inputs of comparator 116. The output 118 of comparator 116 is coupled to a first input of a logic circuit 120. Logic circuit 120 may include AND gates, OR gates, latches, and flip-flops. A second input of logic circuit 120 is coupled to the output of an IZERO circuit 132. IZERO circuit 132 detects when the current through an inductor 142 crosses a threshold, such as zero amperes.
[0012] The output of logic circuit 120 is coupled to the input of gate driver circuit 134. A first output of gate driver circuit 134 is coupled to the gate of transistor 138. A second output of gate driver circuit 134 is coupled to the gate of transistor 140. Transistor 138 is connected between V IN136 and the switch terminal SW. The transistor 140 is coupled between the switch terminal SW and a ground terminal. The inductor 142 is coupled between the switch terminal SW and the output voltage terminal V OUT 150. A first terminal of the resistor 144 is coupled to the switch terminal SW and to the inductor 142. A capacitor 148 and a resistor 152 are connected between the output voltage terminal V OUT 150 and the ground connection connected in parallel.
[0013] Resistors 154 and 152 are connected between the output voltage terminal V OUT 150 and the ground terminal, forming a voltage divider for the voltage at the output voltage terminal V OUT 150 is created. The output of the voltage divider is connected to the feedback voltage terminal V FB106. Capacitor 146 is coupled between inductor 142 and a second terminal of resistor 144. A capacitor 130 is coupled between capacitor 146 and the inner feedback terminal FB_INNER 114.
[0014] The integrating amplifier 104 compares the voltage at the feedback voltage terminal V FB 106 with a reference voltage V REF 102 and provides an error signal REF_INNER 112 at its output for output voltage regulation. The IZERO circuit 132 has an input current signal proportional to a current flowing through transistor 140. This input current signal is compared to an internal reference current signal. In at least one example, the internal reference current signal is zero, making the IZERO circuit 132 a zero-current detection circuit capable of detecting when the current through inductor 142 crosses zero and reverses its polarity.
[0015] When the output current load decreases, the voltage at the output voltage terminal V OUT 150, which increases the voltage at V FB 106 higher than the voltage at V REF 102. When the voltage at REF_INNER 112 is not clamped, it goes to the negative rail voltage (e.g., ground) because it is coupled to the output of an integrator. When a load transient occurs, the voltage at the output voltage terminal V OUT 150. The output voltage of the error amplifier 104, which typically has a limited bandwidth, may respond relatively slowly to a change in its inputs. Due to the relatively narrow bandwidth of the error amplifier 104, it takes longer for the voltage at the output voltage terminal V OUT 150 returns to its regulated voltage value.
[0016] Clamp circuit 110 is coupled between the first and second inputs of comparator 116 and is useful for clamping the voltage at REF_INNER 112 to a value that keeps the voltage difference between REF_INNER 112 and FB_INNER 114 within a specified range. The clamp circuit assists the comparator in precisely controlling how long voltage regulator 100 remains in power-save mode. The purpose of skip clamp circuit 110 is to limit the voltage swing of REF_INNER 112 during the skip time. Limiting the voltage swing of REF_INNER 112 can reduce the output voltage undershoot when a load current transient occurs. However, voltage regulator 100 faces a trade-off between regulation voltage precision and response time to load transients in power-save mode.
[0017] Under ideal conditions in power saving mode, the voltage difference between the comparator inputs REF_INNER 112 and FB_INNER 114 is always proportional to the voltage difference between the inputs of the integrating amplifier V REF 102 and V FB 106. The voltage at FB_INNER 114 is set by a diode 126, which is coupled to ground via a resistor 128. If the skip clamp circuit 110 is not present, the voltage at REF_INNER 112 is saturated at ground. When a load transient occurs, the output 118 of the comparator 116 does not change its output state until the voltage at the output voltage terminal V OUT 150 to such an extent that the voltage difference between FB_INNER and REF_INNER is overcome. The voltage at the output voltage terminal V OUT150 must drop to near ground to change the output state of comparator 118. This can adversely affect the voltage regulator's response to load transients.
[0018] Fig. Figure 2 shows a circuit diagram 200 for an exemplary voltage regulator control loop with a skip clamp circuit. The integrating error amplifier 104 has a first input connected to the reference voltage terminal V REF 102, and a second input connected to the feedback voltage terminal V FB 106, which is proportional to an output voltage of the voltage regulator. Differential outputs 252 and 254 of error amplifier 104 are coupled as differential inputs to an amplifier 240. Capacitor 108 is coupled between the output of amplifier 240 and ground. A resistor 244 is coupled between the output of amplifier 240 and a first terminal of a switch 246.
[0019] The differential outputs 252 and 254 of error amplifier 104 are also coupled to the differential inputs of an amplifier 242. The output of amplifier 242 is coupled to the input of a current extractor 248. The output of current extractor 248 is coupled to a first terminal of a switch 250. The output of amplifier 240 is coupled to a first input of comparator 116. A second terminal of switch 250 is coupled to a second input of comparator 116 and to a second terminal of switch 246. A current source 124 is connected in series with diode 126 between a voltage supply and the ground terminal. Diode 126 is coupled to FB_INNER 114 through resistor 128 and sets the voltage at FB_INNER 114.
[0020] The skip terminal 110 maintains the voltage difference between REF_INNER 112 and FB_INNER 114 within a certain range. The voltage at REF_INNER 112 can be adjusted by closing switch 246 to connect resistor 244 between REF_INNER 112 and FB_INNER 114. When the voltage at V FB 106 higher than the voltage at V REF 102, the output of error amplifier 104 could saturate at the negative rail if no skip clamp circuit were present. A current flowing through resistor 244 is coupled to REF_INNER, creating a voltage across resistor 244. The current through resistor 244 is proportional to V FB - V REF The worst-case voltage across resistor 244 can be calculated using equation (1): V244=(VFB−VREF)*gml*RCLAMP where g m1 is the combined transconductance of amplifiers 238 and 240 and R CLAMPis the resistance of resistor 244. The skip clamp voltage is dynamic because it depends on the feedback voltage at V FB 106 depends.
[0021] The comparator 116 may have an offset voltage that increases the regulation limit voltage required for state changes of the comparator 116. The comparator 116 changes its state when the voltage difference (V REF - V FB ) overcomes the offset voltage divided by the combined transconductance of amplifiers 238 and 240 (Vos' = Vos / (g m1 *R CLAMP )).
[0022] However, the skip clamp circuit 110 of the voltage regulator 200 has at least one limitation. If the combined ripple and feedback voltage is higher than the reference voltage, this applies a certain clamp voltage across resistor 244 that is greater than the offset voltage, preventing a change in state of the comparator 116. If a load transient occurs at this time, the voltage undershoot coupled across the capacitor 130 must first overcome this clamped voltage before the output 118 of the comparator 116 begins to increase the inductor current to respond to the voltage undershoot.
[0023] A smaller combination of g m1 *R CLAMP provides better response to load transients because it generates a lower clamping voltage. Conversely, a larger g m1for more accurate steady-state voltage regulation. Therefore, there is a performance trade-off, as higher transconductance improves voltage regulation accuracy at the expense of transient response, while lower g m enables faster response to transients at the expense of compromised voltage regulation accuracy.
[0024] Fig. Figure 3 shows a circuit diagram for an example voltage regulator 300 with an active skip clamp in combination with a passive clamp. The input voltage terminal for the voltage regulator 300 is V IN 136 and the output voltage terminal is V OUT 150. An integrating error amplifier 104 has a first input connected to V REF 102 and a second input connected to V FB106. The integrating error amplifier 104 consists of two amplifier stages: preamplifier 238 and amplifier 240. The differential outputs 252 and 254 of preamplifier 238 are coupled to respective differential inputs of amplifier 240.
[0025] Comparator 116 consists of three stages: preamplifier 364, comparator stage 366, and driver 368. The output 112 of amplifier 240, REF_INNER, is coupled to a first input of preamplifier 364. Capacitor Cc 108 is coupled between REF_INNER and a ground terminal. The second input of preamplifier 364 is coupled to an internal feedback terminal FB_INNER 114. Differential outputs 372 and 374 of preamplifier 364 are coupled to respective differential inputs of comparator stage 366. The output of comparator stage 366 is coupled to the input of driver 368. The output of driver 368 is coupled to a first input of logic circuit 120. Logic circuit 120 may include AND gates, OR gates, latches, and flip-flops. A second input of the logic circuit 120 is coupled to the output of an IZERO circuit 132.The IZERO circuit 132 detects when the current through an inductor 142 crosses a certain threshold, such as zero amperes.
[0026] The output of logic circuit 120 is coupled to the input of gate driver circuit 134. A first output of gate driver circuit 134 is coupled to the gate of transistor 138. A second output of gate driver circuit 134 is coupled to the gate of transistor 140. Transistor 138 is connected between V IN 136 and the switching terminal SW. The transistor 140 is coupled between the switching terminal SW and a ground terminal. The inductor 142 is connected between the switching terminal SW and the output voltage terminal V OUT 150. A first terminal of the resistor 144 is coupled to the switch terminal SW and to the inductor 142. A capacitor 148 and a resistor 152 are connected between the output voltage terminal V OUT150 and the ground connection connected in parallel.
[0027] Resistors 154 and 152 are connected between the output voltage terminal V OUT 150 and the ground terminal, forming a voltage divider for the voltage at the output voltage terminal V OUT 150 is created. The output of the voltage divider is connected to the feedback voltage terminal V FB 106 and provides feedback for voltage regulation. Capacitor 146 is coupled between inductor 142 and a second terminal of resistor 144. Capacitor 130 is coupled between capacitor 146 and FB_INNER 114.
[0028] The preamplifier 238 of the integrator 104 compares the voltage at the feedback terminal V FB 106 with a reference voltage V REF 102 and provides a differential output error signal representing the difference between the voltages at V FB 106 and V REF102. The differential output error signal at 252 and 254 is provided as a differential input to amplifier 240. The single-ended output of amplifier 240 is REF_INNER 112. IZERO circuit 132 has an input current signal proportional to a current flowing through transistor 140. This input current signal is compared to an internal reference current signal. The internal reference current signal can be set to zero, transforming IZERO circuit 132 into a zero-current detection circuit capable of detecting when the current through inductor 142 reverses its polarity.
[0029] The differential inputs of transconductance amplifier 370 are coupled to the differential outputs 372 and 374 of preamplifier 364, respectively. An asymmetrical output of transconductance amplifier 370 is coupled to an input of current extractor 376. The output of current extractor 376 is coupled to a first terminal of a switch 362. The output of current extractor 376 provides current when the output of transconductance amplifier 370 is positive and provides no current when the output of transconductance amplifier 370 is negative. A second terminal of switch 362 is coupled to REF_INNER 112. Resistor 244 and switch 360 are coupled between the first input and the second input of preamplifier 364. FB_INNER 114 is coupled to a common-mode voltage generator 380 via resistor 128.
[0030] Voltage regulator 300 uses an active skip clamp circuit in combination with a passive skip clamp circuit. Preamplifier 364 senses the voltage difference between REF_INNER 112 and FB_INNER 114 and provides a differential output to a differential input of transconductance amplifier 370. Transconductance amplifier 370 provides a current at its output that is proportional to the clamp voltage, which corresponds to the voltage difference between REF_INNER 112 and FB_INNER 114. Current extractor 376 provides a current proportional to the output of transconductance amplifier 370. The current at the output of transconductance amplifier 370 is subtracted from the current at the output of integrator 104, and the difference is provided to the first input of preamplifier 364.
[0031] Transconductance amplifier 370, current extractor 376, and switch 362 form a feedback loop to suppress a portion of the current through integrator 104 when the voltage difference between VREF 102 and VFB 106 becomes relatively large. This suppression helps prevent comparator 116 from saturating as a result of an output load transient and becoming stuck in a particular output state. The feedback loop partially suppresses the integrator's transconductance, thereby lowering the clamping voltage. However, the regulation accuracy of the voltage regulator is not affected.
[0032] The clamping voltage between REF_INNER 112 and FB_INNER 114 approaches zero as comparator 116 approaches the trigger point for transitioning from one output state to another. The transconductance GM AUX, which is fed back to the output of integrator 104, also approaches zero. However, the offset voltage in the integrator stage continues to be compensated, which helps maintain the accuracy of the voltage regulation. The equation for the clamp offset voltage in power-save mode under light load is shown in equation (2): VFB_INNER−VREF_INNER=(VFB−VREF)gm1RCLAMP1+gm2RCLAMP−VOSgm2RCLAMP1+gm2RCLAMP where g m1 is the transconductance of the integrator 104 and g m2 is the product of the transconductance of amplifier 370 and the voltage gain of amplifier 364.
[0033] The clamp offset voltage is reduced by the feedback loop because the transconductance g m1 by the transconductance g m2is partially canceled. Therefore, the clamping voltage is reduced to a relatively low value without affecting the voltage regulation accuracy of the regulator. Therefore, a relatively large gain g m2 *R CLAMP used to achieve a small but well-controlled effective clamp offset voltage.
[0034] Fig. 4 shows a circuit diagram 400 for an exemplary circuit including a comparator preamplifier circuit 364, a comparator circuit 366, a transconductance circuit 370, and a current extractor 376. The comparator preamplifier circuit 364 includes transistors M1, M2, M3, and M4 and resistors R1 and R2. The comparator circuit 366 includes transistors M5, M6, M7, and M8. The transconductance circuit 370 includes transistors M5, M7, M9, and M 12. Transistors M5 and M7 are shared by comparator circuit 366 and transconductance circuit 370. Current extractor 376 includes transistors M 10 , M 11 , M 13 , M 14 and M 15 .
[0035] The inputs to the comparator preamplifier circuit 364 are REF_INNER 112 and FB_INNER 114. REF_INNER 112 is coupled to the gate of transistor M1. FB_INNER 114 is coupled to the gate of transistor M2. The differential outputs 372 and 374 of the comparator preamplifier circuit 364 are connected as differential inputs to the transconductance circuit 370 at the gates of transistors M. 12 and M7. The gate of transistor M 12is coupled to the gate of transistor M8, via resistor R2 to the gates of transistors M3 and M4, and via resistors R1 and R2 to the gate of transistor M7. The drain of transistor M4 is coupled to the drain of transistor M2, and the drain of transistor M3 is coupled to the drain of transistor M1. Resistor R2 is coupled between the gate and drain of transistor M4. Resistor R1 is coupled between the gate and drain of transistor M3. The sources of transistors M1 and M2 are coupled to the output of a bias current source, which can be ground or at a different voltage. The sources of transistors M7, M3, M4, M8, M 12 , M 13 and M 14 are linked together.
[0036] The transistors M 12 and M7 are used to supply the current from the comparator preamplifier circuit 364. The transistors M 10 and M 11form a first current mirror, and the transistors M 13 and M 14 form a second current mirror for supplying a feedback current which is supplied to REF_INNER 112 to suppress a portion of the current through the integrator 104.
[0037] Transconductance circuit 370 is turned on and generates a feedback current only when the voltage at FB_Inner 114 is higher than the voltage at REF_INNER 112 or when the regulator is in power-saving mode. To minimize offset, a common gain stage is used to provide better balancing, so the circuit does not overcompensate or undercompensate with the current supplied to REF_INNER 112.
[0038] In at least one case, the product of comparator preamplifier circuit 364 and the transconductance of transconductance circuit 370 is designed to equal the transconductance of integrator 104. Matching the transconductances of these two circuits helps balance the current provided by transconductance circuit 370 with the current provided by integrator 104. However, in other cases, the transconductance of transconductance circuit 370 may differ from the transconductance of integrator 104.
[0039] In this specification, "terminal," "node," "interconnect," "lead," and "pin" are used interchangeably. Unless otherwise specified, these terms generally mean a connection between or termination of a device element, circuit element, integrated circuit, device, or other electronic or semiconductor component.
[0040] In this specification, "ground" includes a chassis ground, an earth ground, a floating ground, a virtual ground, a digital ground, a common ground, and / or any other form of ground connection applicable or suitable to the teachings of this specification.
[0041] In this description, the term "couple" can cover connections, communications, or signal paths that enable a functional relationship consistent with this description. For example, if device A generates a signal to control device B to perform an action, then: (a) in a first example, device A is coupled to device B by a direct connection; or (b) in a second example, device A is coupled to device B via an intervening component C, where the intervening component C does not change the functional relationship between device A and device B, such that device B is controlled by device A via the control signal generated by device A.
[0042] In this description, even though operations are described in a particular order, some operations may be optional, and the operations need not necessarily be performed in that particular order to achieve specified results. In some examples, multitasking and parallel processing may be beneficial. Furthermore, a separation of various system components in the embodiments described above does not necessarily require such separation in all embodiments.
[0043] Modifications of the described embodiments as well as other embodiments are possible within the scope of the claims.
Claims
[1] Circuit comprising: a first amplifier having a first and a second amplifier input and a first amplifier output, the first amplifier input being coupled to a reference voltage terminal and the second amplifier input being coupled to a voltage feedback terminal; a second amplifier having a third and a fourth amplifier input and a second and a third amplifier output, the third amplifier input being coupled to the first amplifier output; a first switch having a first and a second switch terminal, the second switch terminal coupled to the fourth amplifier input; a resistor coupled between the first amplifier output and the first switch terminal; a third amplifier having a fifth and a sixth amplifier input and a fourth amplifier output, wherein the fifth amplifier input is coupled to the second amplifier output and the sixth amplifier input is coupled to the third amplifier output; and a second switch having a third and a fourth switch terminal, wherein the third switch terminal is coupled to the fourth amplifier output and the fourth switch terminal is coupled to the first amplifier output. [2] The circuit of claim 1, further comprising a common mode voltage generating circuit coupled to the fourth amplifier input. [3] The circuit of claim 1, further comprising a current extractor circuit coupled between the fourth amplifier output and the third switch terminal. [4] The circuit of claim 1, further comprising a fourth amplifier having seventh and eighth amplifier inputs and a fifth amplifier output, the seventh amplifier input being coupled to the third amplifier output and the eighth amplifier input being coupled to the fourth amplifier output. [5] The circuit of claim 4, further comprising: a logic circuit having a first and a second logic input and a logic output, the first logic input being coupled to the fourth amplifier output; a driver circuit having a driver input and a first and a second driver output, the driver input being coupled to the logic output; a first transistor coupled between an input voltage terminal and a switching terminal; a second transistor coupled between the switching terminal and a ground terminal; and an inductance coupled between the switching terminal and an output voltage terminal. [6] The circuit of claim 5, wherein the resistor is a first resistor and the circuit further comprises: a first capacitor coupled between the first amplifier output and the ground terminal; a second capacitor coupled between the output voltage terminal and an auxiliary terminal; a third capacitor coupled between the auxiliary terminal and the fourth amplifier input; and a second resistor coupled between the switching terminal and the auxiliary terminal. [7] The circuit of claim 6, further comprising: a third resistor coupled between the output voltage terminal and the second amplifier input; and a fourth resistor coupled between the second amplifier input and the ground terminal. [8] The circuit of claim 7, wherein the third amplifier output is zero unless a voltage at the fourth amplifier input is higher than a voltage at the third amplifier input. [9] The circuit of claim 5, further comprising a current detection circuit having a detection output, wherein the current detection circuit is configured to detect a current through the second transistor. [10] The circuit of claim 9, wherein the current detection circuit is configured to provide a zero crossing signal at the detection output in response to detecting a zero crossing of the current through the second transistor. [11] Voltage regulator circuit comprising: an integrator having a first and a second integrator input and an integrator output, the first integrator input being coupled to a reference voltage terminal and the second integrator input being coupled to a feedback voltage terminal; a comparator having first and second comparator inputs and first and second comparator outputs, the first comparator input coupled to the integrator output and the second comparator input coupled to an internal feedback terminal; a transconductance amplifier having first and second transconductance inputs and a transconductance output, the first transconductance input coupled to the first comparator output, the second transconductance input coupled to the second comparator output, and the transconductance output coupled to the first comparator input; a gate driver circuit having a first and a second gate drive output and a gate drive input, the gate drive input being coupled to the comparator; a high-side transistor having a high-side control terminal, wherein the high-side transistor is coupled between an input voltage terminal and a switch terminal, and the high-side control terminal is coupled to the first gate drive output; and a low-side transistor having a low-side control terminal, wherein the low-side transistor is coupled between a switch terminal and a ground terminal, and the low-side control terminal is coupled to the second gate drive output. [12] A voltage regulator circuit according to claim 11, wherein the transconductance amplifier includes: a first field effect transistor (FET) having a first gate, a first drain and a first source, the first gate coupled to the first comparator output; a second FET having a second gate, a second drain, and a second source, the second source coupled to the first source and the second gate coupled to the second comparator output; a third FET having a third gate, a third drain, and a third source, the third drain coupled to the first drain, the third gate coupled to the third drain, and the third source coupled to the ground terminal; and a fourth FET having a fourth gate, a fourth drain, and a fourth source, wherein the fourth gate is coupled to the fourth drain, the fourth gate is coupled to the third gate, and the fourth source is coupled to the ground terminal. [13] A voltage regulator circuit according to claim 11, further comprising: a current extractor having an extractor input and an extractor output, the extractor input being coupled to the transconductance output; and a switch having a first and a second switch terminal, wherein the first switch terminal is coupled to the extractor output and the second switch terminal is coupled to the first comparator input. [14] The voltage regulator circuit of claim 13, wherein the switch is a first switch and the voltage regulator circuit further comprises: a common-mode voltage generator with a generator output; a second switch having a third and a fourth switch terminal, the third switch terminal being coupled to the generator output; and a resistor coupled between the fourth switch terminal and the first comparator input. [15] The voltage regulator circuit of claim 11, further comprising a comparator driver having first and second driver inputs and a driver output, the first driver input coupled to the first comparator output and the second driver input coupled to the second comparator output. [16] The voltage regulator circuit of claim 15, further comprising a logic circuit having first and second logic inputs and a logic output, wherein the first logic input is coupled to the driver output and the logic output is coupled to the gate driver input. [17] The voltage regulator circuit of claim 11, further comprising an inductor coupled between the switch terminal and an output voltage terminal. [18] A voltage regulator circuit according to claim 17, further comprising: a first resistor coupled between the output voltage terminal and the feedback voltage terminal; a second resistor coupled between the feedback voltage terminal and the ground terminal; and a capacitor coupled between the output voltage terminal and the ground terminal. [19] The voltage regulator circuit of claim 13, wherein the extractor output is zero unless a voltage at the second comparator input is higher than a voltage at the first comparator input. [20] The voltage regulator circuit of claim 16, further comprising a current detection circuit having a detection output, wherein the detection output is coupled to the second logic input, and the current detection circuit is configured to detect a current through the low-side transistor.