Impedance matching circuit for a plasma process system and a plasma process system with such an impedance matching circuit

Abstract

An impedance matching circuit (1) comprises three impedance matching units (6, 7, 8) connected in series. The second impedance matching unit (7) comprises at least one semiconductor switching element (12), with which the transformation ratio can be changed during operation. A first intermediate impedance (Ẕ1), applied at the input (10) of the second impedance matching unit (7) and to which the first impedance matching unit (6) transforms an input impedance (Ẕ0), is selected for a predetermined target input impedance in such a way that the following applies: a) the conductance of the first intermediate impedance (Ẕ1) is greater than the conductance of the impedance that would arise at the input (10) of the second impedance matching unit (7) a the rated power (PNenn) of the impedance matching circuit (1) and the maximum permissible voltage of the at least one semiconductor switching element (12); and b) the resistance of the first intermediate impedance (Ẕ1) is greater than the resistance of the impedance that would arise at the input (10) of the second impedance matching unit (7) at the rated power (PNenn) of the impedance matching circuit (1) and the maximum permissible current of the at least one semiconductor switching element (12).

Description

[0001] Impedance matching circuit for a plasma process system and a plasma process system with such an impedance matching circuit

[0002] The invention relates to an impedance matching circuit for power

[0003] > 500 W, preferably > 2 kW and frequencies in the range of 2 to 100 MHz, in particular in the range of 10 MHz to 50 MHz, for a plasma process system and a plasma process system with such an impedance matching circuit.

[0004] The surface treatment of workpieces using plasma and gas lasers are industrial processes in which, particularly in a plasma process chamber, a plasma is generated using direct current or a high-frequency alternating signal with an operating frequency in the range of a few 10 kHz up to the GHz range, in particular up to 10 GHz.

[0005] The plasma processing chamber is connected to a high-frequency power supply via additional electronic components such as coils, capacitors, cables, or transformers. These additional components can represent resonant circuits, filters, or impedance matching circuits.

[0006] 'High frequency' is also abbreviated to 'HF' in the following. HF refers to frequencies in the range from 2 MHz to 100 MHz, particularly in the range from 10 MHz to 50 MHz.

[0007] The plasma process has the problem that the electrical load impedance of the plasma process chamber, which occurs during the process and is caused by the plasma, which can be considered an electrical load or consumer, depends on the conditions in the plasma process chamber and can vary greatly. In particular, the properties of the workpiece, electrodes, and gas conditions are important.

[0008] RF power supplies have a limited operating range with respect to the impedance of the connected electrical load, also called the "consumer." If the load impedance leaves a permissible range, the RF power supply may be damaged or even destroyed.

[0009] For this reason, an impedance matching circuit, also called a matchbox, is usually required to transform the impedance of the load to a nominal impedance of the RF power supply output.

[0010] Various impedance matching circuits are known. Either the impedance matching circuits are fixed and have a predetermined transformation effect, i.e., they consist of electrical components, particularly coils and capacitors, that do not change during operation. This is particularly useful for constant operation, such as in a gas laser. Furthermore, impedance matching circuits are known in which at least some of the components of the impedance matching circuits are variable, particularly through mechanical modification of the components. For example, motor-driven variable capacitors are known, whose capacitance value can be changed by changing the arrangement of the capacitor plates relative to one another.

[0011] Roughly speaking, a plasma can be assigned to three impedance ranges. In the unignited state, very high impedances exist. During normal operation, i.e., during intended operation with plasma, lower impedances exist. Very low impedances can occur in the case of unwanted local discharges, also called "ares," or in the case of plasma fluctuations. In addition to these three identified impedance ranges, other special states with different associated impedance values ​​can occur. If the load impedance changes suddenly and the load impedance or the transformed load impedance moves outside of a permissible impedance range, the RF power supply or transmission equipment between the RF power supply and the plasma process chamber can be damaged. Furthermore, there are also stable plasma states that are undesirable.

[0012] To adapt the usually fixed output impedance of an RF power supply to the changing electrical load, an impedance matching circuit is usually provided directly upstream of the load. Such an impedance matching circuit is described, for example, in DE 10 2009 001 355 A1.

[0013] Impedance matching circuits, whose electrical properties, such as their capacitances, vary during operation, have motors, for example, to change these electrical properties. However, there are also impedance matching circuits that have semiconductor switches to switch capacitances on and off. The problem here is that, depending on the load condition, the current and voltage carrying capacity of the semiconductor switches is insufficient. The current and voltage carrying capacity of the actual semiconductor switches determines the maximum transferable power of such an impedance matching circuit. Neither in a 50-ohm system nor directly at the plasma process chamber are the impedances suitable for exploiting both the current and voltage limits of a semiconductor switching element in two switching positions. In principle, it can be stated that the semiconductor switching elements are not switched in their optimal range.

[0014] Either the current and / or voltage are too low, so the semiconductor switching elements are not fully controlled, or the current and voltage are so high that the semiconductor switching elements could be damaged. The latter scenario is to be avoided, so that the semiconductor switches provided by the state of the art are never fully utilized.

[0015] It is therefore the object of the present invention to provide an impedance matching circuit whose components are utilized more advantageously than in the prior art.

[0016] The object is achieved by the impedance matching circuit according to independent claim 1 and by the plasma process system with such an impedance matching circuit according to claim 19. Claims 2 to 18 describe advantageous embodiments of the impedance matching circuit, and claim 20 describes an advantageous embodiment of the plasma process system.

[0017] The impedance matching circuit according to the invention is used in particular in a plasma processing system, wherein the impedance matching circuit is designed for a predetermined nominal power. The impedance matching circuit comprises an input terminal designed to electrically, in particular galvanically, connect the impedance matching circuit to an RF power supply. The impedance matching circuit is designed in particular for power levels >500 W, preferably >2 kW, and frequencies in the range from 2 MHz to 100 MHz. The impedance matching circuit also comprises an output terminal designed to electrically, preferably galvanically, connect the impedance matching circuit to a load, in particular in the form of a plasma processing chamber.The impedance matching circuit comprises a first impedance matching unit, which is electrically connected to the input terminal and is designed to transform the input impedance at the input terminal to a first intermediate impedance, wherein the transformation ratio is fixed during operation. The input impedance is preferably 50 ohms and thus preferably also around the nominal impedance of the RF power supply. The wording according to which the "transformation ratio is fixed during operation" means that no automatic adjustment, e.g., by motor or semiconductor switch, of capacitance values ​​and / or inductance values ​​is possible during operation. The impedance matching circuit further comprises a second impedance matching unit with at least one semiconductor switching element. The second impedance matching unit comprises an input and is electrically connected via this input to the output of the first impedance matching unit.The second impedance matching unit is designed to transform the first intermediate impedance at its input to a second intermediate impedance at its output, wherein the transformation ratio can be changed during operation by the at least one semiconductor switching element. The impedance matching circuit further comprises a third impedance matching unit that is electrically connected to the output of the second impedance matching unit. An output of the third impedance matching unit is electrically connected to the output terminal of the impedance matching circuit. The third impedance matching unit is designed to transform the second intermediate impedance to an output impedance that is provided at the output terminal. The at least one semiconductor switching element of the impedance matching unit is operable up to a maximum permissible voltage and up to a maximum permissible current.These values ​​can be taken, for example, from the corresponding data sheet of the semiconductor switching element used. The first intermediate impedance, to which the first impedance matching unit transforms the input impedance, is selected for a predetermined target input impedance such that: a) the conductance of the first intermediate impedance is greater than the conductance of the impedance that would occur at the input of the second impedance matching unit at the rated power of the impedance matching circuit and the maximum permissible voltage of the at least one semiconductor switching element; and b) the resistance of the first intermediate impedance is greater than the resistance of the impedance that would occur at the input of the second impedance matching unit at the rated power of the impedance matching circuit and the maximum permissible current of the at least one semiconductor switching element.

[0018] The inventive dimensioning of the impedance matching circuit, which was determined through calculations, simulations, circuit design, tests, and investigations, ensures that at least one semiconductor switching element is fully utilized, yet not overstressed. This is particularly the case for such an impedance matching circuit designed for power levels greater than or equal to 2 kW, since in this power range the voltages and currents overload conventional semiconductor switching elements. It was thus determined that the impedance matching unit should meet the above-mentioned criteria regarding the transformation of the input impedance to a first intermediate impedance, wherein the input impedance is preferably constant and, more preferably, corresponds to 50 ohms.As a result of this, and the maximum permissible voltage and current of the semiconductor switching element, the transformation ratio, which is set by the first impedance matching unit, can be precisely calculated. The at least one semiconductor switching element is thereby precisely not overloaded, but rather switches currents and voltages that are preferably below the maximum permissible values. This ensures that the at least one semiconductor switching element is fully controlled, which in turn means that the semiconductor switching element does not have to be oversized, which in turn saves costs. The dimensioning rule ensures that no critical situations arise regarding the current and dielectric strength of the at least one semiconductor switching element.In the impedance matching circuit according to the invention, it is particularly possible to dispense with the need to connect several semiconductor switching elements in parallel and / or in series. This is advantageous because the effort required to actually switch the several semiconductor switching elements at the same time is very high. If one semiconductor switching element switches slightly later than the other semiconductor switching elements, this can lead to the destruction of the impedance matching circuit. However, this is successfully avoided by the dimensioning according to the invention. The dimensioning can thus ensure that, for a defined input impedance, which is predetermined in particular by the RF power supply, no operating situation arises for the at least one semiconductor switching element in which the at least one semiconductor switching element could be destroyed.The at least one semiconductor switching element only needs to switch currents and / or voltages that are below the maximum permissible voltage and / or current. An additional control loop for measuring voltages and / or currents and making the switching behavior dependent on them is therefore unnecessary. As a result, the semiconductor switching element does not have to be significantly oversized, as is the case with prior art impedance matching circuits, making the impedance matching circuit according to the invention more cost-effective to manufacture.

[0019] For the term "conductance" of a complex impedance Z, it should generally be assumed that the conductance is real and equal to G, with the following relationship:

[0020] Z = 1 / Y = 1 / (G + jß).

[0021] Consequently, the conductance of the first intermediate impedance Zi is determined as Gi, where: Zi = 1 / Yi = 1 / (Gi + jßi).

[0022] B, Bi are the imaginary parts of the complex conductance Y, Yi. The term "resistance" of a complex impedance Z should generally be understood as meaning that the resistance is real and equal to R, with the following relationship: Z = R + jX.

[0023] The resistance of the first intermediate impedance is therefore Ri where: Zi = Ri + jXi.

[0024] X, Xi is the imaginary part of the complex impedance Z, Zi.

[0025] In an advantageous embodiment of the impedance matching circuit, the first intermediate impedance is selected such that: Gl > PNenn / Umax 2 , with

[0026] Gi = conductance of the first intermediate impedance;

[0027] PNom = rated power of the impedance matching circuit;

[0028] Umax = maximum voltage at the at least one semiconductor switching element; and

[0029] Rl > PNom / I max 2 , with

[0030] Ri= resistance of the first intermediate impedance;

[0031] PNom = rated power of the impedance matching circuit;

[0032] Imax = maximum current at at least one semiconductor switching element.

[0033] This allows the dimensions to be adjusted even more precisely.

[0034] In an advantageous embodiment of the impedance matching circuit, in one of the two switching positions of the at least one semiconductor switching element, a voltage or a current is applied to the semiconductor switching element which is less than 20%, in particular less than 10%, away from the maximum permissible values ​​for voltage or current.

[0035] In an advantageous embodiment of the impedance matching circuit, the input impedance is essentially constant during operation of the impedance matching circuit and is equal to the specified target input impedance. This ensures, on the one hand, that a constant impedance is presented to the RF power supply, and, on the other hand, that the constant transformation ratio from the input impedance to the first intermediate impedance by the first impedance matching unit ensures that the at least one semiconductor switching element is always operated within the tolerances and at a high level of control.

[0036] In an advantageous embodiment of the impedance matching circuit, the first intermediate impedance on the Smith chart is closer to the output impedance than to the input impedance. Additionally or alternatively, the second intermediate impedance on the Smith chart is closer to the output impedance than to the first intermediate impedance. This maximizes the control of the at least one semiconductor switching element.

[0037] In an advantageous embodiment of the impedance matching circuit, the at least one semiconductor switching element of the second impedance matching unit is a transistor or a diode. This allows the transformation ratio to be changed particularly quickly during operation.

[0038] A transistor can be implemented as a metal-oxide-semiconductor field-effect transistor (MOSFET). A switching diode can be implemented as a PIN diode, for example.

[0039] In an advantageous embodiment, the output impedance can be determined by the load, particularly in the form of the plasma processing chamber, and can be changed during operation. The output impedance can be within a specific range on the Smith chart. The at least one semiconductor switching element assumes different switching positions for those points of the output impedance that are furthest apart in the Smith chart within the specific range. The "specific range" can also be defined as the permissible range in which the load can be operated. This "specific range" can be defined in advance.

[0040] In an advantageous embodiment, the transformation ratio of the third impedance matching unit is unchangeable during operation.

[0041] In another advantageous embodiment, the impedance matching unit comprises at least one motor-adjustable capacitance, which allows the transformation ratio of the third impedance matching unit to be changed during operation. This allows for even more precise response to a changing output impedance from the load during operation.

[0042] In an advantageous embodiment, the second intermediate impedance to which the second impedance matching unit transforms the first intermediate impedance is selected such that: a) the conductance of the second intermediate impedance is greater than the conductance of the impedance that would occur at the rated power of the impedance matching circuit and the maximum voltage across the at least one motor-adjustable capacitance; and b) the resistance of the second intermediate impedance is greater than the resistance of the impedance that would occur at the rated power of the impedance matching circuit and the maximum current across the at least one motor-adjustable capacitance.

[0043] This also ensures that the motor-adjustable capacitance of the third impedance matching unit is fully controlled, while at the same time not exceeding the maximum permissible values ​​for current and voltage. In this case, the motor-adjustable capacitance does not need to be oversized, thus optimizing the costs for the third impedance matching unit. The conductance of the second intermediate impedance Z2 is G2, where: Z2 = I / Y2 = 1 / (G2 + jß2).

[0044] The resistance of the second intermediate impedance is R.2 where: Z2 = R2 + jX2.

[0045] In an advantageous embodiment of the impedance matching circuit, the second intermediate impedance is selected such that:

[0046] G2 > PNom / Umax 2 , with

[0047] G2 = conductance of the second intermediate impedance;

[0048] PNom = rated power of the impedance matching circuit;

[0049] Umax = maximum voltage at the at least one motor-adjustable capacitor; and

[0050] R.2 > PNom / Imax 2 , with

[0051] R.2 = resistance of the second intermediate impedance;

[0052] PNom = rated power of the impedance matching circuit;

[0053] Imax = maximum current at at least one motor-adjustable capacitor.

[0054] In an advantageous embodiment of the impedance matching circuit, the third impedance matching unit is free of a semiconductor switching element. This offers particular advantages when the load is subject to significant impedance changes. This also applies if the capacitance of the third impedance matching unit is motor-adjustable. Such a "motor-adjustable capacitance" is not understood to mean the stepwise switching of capacitances on and off, but rather merely the adjustment of the distance between two plates of a plate capacitor, which thus changes its capacitance.

[0055] In an advantageous embodiment, the first impedance matching unit comprises an output, at least one coil, and at least one first capacitor, each of which is embodied as a discrete component. The at least one coil connects the input terminal of the impedance matching circuit to a reference ground. The at least one first capacitor connects the input terminal of the impedance matching circuit to the output at which the first intermediate impedance is present. Such a configuration is particularly suitable for frequencies from 2 MHz to 50 MHz, particularly in the range from 10 MHz to 30 MHz, and particularly preferably at approximately 13 MHz.

[0056] In an advantageous embodiment, the first impedance matching unit comprises at least one second capacitor, which is particularly designed as a discrete component. The at least one second capacitor connects the output of the first impedance matching unit to the reference ground. Such a configuration is particularly suitable for frequencies from 2 MHz to 50 MHz, particularly in the range from 10 MHz to 30 MHz, particularly preferably at approximately 27 MHz.

[0057] In an advantageous embodiment, the second impedance matching unit comprises at least one coil, at least one first capacitance, and at least one further capacitance, each of which is embodied as a discrete component. The first intermediate impedance is present at an input of the second impedance matching unit. The second intermediate impedance is present at an output of the second impedance matching unit. The at least one coil is arranged in a transmission path that connects the input to the output. The at least one semiconductor switching element is designed to effectively electrically connect the transmission path to a reference ground via the at least one first capacitance and / or to effectively connect the at least one further capacitance in series with the transmission path.

[0058] In an advantageous embodiment, the second impedance matching unit comprises a plurality of semiconductor switching elements and a plurality of capacitors. The plurality of semiconductor switching elements are designed to: a) electrically connect the transmission path to a reference ground via each of the capacitors, wherein one semiconductor switching element is arranged in series with each capacitor and wherein each capacitor is arranged with its respective semiconductor switching element in parallel with the other capacitors with their respective semiconductor switching elements, whereby a plurality of transformation ratios can be set; and / or b) effectively connect at least one capacitor and / or coil into the transmission path, wherein one semiconductor switching element is arranged in series or parallel with each capacitor or coil. This allows the transformation ratio to be changed during operation in a very efficient manner.

[0059] In an advantageous embodiment, the third impedance matching unit comprises at least one coil and at least one capacitor, each embodied as a discrete component. The third impedance matching unit comprises an input, the output terminal, and a transmission path, wherein the transmission path electrically connects the input to the output terminal. The second intermediate impedance is present at the input. The at least one coil connects the transmission path to the reference ground.

[0060] In an advantageous embodiment, the at least one coil of the third impedance matching unit is connected to the input directly or via the at least one capacitor of the third impedance matching unit. Additionally or alternatively, the at least one coil of the third impedance matching unit is connected to the output terminal directly or via the at least one capacitor and / or another coil. Such a configuration has delivered very good results in practice. In an advantageous embodiment, the at least one semiconductor switching element can be cooled by a fluid. The fluid can be water, for example. This also includes distilled water.

[0061] The plasma processing system according to the invention comprises an impedance matching circuit as described above. Furthermore, the plasma processing system comprises an RF power supply and at least one load, in particular in the form of a plasma processing chamber. The RF power supply is connected to the input terminal of the impedance matching circuit. The output terminal of the impedance matching circuit is connected to the at least one load. The input impedance of the impedance matching circuit corresponds to the nominal impedance of the RF power supply. Therefore, matching is present, and no or only very little power is reflected back toward the RF power supply. Due to the dimensioning rule for the first intermediate impedance described above, the maximum permissible voltage and the maximum permissible current at the at least one semiconductor switching element are not exceeded.

[0062] In an advantageous embodiment, the plasma process system comprises a measuring unit arranged between the RF power supply and the impedance matching circuit. The measuring unit comprises a directional coupler or a sensor pair comprising a current sensor and a voltage sensor. A control and / or detection device is also provided, wherein the control and / or detection device is configured to receive measured values, such as power transmitted into the impedance matching circuit, from the measuring unit. Additionally or alternatively, power reflected by the impedance matching circuit can also be received by the measuring unit. These measured values ​​describe input variables present at the input terminal of the impedance matching circuit.The control and / or detection device is designed to control the at least one semiconductor switching element based on the measured values ​​in such a way that the plasma is generated in the plasma process chamber in the desired form.

[0063] The invention is described below purely by way of example with reference to the drawings. They show:

[0064] Figure 1: an embodiment of the plasma process system according to the invention with an impedance matching circuit according to the invention;

[0065] Figures 2A, 2B: various embodiments of how a first impedance matching unit of the impedance matching circuit can be constructed;

[0066] Figures 3A, 3B, 3C, 3D, 3E and 3F: various embodiments of how a second impedance matching unit of the impedance matching circuit can be constructed;

[0067] Figures 4A, 4B, 4C, 4D, 4E: various embodiments of how a third impedance matching unit of the impedance matching circuit can be constructed;

[0068] Figure 5: an embodiment of a plasma process supply system; and

[0069] Figure 6 shows part of a measuring unit of a plasma process system. Figure 1 shows a plasma process system 100, which comprises an impedance matching circuit 1. The plasma process system 100 further comprises an RF power supply 101 and at least one consumer 102 in the form of a plasma process chamber. The RF power supply 101 is designed to provide an RF signal, in particular in the form of a uniform signal, also called a continuous wave signal, or CW signal for short, with a nominal power PNom. The impedance matching circuit 1 comprises an input terminal 2, wherein the RF power supply 101 is connected to the input terminal 2. The impedance matching circuit 1 further comprises an output terminal 3. The output terminal 3 is connected to the at least one consumer 102. The RF power supply 101 is preferably connected to the impedance matching circuit 1 via a first cable arrangement 4.The impedance matching circuit 1 is preferably connected to the load 102 via a second cable arrangement 5. The first and / or second cable arrangement 4, 5 can comprise one or more cables, for example, connected in series and / or in parallel. Coaxial cables are preferably used.

[0070] The consumer 102, i.e. the plasma process chamber, comprises at least one electrode 103 for generating a plasma 104. The electrode 103 is connected, in particular galvanically, to the output terminal 3 of the impedance matching circuit 1.

[0071] The plasma process system 100 further comprises a control and / or detection device 105. This can preferably comprise a processor and / or a programmable logic component, in particular an FPGA and / or microcontroller and / or a preconfigured logic component, in particular an ASIC. The control and / or detection device 105 can also comprise a memory unit. The control and / or detection device 105 is designed to control the RF power supply 101, in particular to activate or deactivate it. Additionally or alternatively, the control and / or detection device 105 is also designed to change the power and / or frequency of the RF signal. Additionally or alternatively, the control and / or detection device 105 is designed to change the waveform of the RF signal, in particular the type of the RF signal or modulation of the RF signal.

[0072] The control and / or detection device 105 is preferably also designed to control the impedance matching circuit 1. In particular, the control and / or detection device 105 is designed to change the transformation ratio within the impedance matching circuit 1.

[0073] The plasma process system 100 preferably also comprises a measuring unit 106. The measuring unit 106 is arranged between the RF power supply 101 and the impedance matching circuit 1. The measuring unit 106 can, for example, comprise at least one directional coupler or a combination of a current sensor and a voltage sensor. Using the at least one directional coupler, the measuring unit 106 can measure the power of the RF signal transmitted from the RF power supply 101 toward the impedance matching circuit 1. Preferably, the measuring unit 106 can also measure the power of an RF signal reflected back toward the RF power supply 101 by the impedance matching circuit 1. The power of the RF signal transmitted from the RF power supply 101 toward the impedance matching circuit 1 can also be determined using the combination of a current sensor and a voltage sensor.A power of an RF signal reflected by the impedance matching circuit 1 can also be detected by the current sensor and / or the voltage sensor.

[0074] The plasma process system 100 preferably also comprises an operating unit

[0075] 107. The operating unit 107 preferably has a screen, in particular a touch-sensitive screen. In addition to a screen, the operating unit 107 can also include input means such as a keyboard and / or mouse. The operating unit 107 can also be a web server that provides data and receives user input. The control and / or detection device 105 is designed to display current settings of the RF power supply 101 and / or the impedance matching circuit 1 on the operating unit 107. The control and / or detection device 105 can also be designed to display the measured values ​​received by the measuring unit 106 on the operating unit 107.The control and / or detection device 105 is preferably designed to receive setpoint specifications, for example for the power of the RF signal, the frequency of the RF signal and / or the waveform of the RF signal, from the operating unit 107 and to generate corresponding manipulated variables for the RF power supply 101 and to transmit them to the latter.

[0076] Before explaining the impedance matching circuit 1 according to the invention in detail, reference is made to Figures 5 and 6, each of which describes a measuring unit 106. This can be the same measuring unit in two different views. In these exemplary embodiments, the measuring unit 106 is designed to measure a voltage and a current without contact. For this purpose, the measuring unit 106 comprises a current sensor 110 and a voltage sensor 111.

[0077] However, the phase relationship between current and voltage is preferably determined and / or measured.

[0078] The current sensor 110 of the measuring unit 106 is a coil, in particular in the form of a Rogowski coil. Both ends of the coil are preferably connected to each other via a shunt resistor 112. The voltage drop across the shunt resistor 112 can be digitized using a first A / D converter 113.

[0079] The voltage sensor 111 of the measuring unit 106 is preferably designed as a capacitive voltage divider. A first capacitance 114 is formed by an electrically conductive ring 114. An electrically conductive cylinder could also be used. The first cable arrangement 4 is routed through this electrically conductive ring 114. A second capacitance 115 of the voltage sensor 111, which is designed as a voltage divider, is connected to the reference ground. Connected in parallel to the second capacitance 115 is a second A / D converter 116, which is designed to detect and digitize the voltage drop across the second capacitance 115.

[0080] In principle, the measuring unit 106 can also be arranged or constructed on a (common) printed circuit board. The first capacitor 114 can be formed by a coating on a first and an opposite second side of the printed circuit board. In this case, the coatings on the first and second sides are electrically connected to one another by vias. The first cable arrangement 4 is guided through an opening in the printed circuit board. The second capacitor 115 can be formed by a discrete component.

[0081] The current sensor 110 in the form of a coil, in particular in the form of a Rogowski coil, is spaced further from the first cable arrangement 4 than the first capacitor 114. The coil can also be formed on the same circuit board by appropriate coatings and vias. The coil for current measurement and the first capacitor for voltage measurement preferably run through a common plane. The shunt resistor 112 can also be arranged on this circuit board. The same applies to the first and / or second A / D converters 113, 116. The first and / or second A / D converters 113, 116 are read and / or controlled by the control and / or detection device 105.

[0082] The control and / or detection device 105 is preferably designed to control the impedance matching circuit 1 based on the measured values ​​of the measuring unit 106.

[0083] Referring again to Figure 1 below, the structure of the impedance matching circuit 1 is explained in more detail. The impedance matching circuit 1 comprises a first impedance matching unit 6, a second impedance matching unit 7, and a third impedance matching unit 8. The first impedance matching unit 6 is electrically connected to the input terminal 2.

[0084] The first impedance matching unit 6 is designed to transform an input impedance Zo, which is present at the input terminal 2, into a first intermediate impedance Zi. The first intermediate impedance Zi is present at an output 9 of the first impedance matching unit 6. The transformation ratio is unchangeable during operation. The second impedance matching unit 7 is connected to the first impedance matching unit 6 in the transmission direction of the RF signal from the RF power supply 101 to the load 102. In particular, the second impedance matching unit 7 comprises an input 10, which is connected to the output 9 of the first impedance matching unit 6 or which is identical to the output 9. The first intermediate impedance Zi is therefore also present at the input 10.The second impedance matching unit 7 is designed to transform the first intermediate impedance Zi at its input 10 to a second intermediate impedance Zz at its output 11, wherein the transformation ratio can be changed during operation by at least one semiconductor switching element 12. The third impedance matching unit 8 is connected to the second impedance matching unit 7 in the transmission direction of the RF signal from the RF power supply 101 to the load 102. In particular, the third impedance matching unit 8 comprises an input 13 which is connected to the output 11 of the second impedance matching unit 7 or which is identical to the output 11. The second intermediate impedance Z2 is therefore also present at the input 13. The third impedance matching unit 8 is designed to transform the second intermediate impedance Z2 at its input 13 to an output impedance Zp at its output 14.The transformation ratio can be fixed or variable during operation. The output 14 of the third impedance matching unit 8 is electrically connected to the output terminal 3 of the impedance matching circuit 1. This also includes the possibility that the output 14 of the third impedance matching unit 8 is identical to the output terminal 3 of the impedance matching circuit 1.

[0085] The second impedance matching unit 7 has at least one semiconductor switching element 12, as shown in Figures 3A to 3F and explained in more detail later. This at least one semiconductor switching element 12 of the second impedance matching unit 7 can be operated up to a maximum permissible voltage and up to a maximum permissible current.The first intermediate impedance Zi, to which the first impedance matching unit 6 transforms the input impedance Zo, is selected for a predetermined target input impedance such that: a) the conductance of the first intermediate impedance Zi is greater than the conductance of the impedance that would occur at the input 10 of the second impedance matching unit 7 at the rated power PNenn of the impedance matching circuit 1 and the maximum permissible voltage of the at least one semiconductor switching element 12; and b) the resistance of the first intermediate impedance Zi is greater than the resistance of the impedance that would occur at the input 10 of the second impedance matching unit 7 at the rated power PNenn and the maximum permissible current of the at least one semiconductor switching element 12.

[0086] The rated power PNom of the impedance matching circuit 1 is preferably identical to the rated power PNom of the RF power supply 101.

[0087] A transmission path for transmitting the RF signal runs between the input terminal 2 and the output terminal 3 of the impedance matching circuit 1. The first, second, and third impedance matching units 6, 7, 8 are arranged in the transmission path.

[0088] In the following figures, a possible structure of the first, second and third impedance matching units 6, 7, 8 of the impedance matching circuit 1 is explained in more detail.

[0089] Figures 2A and 2B describe a possible structure of the first impedance matching unit 6. The first impedance matching unit 6 has a transformation ratio that is constant and thus unchangeable during operation.

[0090] In Figure 2A, the first impedance matching unit 6 comprises a coil 15 and a first capacitor 16. These are preferably designed as discrete components. The coil 15 connects the input terminal 2 to a reference ground. The first capacitor 16 connects the input terminal 2 to the output 9 of the first impedance matching unit 6. The first intermediate impedance Zi is also present at this output.

[0091] In Figure 2B, the first impedance matching unit 6 also includes a second capacitor 17. In contrast to Figure 2A, the second capacitor 17 from Figure 2B also connects the output 9 of the first impedance matching unit 6 to the reference ground.

[0092] Figures 3A, 3B, 3C, 3D, 3E, 3F describe a possible structure of the second impedance matching unit 7.

[0093] In Figure 3A, the second impedance matching unit 7 comprises a first capacitance 20, a second capacitance 21, a first coil 18, and a semiconductor switching element 12. The first coil 18 connects the input 10 of the second impedance matching unit 7 to the output 11 of the second impedance matching unit 7. The first capacitance 20 and the second capacitance 21 are connected in series, with the first capacitance 20 being connected to the input 10 and the second capacitance 21 being connected to the reference ground. The semiconductor switching element 12 is arranged in parallel with the second capacitance 21. The semiconductor switching element 12 is preferably a transistor. If the semiconductor switching element 12 is conductive, the second capacitance 21 is inactive. The second capacitance 21 is bridged. If the semiconductor switching element 12 is blocking, an electrically active series connection of the first capacitance 20 and the second capacitance 21 is present.

[0094] In Figure 3B, the second impedance matching unit 7 comprises a first capacitance 20, a second capacitance 21, and a semiconductor switching element 12. The first capacitance 20 is connected to the output 11 of the second impedance matching unit 7. A parallel circuit comprising the second capacitance 21 and the semiconductor switching element 12 is arranged in series with the first capacitance 20. This parallel circuit is also connected to the input 10 of the second impedance matching unit 7. If the semiconductor switching element 12 is conductive, only the first capacitance 20 is active between the input 10 and the output 11. The second capacitance 21 is bridged by the semiconductor switching element 12. If the semiconductor switching element 12 is blocking, the second capacitance 21 is electrically active, and a series circuit comprising the first capacitance 20 and the second capacitance 21 is formed between the input 10 and the output 11.

[0095] Figure 3C shows a combination of the embodiments from Figures 3A and 3B. A first, second, third, and fourth capacitor 20, 21, 22, 23 are provided. Furthermore, two semiconductor switching elements 12 and a first coil 18 are provided. The input 10 is connected to the reference ground via a series circuit. The series circuit comprises the following elements: a) the first capacitor 20; b) a parallel circuit comprising the second capacitor 21 and the semiconductor switching element 12.

[0096] The input 10 is connected to the output 11 via another series circuit. The other series circuit comprises the following elements: a) the first coil 18; b) a parallel circuit consisting of the fourth capacitor 23 and the semiconductor switching element 12; c) the third capacitor 22.

[0097] Figure 3D shows a further exemplary embodiment which is based on the exemplary embodiment in Figure 3A. A first, second, third and fourth capacitance 20, 21, 22, 23 are provided. Furthermore, three semiconductor switching elements 12 and a first coil 18 are provided. The first coil 18 connects the input 10 to the output 11. The input 10 is further connected to the reference ground via a series circuit. The series circuit comprises the following elements: a) the first capacitance 20; b) a parallel circuit which comprises three further series circuits, wherein the first further series circuit comprises the second capacitance 21 and a semiconductor switching element 12, wherein the second further series circuit comprises the third capacitance 22 and a semiconductor switching element 12, and wherein the third further series circuit comprises the fourth capacitance 23 and a semiconductor switching element 12.

[0098] If all three semiconductor switching elements 12 were off, the first capacitor 20 would not be connected to the reference ground. Each semiconductor switching element 12 that is conducting connects the first capacitor 20 to the reference ground via its second, third, or fourth capacitor 21, 22, 23, respectively.

[0099] Figure 3E shows a further embodiment based on the embodiment of Figure 3D. A first, second, third and fourth capacitor 20, 21, 22, 23 is provided. Furthermore, three semiconductor switching elements 12, a first coil 18 and a second coil 19 are provided. The first coil 18 connects the input 10 to the output 11. A series circuit comprising the second coil 19 and a semiconductor switching element 12 is arranged parallel to the first coil 18. If the semiconductor switching element 12 is conducting, the second coil is electrically connected in parallel to the first coil 18. In this case, the input 10 is connected to the output 11 via the parallel circuit comprising the first and second coils 18, 19. If the semiconductor switching element 12 is blocking, no current flows through the second coil 19. The input 10 is connected to the output 11 only via the first coil 18.The input 10 is further connected to the reference ground via a series circuit. The series circuit comprises the following elements: a) the first capacitor 20; b) a parallel circuit comprising three further series circuits, wherein the first further series circuit comprises the second capacitor 21 and a semiconductor switching element 12, wherein the second further series circuit comprises the third capacitor 22 and a semiconductor switching element 12, and wherein the third further series circuit comprises the fourth capacitor 23 and a semiconductor switching element 12.

[0100] If all three semiconductor switching elements 12 were off, the first capacitor 20 would not be connected to the reference ground. Each semiconductor switching element 12 that is conducting connects the first capacitor 20 to the reference ground via its second, third, or fourth capacitor 21, 22, 23, respectively.

[0101] In Figures 3A, 3B, 3C, 3D, and 3E, the semiconductor switching elements 12 can be configured as transistors. Figure 3F corresponds structurally to the embodiment in Figure 3D. In contrast to Figure 3D, the semiconductor switching element 12 is configured as a diode arrangement. The cathode side of each diode is connected to the reference ground. A DC voltage can be applied to the anode side of each diode 12, causing the respective diode to become conductive. The DC voltage can be applied individually to each diode. This allows the diodes to be switched separately. The diodes are preferably PIN diodes.

[0102] The semiconductor switching elements 12 in Figures 3A to 3F may also comprise a mixture of transistors and diodes.

[0103] The control signal, in particular the DC voltage, for the semiconductor switching element 12 in the form of a transistor and / or a diode, can be generated by the control and / or detection device 105.

[0104] Figures 4A, 4B, 4C, 4D, 4E, 4F describe a possible structure of the third impedance matching unit 8.

[0105] In Figure 4A, the third impedance matching unit 8 comprises a first capacitance 27 and a first coil 24. The first capacitance 27 and the first coil 24 are arranged in an L-circuit with each other. The first coil 24 connects the input 13 of the third impedance matching unit 8 to a reference ground. The first capacitance 27 connects the input 13 to the output 14. The output 14 of the third impedance matching unit 8 can be directly connected to the output terminal 3 of the impedance matching circuit 1. In Figure 4B, the third impedance matching unit 8 comprises a first capacitance 27, a second capacitance 28, and a first coil 24. The first capacitance 27, the second capacitance 28, and the coil 24 are arranged in a T-circuit with each other. The input 13 is connected to the output 14 via the first and second capacitances 27, 28, which are connected in series.The first coil 24, which establishes a connection to the reference ground, is arranged between the first capacitor 27 and the second capacitor 28. In this case, the input 13 is connected to the reference ground via the first capacitor 27 and the first coil 24. The output 14 is connected to the reference ground via the second capacitor 28 and the first coil 24.

[0106] In Figure 4C, the third impedance matching unit 8 comprises a first capacitor 27, a second capacitor 28, and a first coil 24. The first capacitor 27, the second capacitor 28, and the coil 24 are arranged in a PI circuit. The input 13 is connected to the reference ground via the first coil 24. The input 13 is also connected to the output 14 via the first capacitor 27. The output 14 is connected to the reference ground via the second capacitor 28.

[0107] In Figures 4A, 4B, and 4C, the transformation ratio of the third impedance matching unit 8 is fixed during operation. To change the transformation ratio, the corresponding capacitances 27, 28 or the first coil 24 would have to be replaced with different capacitances or with a different first coil with different values.

[0108] In Figure 4D, the third impedance matching unit 8 comprises a first capacitance 27, a second capacitance 28, a first coil 24, and a second coil 25. The input 13 is connected to the reference ground via a series circuit comprising the first coil 24 and the first capacitance 27. In this case, the first capacitance 27 is variable, in particular its height is adjustable by a motor. The input 13 is also connected to the output 14 via a series circuit comprising the second coil 25 and the second capacitance 28. In this case, the second capacitance 28 is variable, in particular its height is adjustable by a motor. In principle, only one of the two capacitances 27, 28 could be variable.

[0109] In Figure 4E, the third impedance matching unit 8 comprises a first capacitance 27, a second capacitance 28, a first coil 24, and a second coil 25. The input 13 is connected to the reference ground via a series circuit comprising the first capacitance 27 and first coil 24. The input 13 is also connected to the output 14 via a series circuit comprising the first capacitance 27, the second coil 25, and the second capacitance 28. In this case, the first capacitance 27, the second coil 25, and the second capacitance 28 are arranged in the signal transmission path between the input 13 and the output 14. The output 14 is therefore connected to the reference ground via a series circuit comprising the second capacitance 28, the second coil 25, and the first coil 24. The first capacitance 27 is variable in this case, in particular its height can be adjusted by a motor.In this case, the second capacity 28 is also variable, specifically its height is motor-adjustable. In principle, only one of the two capacities 27 and 28 could be variable.

[0110] Such a typical impedance matching circuit 1 is described, for example, in patent application DE 10 2023 104 942.9, filed on February 28, 2023, entitled "Impedance matching circuit, plasma process supply system, and plasma process system," which is hereby fully incorporated by reference into the present application. In particular, the further impedance matching circuit (1) described in the cited application can further develop the present impedance matching circuit 1 with some or all of its features. Such a typical plasma process system 9 is described, for example, in patent application DE 10 2023 104 948.8, filed on February 28, 2023, entitled "Impedance matching circuit, plasma process supply system, and plasma process system," which is hereby fully incorporated by reference into the present application.In particular, the second impedance matching unit (7, 7a - 7f) described in the cited application can be an advantageous embodiment of the second impedance matching unit 7 described here. With the features described above, the number of components, for example, semiconductor switching elements or reactances, e.g., coils and / or capacitors, as well as capacitances and / or inductances, can be kept lower, thus achieving an even more compact design.

[0111] The invention is not limited to the described embodiments. Within the scope of the invention, all described and / or illustrated features can be combined with one another in any way.

Claims

Claims 1. Impedance matching circuit (1) for a plasma process system (100), for powers > 500 W and frequencies in the range from 2 MHz to 100 MHz, wherein the impedance matching circuit (1) is designed for a predetermined nominal power (PNom), having the following features: - an input terminal (2) is provided which is designed to electrically connect the impedance matching circuit (1) to an RF power supply (101); - an output terminal (3) is provided which is designed to electrically connect the impedance matching circuit (1) to a consumer (102), in particular in the form of a plasma process chamber; - the impedance matching circuit (1) comprises a first impedance matching unit (6) which is electrically connected to the input terminal (2) and which is designed to transform an input impedance (Zo) at the input terminal (2) to a first intermediate impedance (Zi), wherein the transformation ratio is invariable during operation; - the impedance matching circuit (1) comprises a second impedance matching unit (7) with at least one semiconductor switching element (12), which is electrically connected at its input (10) to the first impedance matching unit (6) and which is designed to transform the first intermediate impedance (Zi) at its input (10) to a second intermediate impedance (Z2) at its output (11), wherein the transformation ratio can be changed during operation by the at least one semiconductor switching element (12); - the impedance matching circuit (1) comprises a third impedance matching unit (8) which is electrically connected to the output (11) of the second impedance matching unit (7) and which is electrically connected with its output (14) to the output terminal (3) and which is designed to transform the second intermediate impedance (Z2) at its input (13) to an output impedance (Zp) at the output terminal (3); - the at least one semiconductor switching element (12) of the second impedance matching unit (7) is operable up to a maximum permissible voltage and a maximum permissible current; - the first intermediate impedance (Zi), to which the first impedance matching unit (6) transforms the input impedance (Zo), is selected for a predetermined target input impedance such that: a) the conductance of the first intermediate impedance (Zi) is greater than the conductance of the impedance that would occur at the input (10) of the second impedance matching unit (7) at the rated power (PNenn) of the impedance matching circuit (1) and the maximum permissible voltage of the at least one semiconductor switching element (12); and b) the resistance of the first intermediate impedance (Zi) is greater than the resistance of the impedance that would occur at the input (10) of the second impedance matching unit (7) at the rated power (PNenn) of the impedance matching circuit (1) and the maximum permissible current of the at least one semiconductor switching element (12).

2. Impedance matching circuit (1) according to claim 1, characterized by the following feature: - the first intermediate impedance (Zi) is chosen such that: Gl > PNom / Umax 2 , with Gi = conductance of the first intermediate impedance (Zi); PNom = rated power of the impedance matching circuit (1); Umax = maximum voltage at the at least one semiconductor switching element (12); and R.1 > PNom / Imax 2 , with Ri = resistance of the first intermediate impedance (Zi); PNom = rated power of the impedance matching circuit (1); Imax = maximum current at the at least one semiconductor switching element (12).

3. Impedance matching circuit (1) according to claim 1 or 2, characterized by the following feature: - the input impedance (Zo) is substantially constant and equal to the specified target input impedance during operation of the impedance matching circuit (1).

4. Impedance matching circuit (1) according to one of the preceding claims, characterized by the following features: - the first intermediate impedance (Zi) is closer to the output impedance (Zp) than to the input impedance (Zo) on the Smith chart; and / or - the second intermediate impedance (Z2) is closer to the output impedance (Zp) on the Smith chart than to the first intermediate impedance (Zi).

5. Impedance matching circuit (1) according to one of the preceding claims, characterized by the following feature: - the at least one semiconductor switching element (12) of the second impedance matching unit (7) is a transistor or a diode.

6. Impedance matching circuit (1) according to one of the preceding claims, characterized by the following feature: - the output impedance (Zp) can be determined by the consumer (102), in particular in the form of the plasma process chamber, and can be changed during operation, wherein the output impedance (Zp) is in a certain range on the Smith chart and wherein the at least one semiconductor switching element (12) assumes different switching positions for those points of the output impedance (Zp) which are furthest apart in the Smith chart in the certain range.

7. Impedance matching circuit (1) according to one of the preceding claims, characterized by the following feature: - a transformation ratio of the third impedance matching unit (8) is unchangeable during operation.

8. Impedance matching circuit (1) according to one of claims 1 to 6, characterized by the following feature: - the third impedance matching unit (8) comprises at least one motor-adjustable capacitance (27, 28), whereby the transformation ratio of the third impedance matching unit (8) can be changed during operation.

9. Impedance matching circuit (1) according to claim 8, characterized by the following feature: - the second intermediate impedance (Z2) to which the second impedance matching unit (7) transforms the first intermediate impedance (Zi) is selected such that: a) the conductance of the second intermediate impedance (Z2) is greater than the conductance of the impedance that would be set at the rated power (PNenn) of the impedance matching circuit (1) and the maximum voltage at the at least one motor-adjustable capacitance (27, 28); and b) the resistance of the second intermediate impedance (Z2) is greater than the resistance of the impedance that would be set at the rated power (PNenn) of the impedance matching circuit (1) and the maximum current at the at least one motor-adjustable capacitance (27, 28).

10. Impedance matching circuit (1) according to claim 9, characterized by the following feature: - the second intermediate impedance (Z2) is selected such that: G2 > PNenn / Umax 2 , with G2 = conductance of the second intermediate impedance (Z2); PNom = rated power of the impedance matching circuit (1); Umax = maximum voltage at the at least one motor-adjustable capacitor (27, 28); and R.2 > PNom / Imax 2 , with R.2 = resistance of the second intermediate impedance (Z2); PNom = rated power of the impedance matching circuit (1); Imax = maximum current at at least one motor-adjustable capacitor (27, 28).

11. Impedance matching circuit (1) according to one of the preceding claims, characterized by the following feature: - the third impedance matching unit (8) is free of a semiconductor switching element (12).

12. Impedance matching circuit (1) according to one of the preceding claims, characterized by the following features: - the first impedance matching unit (6) comprises at least one output (9), one coil (15) and at least one first capacitor (16), each of which is designed as a discrete component; - the at least one coil (15) connects the input terminal (2) to a reference ground; - the at least one first capacitor (16) connects the input terminal (2) of the impedance matching circuit (1) to the output (9), where the first intermediate impedance (Zi) is present.

13. Impedance matching circuit (1) according to claim 11, characterized by the following features: - the first impedance matching unit (6) comprises at least one second capacitor (17) which is designed as a discrete component; - the at least one second capacitor (17) connects the output (9) of the first impedance matching unit (6) to the reference ground.

14. Impedance matching circuit (1) according to one of the preceding claims, characterized by the following features: - the second impedance matching unit (7) comprises at least one coil (18), at least one first capacitor (20) and at least one further capacitor (23), each of which is designed as a discrete component; - the first intermediate impedance (Zi) is present at an input (10) of the second impedance matching unit (7) and the second intermediate impedance (Z2) is present at an output (11) of the second impedance matching unit (7); - the at least one coil (18) is arranged in a transmission path connecting the input (10) to the output (11); - the at least one semiconductor switching element (12) is designed to: a) effectively electrically connect the transmission path to a reference ground via the at least one first capacitor (20); and / or b) effectively connect the at least one further capacitor (23) in series into the transmission path.

15. Impedance matching circuit (1) according to claim 14, characterized by the following features: - the second impedance matching unit (7) comprises a plurality of semiconductor switching elements (12) and a plurality of capacitors (21, 22, 23); - the plurality of semiconductor switching elements (12) are designed to: a) electrically connect the transmission path to a reference ground via each of the capacitors (21, 22, 23), wherein one semiconductor switching element (12) is arranged in series with each capacitor (21, 22, 23), and wherein each capacitor (21, 22, 23) is arranged with its respective semiconductor switching element (12) in parallel with the other capacitors (21, 22, 23) with their respective semiconductor switching elements (12), whereby a plurality of transformation ratios can be set; and / or b) effectively connect at least one capacitor (23) and / or a coil (19) into the transmission path, wherein one semiconductor switching element (12) is arranged in series or parallel with the at least one capacitor (23) or coil (19), whereby a plurality of transformation ratios can be set.

16. Impedance matching circuit (1) according to one of the preceding claims, characterized by the following features: - the third impedance matching unit (8) comprises at least one coil (24, 25) and at least one capacitor (27, 28), each of which is designed as a discrete component; - the third impedance matching unit (8) comprises an input (13), the output terminal (3) and a transmission path, wherein the transmission path electrically connects the input (13) to the output terminal (3); - the second intermediate impedance (Z2) is present at the input (13); the at least one coil (24) connects the transmission path to a reference ground.

17. Impedance matching circuit (1) according to claim 16, characterized by the following features: - the at least one coil (24) is connected to the input (13) directly or via the at least one capacitor (27); and / or - the at least one coil (24) is connected to the output terminal (3) directly or via the at least one capacitor (28) and / or a coil (25).

18. Impedance matching circuit (1) according to one of the preceding claims, characterized by the following feature: - the at least one semiconductor switching element (12) can be cooled by a fluid.

19. Plasma process system (100) with the impedance matching circuit (1) according to one of the preceding claims, characterized by the following features: - an RF power supply (101) and at least one consumer (102) in the form of a plasma process chamber are provided, wherein the RF power supply (101) is designed to provide an RF signal with the nominal power (PNom); - the RF power supply (101) is connected to the input terminal (2) of the impedance matching circuit (1); - the output terminal (3) of the impedance matching circuit (1) is connected to the at least one consumer (102).

20. Plasma processing system (100) according to claim 19, characterized by the following features: - a measuring unit (106) is provided and arranged between the RF power supply (101) and the impedance matching circuit (1); - the measuring unit (106) comprises at least one directional coupler or a combination of current sensor (110) and voltage sensor (St.); - a control and / or detection device (105) is provided, wherein the control and / or detection device (105) is designed to receive measured values, such as a power transmitted into the impedance matching circuit (1), from the measuring unit (106), which describe input variables present at the input terminal of the impedance matching circuit (1); - the control and / or detection device (105) is designed to control the at least one semiconductor switching element (12) on the basis of the measured values ​​in such a way that the desired plasma is generated.