CIRCUIT ARRANGEMENT FOR LIMITING THE GATE CURRENT AT A FIELD EFFECT TRANSISTOR

Description

Description

[0001] The present invention relates to an amplifier circuit with a circuit arrangement for limiting the gate current at a field-effect transistor, in particular an analog amplifier circuit with a circuit arrangement for limiting the gate current at a GaN or GaAs RF power HEMT. State of the art

[0002] The development of electronics capable of delivering higher frequencies and power levels in smaller dimensions presents a particular challenge in the microwave range due to the prevailing physical laws. Higher transmission frequencies in telecommunications enable greater bandwidth and faster data transmission (e.g., 5G), as well as finer temporal and spatial resolution for radar applications in both civilian and military fields. A significant contribution to the current state of the art is owed to the High Electron Mobility Transistor (HEMT), also known as the Heterojunction Field-Effect Transistor (HFET), Two-Dimensional Electron-Gas Field-Effect Transistor (TEGFET), Modulation-Doped Field-Effect Transistor (MODFET), or simply Field-Effect Transistor (FET).This special field-effect transistor utilizes two heterogeneous semiconductor materials with different band gaps to provide a quasi-two-dimensional channel filled with electrons at the interface. High electron mobilities can be achieved in this undoped region, also known as 2-DEG ("two-dimensional electron gas"), which enables the high operating frequencies attainable with this technology.

[0003] The most widely used HEMT is based on gallium arsenide (GaAs) technology, which, however, is being replaced in many areas by the emerging gallium nitride (GaN) technology. Due to the higher bandgap and current-carrying capacity of GaN, significantly higher power levels can be achieved without any significant disadvantages in other electrical parameters such as noise figure. This allows transceivers consisting of a low-noise amplifier (LNA) to be monolithically integrated onto a single chip, thus saving costs and reducing the complexity and size of the component.

[0004] In general, a low-noise amplifier is optimized to amplify weak RF signals (signals in the high-frequency (HF) range from 9 kHz to approximately 30 GHz) with as little noise as possible. However, even here, high power levels can occur at the input, even at frequencies outside the actual receiving frequency, for example, due to unwanted coupling, reflections from the power amplifier, or strong interference signals (jammers). These can temporarily or permanently impair the receiver's functionality.

[0005] To protect the sensitive and critical component, conventional GaAs LNAs use limiter diodes (diodes, Zener diodes) as limiting switches at the input. However, these cannot be monolithically integrated and require a second chip. GaN HEMTs, on the other hand, do not necessarily rely on external limiting circuitry, as their high breakdown voltage allows them to tolerate significantly higher power levels. These are typically in the range of 10 W. However, values ​​up to 30 W can be achieved if a high-impedance resistor is used at the gate (M. Rudolph et al., "Robust Stacked GaN-Based Low-Noise Amplifier MMIC for Receiver Applications", IEEE Trans. Microwave Theory Tech., Vol. 1, No. 55, pp. 37-43, Jan 2007).In case of overload, the gate current is limited by this series resistance; however, the resulting voltage drop across it causes a shift in the operating point of the transistor into a deep Class C operation with simultaneously increasing negative gate voltages.

[0006] At high input powers, the voltage amplitudes at the transistor's input are so large that a gate current develops. This gate current has a particularly detrimental effect on the robustness and lifespan of the transistor (M. Broasa et al. "Correlation of gate leakage and strain distribution in GaN / AIGaN HEMT structures", in 27th European Symposium on Reliability of Electron Devices, failure physics and analysis (ESREF), Halle (Saale), Germany, 2016). The gate current is typically reduced by the aforementioned high-resistance component in the gate supply network.

[0007] The voltage drop across the resistor caused by the flowing current is polarized in such a way that more negative voltages are established at the gate. These, in turn, drive the transistor further into pinch-off mode, thus protecting it from high gate currents at the cost of increased negative reverse voltages (GB 2 165 114 A). However, this method does not allow the gate current to be completely eliminated, but only reduced. Therefore, with increasing input power, the gate current continues to increase.

[0008] WO 2006 / 036060 A1 relates to an amplifier circuit and a circuit for providing a bias voltage at the gate terminal of a field-effect transistor (FET). WO 2017 / 027346 A1 relates generally to cascade amplifiers and, in particular, to DC bias regulators for cascade amplifiers. US 2016 / 0380600 A1 relates to high-power RF power amplifiers. A dynamic supply modulator suitable for converting DC current to RF power in RF transmitters, connected to the drain-bias terminal of an 8-wavelength band RF power amplifier, is known from the publication by Délias et al. ("A GaN-based supply modulator for energy efficiency enhancement of active phased-array antennas." 2014 International Workshop on Integrated Nonlinear Microwave and Millimetre-wave Circuits (INMMiC). IEEE, 2014). Disclosure of the invention

[0009] It is therefore an object of the present invention to provide an amplifier circuit with a circuit arrangement for limiting the gate current at a field-effect transistor, with the aid of which the forward current is effectively limited in the case of input-side overload. In particular, the forward current at the gate should also be limited and not increase further even at very high input powers.

[0010] These problems are solved according to the invention by the features of claim 1. Advantageous embodiments of the invention are contained in the respective dependent claims. Furthermore, a device for receiving microwave signals is proposed based thereon.

[0011] An amplifier circuit according to the invention, comprising a circuit arrangement for limiting the gate current of a field-effect transistor (FET) in the case of input-side overload, includes a first FET and a DC voltage supply network connected to a gate terminal of the first FET; wherein the supply network provides a voltage Vgg (gate voltage, also referred to as gate-ON voltage, auxiliary voltage, or gate bias voltage) at the gate terminal of the first FET via a first connection comprising a high-resistance resistor R1 and a second FET connected in series therewith with a gate terminal; wherein the second FET has an ON state at a gate-source voltage of 0 V and its gate terminal is also connected to the gate terminal of the first FET via a second connection; wherein the second connection provides a current path in parallel with the resistor R1;wherein a voltage drop across resistor R1 leads to an increasing blocking of the second FET, and an input power P to be amplified is fed into the first FET via a third connection connected to the gate terminal of the first FET. This can, in particular, be an analog LNA amplifier circuit.

[0012] High-impedance resistors are defined as those with several thousand ohms. Preferably, resistor R1 has a value between 1 kΩ and 10 MΩ, more preferably between 1 kΩ and 1 MΩ, more preferably between 1 kΩ and 100 kΩ, more preferably between 1 kΩ and 10 kΩ, and even more preferably between 5 kΩ and 10 kΩ. Smaller, high-impedance resistors in the supply network allow for shorter discharge and charge times (time constants) and thus contribute to a faster recovery of the first transistor after an overload scenario (the original bias of the supply point is restored more quickly). In principle, any type of field-effect transistor with an ON state at a gate-source voltage of 0 V is suitable for the proposed circuit. Preferably, the first and second connections are connected to the gate terminal of the first FET without any further switching elements.Sectionally, the first and second connections can also be implemented as a common connection. A connection is understood to be, in particular, an electrical conductor or, more generally, an electrical conductor or line for connecting electronic components. Preferably, the connection of the power supply network to the gate terminal of the first FET comprises no elements other than those named in this application as being according to the invention. Preferably, the first FET is based on GaN technology, which, due to its higher band gap and associated high blocking voltage, as well as its higher current-carrying capacity, can achieve significantly higher power outputs without exhibiting any significant disadvantages in other electrical parameters such as the noise figure. The FET is particularly preferably a HEMT.A circuit arrangement according to the invention is particularly suitable for constructing an analog LNA amplifier circuit with high input power.

[0013] The invention thus describes a modification in the DC supply network of a FET, with the aid of which the forward current in the input-side overload case is effectively limited by a current-dependent adaptive resistor control. The limiting circuit essentially consists of the second FET (normal-AN, depletion type) and the first resistor R1. The value of resistor R1, together with the threshold voltage of the second FET, determines the effectiveness of the circuit. A higher resistance leads to stronger overcurrent suppression, although this reduces the time constant of the supply network.

[0014] This is a simple feedback loop. However, the existing gate resistor is not used for current limiting as usual. Instead, a control voltage is generated via the voltage drop when the gate current flows. This control voltage then increasingly switches off the second FET connected in series (depletion mode, normal-ON). This can be compared to a variable resistor in the power supply network, whose value steadily increases with increasing gate current, thus effectively limiting the current, which is then largely independent of the RF input power applied to the first FET.

[0015] This arrangement has no negative impact on the small-signal behavior, the noise figure of an amplifier built with it, or the resulting reverse voltages. Simulations demonstrate that, with constant resistor values, a current reduction of approximately 20-fold is possible for high input power (44 dBm), and the current is effectively limited, with its magnitude determined by the selected resistance value of the first resistor R1 and the threshold voltage of the second FET. Furthermore, with consistent protection characteristics, it is possible to select a lower resistor, thereby reducing the time constant of the power supply network and thus achieving shorter recovery times for an LNA after an overload scenario.

[0016] A further advantage over diode-based gate current limiting circuits for analog amplifiers is that the maximum tolerable gate current can be freely selected and is determined by the resistance value of the first resistor R1 and the pinch-off voltage of the second FET. A circuit arrangement according to the invention is largely independent of the package type of the second FET used. It only needs to be capable of tolerating reverse voltages between drain and source, which also occur across the resistor in the supply network using the conventional method.

[0017] Preferably, a second high-impedance resistor R2 is arranged in the second connection for RF decoupling. Preferably, the resistance R2 has a value between 1 kΩ and 10 MΩ, more preferably between 1 kΩ and 1 MΩ, more preferably between 1 kΩ and 100 kΩ, and even more preferably between 1 kΩ and 10 kΩ.

[0018] Preferably, for RF decoupling, the first and second connections are connected to the gate terminal of the first FET via a common inductance L (acting as a choke). A connection via a common inductance means that, at least in one section, the first and second connections are also implemented as a common connection, with this section having an inductance L or comprising an inductive element with an inductance value L. The inductance L is considered an element of the power supply network. Its value depends, for example, on the operating frequency of the amplifier in an amplifier circuit. Preferably, the inductance L has a value between 1 nH and 10 mH, more preferably between 10 nH and 1 mH, and even more preferably between 10 nH and 100 µH.

[0019] Preferably, the first FET is a GaN or GaAs RF power HEMT. Due to its large bandgap and the resulting high breakdown voltage, GaN HEMT technology is characterized as a robust technology for the RF power range; however, forward currents, especially those occurring at high input powers, have proven particularly detrimental to its lifetime. In contrast, a circuit arrangement according to the invention is able to effectively limit this current. Furthermore, the small-signal and noise performance is not affected, so that particularly robust and interference-insensitive LNAs for the high-power range can be realized. However, a first FET based on GaAs HEMT technology can also be used in a circuit arrangement according to the invention, albeit with slight limitations.

[0020] Preferably, the first and second FETs are monolithically integrated on a single chip. This allows for the realization of particularly compact and robust LNAs and increases their frequency bandwidth. Furthermore, this simplifies the manufacturing of LNAs and reduces their assembly costs.

[0021] Alternatively, the first and second FETs can also be located on different chips. Although this generally results in higher manufacturing costs and losses, such a hybrid approach can achieve greater flexibility in the tuning of the individual circuit elements.

[0022] Preferably, the circuit arrangement does not include diodes or Zener diodes for limiting the gate current at the first FET. These are typically used as limiter diodes at the input of LNAs to protect this sensitive and important component. However, these cannot be monolithically integrated and require a second chip.

[0023] Another aspect of the invention relates to a device for receiving microwave signals, which includes an amplifier circuit according to the invention. These microwave signals can be, in particular, signals for data transmission (e.g., 5G) or for radar applications in both civilian and military fields of operation.

[0024] Further preferred embodiments of the invention result from the features mentioned in the dependent claims.

[0025] Unless otherwise stated in individual cases, the various embodiments of the invention mentioned in this application can be advantageously combined with one another. Brief description of the drawings

[0026] The invention is explained below using exemplary embodiments with reference to the accompanying drawing. The drawing shows: Fig. 1 a schematic representation of a conventional amplifier circuit with a circuit arrangement for limiting the gate current in an amplifier circuit, Fig. 2 a schematic representation of a first embodiment of an amplifier circuit according to the invention with a circuit arrangement for limiting the gate current in an amplifier circuit, Fig. 3 a schematic representation of a second embodiment of an amplifier circuit according to the invention with a circuit arrangement for limiting the gate current in an amplifier circuit, Fig. 4 a schematic representation of a third embodiment of an amplifier circuit according to the invention with a circuit arrangement for limiting the gate current in an amplifier circuit, and Fig. 5 various characteristic curves for comparing a conventional current limiter circuit and a current limiter circuit according to the invention. Detailed description of the drawings

[0027] Fig. 1Figure 1 shows a schematic representation of a conventional amplifier circuit with a circuit arrangement for limiting the gate current. This circuit comprises a FET 10 whose gate current is to be limited and a DC supply network 20 connected to a gate terminal 12 of the FET 10. The supply network 20 provides a voltage Vgg at the gate terminal 12 of the FET 10 via a connection 22, which includes a high-value resistor R220. A voltage drop across resistor R220 leads to a progressive reduction of the gate current at the FET 10. In the exemplary amplifier circuit shown, an input power Pin to be amplified is fed into the first FET 10 via a third connection 30, which is connected to the gate terminal 12 of the first FET 10.

[0028] At high input powers Pin, the voltage amplitudes at the input of FET 10 are so large that a forward current develops at the gate terminal 12. This has a particularly detrimental effect on the robustness and lifespan of FET 10 and is reduced by the high-value resistor R220 in the supply network 20. The voltage drop across resistor R220 due to the current flow is polarized such that more negative voltages develop at the gate terminal 12. These negative voltages, in turn, drive FET 10 further into pinch-off mode, thus protecting it from high gate currents at the cost of increased negative reverse voltages. However, this method does not allow the gate current to be regulated, only reduced. Therefore, with increasing input powers Pin, the forward current at the gate terminal 12 continues to increase.

[0029] Fig. 2Figure 1 shows a schematic representation of a first embodiment of an amplifier circuit according to the invention with a circuit arrangement for limiting the gate current in an amplifier circuit.This comprises a first FET 10, the gate current of which is to be limited, and a DC voltage supply network 20 connected to a gate terminal 12 of the first FET 10; wherein the supply network 20 provides a voltage V gg at the gate terminal 12 of the first FET 10 via a first connection 22, which includes a high-resistance resistor R 1 220 and a second FET 222 connected in series with it, having a gate terminal 224; wherein the second FET 222 has an ON state at a gate-source voltage of 0 V and its gate terminal 224 is also connected to the gate terminal 12 of the first FET 10 via a second connection 24 in parallel with the resistor R 1 220; wherein a voltage drop occurring across the resistor R 1 220 leads to an increasing blocking of the second FET 222.In the exemplary amplifier circuit according to the invention, an input power P to be amplified is fed into the first FET 10 via a third connection 30, which is connected to the gate terminal 12 of the first FET 10.

[0030] A control voltage is generated across the first resistor R1220 when the gate current is flowing. This control voltage increasingly switches off the series-connected FET (depletion mode, normal-ON). This can be compared to a variable resistor in the power supply network, whose value increases steadily with increasing gate current, thus effectively limiting the current, which is largely independent of the input power Pin. The first FET 10 can be, in particular, a GaN RF power HEMT, and the first FET 10 and the second FET 222 can be monolithically integrated on a single chip.

[0031] Fig. 3Figure 1 shows a schematic representation of a second embodiment of an amplifier circuit according to the invention, with a circuit arrangement for limiting the gate current. The basic circuit structure corresponds to that shown in Figure 2. Fig. 2 The embodiment shown is shown. Therefore, the reference numerals and their respective assignment to the individual features apply accordingly. For RF decoupling, however, a second high-resistance resistor R 2 240 is connected in parallel with the high-resistance resistor R 1 220 in the second connection 24. According to the invention, RF decoupling for limiting the gate current is thus achieved via two high-resistance resistors R 1 220 and R 2 240, whereby a voltage drop occurs across resistor R 1 220, which is connected in series with the second FET 222. This voltage increasingly blocks the second FET 222 and thereby limits the gate current of the first FET 10.

[0032] Fig. 4Figure 1 shows a schematic representation of a third embodiment of an amplifier circuit according to the invention, with a circuit arrangement for limiting the gate current. The basic circuit structure corresponds to that shown in Figure 2. Fig. 2 The embodiment shown is shown. Therefore, the reference numerals and their respective assignment to the individual features apply accordingly. For RF decoupling, however, the first connection 22 and the second connection 24 are connected to the gate terminal of the first FET 10 via a common inductor L 26. RF decoupling during gate current limiting is thus achieved according to the invention via an inductor L connected to the gate terminal 12 of the first FET 10. The resistor R 1 serves here only to generate a negative reverse voltage at the gate-source of the second FET 222 located in the supply network 20.

[0033] Fig. 5shows various characteristic curves for comparison of a conventional current limiter circuit and a current limiter circuit according to the invention.

[0034] Figure a) shows a linearly scaled comparison and figure b) a logarithmically scaled comparison between the gate current (in amperes (A)) occurring with a conventional resistor circuit to limit the gate current according to Fig. 1 (interrupted curve profile) and a circuit arrangement according to the invention Fig. 3 (continuous curve progression), each as a function of the input power P in (in decibel milliwatts (dBm)). It is clearly evident that in the embodiment according to the invention, extensive regulation of the gate current is possible, whereby the maximum permissible gate current can be selected by adjusting the first resistor R1.

[0035] Figures c) and d) show the reverse voltage at the gate of the first FET and the voltage drop across the first resistor R1 with a conventional resistor circuit to limit the gate current. Fig. 1 (interrupted curve profile) and a circuit arrangement according to the invention Fig. 3 (Continuous curve progression), each as a function of the input power Pin (in decibel milliwatts (dBm)). The voltage drop across the first resistor R1 in the conventional circuit does not differ from the voltage across the first FET (Vds) and therefore poses no challenge whatsoever, especially for GaN technology. Reference symbol list

[0036] 10th FET 12Gate connection (first FET) 20 Supply network 22 First connection 220 High-resistance resistor R1 222 Second FET 224 Gate connection (second FET) 24 Second connection 240 Second high-resistance resistor R2 26 Inductor L 30 Third connection

Claims

1. An amplifier circuit with a circuit arrangement for limiting a gate current at a first field-effect transistor (FET) (10) in case of an input-side overload, the circuit arrangement comprising the first FET (10) and a DC voltage supply network (20) connected to a gate terminal (12) of the first FET (10); wherein the supply network (20) provides a voltage Vgg at the gate terminal (12) of the first FET (10) via a first connection (22), which comprises a high-resistance resistor R1 (220) and a second FET (222) connected in series with a gate terminal (224); wherein the second FET (222) has an ON state at a gate-source voltage of 0 V and the gate terminal (224) thereof is also connected to the gate terminal (12) of the first FET (10) via a second connection (24); wherein the second connection (24) provides a current path in parallel to the resistor R1 (220); wherein a voltage drop occurring across the resistor R1 (220) leads to an increasing blocking of the second FET (222), wherein a to-be-amplified input power Pin is fed into the first FET (10) via a third connection (30) connected to the gate terminal (12) of the first FET (10).

2. The amplifier circuit according to claim 1, wherein a second high-impedance resistor R2 (240) is arranged in the second connection (24) for RF decoupling.

3. The amplifier circuit according to claim 1 or 2, wherein for the RF decoupling, the first connection (22) and the second connection (24) are connected to the gate terminal of the first FET (10) via a common inductance L (26).

4. The amplifier circuit according to any one of the preceding claims, wherein the first FET (10) is a GaN or GaAs RF power HEMT.

5. The amplifier circuit according to any one of the preceding claims, wherein the first FET (10) and the second FET (222) are monolithically integrated on a single chip.

6. The amplifier circuit according to any one of claims 1-4, wherein the first FET (10) and the second FET (222) are arranged on different chips.

7. The amplifier circuit according to any one of the preceding claims, wherein the power supply network (20) does not comprise any diodes or Zener diodes for limiting the gate current at the first FET (10).

8. A device for receiving microwave signals, comprising the amplifier circuit of any one of the preceding claims.