DEVICE, ARRANGEMENT AND SYSTEM FOR OPERATING A HARDWARE-BASED ARTIFICIAL NEURAL NETWORK AND METHOD FOR TRAINING THE SAME

Description

[0001] The invention relates to a device, an arrangement and a system for operating a hardware-based artificial neural network and a method for training the same.

[0002] Artificial intelligence can be used to recognize patterns in technical applications, such as image recognition or monitoring machine parameters. Artificial neural networks, which mimic the function of biological neurons, can provide artificial intelligence. These artificial neural networks can be trained evolutionarily with training data, whereby the training adapts the artificial neural networks in such a way that they improve their ability to perform their tasks. In this process, the individual elements of the artificial neural network are rewired in each training iteration.

[0003] In principle, such systems can be implemented as hardware-based or software-based systems. In hardware-based systems, modifiable electronic elements are linked together to form an artificial neural network. Dozens of linked elements can be removed without affecting the system's performance. Furthermore, hardware-based artificial neural networks may contain elements that are not linked to the rest of the network—that is, elements that are not integrated and not used—and which cannot be removed without reducing or eliminating the performance of the hardware-based artificial neural network.

[0004] To reduce this effect, it is known, for example, from Cramer, B., Stöckel, D., Kreft, M., Wibral, M., Schemmel, J., Meier, K., & Priesemann, V. Control of criticality and computation in spiking neuromorphic networks with plasticity, Nature Communications, 11(1) (2020) 2853, to implement the largest possible signal-to-noise ratio between the linked elements, as this allows the number of sub-components to be increased into the thousands and the number of evolutionarily linkable connections into the tens of thousands.

[0005] From CHERUPALLY SAI KIRAN ET AL: "Improving DNN Hardware Accuracy by In-Memory Computing Noise Injection", IEEE DESIGNGTEST, IEEE, PISCATAWAY, NJ, USA, Vol. 39, No. 4, December 27, 2021 (2021-12-27), pages 71-80, a device is known in which an artificial neural network is trained on an in-memory chip. During training, noise from other components is injected into the in-memory chip, influencing a partial summation layer.

[0006] Compared to software-based artificial neural networks, hardware-based artificial neural networks currently have a significantly more limited number of elements and connections, lower trainability, and lower complexity and flexibility.

[0007] The object of the invention is therefore to provide an improved hardware-based artificial neural network that overcomes the aforementioned disadvantages.

[0008] The problem is solved by the features of the independent claims. Advantageous further developments are the subject of the dependent claims and the following description.

[0009] According to a first aspect, the invention relates to a device for operating a hardware-based artificial neural network, comprising at least one hardware-based artificial neural network, wherein, according to the invention, the device has at least one interference device for coupling at least one interference signal into at least one region of the hardware-based artificial neural network and at least one coupling device, wherein the coupling device is arranged between the interference device and the hardware-based artificial neural network and is configured to transmit the at least one interference signal from the interference device into the entire at least one region.

[0010] A hardware-based artificial neural network is understood to be an electronic circuit similar to biological neural networks, where the nodes typically have comparable properties (weight, transfer function, etc.) and are arranged in layers. Unlike biologically inspired neural networks, the nodes of an artificial neural network possess various digital and / or analog circuit elements. These elements are not arranged in layers as in biologically inspired networks, but instead are connected stochastically as an electronic circuit. This means that, for example, some circuit elements intended as outputs can be used as inputs, and vice versa. From the perspective of conventional electronics, this can result in circuits that appear "meaningless" but acquire their "intelligence" through training.Hardware-based artificial neural networks can therefore also be referred to as trainable electronic networks.

[0011] The invention provides a device for operating a hardware-based artificial neural network, in which an interference signal is coupled into at least one region of the hardware-based artificial neural network. The interference signal is coupled into the entire region; that is, the interference signal is present throughout the entire region, or the region corresponds to the areas of the hardware-based artificial neural network covered by the interference signal. The at least one region can be smaller than the entire hardware-based artificial neural network. Furthermore, the device includes an interference device that can couple an interference signal into a hardware-based artificial neural network. A coupling device is provided between the interference device and the hardware-based artificial neural network for coupling the interference signal.In one example, the coupling device might simply consist of an air-filled space between the interfering device and the hardware-based artificial neural network. The interfering signal emitted by the interfering device is guided by the coupling device to the at least one region and coupled in there. The coupling of the interfering signal increases the noise in the at least one region, thus reducing the signal-to-noise ratio during signal transmission between elements, such as nodes, of the hardware-based artificial neural network. Contrary to all efforts in the implementation of electronic circuits, this counterintuitively results in a spatial and / or temporal and / or partial reduction of the signal-to-noise ratio in the at least one region of the hardware-based artificial neural network, rather than an increase.This reduction is limited to the at least one area where the noise signal is coupled in, i.e., it is restricted to some electronic components of the hardware-based artificial neural network's circuit. The signal-to-noise ratio (S / N) is defined as: S / N = 10 * log(signal power / noise power), expressed in decibels (dB), or S / N = 20 * log(signal voltage / noise voltage). Signals that can be transmitted well have an S / N greater than 15 dB, while an S / N less than 10 dB is considered very noisy. If the signal power equals the noise power, the signal is no longer identifiable at the receiver. Surprisingly, the performance of the hardware-based artificial neural network trained with coupled noise signals is improved.Since training is performed with the injected noise signals, the normal operation of the hardware-based artificial neural network also involves the injection of these noise signals. The increased performance means, among other things, that pattern recognition, such as of images or speech, is performed correctly with a higher probability without increasing the number of nodes in the network. This results in an improved hardware-based artificial neural network that overcomes the aforementioned disadvantages of the state of the art.

[0012] According to an example, the hardware-based artificial neural network can have at least one component in the at least one area which, upon receiving the at least one interference signal, is configured to reduce the signal-to-noise ratio, wherein the interference device preferably generates an optical, acoustic, capacitive, electromagnetic, quantum mechanical, ohmic, thermal and / or ionizing interference signal.

[0013] Reducing the signal-to-noise ratio is achieved by increasing the noise within the component. The component can be designed to be sensitive to the interfering signal. For example, using an optical interference signal can increase the noise within the component when transmitting electrical signals.

[0014] According to the invention, the jamming device has a plurality of individually controllable jamming elements for coupling a jamming signal into the hardware-based neural network, wherein the jamming elements couple a jamming signal into different areas of the hardware-based artificial neural network.

[0015] This allows multiple areas of the hardware-based artificial neural network, preferably the entire hardware-based artificial neural network, to be influenced by noise signals. Since the noise elements can be controlled independently, each area of ​​the hardware-based artificial neural network can be individually subjected to its own noise signal. The areas can overlap and / or be separate from each other.

[0016] Furthermore, for example, the multitude of interference elements can be distributed on a plane, preferably arranged in an array-like manner, wherein the coupling device has a medium with a multitude of coupling elements for transmitting the at least one interference signal into the at least one area, wherein the coupling elements are distributed in the plane like the interference elements.

[0017] This allows a noise signal pattern to be generated using the noise elements, which is then transmitted to the hardware-based artificial neural network via the coupling device. Since the distribution of the noise elements in the plane is known, specific areas within the hardware-based artificial neural network can be targeted with noise signals. In particular, the distribution of the noise elements in the plane can be configured such that the noise elements are arranged analogously to the components of the neural network. This allows for the targeted coupling of noise signals into individual components.

[0018] Furthermore, at least some of the numerous interfering elements can be designed as resistance heaters, Peltier elements, light-emitting diodes, electromagnetic radiators and / or transmitters, and / or piezoelectric components.

[0019] In another example, at least one area can have an extent that corresponds to the size of the hardware-based artificial neural network, or be smaller than the size of the hardware-based artificial neural network.

[0020] If the at least one region has the same extent as the hardware-based artificial neural network, the interference device or coupling device can be designed homogeneously to apply an interference signal homogeneously to the entire hardware-based artificial neural network. With a finer level of structuring, the interference signals can be coupled to different regions within a component, for example, only to a signal input or a signal output of a circuit element of the hardware-based artificial neural network. If the extent of the at least one region is, for example, equal to the extent of a component of the hardware-based artificial neural network, and each component is assigned a region, an independent interference signal can be coupled into each component of the neural network.

[0021] The multitude of coupling elements can thus exhibit a structure that is identical to the structure of the multitude of interference elements. Furthermore, the structure of the coupling elements can also correspond to the structure of the hardware-based artificial neural network. However, this does not preclude the possibility that the structure of the coupling elements could be finer or coarser than the structure of the interference elements or the hardware-based artificial neural network.

[0022] According to another example, the device can have at least one semiconductor chip, wherein the semiconductor chip has the hardware-based artificial neural network, wherein the hardware-based artificial neural network is preferably formed in an integrated circuit, more preferably in a Field Programmable Gate Array (FPGA) or in an application-specific integrated circuit (ASIC).

[0023] The neural network can be implemented as a circuit on the semiconductor chip, with the network's nodes acting as components of that circuit. In this example, the neural network elements can be implemented as components of a Field Programmable Gate Array (FPGA), meaning the FPGA can be configured such that its circuitry forms a neural network. A hardware-based artificial neural network implemented as an FPGA can be further trained. In contrast, a hardware-based artificial neural network is hard-wired onto an application-specific integrated circuit and must have been optimized beforehand in other ways.

[0024] Furthermore, it is conceivable that the device may have a shielding device for shielding external interference signals of the same type as the at least one interference signal, wherein the shielding device surrounds the hardware-based artificial neural network, the coupling device and the interference device.

[0025] The shielding device can, for example, be designed as an encapsulation forming an outer shell of the device. The interference device, the coupling device, and the hardware-based artificial neural network are therefore surrounded by the shielding device. The shielding device can block external interference signals that could alter the signal-to-noise ratio in an uncontrolled and non-reproducible manner. Thus, the interference signals from the interference device cause changes in the signal-to-noise ratio almost exclusively within the areas of the neural network.

[0026] In a second aspect, the invention relates to an arrangement of a plurality of devices according to the preceding description, wherein the hardware-based artificial neural networks of the devices are electrically connected to each other serially and / or in parallel, wherein preferably the jamming devices of at least a first device of the plurality of devices and a second device of the plurality of devices are configured as a common jamming device, wherein further preferably an output level of the hardware-based artificial neural network of a third device of the plurality of devices is configured to control the jamming device of a fourth device of the plurality of devices.

[0027] The advantages, effects, and further developments of this arrangement are derived from the advantages, effects, and further developments of the device described above. To avoid repetition, reference is therefore made to the preceding description in this regard.

[0028] The arrangement comprises at least two devices as described above. In the arrangement, the output level of a hardware-based artificial neural network of a first device is electrically connected, among other things, to an input of a jamming device of a second device or of several other devices. The first device can then control the jamming device of the second device or influence its function. In this way, all devices can be coupled to the jamming devices of other devices in the arrangement via an electrical connection of their neural networks.

[0029] Furthermore, in a third aspect, the invention relates to a system comprising a plurality of arrangements according to the preceding description, wherein a first arrangement of the plurality of arrangements for controlling at least one interference device is configured in a second arrangement of the plurality of arrangements.

[0030] The advantages, effects, and further developments of the system result from the advantages, effects, and further developments of the device and arrangement described above. To avoid repetition, reference is therefore made to the preceding description in this regard.

[0031] The first arrangement can, for example, form a base level whose devices output a signal that is processed as an input signal by the devices of the second arrangement, e.g., after further processing. At least one interference device of a device in the second arrangement can be coupled to the output level of at least one device in the first arrangement. This can be referred to as forward feedback. It is also conceivable that at least one interference device of a device in the first arrangement can be coupled to the output level of at least one device in the second arrangement. This can be referred to as backward feedback.

[0032] Furthermore, several systems can be considered subsystems and combined into a complex system, with the subsystems being coupled to each other in the manner described above. In this way, a more complex system with even greater performance can be created. Such a complex system could, for example, process signals of different types (optical and acoustic), with one subsystem processing the optical signals and another subsystem processing the acoustic signals.

[0033] In a fourth aspect, the invention relates to a method for training an artificial neural network in a device according to the preceding description, wherein the method comprises at least the following steps: defining target output data when processing provided training data; feeding the training data into the hardware-based artificial neural network and coupling at least one interference signal into the at least one region of the hardware-based artificial neural network by means of the at least one interference device; determining output data of the hardware-based artificial neural network; determining whether at least one deviation exists between the output data and the target output data that is outside a predetermined tolerance range; if the deviation is within the tolerance range: terminating the method;and if the deviation is outside the predetermined tolerance range: modify the hardware-based artificial neural network and preferably modify the at least one disturbance signal and repeat the aforementioned steps.

[0034] The advantages, effects, and further developments of the method result from the advantages, effects, and further developments of the device described above. To avoid repetition, reference is therefore made to the preceding description in this regard.

[0035] This method trains a hardware-based artificial neural network in a state disturbed by a perturbing device. The neural network is thus trained by disrupting the signal transmission in at least one region where a perturbing signal is introduced. In each training iteration, in addition to the changes made to the hardware-based artificial neural network, changes are also made to the at least one introduced perturbing signal. This can involve changing at least one parameter of the at least one perturbing signal, such as its intensity, frequency, or duration. Changing this parameter also modifies the at least one perturbing signal. This method thus allows a perturbing device to be incorporated into the training of a neural network.This method allows for the provision of a trained hardware-based artificial neural network that exhibits increased performance compared to a neural network into which no interference signals are coupled.

[0036] According to an example, a signal-to-noise ratio of at most 15 dB, preferably at most 10 dB, and more preferably at most 0 dB can be generated in at least one area using the coupled interference signal.

[0037] As a rule, well-transmitted signals have a signal-to-noise ratio (SNR) greater than 15 dB. A SNR of less than 10 dB is considered very noisy. If the signal power equals the noise signal power, the signal is no longer identifiable at the receiver. However, a neural network can, in principle, recognize patterns in the noise even at an SNR of 0 dB or less, so that even with an unidentifiable signal, the output of subsequent nodes in the neural network can be influenced. The SNR can also be less than 0 dB, preferably at least -40 dB, more preferably -15 dB, and even more preferably -10 dB.

[0038] Furthermore, it is conceivable that before the step of defining target output data during the processing of provided training data, the hardware-based artificial neural network can be trained, for example, without the coupling of interfering signals.

[0039] This allows the neural network to be initially trained, as is known from the prior art, to achieve an initial performance level, e.g., a first accuracy value for recognizing certain patterns. Subsequent further training with the introduction of noise signals can surpass this initial performance, achieving, for example, a second accuracy value for recognizing the specific patterns that is greater than the first.

[0040] According to the invention, the at least one interference device can have at least a plurality of individually controllable interference elements, wherein each interference element is configured to couple an interference signal into the hardware-based neural network, wherein preferably each interference element couples an interference signal into a different area of ​​the hardware-based artificial neural network, and the plurality of controllable interference elements can be controlled in such a way that the interference signals form a predefined interference signal pattern via the hardware-based artificial neural network, wherein several trainings of the hardware-based artificial neural network are successively carried out with different predefined interference signal patterns.

[0041] The predefined interference pattern can be used, for example, for an initial training run. In subsequent training runs, the interference pattern can be modified by changing the activity of one or more of the individually controllable interference elements, for example, by reducing or increasing the signal strength. Because a predefined interference pattern can be initially introduced, the training can be accelerated by using interference patterns that have already been deemed suitable. Furthermore, the predefined interference pattern can also be used unchanged throughout the entire training process.

[0042] According to a fifth aspect, the invention relates to a method for training artificial neural networks in an arrangement according to the preceding description, wherein the method for training an artificial neural network in a device according to the preceding description is applied to the hardware-based artificial neural networks of the devices, preferably after the devices have been trained separately outside the arrangement using the method for training an artificial neural network in a device according to the preceding description.

[0043] The advantages, effects, and further developments of the method for training artificial neural networks in an array result from the advantages, effects, and further developments of the device, array, and the previously described method. To avoid repetition, reference is therefore made to the preceding description in this regard.

[0044] The method for training artificial neural networks in an array allows all devices in the array to be coordinated through training, thereby improving the array's performance. To achieve this, the devices in the array can be trained together from the outset. Alternatively, the devices can initially be trained individually, preventing any interference from the output signals of other devices. Only in a second training phase, during which the devices in the array are coordinated, can the interference be influenced by the output signals of other devices in the array.

[0045] In a sixth aspect, the invention relates to a method for training artificial neural networks in a system according to the preceding description, wherein the method for training an artificial neural network in a device according to the preceding description is applied to the hardware-based artificial neural networks of the devices, preferably after the arrangements outside the system have been trained separately using the method for training artificial neural networks in an arrangement according to the preceding description.

[0046] The advantages, effects, and further developments of the method for training artificial neural networks in a system arise from the advantages, effects, and further developments of the device, arrangement, system, and other previously described methods. To avoid repetition, reference is therefore made to the preceding description in this regard.

[0047] In the process of training artificial neural networks within a system, the various configurations of the system are coordinated. The configurations can initially be trained individually, without the components of other configurations influencing the interfering signal devices. Furthermore, in this case as well, the components of each configuration can first be trained separately before the configurations themselves, again without any interference from other components affecting the interfering signal devices. Alternatively, the configurations and their components can be coordinated in a single system training session, in which case the output signals of some configurations can influence the interfering signal devices of others.

[0048] The invention is described below with reference to an exemplary embodiment and the accompanying drawing. The drawing shows: Figure 1A, legs, schematic representation of the device; Figure 2A, legs, schematic representation of the device according to Figure 1A, b with further details; Figure 3 a schematic representation of an example of the device with an FPGA chip; Figure 4A, legs schematic representation of the example made of Figure 3in further embodiments; Figure 5 a schematic representation of an example of the device with two jamming devices; Figure 6 a schematic representation of a basic structure of an FPGA chip; Figure 7 a schematic representation of an example of the device with capacitive jamming elements; Figure 8 a schematic representation of an example of the device with heating and cooling jamming elements; Figure 9 a schematic representation of an example of the device with heating jamming elements; Figure 10 a schematic representation of an example of the device with sound-emitting jamming elements; Figure 11 a schematic representation of an example of the device with jamming elements that emit electromagnetic radiation; Figure 12 a schematic representation of an example of the device with a pattern-generating jamming signal device; Figure 13 a schematic representation of an arrangement with a plurality of devices;Figure 14: A schematic representation of a system with a multitude of arrangements; Figure 15: A schematic representation of another example of the system in an alternative representation; Figure 16: A schematic representation of an example with a multitude of systems interconnected via the jamming devices; Figure 17: A schematic representation of further examples of an arrangement of devices; Figure 18: A flowchart of the procedure for training artificial neural networks in a system.

[0049] The Figures 1A and 1B shows the devices, which are further detailed below: according to Figure 1A in a spatial arrangement, according to Figure 1BThe essential components of the device are shown in cross-section. For example, this is an FPGA chip on a control board 13, whose individual components are linked, configured, and trained to form a hardware-based artificial neural network 11 via an evolutionary learning process. This level of the hardware-based artificial neural network 11 largely corresponds to the chip-based systems and controls described in the prior art and available industrially.

[0050] In the following, the term "FPGA" is used to represent all freely configurable electronic semiconductor chips. At a distance d, which will be specified in more detail in the following examples, there is another optionally array-like layer acting as a jamming device 12. The elements of this jamming device, represented here as small spheres, can be controlled, switched on / off, or adjusted. The control elements are not shown here.

[0051] This level of the interference device 12 can generate interference signals in patterns and is referred to as the "interference signal level." It, or its elements, can generate interference signals that couple locally into at least one region of the hardware-based artificial neural network 11 via the space that is part of a coupling device 15, coupling the interference signal into the entire region. The region therefore corresponds to the areas of the hardware-based artificial neural network 11 covered by the interference signal. The region can cover the entire network, i.e., the interference signal can couple into the entire network. This can occur homogeneously. Furthermore, if, for example, several regions are provided, the extent of the regions can be assigned to a group of individual FPGA components, individual components, or merely subregions of the individual components.Suitable interference array components can be miniaturized heating or cooling elements, optical, acoustic, resistive, electromagnetic, capacitive, mechanical, or even quantum mechanical components. Anything that can couple into an electronic circuit, such as that implemented at the level of the hardware-based artificial neural network 11, is applicable.

[0052] The coupling device 15, hereinafter also referred to as the "coupling space," allows the signals generated in the interference device 12 to be coupled as patterns into the plane of the hardware-based artificial neural network 11. Corresponding to the elements of the plane of the interference device 12, the coupling device 15 can be a medium that mediates, for example, thermal, resistive, electromagnetic, capacitive, mechanical, or even quantum mechanical transmission of the signals. In the simplest case, it can be a homogeneous medium, such as a gas, liquid, or solid. However, the medium typically comprises a vertically and / or horizontally structured combination of different materials to achieve a local effect adapted to the plane of the hardware-based artificial neural network 11 and its array structure.The medium of the coupling device 15 can be adapted to the arrangement of the linkable elements of the FPGA chip, i.e., to the hardware-based artificial neural network. The distance d can also be varied, but is usually chosen to be small compared to the area of ​​the plane of the hardware-based artificial neural network 11 in order to be able to generate local effects in the hardware-based artificial neural network 11, especially in the FPGA chip.

[0053] Unlike conventional uses of semiconductor chips and semiconductor components, the components on the board of the level of the hardware-based artificial neural network 11 can be partially and not completely shielded from external influences, so that only coupling from the level of the interference device 12 is possible.

[0054] Therefore, due to the increased sensitivity of the components of the hardware-based artificial neural network 11 to external signals, an encapsulation can be provided as a shielding device 14 of the device against precisely these interference signals.

[0055] In this basic arrangement of a hardware-based artificial neural network 11 according to the invention, the main component for the evolutionary learning process is the level of the hardware-based artificial neural network 11. The level of the perturbation device 12 forms a higher-level, but subordinate, component that makes this process more complex at the level of the hardware-based artificial neural network 11 and can also be optimized via the same or a second evolutionary algorithm and learning process. The entire unit consisting of 11 to 15 can be considered and referred to as an intelligent hardware AI system and as the basic AI unit.

[0056] The training process can be carried out in two ways. In the first alternative, the hardware-based artificial neural network 11 and the interfering device 12 can be modified simultaneously during the evolution process. In the second alternative, only the hardware-based artificial neural network 11 can be trained first, and if this training shows positive results, the interfering device 12 can be added. If the device has more than one hardware-based artificial neural network 11 and more than one interfering device 12, any combination can be subjected to separate and joint training according to the first or second alternative.

[0057] In contrast to state-of-the-art systems, highly complex systems can be realized and controlled by avoiding undefined interference, defining the separation of the interference signals by the interference device 12 and the coupling device, and increasing the probability of achieving a positive training result.

[0058] In the Figures 2A and 2B An example is shown to illustrate the spatial relationships. Figure 2A shows a three-dimensional exploded view and Figure 2B a cut along line SS in Fig. 2A .

[0059] An FPGA chip 24, in which the hardware-based artificial neural network is implemented, can be arranged on a board 21, e.g., a multi-layer printed circuit board for controlling and configuring the FPGA via the connectors 26. Configuration can be performed using a digital computer. The FPGA 24 is not shielded but can instead be covered with the coupling medium 23 of the coupling device, followed by the interference device 22, which is shown here in an array-like, checkerboard pattern with individual interference elements for locally generating interference signals for the FPGA. The interference device 22 is in turn connected to a board 25 for controlling the interference elements via the connectors 27. In the simplest case, arbitrary patterns can be generated by switching the interference elements of the interference device on and off, which act locally on the FPGA chip 24 via the coupling medium 23.

[0060] Regarding the distance d from Fig. 1AIn this example, it is small compared to the area of ​​the FPGA chip 24. Typically, the distance is between 0.1 mm and 5 mm, preferably 0.5 mm. The geometric relationships are in section SS in Fig. 2B recognizable.

[0061] For example, the array of the jamming device 22 can consist of small heating elements or Peltier elements connected to a medium 23 with high thermal conductivity, e.g., a metal or diamond layer. This layer can be structured in an array-like fashion into columns with good and poor thermal conductivity and transmit a temperature pattern to the FPGA. This allows a variable, trainable, and switchable jamming signal pattern to be generated.

[0062] A first structuring level of the interfering device, which is a measure of the structuring of the distribution of the interfering elements, can be adapted to the structuring of the FPGA, whose structuring in this example can be specified with a second structuring level, i.e., chosen to be geometrically similar. Then, in each region where an interfering signal from the interfering device couples into the hardware-based artificial neural network implemented in the FPGA, a basic element of the FPGA is located. That is, each interfering element then affects one basic element of the FPGA.

[0063] However, this is not mandatory, as the first level of structuring can be structured both more finely and more coarsely than the second level of structuring; preferably, the ratio of the first level of structuring to the second level of structuring has values ​​in a range between 10:1 for the finer structuring and 0.1:1 for the coarser structuring.

[0064] The coupling medium 23 of the coupling device can have a structure that is specified by a third structuring grade. The third structuring grade can also be finer or coarser than the second structuring grade.

[0065] In Figure 3 is a compact technical arrangement of the under Fig. 1A and 1BThe described device is illustrated. An FPGA chip 32 with the interconnectable electronic basic components 33 can be arranged in a semiconductor chip holder 31, e.g., a ceramic with a plurality of contact pads. The coupling medium 34 and, directly on this, the interference device 35 with an array of interference elements can be arranged above it.

[0066] The entire chip can then be encapsulated to shield against external influences. 36. In the case of electromagnetic elements in the interference device, this can be, for example, a metal encapsulation; in the case of optical interference signals, an opaque covering.

[0067] This compact chip design allows such chips to be combined on a single board to form complex structures or stacks, as illustrated in the following examples. A multitude of basic AI units and their combinations in layers and hierarchies can be assembled using such chips.

[0068] In the Figures 4A and 4B The diagram schematically illustrates an exemplary combination of compact chip systems. Figure 4A is a device as an AI basic unit according to the Fig. 3 The figure comprises the FPGA 41, the coupling medium 43 of the coupling device, and the interference device 42 with the electrical contact pads 44. The thickness of the coupling medium can vary between 100 µm and 5 mm, preferably 200 µm to 600 µm. Furthermore, the coupling medium can have a plurality of coupling elements, which can be structured or unstructured according to a third level of structuring. In particular, structuring of the coupling medium is provided for the use of signal patterns.

[0069] In Figure 4BTwo devices are shown combined. The combination of the two devices comprises two FPGAs 41, which are connected via two coupling media 43 to a common interference device 42. The FPGAs are aligned head-to-head.

[0070] Similarly, further combinations can be implemented as horizontal or vertically oriented stacks. The advantage of a shared jamming device for multiple FPGAs lies in the reduction of the control effort.

[0071] Furthermore, interference patterns can be generated, either predefined or evolutionarily optimized during FPGA training. Such systems also offer the advantage that the upper and lower FPGAs can be subjected to different interference patterns sequentially or alternately, resulting in more complex training and more sophisticated AI systems with minimal switching effort.

[0072] In Figure 5 Another variant is shown. In this example, an FPGA 51 is arranged between two coupling media 53a and 53b and two interference signal levels 52a and 52b. This results in numerous possibilities for coupling interference signals, in line with the increasing, yet well-defined, complexity of the device.

[0073] For example, symmetrical coupling of identical interference signal patterns from above and below can be implemented onto the FPGA chip in the middle. Alternatively, asymmetrical coupling of identical or different interference signal patterns into the FPGA chip can be implemented. Another alternative is, for example, temporally separated coupling from above and below. Furthermore, alternating coupling of asymmetrical interference signals from above and below is also possible.

[0074] In Figure 6The diagram schematically illustrates the basic principle and structure of FPGA chip arrays. Since FPGAs are typically structured as arrays, the representation with rows 1 to m and columns 1 to n was chosen for clarity.

[0075] Electronic basic elements, whose positions can be identified by the indices 11, 12, [...], m5, mn, can be configured to form a hardware-based artificial neural network via four connections each (A, B, C, D). These connections are short-circuit proof. Incorrect wiring configurations, such as using the output of an element as an input, are also permitted in hardware-based artificial neural networks.

[0076] As exemplified by the basic elements at positions 11 to 15 in the top row of the array shown, the FPGA elements can be either digital or analog circuits. The symbols used correspond to electronic nomenclature. Combinations of analog and digital devices are also possible. The electronic elements are not shielded against interference as is usually the case, but may even include components that are sensitive to optical, acoustic, thermal, electromagnetic, and other signals generated by the interfering device. The configuration method and the evolutionary programs used for training are state of the art and are therefore not described in detail here.

[0077] In Figure 7 The three levels of the device (hardware-based artificial neural network, coupling device and interference device) are shown with a capacitive interference.

[0078] In this example, the FPGA 71, as a hardware-based artificial neural network, exhibits a second level of structuring that is finer than the first and third levels of structuring of the jamming device 72 and the coupling device 73. The structuring of the FPGA, the jamming device, and the coupling device can be similar or different. Accordingly, not only a single basic element of the FPGA, but a group of basic elements simultaneously, or only a sub-area of ​​a basic element, can be influenced.

[0079] The interference device 72 can, for example, comprise metal plates or metal pads 72a embedded in an electrically insulating medium 72b. Each pad 72a can be controlled by a computer program, analogous to the operation of the FPGA. In the simplest example, three configurations are possible for each pad, as shown in Figure 74: 1. Application of a positive or negative voltage Ux, 2. Open pad, i.e., no potential bond, where the pad finds its own potential in the chip environment, and 3. Connection to ground, so that arbitrary charge patterns can be generated in the array.

[0080] In the illustrated example, the coupling device 73 is structured in the same way, such that a material with a high dielectric constant 73a can be arranged as a coupling element under each metal pad, embedded in a medium with a low dielectric constant 73b. The metal pads form local capacitors with the surface of the FPGA 71, through which displacement currents can be coupled into the respective locally adjacent areas of the hardware-based artificial neural network.

[0081] In the evolutionary training process, analogous to the training of the hardware-based artificial neural network, the configurations of the perturbation elements 72a can also be varied using an evolutionary algorithm. This means that initially, a random configuration of input signals can be generated and applied to the perturbation device 72. Then, the artificial neural network implemented in the FPGA can receive an input signal. If this signal is correctly interpreted by the neural network at the output, the configuration of the perturbation device 72 remains unchanged, and the next training signal is applied to the FPGA. If this signal is, for example, interpreted incorrectly, a few pads or perturbation elements are randomly modified in their configuration, just as happens with the circuit connections in the FPGA. The two algorithms can, but do not necessarily have to, match.If this is done several hundred to a thousand times, which can be referred to as "generations" in the evolutionary algorithm, the desired success rate of the entire device can be achieved.

[0082] In Figure 8 Figure 1 shows a 3-layer AI chip in which interference signals can be generated via an array of heating and / or Peltier elements 82, which represent the interference elements in this example. The temperature from the interference elements can be transferred to the local basic elements of the FPGA 81 via the coupling device 83. The basic elements, arranged in an array at positions 11 to mn of the FPGA, can either be manufactured to be temperature-sensitive using conventional semiconductor manufacturing processes or are designed to react to small temperature differences, e.g., several degrees or fractions thereof, in their signal behavior.

[0083] The coupling device 83, in this example as well, is composed of two components: the highly thermally conductive, cylindrical areas 83a and the poorly thermally conductive areas 83b in between. The material 83a can be, for example, a metal such as copper or silver, or a semiconductor-processed diamond layer. The insulating material 83b can be a poorly thermally conductive plastic material, glass, or even a ceramic material.

[0084] The interference device 82, in this example, can comprise a variety of heating and / or cooling elements, e.g., miniaturized resistance elements or Peltier elements. In this way, any desired temperature pattern can be transmitted to the underlying FPGA. The temperature differences can be selected over a wide range, e.g., between -20°C and 100°C, but preferably in the degree range of or below near room temperature.

[0085] In box 85, which is located at the top center of the Figure 8 The structure of this basic AI unit is shown in the vertical section SS. Here too, the array structure of the layers of the jamming device, the coupling device, and the neural network need not match; that is, the number of jamming elements and coupling elements can, but does not have to, correspond to the number of basic electronic elements.

[0086] The generated temperature patterns are typically static, meaning they remain constant for the duration of the neural network's duty cycle, which corresponds to one decision-making pass. However, it is also possible to generate dynamic changes across multiple decision-making passes of the FPGA.

[0087] The training is conducted analogously to the description from Fig. 7 .

[0088] In Figure 9 The device shown is one with a fault detection mechanism and only includes heating elements. Otherwise, this example is as in Fig. 7 and 8 The structure is described.

[0089] In Figure 10 Figure 102 depicts a jamming device which includes miniaturized sound emitters as jamming elements. These emitters emit sound signals of varying frequencies, for example, via vibration. The sound emitters can be piezoelectric elements, piezoelectric crystals, or small membranes that generate individually controlled sound patterns.

[0090] The coupling device 103 in this example can have sound-transmitting areas 103a, e.g. a mechanical solid-state coupling or miniature sonotrodes, and sound-absorbing spaces 103b, e.g. sound-absorbing materials, e.g. material with tiny cavities.

[0091] The basic components of the FPGA 101 can be designed to be susceptible to some degree of interference from sound frequencies. This effect can be amplified and made more complex if the FPGA's electronic components include, for example, sound receivers. This can be the case for some or all of the FPGA's components. The advantage of using sound is its wide frequency range, extending from infrasound through the human hearing range to ultrasound. This allows for the generation of not only sound patterns of a single frequency, but also sound patterns of different frequencies.

[0092] This example clearly illustrates the expanded possibilities that the integration of jamming and coupling devices into hardware-based artificial neural networks brings. In interconnected arrangements and systems, as explained in the following figures, each of these jamming devices can be operated as a fixed sound pattern with varying intensity, with a shifted overall frequency, with a modified frequency composition / spectrum, with a changed pattern, or in combination with the preceding options.

[0093] If it is assumed that the overall system, consisting of a hardware-based artificial neural network, jamming device, and coupling device, has been optimized for a specific frequency pattern and achieves its highest success rate under this control, then altering or detuning the jamming signals would lead to a deterioration in performance. In extreme cases, the neural network only functions within a specific intensity or frequency range. This makes it possible to improve or worsen the performance of devices solely through the jamming signals if they were previously operating suboptimally. This opens up possibilities for interconnecting many devices hierarchically or even on an equal footing, such that the success rate of one neural network can influence other connected hardware-based artificial neural networks via their jamming signals.

[0094] Figure 11Figure 111 shows an FPGA comprehensively implementing an artificial neural network of the type already described. In this example, the jamming device 112 can comprise miniaturized transmitters for high-frequency electromagnetic waves up to the microwave range as jamming elements, which can, for example, be designed like antennas or transmit their signal to the FPGA via the coupling device 113 using a waveguide 113a as a coupling element.

[0095] Similarly, the jamming device can incorporate infrared or LED elements in the visible or ultraviolet spectral range as jamming elements. Furthermore, coupling can be achieved via optical fibers or small pinholes as coupling elements. This device also offers a very wide range of possible operating and training modes, analogous to... Fig. 10 .

[0096] In Figure 12An alternative device with a jamming device capable of generating patterned jamming signals is shown. For this purpose, the coupling device 123 has two or more levels 123a, 123b, each of which can have patterns applied, e.g., concentric rings on each level that are alternately transparent and opaque, with the centers of the concentric rings of the two levels offset relative to each other. This results in symmetrical or asymmetrical superposition patterns. The jamming device 122 can then include an array of light-emitting diodes. In this case, the coupling device 123 is not an array as in the previous examples. Instead, the superposition pattern can define the pattern formation of the jamming signals in the neural network. The FPGA chip 121 can, for example, include light-sensitive components in its basic electronic elements.

[0097] In Figure 13is an arrangement of devices as an ensemble of basic AI units according to Figs. 3 to 5 The diagram shows that FPGA chips 131 can be electrically contacted on the control board 135, and that the interference devices 132 can be electrically contacted on the underside of the upside-down, transparently shown control board 136. The coupling devices 133 are arranged between them.

[0098] The AI ​​basic units 134 can be trained separately and / or jointly, as already described, via first control inputs 139 of the control board 135 for the FPGAs 131 and second control inputs 140 of the control board 136 for the jamming devices 132. If each AI basic unit 134 has been trained on a different feature group, for example, one on recognizing cats, one on dogs, one on horses, etc., then the arrangement in Fig. 13a more complex AI system with higher performance / intelligence than the basic AI units represent as individual devices.

[0099] The jamming devices can be partially electrically interconnected, as schematically shown by the broken lines 137 and 138. This provides a further possibility for controlling and for the evolutionary training of the entire arrangement.

[0100] These connections allow signals to be transmitted between the interfering devices 132, which modify the performance of other AI basic units in a defined manner, e.g., solely through the coupling of interfering signals that can influence the corresponding artificial neural networks in the FPGAs, as explained above. This can be achieved, for example, by increasing or decreasing the intensity of the interfering signal in the connected AI basic unit. This means that the respective AI basic unit can be improved or even operate optimally, e.g., the devices connected via the dashed line 138, or it can be detuned and thus degraded or shut down, e.g., the devices connected via the line 137. For example, in the animal recognition example mentioned above...It is assumed that half of the AI ​​units can recognize animals, and the other half can recognize artworks that resemble animals. This can be achieved through a circuit in which, initially, many of the AI ​​units are controlled in a suboptimal range by detuning their respective interference devices, for example, operating at 80% of their maximum performance. When the devices are presented with an input signal, such as an image of a mule, the individual AI units classify this input signal with varying results.

[0101] The devices that can recognize cats, for example, output a 2% match between a mule and a cat; the devices that can recognize horses, for example, output a 90% match; and the devices that can recognize works of art, for example, can also react within a recognition range of a few percent up to 60% in the case of horse sculptures. The AI ​​base unit with the highest match rate, in this case the devices that can recognize horses, can then switch its jamming device to optimal operation. Furthermore, previously detuned jamming devices of the AI ​​base units connected to it can also be switched to the optimal jamming signal mode simultaneously, for example, one AI base unit for recognizing wild horses, one for recognizing zebras, and one for recognizing hybrids of the horse family.Simultaneously, it can, via connections to the devices capable of recognizing artworks, suppress all but the one with the highest success rate. This device with the highest success rate for recognizing artworks can, via its connections, activate further devices capable of recognizing artworks through optimal adjustment of the jamming mechanisms.

[0102] Now another iteration of the mule image can be started until it is decided which object in the overall system the mule is closest to and whether it is an animal or an object.

[0103] Such an arrangement has one more training level than the basic AI units, namely the networking of the devices with each other, which can also be done via evolutionary optimization strategies.

[0104] With a plurality, at least two, arrangements according to Fig. 13, hierarchically or otherwise complexly organized systems can be built, as in Figure 14 The diagram shows a basic level 141, comprising any number of basic AI units, where, for the sake of clarity, in Figure 14 By way of example, only four devices designated a1 to a4 are shown, which can be interconnected via electrical connections 143 between the associated interference devices in an activating or suppressing manner. The input signal 144 can be fed into this level into all AI basic units a1 to a4, e.g. by connecting the inputs of the devices in parallel.

[0105] The AI ​​basic unit with the highest detection probability can couple to the next higher level 142. There, the input signal 144 can also be present at all AI basic units. For clarity, only two devices, b1 and b2, are shown in level 142, which can also be partially or completely interconnected via electrical connections 143 between the jamming devices. In this level as well, an AI basic unit with the highest detection probability can be identified, which can then generate the output signal 147.

[0106] Typically, the number of basic AI units is highest at the lowest level and decreases towards higher levels. However, this is not mandatory. Each level can introduce expanded evaluation categories or new connections. For example, after object recognition, patterns can be compared at higher levels, and acoustic signals can be added at the next level to reveal inconsistencies that would otherwise lead to misinterpretations. For instance, if an object identified as a cat neighs like a horse. Such a system can have a larger number of basic AI units at higher levels than at any of the lower levels.

[0107] Figure 15 The figure on the left shows a system with a hierarchical AI structure, consisting of three levels 151, 152 and 153 with input 154 and output 155 analogous to Fig. 14Such complex AI interconnections are shown below, as on the right in Figure 15 represented as cylinder 156, with input 154 and output 155 combined to allow for the representation of more complex structures.

[0108] In Figure 16 The diagram schematically depicts an even more complex structure. It consists of a multitude of systems according to Figure 15 , which are represented as cylinders 164-166. They can be oriented in the same direction in one plane, whereby, for the sake of clarity, only the respective input 161 is shown pointing downwards and the respective output 169 pointing upwards on cylinder 164 as an example.

[0109] The systems can be arranged in domains, which are marked by a specific pattern on the top of the corresponding cylinders, with each pattern marking one system of a domain.

[0110] In Fig. 16Three domains are depicted, each composed of three system types: 164, 165, and 166. As can be seen with system type 166, not all systems within a domain need to be in close proximity. Individual systems can also be arranged as solitary units in another domain (not shown here). In this way, strong and weak interactions between the domains can be achieved via the interference devices.

[0111] The systems within a domain can receive a common input signal. It is advantageous to organize the domains in such a way that they each receive different or modified input signals, e.g., parts of the common input signal, which are then processed in... Figure 16 are designated with the reference numbers 161, 162 and 163.

[0112] Reciprocal or directional connections can exist between the systems, through which they can be stimulated or suppressed, or vice versa. These connections can usually originate from the highest level, i.e., the result level (see...). Fig. 15 , exit. If input signals 161 to 163 are present, the individual systems can already produce more complex responses with different recognition probabilities than without these connections.

[0113] Analogous to the way individual systems work according to Fig. 14 and 15The systems within and beyond the domain can reinforce and weaken each other. Through connections to other domains, which can be quite far apart (as exemplified by the connecting arrow from System 164a to System 164b), larger system ensembles can be controlled in their activity via the jamming devices. These system ensembles have an additional training layer beyond those already described above.

[0114] The system with the highest hit rate of a domain can couple via a switch level 167, which feeds the result into a projection level 168, in which the results of the other domains with high hit rates and the input signal can be coupled in and displayed for comparison.

[0115] This arrangement allows, for example, the implementation of pandemonium-like structures, such as those suspected to exist in the human brain. The systems correspond to the columnar structure of the cerebral cortex, with the domains corresponding to, for example, the visual, auditory, haptic, and olfactory cortex. Through the interconnections between the systems and between the domains, association-like modes can be generated and trained, which ultimately represent nothing more than links between phenomena that are not actually related to each other—for example, the translation of a visual pattern into music, etc. As can be seen, the underlying mechanisms, e.g.,FGPA with jamming devices, their networking and manipulation via the jamming devices, the linking of devices into arrangements and their aggregation into systems, subsequently creating a comprehensive AI system via the arrangement of the systems into layers and domains, which can be made universally intelligent through a multitude of sequential and / or jointly executed evolutionary training cycles. The more extensive the systems, the more complex the training structure can be designed.

[0116] In the Figures 17A to 17D Alternative devices are shown. In the event that the jamming device 172 is not to be located close to the FPGAs 171, in order to avoid jamming signals in such fine patterns as in Figs. 1 to 16 , but to couple these more broadly and for many FPGAs in the same or similar way, the device can have several FPGAs 171 and control boards, which e.g. according to Figure 17AThey are arranged in a square around a common jamming device 172, which can be configured as a column. Such a group of four FPGAs 171, or, for example, a group of eight (only seven are shown for clarity), can then form a basic AI unit in conjunction with the jamming device 172 and the coupling device 173 arranged between them.

[0117] In the Figures 17B to 17D Further examples of devices are shown in top view. Figure 17B are the FPGAs of a device arranged in a triangular configuration and in Figure 17C in a hexagonal arrangement.

[0118] Figure 17DFigure 173 shows a device whose FPGAs, and thus hardware-based artificial neural networks, are arranged in a quadrilateral chain system. The coupling medium of the coupling device 173 can be a gas or a material that transmits the respective interference signals well to the FPGA chips. Typically, due to the wide-ranging effect from the interference signal column 172, it can be homogeneous. Alternatively, it can have a layered or other composition of materials with good and poor transmission characteristics. Other groupings can be made analogously. All of them have in common that they can be combined into more complex arrangements, systems, and ensembles, as described in Figure 173. Figs. 13 to 16 were described.

[0119] In Figure 18A flowchart is shown that depicts a procedure for training a system according to the preceding description, wherein a procedure 180 for training an artificial neural network in a device according to the preceding description is first carried out. The devices of the system can be trained first.

[0120] In a first optional step 187 of the procedure 180, the hardware-based artificial neural network of a device can initially be trained without the coupling of interfering signals. In this step, the hardware-based artificial neural network is trained to a preliminary performance value.

[0121] In a further step (181), target output data can be defined, representing the desired result of the processing of provided training data by the hardware-based artificial neural network. This step can be performed at any time before the subsequent steps, and also simultaneously or before the optional step (187).

[0122] Furthermore, in step 182, the provided training data can be used to train the hardware-based artificial neural network. For this purpose, the training data is fed into the input level of the neural network, with the perturbation device coupling perturbation signals into at least one region of the hardware-based artificial neural network. Parts of a node of the hardware-based artificial neural network, an entire node, or multiple nodes can be located in this at least one region.

[0123] In a further step, the output data of the hardware-based artificial neural network is determined. Since the network is hardware-based, the processing of the training data takes place simultaneously in all nodes of a network layer, so that the output data is available within a few milliseconds.

[0124] In step 184, a deviation between the output data and the target output data is then determined. If the deviation lies outside a predefined tolerance range, e.g., if the deviation exceeds 1%, the hardware-based artificial neural network is reconfigured. Optionally, at least one interference signal can also be modified. If multiple interference signals are used, it is sufficient to modify a single interference signal, e.g., by controlling an interference element of the interference device.

[0125] Steps 182 to 184 are repeated with the modified hardware-based artificial neural network and the input of the possibly modified interference signals.

[0126] Provided the deviation is within the predefined tolerance range, the training of the device is terminated with step 185.

[0127] Once all devices have been trained using method 180, an arrangement of the devices can be trained in a further method 188. For this purpose, the devices of the arrangement, coupled to each other via the jamming devices, are trained according to steps 182 to 186. However, it is not excluded that the arrangement can also be trained without prior execution of the method for the devices.

[0128] The training of the arrangement can be carried out analogously to method 180, whereby at least some interfering devices can be influenced or controlled by the hardware-based artificial neural networks of other devices.

[0129] Once all arrangements of a system have been trained using procedure 188, the system can be trained according to procedure 189. For this purpose, the devices or arrangements of the system, coupled to each other via the jamming devices, are trained according to steps 182 to 186. However, it is not excluded that the system can also be trained without prior execution of the procedure for the arrangements or devices.

[0130] Furthermore, an ensemble can be trained by first training the systems according to the description above, and then training the entire ensemble. However, it is not impossible that the ensemble can also be trained without prior training of the systems, the setup, and / or the devices.

[0131] The example described above does not in any way limit the invention.

Claims

1. A device for operating a hardware-based artificial neural network, comprising at least one hardware-based artificial neural network (11, 24, 32, 41, 51, 71, 81, 101, 111, 121, 131, 171) wherein the device comprises at least one disturbance device (12, 22, 35, 42, 52a, 52b, 72, 82, 102, 112, 122, 132, 172) for coupling at least one disturbance signal in at least one region of the hardware-based artificial neural network and at least one coupling device (15, 23, 34, 43, 53a, 53b, 73, 83, 103, 113, 123, 133, 173), wherein the coupling device is located between the disturbance device and the hardware-based artificial neural network and is designed to transmit at least one disturbance signal from the disturbance device to the entire at least one area, characterized in that the disturbance device contains a plurality of individually controllable disturbance elements (72a) for coupling a disturbance signal into the hardware-based neural network, where the disturbance elements couple a disturbance signal into different areas of the hardware-based artificial neural network.

2. The apparatus according to claim 1, wherein the hardware-based artificial neural network in which at least one region has at least one component which is designed to reduce the signal-to-noise ratio when receiving at least one disturbance signal, wherein the disturbance device preferably generates an optical, acoustic, capacitive, electromagnetic, quantum mechanical, resistive, thermal and / or ionizing disturbance signal.

3. The apparatus according to claim 1 or 2, wherein the plurality of the disturbance elements is distributed on a plane, preferably array-like, wherein the coupling means has a medium having a plurality of coupling elements (73a, 83a, 103a, 113a) for transmitting at least one disturbance signal to at least one region, wherein the coupling elements are distributed in the plane like the disturbance elements.

4. An apparatus according to any one of claims 1 to 3, wherein at least one region has an extent equal to the size of the hardware-based artificial neural network or is smaller than the size of the hardware-based artificial neural network.

5. Apparatus according to any of the preceding claims, wherein the apparatus comprises at least one semiconductor chip, wherein the semiconductor chip comprises the hardware-based artificial neural network, wherein the hardware-based artificial neural network is preferably formed in an integrated circuit, further preferably in a field programable gate array or in an application-specific integrated circuit.

6. An apparatus according to any one of the preceding claims, wherein the apparatus comprises a shielding device (14, 36) for shielding external disturbance signals which are of the same type of at least one disturbance signal, wherein the shielding device surrounds the hardware-based artificial neural network, the coupling device and the disturbance device.

7. The arrangement of a plurality of devices according to any of the preceding claims, wherein the hardware-based artificial neural networks of the devices are electrically connected to each other in series and / or parallel, wherein preferably the disturbance devices of at least one first device of the plurality of devices and of a second device of the plurality of devices are formed as a common disturbance device, wherein furthermore preferably an output plane of the hardware-based artificial neural network of a third device of the plurality of devices is formed to control the disturbance device of a fourth device of the plurality of devices.

8. A system comprising a plurality of arrangements according to claim 7, wherein a first arrangement of the plurality of arrangements for controlling at least one disturbance device is formed in a second arrangement of the plurality of arrangements.

9. A method for training a hardware-based artificial neural network in a device according to any one of claims 1 to 6, wherein the method (180) comprises at least the following steps: - defining (181) target output data when processing provided training data; - feeding (182) the training data into the hardware-based artificial neural network and coupling at least one disturbance signal into at least one area of the hardware-based artificial neural network by means of at least one disturbance device; - determining (183) of output data of the hardware-based artificial neural network; - determining (184) whether there is at least one discrepancy between the output data and the target output data that is outside a predetermined tolerance range; if the deviation is within the tolerance range: - termination (185) of the method; and if the deviation is outside the predetermined tolerance range: - modifying (186) the hardware-based artificial neural network and preferably changing the at least one disturbance signal and repeat the aforementioned steps 182 to 184, whereby the plurality of controllable disturbance elements of the disturbance device is controlled in such a way that the disturbance signals form a predefined disturbance signal pattern via the hardware-based artificial neural network, whereby several trainings of the hardware-based artificial neural network with different predefined disturbance signal patterns are carried out one after the other.

10. The method of claim 9, wherein a signal-to-noise ratio of not more than 15 dB, preferably not more than 10 dB, and preferably not more than 0 dB is generated by means of the coupled disturbance signal in at least one region.

11. The method of claim 9 or 10, wherein before the step: defining target output data in the processing of provided training data the hardware-based artificial neural network is trained without coupling disturbance signals (187).

12. A method for training hardware-based artificial neural networks in an arrangement according to claim 7, wherein the method (188) for training a hardware-based artificial neural network in a device according to any one of claims 9 to 11 is applied to the hardware-based artificial neural networks of the devices, preferably after the devices have been trained separately outside the arrangement by means of method (180) according to one of claims 10 to 13.

13. A method (189) for training hardware-based neural networks in a system according to claim 8, wherein the method (180) for training a hardware-based artificial neural network in a device according to any one of claims 9 to 11 is applied to the hardware-based artificial neural networks of the devices, preferably after the arrangements have been trained separately outside of the system by means of method (188) for training hardware-based artificial neural networks in an arrangement according to claim 12.