MONOLITHICALLY INTEGRATED TRANSISTORS FOR A BUCK CONVERTER

Description

BACKGROUND

[0001] Synchronous buck voltage converters are widely used in power supplies for portable computers, servers, telecommunication devices, computing applications, and various other portable systems. Unfortunately, many buck converters are fairly large, so that they can handle high current levels at high switching frequencies and may do so with lower switching efficiency. US 2011 / 210956 A1 discloses a current sensor which can be used to measure current flowing through a semiconductor substrate of a direct current (DC) to DC converter or other device. Further, US 2013 / 164896 A1 discloses a voltage converter including an output circuit having a high side device and a low side device which can be formed on a single die and connected to each other through a semiconductor substrate. Moreover, US 2010 / 171543 A1 discloses a packaged switching device for power applications. In addition, WO 2009 / 030165 A1 discloses a LDMOS and a semiconductor device integrated with LDMOS and CMOS. Further prior art documents are JP 2001 / 250870 A, US 2010 / 109081 A1, US 2013 / 207228 A1 and US 2011 / 049622 A1.SUMMARY

[0002] The invention is defined by the features of the appended claims.BRIEF DESCRIPTION OF THE DRAWINGS

[0003] FIG. 1 is a schematic of a buck converter including a pair of monolithically formed transistors in accordance with various implementations. FIG. 2 shows an example of an implementation of the monolithically formed transistors of FIG. 1 not forming part of the claimed invention. FIG. 3 shows another example of an implementation of the monolithically formed transistors of FIG. 1 including an additional insulating layer and also not forming part of the claimed invention. FIG. 4 shows yet another example of implementation of the monolithically formed transistors of FIG. 1 according to the claimed invention. DETAILED DESCRIPTION OF EXAMPLE EMBODIMENTS

[0004] Existing synchronous buck converters with high current handling capability use discrete power metal oxide semiconductor field effect transistors (MOSFETs). One transistor is called the low side transistor, and another transistor is called the high side transistor. Such discrete solutions may introduce large parasitic inductance and resistance, which results in lower conversion efficiency. Some converters use package integrated MOSFETs, but such solutions may have higher package costs. Other solutions use monolithically-integrated transistors for the buck converter, but use laterally-diffused metal oxide semiconductor (LDMOS) transistors as both low side and high side transistors. Because of lateral current flow and limitations of metal spreading resistance, it may be difficult for such solutions to achieve satisfactorily high current handling capability with an acceptably high conversion efficiency. The embodiments described herein address these problems.

[0005] FIG. 1 shows an example of a buck converter 100 in accordance with various implementations described herein. As shown, the converter 100 includes a controller 102, a pair of transistors 110, an inductor L1, and an output capacitor Cout. Additional components are possible as well. For example, an input capacitor Cin is shown, as well as a capacitor on the VDD input to the controller 102. An input voltage Vin is provided to the Vin input terminal, and a pulse width modulated signal is provided to the PWM input of the controller. The PWM input signal is used by the controller 102 to control the voltage level of the output voltage Vo. By adjusting the PWM input signal, different output voltage levels are made possible based on the input voltage Vin. Accordingly, the Vin input voltage is converted to a different (typically lower) output voltage Vo.

[0006] The transistors 100 include a transistor pair 110, including a "high side" transistor 120 (sometimes referred to as a "control FET") and a "low side" transistor 130 (sometimes referred to as a "sync FET"). The transistors 120, 130 function as switches and are turned on and off under control by the controller 102. The controller asserts a high side gate control output signal (HG) that controls the gate of the high side transistor 120, and a low side gate control output signal (LG) that controls the gate of the low side transistor 130. The controller reciprocally turns each of the high and low side transistors 120, 130 on and off in accordance with the level of the PWM input signal. The two transistors 120, 130 are generally not both on at the same time-accordingly, while one is on, the other is off and vice versa, although both transistors may be off at the same time. The duty cycle of the transistors dictates the output voltage level of the output voltage Vo.

[0007] The transistor pair 110 (including high side transistor 120 and low side transistor 130) is formed on a single semiconductor substrate. Accordingly, the transistors 120, 130 are monolithically integrated on a single semiconductor chip. FIG. 2 shows an example of a monolithically integrated transistor pair 110a for use in the buck converter 100. The low side transistor 130 is shown on the left side of the semiconductor structure, and the high side transistor 120 is shown on the right side of the semiconductor structure. An edge region 109 (e.g., a dielectric) separates the two transistors 120, 130. The low side transistor 130 is implemented as a source down MOSFET. The high side transistor 120 is implemented as an LDMOS transistor.

[0008] In this example, the low side transistor 130 includes an n-doped drain that includes a lightly doped drain region (N-LDD) 132 that is long enough to maintain the required breakdown voltage, a source formed by the substrate 138, and a gate 134. An electrical connection to the N-LDD 132 is provided through metal 136, which is provided down a via 137 to the N-LDD 132. The source is provided by a P+ doped substrate 138, whose doping concentration generally increases from top surface 138a towards opposing bottom surface 138b. The gate 134 and N-LDD 132 are provided on one side of the silicon substrate 138, while the source connection 115 is on the back side of the silicon on the substrate 138.

[0009] The high side transistor 120 includes a drain formed in the n-doped well region (N-well) 122, a source formed in a p-doped (P+) region 126, and a gate 124. An electrical connection to the N-well 122 (drain) is provided by metal 128, which is provided down a via 127 to the N-well / drain. Thus, the source of the high side transistor 120 is formed as part of the P+ region 126, and the drain is formed in the N-well 122. The drain in N-LDD 132 of the low side transistor 130 is electrically connected to the source in P+ region 126 of the high side transistor 120 through a metal, which forms a switch node VSW 140. Region 129 is a dielectric material. The N-well 122 (drain) of the high side transistor 120 forms the input node Vin of the buck converter (see also FIG. 1) to which a connection can be made at electrical contact 117. The output node Vo of the buck converter is provided via contact 116 by the VSW node 140 through the inductor L1 (as shown in FIG. 1).

[0010] The low side transistor 130 in the example of FIG. 2 (as well as in FIGS. 3 and 4) is a source down MOSFET, so current generally flows vertically down the structure from the N-LDD 132 (drain) through the gate-controlled channel and down through the substrate 138 (source) and out the back side of the structure (i.e., the opposite side of the substrate 138 from the N-LDD 132). The high side transistor 120 in this integrated transistor pair 110 is an LDMOS transistor in which current flows from the Vin node down via 127 to the drain in N-well 122, across a channel (not specifically shown) formed in the device to the P+ region 126 (source), and across the metal VSW node 140 to the drain of N-LDD region 132 of the low side transistor 130.

[0011] Isolation between the high side transistor 120 and the low side transistor 130 is provided, at least in part, by the N-well 122, which is formed between the substrate 138 and the source of the high side transistor. The N-well 122 and the P+ region 126 form a P-N junction, which is reverse biased due to application of the input voltage Vin to the n-doped well (N-well 122). As a reverse biased P-N junction, current is not permitted to flow through the N-well 122 from the P+ region 126 of the high side transistor 120 to the substrate 138, which also is the source of the low side transistor 130. Thus, the sources of the two transistors 120, 130 are isolated from each other.

[0012] The example of FIG. 2 also includes field plates 131a, 131b, and 131c formed over the various gates 134 and 124. The field plates 131a-c are metal and are connected to the grounded substrate 138. The field plates 131a-c provide electrical shielding for the transistor gates. Field plate 131a is connected to the substrate at point 135, which is provided in a trench 119. Field plate 131b is connected to the substrate 138 in trench 141 formed in the substrate in the edge region between the transistors. The metal of the field plates 131a-b is well-grounded through sufficient contact area with the grounded substrate 138. The depth of the trench 139 provides a contact point to higher doped areas of the substrate for improved grounding performance. The high side gate 124 also is shielded by the field plate 131c, which is part of the metal VSW node 140.

[0013] FIG. 3 provides a monolithically integrated transistor pair 100b, similar to that of FIG. 2. A difference between the structure of FIGS. 2 and 3 is that the structure of FIG. 3 includes an insulating layer 150. In various implementations, the insulating layer 150 is provided between the N-well 122 (drain) of the high side transistor 120 and at least portions of the substrate 138. The insulating layer 150 may be formed by, for example, oxygen implantation or other insulating doping. The insulating layer 150 provides additional decoupling of the high side N-well 122 from the P+ substrate 138, and functions to further disable the parasitic p / n / p bipolar transistor that otherwise might be formed by the high side P+ region 126, N-well 122, and substrate 138.

[0014] FIG. 4 shows yet another implementation of a monolithically formed transistor pair 110c for buck converter 100. In the example of FIG. 4, the low side transistor 130c is generally the same as in the implementations of FIGS. 2 and 3, although additional gates (LG) are shown. The high side transistor 120c, however, is different than in the previous embodiments. In FIG. 4, the N-LDD region 155 represents the drain of the high side transistor, and the P-well 157 represents the source of the high side transistor. The P-well region is a p-doped region and is generally at the same voltage potential as the neighboring P+ regions 161 and 163. The P+ regions 161 and 163 have a higher doping concentration than the P-well 157. The voltage switch node (VSW) 140 connects the N-LDD region 132 (drain of the low side transistor 130c) to the source of the high side transistor 130c. More specifically, the metal of the VSW node 140 is provided down a trench 172 to thereby contact the P+ region 161. The P+ region 163 is also contacted by metal from VSW node 140 in trench 175. Although FIG. 4 seems to show two different instances of the VSW node 140, the two VSW node 140 instances are connected together, partially through the metal in the trenches 172, 175, and 177 and through the P+ regions 161, 163 and the P-well, but also by separate metal connections in the structure that are not shown in the FIG. 4. Similarly, the two instances of the Vin node 128 shown in FIG. 4 are electrically connected together by metal (not shown) in FIG. 4. Regions 149 in FIG. 4 represent dielectric material to electrically isolate the Vin node 128 from the Vout nodes 140.

[0015] The structure of FIG. 4 includes a P-well 157 within the N-well 122 for improved isolation between high and low side transistors 120c and 130c. Also, individual n-sinkers 180 are included with the high side transistor 120c to provide a low resistance path from Vout (VSW node 140) to the N-well 122. The N-sinkers are heavily n-doped regions and help to ensure the N-well potential is at the Vout (VSW) potential with minimal voltage variation laterally through the structure due to current flow.

[0016] Unlike in the structures of FIGS. 2 and 3, the N-well 122 in the structure of FIG. 4 does not represent the drain of the high side transistor. However, like the previous structures, the N-well 122 of FIG. 4 helps to isolate the high side transistor 120 from the low side transistor 130.

[0017] As described previously, the various gates 134 and 124 in FIG. 4 are shielded with field plates 131 whose metal contacts the P+ regions in the various trenches.

[0018] The embodiments described herein generally achieve smaller parasitic inductance and higher conversion efficiency than other solutions may be able to achieve. If a buck converter was constructed by a pair of discrete power transistors, the parasitic source inductances associated with the transistor packaging and printed circuit board (PCB) traces will affect the switching performance of the converter and cost additional power loss. In the disclosed examples above, the drain in the N-LDD 132 of the low side transistor 130 is electrically connected to the source in the P+ region 126 of the high side transistor 120 through a metal directly. The parasitic source inductance of the high side transistor (associated with the transistor packaging and PCB traces that otherwise would be present in discrete transistor implementations) is removed from the circuit. Accordingly, the additional power loss noted above is avoided.

[0019] Modifications are possible in the described embodiments, and other embodiments are possible, within the scope of the claims.

Claims

1. An integrated semiconductor transistor chip (110c) for use in a buck converter (100), comprising: a high side transistor (120c) formed on the chip (110c) and including an extended drain metal oxide semiconductor, EDMOS, transistor; a low side transistor (130c) formed on the chip (110c) and including a source down metal oxide semiconductor field effect transistor, MOSFET; a substrate (138) of the chip (110c) for use as a source for the low side transistor (130c); an n-well (122) for isolation of the high side transistor (120c) from the source (138) of the low side transistor (130c); a p-well (157) formed within the n-well (122) for further isolation; and a plurality of n-sinkers (180) within the region of the integrated semiconductor transistor chip (110c) containing the high side transistor (120c) to provide low resistance paths from a switch node (140) to the n-well (122), wherein the switch node (140) includes a metal layer (131a, 131b, 131c) interconnecting a drain (132) of the low side transistor (130c) and the source (126) of the high side transistor (120c) to maintain the n-well (122) at the same potential as the switch node (140).

2. The integrated semiconductor transistor chip of claim 1, wherein the n-well (122) is formed between the substrate (138) and a source of the high side transistor (120c).

3. A buck converter (100) comprising the integrated semiconductor transistor chip (110c) of claim 1 or 2.