Quantum device with semiconductor qubits comprising gates arranged in a semiconductor

Abstract

The invention relates to a quantum device (100) with semiconductor qubits, comprising at least:• - a layer (104) of a first semiconductor arranged on a layer (106) of a second semiconductor, the forbidden energy band of which is different from that of the first semiconductor, such that one of the layers (104, 106) forms a confinement potential barrier with respect to the electrons or the holes intended to be located in confinement regions formed in the other layer (104, 106);• - cavities (108) formed through only one portion of the thickness of the layer (104) of the first semiconductor; - electrically conductive control gates (110) at least partially arranged individually in one of the cavities (108).

Description

[0001] Description

[0002] Title: QUANTUM DEVICE WITH SEMICONDUCTOR QUBITS COMPRISING

[0003] GRIDS ARRANGED IN A SEMICONDUCTOR

[0004] TECHNICAL FIELD

[0005] The invention relates to the field of quantum devices, quantum information processing and quantum computing. Advantageously, the invention applies to the development of quantum processors in which qubits, i.e. the elementary units of quantum information, are encoded in semiconductor quantum dots, in particular for spin qubits where the quantum information is encoded in the spin states (i.e. the magnetic moments) of electrons or holes confined by electrostatic potentials and / or possibly micro-structuring, or for charge qubits where the quantum information is encoded in the confined electric charge.

[0006] State of the prior art

[0007] Quantum computing is based on the use of a quantum state with two measurable levels as an information carrier, called a quantum bit or, in English, "quantum bit" or, in one word, "qubit". Laws and properties of quantum mechanics, such as superposition, entanglement, and measurement are exploited to execute algorithms. A quantum device comprising qubits allows the quantum state of these qubits to be manipulated.

[0008] Spin or charge qubits can be formed in semiconductors. Semiconductor technologies are being studied for the production of qubits due to their high integration potential, similar to classical electronics. In such qubits, electrons or holes are confined at cryogenic temperatures in nanometric confinement structures defined electrostatically and, in the case of silicon, with an architecture similar to that of MOSFETs. These confinement structures correspond to quantum dots. A quantum dot behaves like a potential well confining one or more elementary charges (electrons or holes) in a semiconductor region.

[0009] For a quantum processor to solve problems of practical importance, it must have a sufficiently large number of qubits, beyond the maximum number of qubits that can be simulated on a classical computing machine (i.e., more than about 50 qubits). However, achieving such a large number of qubits within a single device poses technological challenges, in particular the management of variability between qubits.

[0010] In a quantum device with semiconductor qubits (spin or charge qubits), the electrons or holes used for encoding quantum information are confined using metal gates deposited above a structure or heterostructure of semiconductor(s) covered with a layer of insulating material (SiO?, AI2O3, etc.) serving as a gate oxide. There may be one or more levels of metal gate superimposed and separated by layers of insulating material. The electrons or holes are confined in the portion of semiconductor located below the gates (at or near them), either at the interface between the semiconductor and the gate oxide, or in buried quantum wells created by stacking layers of semiconductors of different compositions.Such a quantum well comprises, for example, a portion of silicon or germanium in which charge carriers (electrons in the case of silicon, holes in the case of germanium) are confined by SiGe barriers between which the silicon or germanium portion is located. In all cases, the confinement of electrons or holes is sensitive to the presence of trapped electric charges mainly at the interfaces between the semiconductor structure and the dielectric material(s) deposited on its surface. This charge disorder is one of the main causes of variability between qubits.

[0011] While the electric field generated by the charges trapped directly beneath the metal gates is partially screened by the gates, the electric field generated by the charges between the gates is much less so. Therefore, the charge disorder associated with the semiconductor / dielectric interfaces that are relatively far from the metal gates has a dominant effect on the variability between qubits. DISCLOSURE OF THE INVENTION

[0012] An aim of the present invention is to propose a quantum device with semiconductor qubits whose structure makes it possible to significantly reduce the variability between the qubits.

[0013] For this, the present invention proposes a quantum device with semiconductor qubits, comprising at least:

[0014] - a layer of a first semiconductor arranged on a layer of a second semiconductor whose bandgap energy is different from that of the first semiconductor, such that one of the layers forms a confinement potential barrier with respect to electrons or holes intended to be located in confinement regions formed in the other layer;

[0015] - cavities formed through only part of the thickness of the layer of the first semiconductor;

[0016] - electrically conductive control grids, each arranged at least partly in one of the cavities.

[0017] This device can be applied to all qubits made from a semiconductor heterostructure in which the vertical confinement (or direction parallel to the stacking direction, or growth direction, of the semiconductor layers) of the charge carriers (electrons or holes) takes place in one of the semiconductor layers forming potential wells.

[0018] In order to reduce the effect of charge disorder associated with semiconductor / oxide surface interfaces not covered by metal gates, this quantum device proposes the use of a so-called "penetrating" gate structure, i.e. made within one of the semiconductor layers. This gate geometry allows, compared to traditional gates with a gate dielectric formed above the semiconductor stack forming the quantum wells, to distance the semiconductor / dielectric interfaces between adjacent gates, and, consequently, to reduce the impact of the associated charge disorder and charge noise, and thus to reduce the variability between the qubits of the device. This reduction in qubit variability simplifies the control architecture associated with this quantum device and facilitates the tuning of the qubits.

[0019] In this device, the encoding of quantum information can take place on a spin degree of freedom (i.e., the spin states of a particle in the presence of a static magnetic field) or charge of electrons or holes trapped in the confinement regions, or on charges present in the confinement regions.

[0020] The invention advantageously applies to a quantum device comprising at least 50 qubits.

[0021] Such a quantum device differs from a MOSFET-type device in that the semiconductor regions next to the quantum dots topped by the control gates form "tunnel barriers" that isolate the quantum dots from each other.

[0022] Each of the control gates can be used to form a quantum dot or to control the height of one of the tunnel barriers located between two quantum dots, i.e. to control the coupling between these dots. In the case of a control gate used to form a quantum dot, the confinement region of this quantum dot is generally located in the vicinity of the interface between the layers of the first and second semiconductors, directly above the cavities or in the vicinity of them.

[0023] Confinement regions are created by all or part of the control gates depending on the potential applied to them. In other words, a qubit is not necessarily associated with each control gate.

[0024] Depending on the manufacturing process used to form the control grids in the cavities, the control grids may partially or completely fill the cavities. It is also possible for the control grid material to overflow from the cavities.

[0025] Each of the control grids may comprise at least one metallic material.

[0026] Advantageously, in a first embodiment:

[0027] - the semiconductor of said one of the layers forming the confinement potential barrier may be AIGaAs and the semiconductor of said other layer may be GaAs, or - the semiconductor of said one of the layers forming the confinement potential barrier may be SiGe and the semiconductor of said other layer may be Si or Ge.

[0028] Beyond these combinations of semiconductor materials, the invention can be applied generally to any type of heterostructure obtained by stacking two different semiconductor materials, such as for example the following pairs of materials: InAs / InGaAs, InGaAs / lnP, CdTe / HgTe, etc.

[0029] In a second embodiment, the device may further comprise a layer of a third semiconductor such that the layer of the second semiconductor is disposed between the layers of the first and third semiconductors, and the band gap energy of the second semiconductor may be lower than those of the first and third semiconductors such that the layers of the first and third semiconductors form confinement potential barriers with respect to electrons or holes intended to be located in the confinement regions formed in the layer of the second semiconductor.

[0030] In this second embodiment, the confinement regions can be located in the layer of the second semiconductor, directly above the cavities or in the vicinity of them.

[0031] Advantageously, in this second embodiment, the first and third semiconductors may be SiGe and the second semiconductor may be Si (allowing electrons to be confined) or Ge (allowing holes to be confined), or the first and third semiconductors may be AIGaAs and the second semiconductor may be GaAs.

[0032] The thickness of the layer of the second semiconductor may be between 5 nm and 50 nm and advantageously between 10 nm and 20 nm, and / or the thickness of the layer of the first semiconductor may be between 5 nm and 200 nm and advantageously between 10 nm and 100 nm, and / or the thickness of a portion of the layer of the first semiconductor arranged under the cavities may be less than the thickness of the layer of the first semiconductor and between 5 nm and 100 nm and advantageously between 5 and 30 nm. The quantum device may further comprise at least one layer of dielectric material arranged at least between walls of each of the cavities and each of the control gates.

[0033] The layer of dielectric material may have a thickness less than or equal to 20 nm and advantageously less than or equal to 10 nm.

[0034] Qubits can be arranged to form a qubit matrix.

[0035] A method for producing a quantum device with semiconductor qubits is also proposed, comprising at least:

[0036] - production of a layer of a first semiconductor on a layer of a second semiconductor whose band gap energy is different from that of the first semiconductor, such that one of the layers forms a confinement potential barrier with respect to electrons or holes intended to be located in confinement regions formed in the other layer;

[0037] - production of cavities through part of the thickness of the layer of the first semiconductor;

[0038] - production of electrically conductive control grids, each arranged at least partly in one of the cavities.

[0039] Advantageously, the cavities can be made by local etching of the first semiconductor, and the gates can be made by filling these cavities with metal, thus making it possible to obtain gates that are self-aligned with respect to the confinement regions.

[0040] Throughout the document, the term "on" is used without distinction of the orientation in space of the element to which this term relates. For example, in the characteristic "on a face of a layer", this face is not necessarily oriented upwards but can correspond to a face oriented in any direction. Furthermore, the arrangement of a first element on a second element must be understood as being able to correspond to the arrangement of the first element directly against the second element, without any intermediate element between the first and second elements, or as being able to correspond to the arrangement of the first element on the second element with one or more intermediate elements arranged between the first and second elements.

[0041] BRIEF DESCRIPTION OF THE DRAWINGS

[0042] The present invention will be better understood by reading the description of exemplary embodiments given purely for informational purposes and in no way limiting, with reference to the appended drawings in which:

[0043] Figures 1, 2 and 3 represent steps of a method for producing a semiconductor qubit quantum device, object of the present invention, according to a first embodiment;

[0044] Figures 4 and 5 represent part of the steps of a method for producing a quantum device with semiconductor qubits, the subject of the present invention, according to a variant of the first embodiment;

[0045] Figures 6, 7 and 8 represent steps of a method for producing a quantum device with semiconductor qubits, object of the present invention, according to a second embodiment;

[0046] Figures 9 and 10 represent part of the steps of a method for producing a semiconductor qubit quantum device, the subject of the present invention, according to a variant of the second embodiment;

[0047] Figure 11 schematically represents a top view of an example of arrangement of several grids of a semiconductor qubit quantum device, object of the present invention;

[0048] Figure 12 represents results of simulations carried out to compare the susceptibility to charge disorder of a semiconductor qubit quantum device, object of the present invention, with that of a quantum device of the prior art.

[0049] Identical, similar or equivalent parts of the different figures described below bear the same numerical references so as to facilitate the transition from one figure to another. The different parts represented in the figures are not necessarily shown on a uniform scale, in order to make the figures more readable.

[0050] The different possibilities (variants and embodiments) must be understood as not being mutually exclusive and can be combined with each other.

[0051] Detailed description of specific embodiments

[0052] In the description below, for the sake of simplification, only the production of the control gates of a quantum device with semiconductor qubits is described. The other elements or characteristics of this device, particularly relating to the coupling between qubits and the other control and measurement elements, are not described.

[0053] An example of a method for producing a quantum device 100 with semiconductor qubits according to a first embodiment is described below in connection with Figures 1 to 3 which correspond to cross-sectional views of the device produced. In the example described in these figures, the production of the gate of a single qubit is described. However, this method is implemented to produce a quantum device 100 comprising several qubits, for example arranged in the form of a matrix and such that each qubit can interact with one or more neighboring qubits.

[0054] This method is implemented from a substrate 102 corresponding for example to a wafer, or plate, based on Si, Ge, GaAs, or another semiconductor.

[0055] Epitaxy steps are implemented in order to form on the substrate 102 a stack of semiconductors comprising at least one layer 104 of a first semiconductor and one layer 106 of a second semiconductor together forming a heterostructure (see FIG. 1). The layer 106 is arranged between the substrate 102 and the layer 104. The thickness t (dimension parallel to the Z axis shown in FIG. 1, and parallel to the direction of the stack or direction of growth of the layers 104, 106) of the layer 104 is for example between 5 nm and 200 nm and advantageously between 10 nm and 100 nm. The thickness of the layer 106 is for example between a few nanometers and 10 micrometers or more. A significant thickness may be necessary in some cases to relieve stresses induced by mesh differences between the layer 106 and the substrate 102.The stoichiometric composition of the layer 106 may vary during epitaxial growth in order to obtain the desired composition at the top of the layer 106 with the desired stress state. The portion of the layer 106 comprising the desired composition, or the entire layer 106 when this layer comprises the desired composition over its entire thickness, may have a thickness for example between 5 nm and 50 nm and advantageously between 10 nm and 20 nm.

[0056] The first and second semiconductors of the layers 104, 106 are chosen such that the bandgap energy of the second semiconductor is different from that of the first semiconductor, so that, in each of the qubits produced, one of the layers 104, 106 forms a confinement potential barrier with respect to electrons or holes intended to be located in confinement regions formed in the other of the layers 104, 106.

[0057] In a first configuration, the bandgap energy of the second semiconductor of the layer 106 is lower than that of the first semiconductor of the layer 104, so that, in each of the qubits produced, the potential barrier is formed by the first semiconductor of the layer 104 and the confinement region is formed in the second semiconductor of the layer 106 near the interface with the first semiconductor. According to an example of this first configuration in which the qubits of the device 100 are electron (or hole) spin (or charge) qubits, the first semiconductor of the layer 104 is AIGaAs and the second semiconductor of the layer 106, as well as of the substrate 102, are GaAs.According to another example of this first configuration in which the qubits of the device 100 are spin or electron charge qubits, the first semiconductor of the layer 104 is SiGe and the second semiconductor of the layer 106 is Si. According to another example of this first configuration in which the qubits of the device 100 are spin or hole charge qubits, the first semiconductor of the layer 104 is SiGe and the second semiconductor of the layer.

[0058] 106 is Ge. In a second configuration, the bandgap energy of the first semiconductor of layer 104 is lower than that of the second semiconductor of layer 106, so that, in each of the qubits produced, the potential barrier is formed by the second semiconductor of layer 106 and the confinement region is formed in the first semiconductor of layer 104 near the interface with the second semiconductor. The examples of materials described above for the first configuration can be applied to this second configuration, by reversing the materials of layers 104, 106.

[0059] After the layers 104, 106 have been produced on the substrate 102, cavities 108 are produced through only a portion of the thickness t of the layer 104 (in FIG. 2, a single cavity 108 is shown). The cavities 108 are, for example, obtained by a controlled process of partial etching of the layer 104. Each of the cavities 108 has, in a plane parallel to the upper face of the layer 104 through which the cavities 108 are produced (and parallel to the plane (X, Y) shown in FIG. 2), a section, for example in the shape of a disc or a polygon, including the case of a very anisotropic shape, for example narrow in one direction and long in another direction.

[0060] The thickness h of the remaining portion of the layer 104 located under the cavities 108 is less than the initial thickness t of the layer 104 and is for example between 5 nm and 100 nm and advantageously between 5 and 30 nm.

[0061] Electrically conductive control gates 110 are then produced in the cavities 108 (see FIG. 3 in which a single gate 110 is shown). In the exemplary embodiment described, the gates 110 comprise at least one metallic material. The gates 110 may be produced by depositing one or more metallic materials in each of the cavities 108, thus enabling a self-aligned production of these gates 110. Portions of this or these metallic materials deposited outside the cavities 108 may be removed by chemical-mechanical planarization (CMP) or other method. The gate material 110 may in this case be flush with the same level as an upper face of the layer 104. Advantageously, the filling may be carried out so as to completely fill each cavity 108 with a gate 110. The device 100 obtained at this stage comprises several qubits controlled by gates 110.The number of gates is typically equal to or greater than the number of qubits. Some of the 110 gates can be used to modulate tunnel couplings between qubits. In general, a higher number of gates allows better control of the qubit confinement potentials, making them easier to manipulate and couple.

[0062] The grids 110, or a portion of these grids 110, may be arranged directly above electron (or hole) confinement regions formed in the layer 106 (case of the first configuration described previously) or in the layer 104 (case of the second configuration described previously). This corresponds to the case where these grids 110 act in accumulation mode by attracting the electrons (or holes) below themselves.

[0063] Alternatively, in the case where a two-dimensional gas of electrons (or holes) is already present in the absence of potentials applied to the grids 110, the grids 110 or a part of these grids 110 can act in depletion mode by repelling the electrons (or holes). As a result, the electron (or hole) qubits are located between the grids 110, either in the layer 106 (case of the first configuration described previously), or in the layer 104 (case of the second configuration described previously). This gas of electrons or holes can result:

[0064] - deliberate doping, for example of layer 104. The carriers released in layer 104 are in this case captured by layer 106 whose band gap is smaller. This deliberate doping is generally introduced in an atomic plane of layer 104 (delta doping type doping), with densities for example between 10 11 and 10 12 at / cm 2,

[0065] - doping due to the presence of defects at the interface between layer 104 and the surface of the device which release charges,

[0066] - the presence of a global gate on the rear face (under the layer 106, for example formed by the substrate 102 itself). Suitably polarized, this global gate attracts carriers in the layer 106, and the resulting gas is then depleted, or emptied of its charges, locally with the gates 110. A variant of the first embodiment is described below in connection with figures 4 and 5. In the example described in these figures, the production of the gate of a single qubit is described. However, as previously, this method is implemented to produce a quantum device 100 comprising several qubits for example arranged in the form of a matrix and such that each qubit can interact with one or more neighboring qubits.

[0067] As in the example previously described, the stack of layers 104 and 106 is produced on the substrate 102. The cavities 108 are then produced through a portion of the thickness t of the layer 104.

[0068] As shown in Figure 4, a layer 112 of dielectric material is then deposited against the walls (bottom wall and side walls) of the cavities 108 (a single cavity 108 is shown in Figure 4). The deposition implemented corresponds to a conformal deposition, that is to say that the thickness of the layer 112 is substantially constant over all of the walls covered by the layer 112. The layer 112 can then entirely cover the bottom wall as well as the side walls of the cavity 108. The thickness of the layer 112 is advantageously less than or equal to 10 nm. The dielectric material of the layer 112 corresponds for example to an oxide such as AhCh or SiO?, or to a nitride such as AIN or SisIXk, or to another dielectric material. Alternatively, it is possible that layer 112 corresponds to a stack of several different dielectric materials.

[0069] The grids 110 are then produced in the cavities 108, on the layer 112 such that the layer 112 is disposed between the walls of the cavities 108 and the grids 110 (a single grid 110 is visible in FIG. 5). As previously, the grids 110 each comprise at least one metallic material. The grids 110 may be produced by depositing one or more metallic materials in each of the cavities 108. Portions of this or these metallic materials deposited outside the cavities 108 may be removed by CMP or by other methods.

[0070] In the example shown in Figures 4 and 5, parts of the layer 112 are arranged outside the cavities 108. It is possible for these parts of the layer 112 to be removed before or after the production of the gates 110. Advantageously, in this embodiment, each cavity 108 can be entirely filled by a stack formed of the layer 112 of dielectric material and by the gate. An example of a method for producing a quantum device 100 with semiconductor qubits according to a second embodiment is described below in connection with Figures 6 to 8 corresponding to sectional views of the device produced. In the example described in these figures, the production of the gate of a single qubit is described. However, this method is implemented to produce a quantum device 100 comprising several qubits, for example arranged in the form of a matrix and such that each qubit can interact with one or more neighboring qubits.

[0071] As in the first embodiment, epitaxy steps are implemented in order to form on the substrate 102 a stack of semiconductors forming a heterostructure. In addition to the layers 104 and 106 similar to those produced in the first embodiment, the stack produced on the substrate 102 also comprises a layer 114 of a third semiconductor such that the layer 106 of the second semiconductor is arranged between the layers 104 and 114.

[0072] In this second embodiment, the first, second and third semiconductors of the layers 104, 106 and 114 are chosen such that the band gap energy of the second semiconductor is lower than that of the first and third semiconductors. Thus, the layers 104 and 114 of the first and third semiconductors form confinement potential barriers with respect to electrons or holes intended to be located in confinement regions formed in the layer 106 of the second semiconductor.

[0073] In this stack, the first and third semiconductors of layers 104 and 114 are therefore intended to form potential barriers with respect to confinement regions formed in the second semiconductor of layer 106. When the first and third semiconductors are SiGe and the second semiconductor is Si, the charge carriers intended to be confined are electrons, whereas when the first and third semiconductors are SiGe and the second semiconductor is Ge, the charge carriers intended to be confined are holes. The thickness t of layer 104 is for example similar to that previously described in the first embodiment. The thickness of layer 106 is for example between 5 nm and 50 nm and advantageously between 10 nm and 20 nm.

[0074] The thickness of the 114 layer may vary from a few nanometers to typically 10 micrometers or more. This thickness is chosen based on the possible need to relieve stresses induced by differences in lattice parameters between the 114 layer and the substrate 102. The stoichiometric composition of the 114 layer may vary during epitaxial growth to achieve the desired composition with the desired stress state.

[0075] As in the first embodiment previously described, the cavities 108 are then produced in a part of the thickness t of the layer 104 (see figure 7 in which a single cavity 108 is visible), then the grids 110 are produced in the cavities 108 (see figure 8 in which a single grid 110 is visible).

[0076] A variant of the second embodiment is described below in connection with Figures 9 and 10. In the example described in these figures, the production of the gate of a single qubit is described. However, as previously, this method is implemented to produce a quantum device 100 comprising several qubits, for example arranged in the form of a matrix and such that each qubit can interact with one or more neighboring qubits.

[0077] As in the example previously described, the stack of layers 104, 106 and 114 is produced on the substrate 102. The cavities 108 are then produced through a portion of the thickness t of the layer 104.

[0078] As shown in Figure 9, a layer 112 of dielectric material, for example similar to that previously described in connection with Figures 4 and 5, is then deposited against the walls (bottom wall and side walls) of the cavities 108 (only one cavity 108 is visible in Figure 9). The deposition implemented corresponds to a conformal deposition.

[0079] The grids 110 are then produced in the cavities 108, on the layer 112 such that the layer 112 is arranged between the walls of the cavities 108 and the grids 110 (a single grid 110 is visible in FIG. 10). As previously, the grids 110 comprise at least one metallic material. The grids 110 can be produced by depositing one or more metallic materials in each of the cavities 108. Portions of this or these metallic materials deposited outside the cavities 108 can be removed by CMP or lift-off or a controlled etching process, possibly through a masking layer having previously undergone a lithography step.

[0080] The various variants and alternatives previously described for the first embodiment may be applied to the second embodiment.

[0081] Figure 11 schematically represents a top view of an example of arrangement of several grids 110 of a device 100 comprising several qubits. In this example, each grid 110 comprises a section, in the upper face plane of the layer 104 through which the grids 110 are produced, in the shape of a disc, and of diameter d for example between 10 nm and 200 nm. In addition, the centers of two neighboring grids 110 are spaced apart by a distance a for example between 10 nm and 250 nm and greater than the diameter d. Of course, other grid shapes can be envisaged.

[0082] Figure 12 represents results of simulations carried out to compare the susceptibility to charge disorder of a device 100 comprising several qubits whose gates are produced as shown in Figure 11 with respect to a quantum device of the prior art comprising several qubits, whose elements are produced with the same materials (first and third semiconductors corresponding to Sio,2Geo,8; second semiconductor corresponding to Ge) and the same dimensions as for the device 100, but whose gates are produced on the upper surface of a semiconductor layer (and not in a cavity previously formed in the semiconductor layer as in the device 100).In order to obtain a suitable comparison, the thickness of the semiconductor layer on which the gates are made in the prior art device is chosen to be equal to the thickness of the remaining portions of layer 104 located under the cavities of the simulated device 100 in order to ensure essentially the same level of electrostatic coupling between the control gates and the electrons or holes in the underlying quantum dots. In Figure 12, curves 10, 20 and 30 represent, for device 100, the variability, or standard deviation, of the gyromagnetic factors along each of the X, Y and Z axes for values ​​of the gate diameter d ranging from 20 nm to 60 nm. Curves 12, 22 and 32 represent these same values ​​for the prior art quantum device having the gates made above the semiconductor layer.Curve 40 represents the variability of the energy level Eo of the first hole confined in one of the quantum dots of the device 100 for values ​​of the gate diameter d ranging from 20 nm to 60 nm, and curve 42 represents the variability of this same energy level Eo for the quantum device of the prior art comprising the gates produced above the semiconductor layer. The results shown in Figure 12 were obtained with the following parameters:.

[0083] - average charge density at the interface between the first semiconductor and the dielectric layer equal to 10 11 cm -2 ;

[0084] - thickness h = 20 nm;

[0085] - thickness t of the 104 layer = 100 nm;

[0086] - distance a = 80 nm.

[0087] These simulations implicitly imply that the interfacial charges located between the grids generate a much greater electrostatic disorder than the charges located on the interfaces covered by the metal grids. This is a consequence of the screening effect by the grid itself. The use of grids 110 such as proposed in the device 100 therefore makes it possible to move away the less screened charges (trapped on the surface between the grids), reducing the variability due to the charge disorder. The greater the ratios a / d and t / h (with t corresponding to the thickness of the layer 104 in which the grids 110 are made), the more advantageous the use of grids such as proposed in the device 100. In particular, these simulations show that the variability of the energy level Eo can be reduced by a factor of 4 if a / d > 2. The variability decreases with the ratio t / h up to t / h = 3 and it tends to saturate for t / h > 3.In the simulations whose results are shown in Figure 12, the value of the t / h ratio is equal to 5.

Claims

CLAIMS 1. Quantum device (100) with semiconductor qubits, comprising at least: - a layer (104) of a first semiconductor arranged on a layer (106) of a second semiconductor whose bandgap energy is different from that of the first semiconductor, such that one of the layers (104, 106) forms a confinement potential barrier with respect to electrons or holes intended to be located in confinement regions formed in the other layer (104, 106); - cavities (108) formed through only part of the thickness of the layer (104) of the first semiconductor, - electrically conductive control grids (110), each arranged at least partly in one of the cavities (108).

2. The quantum device (100) of claim 1, wherein each of the control gates (110) comprises at least one metallic material.

3. Quantum device (100) according to one of the preceding claims, in which: - the semiconductor of said one of the layers (104, 106) forming the confinement potential barrier is AIGaAs and the semiconductor of said other layer (104, 106) is GaAs, or - the semiconductor of said one of the layers (104, 106) forming the confinement potential barrier is SiGe and the semiconductor of said other layer (104, 106) is Si or Ge.

4. Quantum device (100) according to one of claims 1 or 2, further comprising a layer (114) of a third semiconductor such that the layer (106) of the second semiconductor is disposed between the layers (104, 114) of the first and third semiconductors, and in which the band gap energy of the second semiconductor is lower than those of the first and third semiconductors such that the layers (104, 114) of the first and third semiconductors form barriers of confinement potential with respect to electrons or holes intended to be located in the confinement regions formed in the layer (106) of the second semiconductor.

5. Quantum device (100) according to claim 4, wherein: - the first and third semiconductors are SiGe and the second semiconductor is Si or Ge, or - the first and third semiconductors are AIGaAs and the second semiconductor is GaAs.

6. Quantum device (100) according to one of the preceding claims, wherein the thickness of the layer (106) of the second semiconductor is between 5 nm and 50 nm and advantageously between 10 nm and 20 nm, and / or wherein the thickness of the layer (104) of the first semiconductor is between 5 nm and 200 nm and advantageously between 10 nm and 100 nm, and / or wherein the thickness of a portion of the layer (104) of the first semiconductor arranged under the cavities (108) is less than the thickness of the layer (104) of the first semiconductor and between 5 nm and 100 nm and advantageously between 5 and 30 nm.

7. Quantum device (100) according to one of the preceding claims, further comprising at least one layer (112) of dielectric material disposed at least between walls of each of the cavities (108) and each of the control gates (110).

8. Quantum device (100) according to claim 7, wherein the layer (112) of dielectric material has a thickness less than or equal to 20 nm and advantageously less than or equal to 10 nm.

9. Quantum device (100) according to one of the preceding claims, wherein the qubits are arranged to form a matrix of qubits.

10. Method for producing a quantum device (100) with semiconductor qubits, comprising at least: - production of a layer (104) of a first semiconductor on a layer (106) of a second semiconductor whose bandgap energy is different from that of the first semiconductor, such that one of the layers (104, 106) forms a confining potential barrier with respect to electrons or holes intended to be located in confining regions formed in the other layer (104, 106); - production of cavities (108) through a part of the thickness of the layer (104) of the first semiconductor; - production of electrically conductive control grids (110), each arranged at least partly in one of the cavities (108).

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