Electronic and optoelectronic devices

Abstract

An electronic device (10) in the form of a field effect transistor comprising a substrate (15) and a dielectric layer (20) on the substrate (15). The dielectric layer (20) comprises a polymeric dielectric layer (22) with a cyclic olefin copolymer. The electronic device (10) further comprises a semiconducting two-dimensional material (30) on the dielectric layer (20). The semiconducting two-dimensional material (30) is chosen from at least one of a chalcogenide, phosphorene, graphene or a combination thereof.

Description

DescriptionTitle: Electronic and optoelectronic devicesCross-Reference to Related Applications

[0001] This application claims priority of German Patent Application number DE 10 2022 130 378.0, filed on 16 November 2022. The entire disclosure of the German Patent Application number DE 10 2022 130 378. Ois hereby incorporated herein by reference.Field of the Invention

[0002] The invention comprises an electronic device and a method for manufacturing the electronic device.Background of the Invention

[0003] Two-dimensional semiconducting materials in electronic devices and, for example, in metal oxide semiconductor field effect transistors (MOSFETs) can be grown to an atomic scale thickness. The two-dimensional semiconducting materials are therefore promising candidates as transistor channel layers for a next generation of nanoelectronic devices.

[0004] The two-dimensional semiconducting materials are semiconducting layers located on a dielectric layer. Examples of suitable dielectric layers include, but are not limited to, silicon dioxide (SiCE), aluminium oxide (AI2O3), or hafnium (IV) oxide (HfCE). The dielectric layer is located on a metallic substrate which functions also as a bottom gate electrode. The metal substrate is, for example, heavily doped silicon (Si), aluminium (Al), indium tin oxide (ITO), or graphene. Such semiconductor layers are disclosed in, for example, Sebastian et al. in “Benchmarking monolayer M0S2 and WS2 field-effect transistors”, Nature Communications, 2021, 12: 69. Sebastian et al. describe a field effect transistor comprising a monolayer of M0S2 and WS2 as the semiconducting layer. The field effect transistor in this publication uses AI2O3 as the dielectric layer. The monolayer of M0S2 was grown on sapphire and transferred onto the AI2O3 dielectric layer via a poly(methyl methacrylate) (PMMA)-assisted transfer method.

[0005] Deposition of the two-dimensional semiconducting layer on the dielectric layer for manufacturing novel field effect transistor is an ongoing challenge for reproducibility of themanufacturing method. These challenges in the reproducibility lead to variations in the performance of the electronic devices, such as the field effect transistor in term of their output and their transfer characteristics.

[0006] Trap states are known to appear at the interface between the two-dimensional semiconducting layer and the dielectric layer during the deposition of the two-dimensional semiconducting layer on the dielectric layer. The trap states reduce the field effect mobility and result in a hysteresis of transfer characteristics of the field effect transistors. The traps states further give rise to a pronounced subthreshold behavior, leading to a reduction and masking of the intrinsic properties of the two-dimensional semiconducting layer. The trap states prevent utilization of intrinsic electronic properties of the two-dimensional semiconducting layer.

[0007] Attempts have been made to remove the trap states at the interface between the two- dimensional semiconducting layer and the dielectric layer. For example, Vu Qa et al. describe a method for manufacturing an electronic device comprising a step of encapsulating the transition metal di chalcogenide M0S2 in hexagonal boron nitride (h-BN) in “Near-zero hysteresis and near-ideal subthreshold swing in h-BN encapsulated single-layer M0S2 fieldeffect transistors”, 2D Mater. 2018, 5: 031001. The authors describe encapsulating the M0S2 channel between the top surface and the bottom surface of the dielectric layer made of the h-BN layer, followed by removing trap molecules in bubbles at interfaces between the h-BN dielectric layer and M0S2 by post-annealing. The exfoliating of the h-BN layer was one of the first approaches adopted to encapsulate the two-dimensional materials in a dielectric layer for field effect transistor applications. This approach lacks, however, scalability for standard cleanroom fabrication although the trap state density produced in this approach was low.

[0008] A more recent and potentially scalable attempt was to grow the h-BN dielectric layer by chemical vapor deposition (CVD) on aluminium oxide (AI2O3) grown by atomic layer deposition (ALD), as described in Piacentini et al., “Stable AI2O3 encapsulation of M0S2-FETS enabled by CVD grown h-BN”. Adv. Electron. Mater. 2022: 2200123. However, the field effect transistors using this method still exhibited rather large subthreshold swings of around 250 mV / decade suggesting that the trap densities of the high-k dielectric layer of AI2O3 with a stack formed by the h-BN layers is rather large.

[0009] US Patent application No. US 2016 / 0293769 Al describes an electronic device in the form of a field effect transistor comprising a multiple film active layer located between the dielectric layer and the gate layer. The multiple film active layer comprises further a metal oxide semiconductor layer and a metal oxide passivation layer. The metal oxide semiconductor layer in US 2016 / 0293769 Al comprises at least one of indium oxide (I Ch) and indium zinc oxide (InZnO). The metal oxide passivation layer in US 2016 / 0293769 Al comprises at least one of indium aluminium zinc oxide (InAlZnO) and aluminium zinc oxide (AlZnO).

[0010] Westermeier et al. describe in “Mapping of Trap Densities and Hotspots in Pentacene Thin-Film Transistors by Frequency-Resolved Scanning Photoresponse Microscopy,” Advanced Materials, 25 June 2013, an organic semiconductor field effect transistor. The field effect transistor of Westermeier comprises a semiconducting two-dimensional material made of a pentacene thin film on a dielectric layer.

[0011] Najafidehaghani et al. describe in “ID p-n Junction Electronic and Optoelectronic Devices from Transition Metal Di chalcogenide Lateral Heterostructures Grown by One-Pot Chemical Vapor Deposition Synthesis”, Advanced Functional Materials, 2 July 2021 a p-n junction comprising silicon as a substrate. The p-n junction further comprises a layer located on the substrate comprising silicon dioxide. The p-n junction comprises a semiconducting two-dimensional material on the silicon dioxide layer, wherein the semiconducting two-dimensional material comprises two transition metal dichalcogenides. The transition metal dichalcogenides are molybdenum diselenide and tungsten diselenide. The semiconducting two-dimensional material can have a lateral heterostructure.

[0012] Kalkan et al. describe in “Wafer scale synthesis of organic semiconductor nanosheets for van der Waals heterojunction devices,” npj 2D Materials and Applications, 3 December 2021, organic / inorganic p-n junctions and ambipolar devices. The p-n junctions and ambipolar devices comprise a substrate with silicon. A layer with silicon dioxide is located on the substrate. A semiconducting two-dimensional material with a transition metal di chalcogenide is located on the silicon dioxide layer. Kalkan et al. further describe an organic semiconducting layer located on the transition metal di chalcogenide layer. The organic semiconducting layer is selected from one of pentacene or dinaphtho[2,3-b:2’,3’- f]thieno[3,2-b]thiophene (DNTT).Summary of the Invention

[0013] An electronic device is taught in this disclosure. The electronic device comprises a substrate, a dielectric layer on the substrate and a semiconducting two-dimensional material on the dielectric layer. The dielectric layer comprises at least a polymeric dielectric layer with a cyclic olefin copolymer (COC). The semiconducting two-dimensional material is chosen from at least one of a chalcogenide, phosphorene, graphene or a combination thereof. The polymeric dielectric layer functions as a passivation layer.

[0014] In another aspect, the dielectric layer is a multiple layer comprising the polymeric dielectric layer located on an inorganic dielectric layer.

[0015] In one aspect, the inorganic dielectric layer is selected from at least one of silicon dioxide, silicon nitride, aluminium oxide, or hafnium oxide.

[0016] In a further aspect, the polymeric dielectric layer with the cyclic olefin copolymer comprises preferably ethylene and / or norbornene.

[0017] In one aspect, the chalcogenide is chosen from at least one of InSe, GaSe, GaS, SnS2, SnSe2, or a transition metal di chalcogenide of M0S2, WS2, MoSe2, WSe2, MoTe2, WTe2, PdSe2, PtSe2, PdTe2, PtTe2, PtS2, PdS2 or a combination thereof.

[0018] In one aspect, the semiconducting two-dimensional material has a vertical heterostructure or a lateral heterostructure.

[0019] The polymeric dielectric layer with the cyclic olefin copolymer is deposited in one aspect on the inorganic dielectric layer by spin coating to obtain an ultrathin polymeric dielectric layer.

[0020] The cyclic olefin copolymer is chemically inert and hydrophobic. The semiconducting two-dimensional material can therefore be deposited on the dielectric layer by a standard cleanroom process under ambient conditions and in presence of an organic solvent.

[0021] The presence of the polymeric dielectric layer leads to a lowering and a stabilization of the trap states density of almost fivefold. The lowering and the stabilization of the trap states density results in the obtention of a low-voltage electronic device. The photoresponsivity and the photoconductivity of the electronic device comprising the COC is also increased compared to an electronic device comprising no COC.

[0022] The transition metal dichalcogenides (TMDC) of the two-dimensional semiconducting materials are of interest because the transition metal di chalcogenides enable a furtherminiaturization of the electronic device, a higher heat transfer in the electronic device and enable the obtention of more flexible electronic device.

[0023] In one aspect, the polymeric dielectric layer comprises ethylene and / or norbornene.

[0024] In one aspect, the two-dimensional semiconducting material is a multi-layer material.

[0025] In a further aspect, the two-dimensional semiconducting material is a bilayer material.

[0026] In another aspect, the two-dimensional semiconducting material is a monolayer material.

[0027] In one aspect, the dielectric layer has a thickness between 1 nm and 1 pm.

[0028] In one aspect, the polymeric dielectric layer has a thickness between 2 nm and 500 nm.

[0029] In a further aspect, contacts are located on opposite sides on the two-dimensional semiconducting material. A method for manufacturing the electronic device is also taught in this disclosure. The method comprises depositing a dielectric layer on a substrate. The dielectric layer comprises at least a polymeric dielectric layer. The method further comprises depositing a semiconducting two-dimensional material on the dielectric layer. The semiconducting two-dimensional material is chosen from at least one of a chalcogenide, phosphorene, graphene or a combination thereof.

[0030] In one aspect, the polymeric dielectric layer in the method for manufacturing the electronic device comprises a cyclic olefin copolymer.

[0031] In one aspect, a transfer method is used for depositing the semiconducting two- dimensional material on the polymeric dielectric layer. In one aspect, the transfer method is a polymer assisted transfer method or a dry transfer method.

[0032] The field effect transistor is used in one aspect as a field effect transistor, a photodetector, a diode, a logic element, a photovoltaic device, an electroluminescent light emitting device, a solution gated field effect transistor, a two-dimensional material-based sensor or a saturable absorber.Description of the figures

[0033] Fig. 1A, Fig. IB and Fig. 1C show views of the electronic device. The electronic device is a field effect transistor. Fig. 1 A shows a view of the electronic device comprisingthe inorganic dielectric layer with no polymeric dielectric layer. Fig. IB shows an example of the field effect transistor with the dielectric layer comprising the polymeric dielectric layer located on the inorganic dielectric layer. Fig. 1C shows an example of the field effect transistor with the dielectric layer comprising only the polymeric dielectric layer and no inorganic dielectric layer.

[0034] Fig. 2A shows photoluminescence spectra of the field effect transistor comprising no polymeric dielectric layer (as a comparative example) and of the field effect transistor comprising the polymeric dielectric layer. Fig. 2B shows Raman spectra of the field effect transistor comprising no polymeric dielectric layer and the field effect transistor comprising the polymeric dielectric layer. Fig. 2C shows values of Raman peak characteristics of the field effect transistors with no polymeric dielectric layer of COC and with the polymeric dielectric layer of COC.

[0035] Fig. 3 A to Fig. 3E show transfer curves and characteristics of the field effect transistors comprising no polymeric dielectric layer and the field effect transistors comprising the polymeric dielectric layer under a drain voltage of 0.1 V. Fig. 3 A shows transfer characteristics of four field effect transistors comprising no polymeric dielectric layer and wherein the dielectric layer has a thickness of 300 nm. Fig. 3B shows transfer characteristics of four field effect transistors comprising the polymeric dielectric layer and wherein the inorganic dielectric layer has a thickness of 300 nm. Fig. 3C shows transfer characteristics of four field effect transistors comprising the polymeric dielectric layer and wherein the inorganic dielectric layer has a thickness of 100 nm. Fig. 3D shows subthreshold swings of field effect transistors comprising no polymeric dielectric layer and comprising the polymeric dielectric layer for different thicknesses of the inorganic dielectric layer. Fig. 3E shows transfer characteristics of four field effect transistors with no polymeric dielectric layer and wherein the inorganic dielectric layer has a thickness of 100 nm. Fig. 3F shows onset voltages, the subthreshold swing S, trap state density and hysteresis values of the field effect transistors with the polymeric dielectric layer and with no polymeric dielectric layer.

[0036] Fig. 4A and Fig. 4B show time-resolved photocurrent measurement of the field effect transistors comprising no polymeric dielectric layer and the field effect transistors comprising the polymeric dielectric layer under ambient conditions. The drain voltage in Fig. 4A and Fig. 4B is 10 V, the gate voltage is 5V, the laser power is 100 pW / cm2and the frequency is 1 kHz. Fig. 4C and Fig. 4D show time-resolved photocurrent measurement of the fieldeffect transistors comprising the polymeric dielectric layer under vacuum and illumination by 635 nm and 405 nm. The drain voltage in Fig. 4C is 20 V, the gate voltage is 5 V, the laser power is 10 pW / cm2and the frequency is 1 kHz. The drain voltage in Fig. 4D is 20 V, the gate voltage is -10 V, the laser power is 1.1 pW / cm2and the frequency is 0.2 Hz.

[0037] Fig. 4E shows the responsivity of the field effect transistors used as photodetectors.

[0038] Fig. 5 shows the photoresponsivity and the detectivity under vacuum and under ambient conditions of the field effect transistors with the polymeric dielectric layer and with no polymeric dielectric layer.

[0039] Fig. 6A shows the transconductance and Fig. 6B shows the mobility curves of the field effect transistor comprising the polymeric dielectric layer and comprising no polymeric dielectric layer for a drain voltage of 0.1 V.

[0040] Fig. 7A shows an AFM micrograph of the polymeric dielectric layer. Fig. 7B shows the height profile recorded at the step edge marked in white line on Fig. 7A.

[0041] Fig. 8 A and Fig. 8B show AFM micrographs of the field effect transistor comprising the polymeric dielectric layer after spin coating and after exposure to acetone for 19 hours.

[0042] Fig. 9 shows a flow chart describing the method for manufacturing the field-effect transistor.Detailed description of the invention

[0043] The invention will now be described on the basis of the figures. It will be understood that the embodiments and aspects of the invention described herein are only examples and do not limit the protective scope of the claims in any way. The invention is defined by the claims and their equivalents. It will be understood that features of one aspect or embodiment of the invention can be combined with a feature of a different aspect or aspects and / or embodiments of the invention.

[0044] Fig. 1 A, Fig. IB and Fig. 1C show views of an electronic device 10 in the form of a field effect transistor. The electronic device 10 ofFig. 1 A, IB and 1C comprises a dielectric layer 20 as a gate dielectric and comprising at least one of an inorganic dielectric layer 25 or a polymeric dielectric layer 22. Fig. 1A shows a comparative view of an electronic device 10 in the form of a field effect transistor as known in the prior art. The field effect transistor10 of Fig. 1A comprises a substrate 15 and an inorganic dielectric layer 25 as the gate dielectric located on the substrate 15. The substrate 15 comprises, for example, silicon and the inorganic dielectric layer 25 comprises, for example, silicon dioxide. The prior art field effect transistor 10 of Fig. 1 A does not comprise a polymeric dielectric layer 22.

[0045] The field effect transistor 10 of Fig. 1A, Fig. IB and Fig. 1C comprises a two- dimensional semiconducting material 30 located on the top surface of the dielectric layer 20. The two-dimensional semiconducting material 30 is a monolayer. In one example, the two- dimensional semiconducting material 30 is a transition metal dichalcogenide, such as M0S2. As noted above, the two-dimensional semiconducting material can be InSe, GaSe, GaS, SnS2, SnSe2, WS2, MoSe2, WSe2, MoTe2, WTe2, PdSe2, PtSe2, PdTe2, PtTe2, PtS2, PdS2, phosphorene, graphene or a combination thereof. The two-dimensional semiconducting material can have a lateral heterostructure or a vertical heterostructure known as van der Waals heterostructure.

[0046] The field effect transistor 10 has contacts 35 which are located on opposite sides on the semiconducting two-dimensional material 30.

[0047] Fig. IB shows an example of the field effect transistor 10, wherein the dielectric layer 20 is a multiple layer. One layer of the multiple layer is the inorganic dielectric layer 25 located on the substrate 15. The inorganic dielectric layer 25 in Fig. IB is silicon dioxide The dielectric layer 20 further comprises the polymeric dielectric layer 22 with a cyclic olefin copolymer. The term “cyclic olefin copolymer” is used for co-polymers which are produced by chain copolymerization of cyclic monomers with ethene and / or norbornene. Examples of such cyclic olefin copolymers include Schott Toppac, Apel from Mitsui Chemicals and TOPAS advanced polymers. The polymeric dielectric layer 22 is located on top of the inorganic dielectric layer 25. The two-dimensional semiconducting material 30 of the field effect transistor 10 is located on top of the polymeric dielectric layer 22.

[0048] Fig. 1C shows another aspect of the field effect transistor 10 comprising the polymeric dielectric layer 22 located on the substrate 15 with no inorganic dielectric layer 25. The polymeric dielectric layer 22 forms the gate dielectric.

[0049] Fig. 2A to Fig. 8B show the field effect transistors 10 with the inorganic dielectric layer 25 made of silicon dioxide (SiO2) and the two-dimensional semiconducting material 30 made of molybdenum disulfide (MoS2).

[0050] The trap state density at the interface between the two-dimensional semiconducting material 30 and the inorganic dielectric layer 25 can be determined by applying Shockley’s equations for ideal linear and saturation field effect transistor regimes by a pronounced subthreshold regime.

[0051] The subthreshold swing S is the gate voltage difference required to increase the drain current of the field effect transistor 10 by one decade. The field effect transistor 10 comprising ideally no traps has a subthreshold swing S at room temperature of around 60 mV / decade. The value of 60 mV / decade is known as the thermionic limit.

[0052] The subthreshold swing S of the field effect transistor 10 comprising traps has a subthreshold swing S given by the following equation:S = ^ - (l + a) (1) decade where a is a correction constant depending on the depletion layer of the two-dimensional semiconducting material 30 and depending on the trap state density at the interface between the two-dimensional semiconducting material 30 and the inorganic dielectric layer 25.

[0053] When the field effect transistor 10 comprises at least one layer of the two-dimensional semiconducting material 30, the correction a depends substantially on the trap state density at the interface. The subthreshold swing S is therefore given by: _ 60 mV decadewhere Ci is the capacitance of the dielectric layer 20, e is the elementary charge and Ninteris the interface trap state density. The unit of Ninter is cm'2eV_ |.

[0054] Fig. 2A shows that the characteristic photoluminescence (PL) peak of the field effect transistor 10 comprising the two-dimensional semiconducting material 30 made of M0S2. The field effect transistor 10 in Fig. 2A comprising no polymeric dielectric layer 22 (i.e., the comparative example) is substantially 670 nm. The PL intensity increases by at least 6 times for the field effect transistor 10 with the two-dimensional semiconducting material 30 of M0S2 and with the polymeric dielectric layer 22 with COC.

[0055] Fig. 2B shows the Raman spectra of the field effect transistor 10 of the comparative example (i.e., without the COC polymeric dielectric layer 22 and of the field effect transistor 10 with two-dimensional semiconducting material 30 of M0S2 and the polymeric dielectric layer 22 of COC. Fig. 2B and Fig. 2C show further the vibrational modes E’ and AT of M0S2. Substantially higher intensity and lower full width at half maximum (FWHM) is shown onFig. 2B for the field effect transistor 10 with the polymeric dielectric layer 22 of COC in comparison to the comparative example. Fig. 2B shows a blueshift of the peaks of the vibrational modes E’ and A'i peaks for the field effect transistor 10 with the polymeric dielectric layer 22 of COC.

[0056] Fig. 3 A shows the characteristic transfer curves of four of the field effect transistors 10 deposited on a chip. Fig. 3F shows characteristic values of the four field effect transistors 10. The four field effect transistors 10 of Fig. 3A do not comprise a polymeric dielectric layer 22. The layer 20 of SiO2 has a thickness of 300 nm. The characteristic transfer curves of the field effect transistors 10 vary in terms of onset voltage. Fig. 3 A shows onset voltages varying statistically from -20 V to -8 V. The variation of the onset voltages indicates that the top surface B of the SiCh layer 20 comprises heterogeneous traps. The mean value of the subthreshold swing S is 1566 ± 460 mV / decade. The substantially large value of the subthreshold swing S corresponds to a mean trap state density Ninter of 1.88 x 1012cm'2eV . The value of the subthreshold swing S increases with the onset voltage. The hysteresis of the field effect transistor 10 is lower when the onset voltage is lower, given as dashed line in Fig. 3 A. The mean value of the hysteresis of the field effect transistor 10 can be for example 725 ± 375 mV. The field effect transistors 10 with no polymeric dielectric layer 22 are substantially dominated by a large amount of heterogeneous interface traps.

[0057] Fig. 3B shows the characteristic transfer curves of four field effect transistors 10 deposited on a chip comprising the polymeric dielectric layer 22 of COC. The thickness of the SiO2 inorganic dielectric layer 25 of SiO2 is 300 nm. The mean onset voltage is reduced to -0.9 V ± 0.5 V by comparison to the field effect transistors 10 comprising no polymeric dielectric layer 22, as can be seen on Fig. 3F. The decrease of the mean onset voltage indicates a substantial reduction of the traps state density Ninter Therefore, since the variation of the onset voltage is reduced as well, it is suggested that the field effect transistors 10 with the polymeric dielectric layer 22 are compatible with low voltage applications. The mean value of the subthreshold swing S is 484 mV / decade. The subthreshold swing S is lowered by a factor of 4 compared to field effect transistors 10 comprising no polymeric dielectric layer 22. The value of the subthreshold swing S corresponds to a mean trap state density Ninter of 5.05 x 1011cm^eV'1. The subthreshold swing S was decreased from 484 mV / decade for a thickness of the inorganic dielectric layer 25 SiCh of 300 nm to a subthreshold swing S of 189 mV / decade for a thickness of the inorganic dielectric layer 25 SiCh of 100 nm asshown in Fig. 3C. This huge reduction of the subthreshold swing S is in line with a projected higher gate capacitance for the inorganic dielectric layer 25 of 100 nm oxide thickness.

[0058] The field effect transistor 10 comprising the polymeric dielectric layer 22 of COC can compete with sophisticated ultrathin ALD-grown oxides in terms of trap density.

[0059] Fig. 3E shows the characteristic transfer curves of four field effect transistors 10 deposited on a chip without the polymeric dielectric layer 22. The field effect transistors 10 comprise the inorganic dielectric layer 25 SiCh and the thickness of the inorganic dielectric layer 25 is 100 nm. The subthreshold swing S is 1.5 times lower than the subthreshold swing S of the field effect transistors 10 with no COC and thickness of the SiO2 layer of 300 nm.

[0060] Fig. 3D shows that the subthreshold swing S of the field effect transistors 10 with the polymeric dielectric layer 22 of COC and the SiO2 layer 20 with a thickness of 100 nm (circles) is 189 mV / decade. The reduction of the subthreshold swing S by decreasing the thickness of SiO2 from 300 nm to 100 nm can be seen on Fig. 3D. The mobility of the field effect transistor 10 comprising the polymeric dielectric layer 22 of COC is substantially 4 cm2V1s'1. The field effect transistors 10 comprising only SiO2 approach the value of 4 cm2V 1 of the mobility at a gate voltage of substantially 5 V.

[0061] Fig. 4A - 4B show time-resolved photocurrent (PC) measurements under ambient conditions for the field effect transistors 10 with no polymeric dielectric layer 22 and with the polymeric dielectric layer 22. The drain voltage is 10 V, and the gate voltage is 5 V. The field effect transistors 10 are illuminated with a 635 nm laser diode having a pulse frequency of 1 kHz and power density of 100 pW / cm2.

[0062] The photoresponsivity R, is defined as the generated photocurrent per unit power of the incident light. The photoresponsivity R, is:(3 )where Iph is the photocurrent and k is the dark current.

[0063] The detectivity D*of the field effect transistors 10 is:where S is the effective area of the field effect transistor 10.

[0064] Fig. 5 shows that the field effect transistors 10 comprising the polymeric dielectric layer 22 have higher photoresponsivity R, values by substantially three orders of magnitudethan the field effect transistor 10 comprising no polymeric dielectric layer 22. The detectivity limit is further improved by at least one order of magnitude as shown in Fig. 5

[0065] The rise of the photocurrent and the decay time constants of the field effect transistors 10 comprising the polymeric dielectric layer 22 are substantially in the range of 50 ps corresponding to the resolution limit of a source measure unit.

[0066] The field effect transistors 10 with no polymeric dielectric layer 22 have a common positive photoconductivity (PPC). The field effect transistors 10 comprising the polymeric dielectric layer 22 have a negative photoconductivity (NPC). Balanced minority carrier traps and recombination centers at the top surface B of the dielectric layer 20 result in the negative photoconductivity of the field effect transistor 10. In one example, the two-dimensional semiconducting material 30 of the field effect transistor 10 is made of M0S2 and has hole traps. The field effect transistor 10 is illuminated by monochromatic (635 nm or 405 nm) light and this illumination results in a release of minority charge carriers in the two-dimensional semiconducting material 30. The released minority carriers recombine non-radiatively via recombination centres with majority carriers in the M0S2 layer 30. The conductivity in the M0S2 layer 30 is thereby reduced, resulting in the NPC of the field effect transistor 10.

[0067] Fig. 4C shows time-resolved photoconductivity measurements under vacuum for the field effect transistors 10 comprising the polymeric dielectric layer 22. The field effect transistors 10 are illuminated under a pulsed illumination of 635 nm by a laser at an intensity of 10 pW / cm2and a frequency of 1 kHz. The drain voltage is 20 V, and the gate voltage is 5 V. Fig. 4C shows that high vacuum further increases the photoresponsivity and the detectivity values at least tenfold compared to ambient conditions, as can be seen on Fig. 5.

[0068] Fig. 4D and Fig. 5 shows time-resolved photoconductivity measurements under vacuum for the field effect transistors 10 with the polymeric dielectric layer 22. The field effect transistors 10 is illuminated under a pulsed illumination of 405 nm by a laser. The laser has an intensity of 1 pW / cm2and a frequency of 0.2 Hz. The photoresponsivity of the field effect transistor 10 is 3.0 x 107AAV. The detectivity of the field effect transistor 10 is 4.8 x io15Jones. The photoresponsivity values of the field effect transistor 10 obtained from the time-resolved photoconductivity measurements under vacuum are the highest reported values for field effect transistors comprising transition metal dichalcogenides, as can be seen on Fig. 4E.

[0069] The transconductance for the field effect transistors 10 with the polymeric dielectric layer 22 and with no polymeric dielectric layer 22 (bare) is shown in Fig. 6A. A plateau in the transconductance curve can be seen for the field effect transistor 10 with the polymeric dielectric layer 22 when the gate voltage is about 0.5 V. The transconductance curve for the field effect transistor 10 with no polymeric dielectric layer 22 (i.e., bare, shown as continuous line) does not show this plateau. The reason for this lack of the plateaus is that the field effect transistor 10 with no polymeric dielectric layer 22 is dominated by co-called “subthreshold behavior”. The transconductance is not constant as the transconductance is in the linear region. .

[0070] The mobility obtained from the transconductance by the formula of the field effect transistor 10 drift current in the linear region is shown in Fig. 6B. The mobility of the field effect transistor 10 with the polymeric dielectric layer 22 is 4 cm2V1s'1for a drain voltage of 100 mV. The mobility of the field effect transistor 10 with no polymeric dielectric layer 22 is 1 cm2V1s'1at a gate voltage of 1 V. The mobility of the field effect transistor 10 with no polymeric dielectric layer 22 increases with gate voltage to be 4 cm2V1s'1at a gate voltage of 5 V.

[0071] In one example, the field effect transistor 10 comprising a polymeric dielectric layer 22 can be used as an optoelectronic device, for example a photodetector.

[0072] Fig. 9 shows a method for manufacturing the field-effect transistor 10. In step SI 10, the dielectric layer 20 is deposited on the substrate 15. In the aspect shown in Fig. IB, the silicon dioxide layer with a thickness of 300 mm is formed by thermal oxidation of the top surface of the substrate 15 made of silicon.

[0073] In step SI 15, the semiconducting two-dimensional material 30 is deposited on a substrate. The deposition SI 15 is for example carried out by chemical vapor deposition (CVD).

[0074] In step S120, the two-dimensional semiconducting material 30 is deposited on the polymeric dielectric layer 22 from the substrate using a transfer method. The transfer method is for example a poly (methyl methacrylate) (PMMA) transfer method.

[0075] In one example, the field effect transistor 10 is used as a photodetector, a diode, a logic element, or a saturable absorber. The field effect transistor 10 can further comprise two or more dielectric layers 25 located one above the other as to be used as a p-n junction, p-n- p junction or p-i-n junction.

[0076] In another example, the field effect transistor can be used to block, reflect, transmit light in the field effect transistor or to reduce contact resistance in the field effect transistor.Examples

[0077] Deposition and growth in step SI 15 of the two-dimensional semiconducting material 30. The two-dimensional semiconducting material 30 was M0S2 deposited on a support substrate. The support substrate was a thermally oxidized substrate silicon (Siltronix) with an SiCh layer and had a thickness of 300 nm. The root mean square (RMS) roughness of the support substrate was below 0.2 nm. The M0S2 two-dimensional semiconducting material 30 was deposited and grown on the substrate by chemical vapor deposition in which a Knudsen-type effusion cell was used for delivering sulfur precursors.

[0078] Preparation of the polymeric dielectric layer 22 comprising the COC. The COC was TOPAS 6013-S04. The COC was dissolved in toluene. The COC concentration in toluene was 0.25 wt. %. The solution comprising the COC and toluene was centrifuged for 10 min at 8000 rpm. Then, the solution comprising the COC and toluene was spin-coated as a layer on the SiChlayer for 60 s at 6000 rpm. The COC layer was annealed at 100 °C for 3 min to evaporate the toluene.

[0079] Fabrication of the field effect transistor 10. The two-dimensional semiconducting material 30 M0S2 was transferred in step S120 onto the polymeric dielectric layer 22 comprising the COC using the PMMA assisted transfer method. This transfer resulted in the fabrication of the field effect transistor 10 with the layer of M0S2, a film of PMMA and the polymeric dielectric layer 22 of COC. The field effect transistor 10 was immersed into acetone for 2 hours to remove the film of PMMA. Then, the PMMA (950K A4) was spin-coated on the surface of the two-dimensional semiconducting material 30 of M0S2 and the field effect transistor 10 was annealed at 100 °C for 10 min. A solution comprising methyl isobutyl ketone (MIBK):2-propanol in a ratio of 1 :3 was developed on layer 30 of M0S2 of the field effect transistor 10 for 50 s. The contacts 35 comprising titanium (Ti) and gold (Au) were deposited by physical vapor deposition or sputtering onto the layer 30 of M0S2. The field effect transistor 10 was immersed into acetone for 3 hours to complete lift off process. The surface of the field effect transistor 10 was shown on Fig. 8A and Fig. 8B. The thickness of the polymeric dielectric layer 22 was calculated as shown on Fig. 7A and 7B. The fieldeffect transistor 10 were subjected to a cleanroom nanofabrication procedure for optoelectronic measurements.

[0080] Device Characterization. A home-built ambient probe station coupled to Keithley 2612B was used as a source measure unit for the characterization of the field effect transistor 10 under dark conditions.

[0081] Optical Characterization. Steady-state photoluminescence measurements were conducted using a pulsed laser (NKT Photonics, SuperK Fianium FIU-15) at an excitation wavelength of 532 nm. The pulsed laser was operated with an excitation power of 10pW / cm2. The light was collected with a 20x objective. Steady-state photoluminescence spectra were measured using a SpectraPro HRS-500 spectrometer with a 150 mm'1grating and a PIXIS charge coupled device (all Teledyne Princeton Instruments).

[0082] Raman spectroscopy. Raman spectra were acquired using a Bruker Senterra spectrometer operated in b ackscattering mode at ambient conditions. Measurements at 532 nm were obtained with a frequency-doubled neodymium-doped yttrium aluminum garnet (Nd:YAG) Laser, a 50x objective and a thermoelectrically cooled charge-coupled device (CCD) detector. The spectral resolution of the spectrometer coupled to the Nd: YAG Laser, the objective and the detector was 2 cm'1to 3 cm'1. The Si peak at 520.7 cm'1was used for all Raman spectra for peak shift calibration of the spectrometer.

[0083] Optoelectronic Measurements. An optoelectronic characterization of the field effect transistor 10 was carried out with two Keithley 2634B source measurement units. A first measurement unit was used to change the gate voltage and measure the gate current. A second measurement unit was used to apply the drain voltage and measure the drain current with respect to the grounded source. A Lakeshore vacuum needle probe station TTPX was used to measure the characteristics of the devices in ambient as well as in vacuum at a residual pressure about 10'6mbar at room temperature. The field effect transistor 10 was illuminated using 635 nm and 405 nm single mode fiber pigtailed laser diodes (LP520-SF15 and LP405C1, Thorlabs). The laser diodes were driven using a Thorlabs laser diode controller (ITC4001).Reference numerals10 electronic device15 substrate 20 dielectric layer25 inorganic dielectric layer22 polymeric dielectric layer30 semiconducting two-dimensional material35 contacts

Claims

Claims1. An electronic device (10) comprising: a substrate (15); a dielectric layer (20) on the substrate (15), wherein the dielectric layer (20) comprises at least a polymeric dielectric layer (22) with a cyclic olefin copolymer; a semiconducting two-dimensional material (30) on the dielectric layer (20), wherein the semiconducting two-dimensional material (30) is chosen from at least one of a chalcogenide, phosphorene, graphene or a combination thereof.

2. The electronic device (10) of claim 1, wherein the polymeric dielectric layer (22) with the cyclic olefin copolymer comprises preferably ethylene and / or norbomene.

3. The electronic device (10) of any of the above claims, wherein the chalcogenide is chosen from at least one of InSe, GaSe, GaS, SnS2, SnSe2, or a transition metal dichalcogenide of M0S2, WS2, MoSe2, WSe2, MoTe2, WTe2, PdSe2, PtSe2, PdTe2, PtTe2, PtS2, PdS2 or a combination thereof.

4. The electronic device (10) of any of the above claims, wherein the semiconducting two-dimensional material (30) has a vertical heterostructure or a lateral heterostructure.

5. The electronic device (10) of any of the above claims, wherein the semiconducting two-dimensional material (30) is a multilayer material, a bilayer material or a monolayer material.

6. The electronic device (10) of any of the above claims, wherein the dielectric layer (20) has a thickness between 1 nm and 1 pm.

7. The electronic device (10) of any of the above claims, wherein the polymeric dielectric layer (22) has a thickness between 2 nm and 500 nm.

8. The electronic device (10) of any of the above claims, wherein the dielectric layer (20) is a multiple layer comprising the polymeric dielectric layer (22) located on an inorganic dielectric layer (25).

9. The dielectric layer (20) of claim 892, wherein the inorganic dielectric layer (25) is selected from at least one of silicon dioxide, silicon nitride, aluminium oxide, or hafnium oxide.

10. The electronic device (10) of any of the above claims, wherein contacts (35) are located on opposite sides on the semiconducting two-dimensional material (30).

11. A method for manufacturing an electronic device (10) comprising: depositing (SI 10) a dielectric layer (20) on a substrate (15), wherein the dielectric layer (20) comprises at least a polymeric dielectric layer (22); depositing (S120) a semiconducting two-dimensional material (30) on the dielectric layer (20), wherein the semiconducting two-dimensional material (30) is chosen from at least one of a chalcogenide, phosphorene, graphene or a combination thereof.

12. The method of claim 11, wherein the deposition (SI 10) of the dielectric layer (20) on the substrate (15) comprises a step of spin-coating the polymeric dielectric layer (22).

13. The method of claims 11 or 12, wherein depositing (S120) the semiconducting two- dimensional material (30) on the dielectric layer (20) is by a transfer method.

14. The method of claims 11 to 13, wherein the transfer method is chosen from at least one of a polymer assisted transfer method or a dry transfer method.

15. The method of claims 11 to 14, wherein growing (SI 15) the semiconducting two- dimensional material (30) on a silicon substrate by using chemical vapor deposition (CVD), exfoliation, metalorganic chemical vapor deposition (MOCVD), atomiclayer deposition (ALD) or molecular self-assembly is prior to the deposition (S120) of the semiconducting two-dimensional material (30) on the dielectric layer (20).

16. The method of claims 11 to 15, wherein the polymeric dielectric layer (22) comprises a cyclic olefin copolymer and preferably ethylene and / or norbornene.

17. The method of claims 11 to 16, wherein the semiconducting two-dimensional material (30) is deposited as a monolayer material.

18. The method of claims 11 to 17, wherein the chalcogenide is chosen from at least one of InSe, GaSe, GaS, SnS2, SnSe2 or a transition metal di chalcogenide of M0S2, WS2, MoSe2, WSe2, MoTe2, WTe2, PdSe2, PtSe2, PdTe2, PtTe2, PtS2, PdS2 or a combination thereof.

19. The method of claims 11 to 18, wherein the substrate (15) comprises an inorganic dielectric layer (25) located on a silicon substrate.

0. Use of the electronic device (10) of claims 1 to 10 as a field effect transistor, a photodetector, a diode, a logic element, a photovoltaic device, an electroluminescent light emitting device, a solution gated field effect transistor, a two dimensional material based sensor, or a saturable absorber.

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