Structure comprising a surface layer transferred to a support provided with a charge trapping layer with limited contamination and method for manufacturing same

Abstract

Device comprising a ferroelectric surface layer (20) containing lithium; a dielectric layer (16) comprising an oxide and arranged in contact with the ferroelectric surface layer; and a substrate (10) in contact with the dielectric layer, the substrate comprising a charge trapping layer (14) arranged on a support (12), the charge trapping layer (14) being arranged between the support (12) and the dielectric layer (16), the dielectric layer (16) having a thickness of between 150 nm and 500 nm, preferably between 150 nm and 300 nm; and a nitrogen concentration in the dielectric layer (16) and a surface roughness of the charge trapping layer (14) being such that the charge trapping layer (14) has a lithium content of less than 5x1011at / cm2.

Description

STRUCTURE COMPRISING A SURFACE LAYER TRANSFERRED TO A SUPPORT PROVIDED WITH A CHARGE-TRAPPING LAYER WITH LIMITED CONTAMINATION AND MANUFACTURING METHOD TECHNICAL FIELD OF THE INVENTION

[0001] The invention relates to a structure comprising a surface layer transferred onto a support provided with a charge trapping layer, the structure being capable of limiting the pollution of the charge trapping layer by contaminants. The invention extends to a method of manufacturing this structure. TECHNOLOGICAL BACKGROUND

[0002] Integrated devices are usually developed on wafer-shaped substrates, which mainly serve as a support for their manufacture. However, the increase in the degree of integration and the expected performance of these devices leads to an increasingly significant coupling between their performance and the characteristics of the substrate on which they are formed. This is particularly the case for radiofrequency (RF) devices, processing signals with a frequency between approximately 3kHz and 300GHz, which find their application in particular in the field of telecommunications (telephony, Wi-Fi, Bluetooth, etc.).

[0003] As an example of device / substrate coupling, electromagnetic fields from high-frequency signals propagating in devices penetrate into the depth of the substrate and interact with any electrical charge carriers present there. This results in unnecessary consumption of part of the signal energy due to insertion loss and possible influences between components due to crosstalk.

[0004] Highly resistive silicon-on-insulator (HR SOI) substrates are thus known, comprising a silicon support substrate having a resistivity greater than 1 kOhm.cm, a dielectric layer on the support substrate, and a surface layer of silicon arranged on the dielectric layer. The support substrate may also comprise a charge trapping layer which will be arranged on the side of the dielectric layer, preferably in contact with it. The trapping layer may comprise undoped polycrystalline silicon. The manufacture of this type of substrate is for example described in documents FR2860341, FR2933233, FR2953640, US2015115480, US7268060, US6544656 or WO20211008742.

[0005] Surface acoustic wave (SAW) devices with composite structures incorporating a surface layer of ferroelectric material and a charge trapping layer are also known, forming a substrate similar to that described in the previous paragraph, as detailed for example in document WO 2020 / 200986. These devices are used in many applications, and in particular in electronic applications where they form the central element of filters, oscillators, delay lines or even transformers.

[0006] When an alternating electrical signal is applied to a transducer formed of one or more electrodes in contact with the ferroelectric material, in addition to an electrical wave as described above, a corresponding mechanical signal (i.e. an oscillation or a vibration) is generated at the level of this material: the electrical signal is translated into a mechanical signal exhibiting a frequency dependence with respect to the alternating electrical signal, a dependence which is a function of the characteristics of the electrode(s), the properties of the ferroelectric material and other factors including the characteristics of the semiconductor support of the device.

[0007] However, elastic wave devices exploit this dependence to provide one or more functions dependent on the frequency, and therefore on the characteristics of the support. A dielectric layer interposed between the ferroelectric layer and its support makes it possible to improve the mechanical behavior of the transducer, and more particularly to limit the appearance of parasitic responses, induced losses linked to the properties of the substrate and interface effects within the stack. Increasing the working frequencies may require thinning the dielectric layer for purely mechanical reasons.

[0008] Whether we consider semiconductor substrates or ferroelectric substrates, the problem is the same: The charge trapping layer, by capturing possible electric charge carriers, limits interactions with electromagnetic fields from high-frequency signals from devices formed on the substrate and allows these devices to achieve high levels of performance.

[0009] However, a continuing trend in the evolution of these devices is to employ increasingly higher working frequencies, which require increasingly thin dielectric layers, interposed between the surface layer and the trapping layer.

[0010] However, the thinning of the dielectric layers promotes the diffusion towards the charge trapping layer of contaminating species such as hydrogen originally included in the surface layer or brought during the manufacture of the devices or lithium in the case of ferroelectric surface layers made of lithium niobate or lithium tantalate.

[0011] By diffusion through the dielectric layer, these contaminating species occupy the electric charge trapping sites of the trapping layer, reducing the latter's efficiency and compromising the overall performance of the devices.

[0012] The present invention aims to address, at least in part, this problem of contamination of the electric charge trapping layer exacerbated by the thinness of the dielectric layer. It aims more particularly to propose a structure comprising a surface layer transferred onto a support provided with an electric charge trapping layer limiting the contamination of the latter as well as a method allowing the manufacture of such a structure.

[0013] To achieve this aim, the subject of the invention is a device comprising a ferroelectric surface layer containing lithium; a dielectric layer comprising an oxide and arranged in contact with the ferroelectric surface layer; and a substrate in contact with the dielectric layer, the substrate comprising a charge trapping layer arranged on a support, the charge trapping layer being arranged between the support and the dielectric layer, in which device the dielectric layer has a thickness of between 150 nm and 500 nm, preferably between 150 nm and 300 nm; and a nitrogen concentration in the dielectric layer and a surface roughness of the charge trapping layer are such that the charge trapping layer has a lithium dose of less than 5.10 11 at / cm 2 .

[0014] An advantage of the structure according to the invention is to maintain the effectiveness of the trapping function of the electric charge trapping layer even when the dielectric layer separating the charge trapping layer from the surface layer is thinned, this by avoiding its contamination by chemical species capable of passivating the charge trapping sites, in particular hydrogen and lithium present in the surface layer.

[0015] Consequently, the structure according to the invention makes it possible to provide substrates for the manufacture of components comprising piezoelectric layers and designed to operate at high frequencies and having excellent performance.

[0016] According to additional non-limiting characteristics of the first aspect of the invention, considered individually or in any technically feasible combination: the nitrogen concentration of the dielectric layer can be between 5.10 20 at / cm 3 and 10 22 at / cm 3 ; and the surface roughness of the trapping layer may be less, in peak-valley measurement, than 800 nm, preferably less than 400 nm, and even more preferably less than 100 nm;

[0017] - the dielectric layer may have a thickness of between 150 nm and 250 nm;

[0018] - the nitrogen concentration of the dielectric layer can be between 10 21 at / cm 3 and 6.10 21 at / cm 3 ;

[0019] - the dielectric layer may be a silicon oxide layer and a hydrogen concentration of the dielectric layer may be strictly lower than the nitrogen concentration of the dielectric layer;

[0020] - a hydrogen concentration of the dielectric layer (16) may be at least three times lower than the nitrogen concentration of the dielectric layer;

[0021] - a hydrogen concentration in the dielectric layer can be less than 10 22 at / cm 3 ;

[0022] - the lithium dose in the charge trapping layer can be less than 10 11 at / cm 2 ;

[0023] - the ferroelectric surface layer may comprise lithium niobate or lithium tantalate;

[0024] - the charge trapping layer may comprise polycrystalline silicon;

[0025] - the ferroelectric surface layer can be made of a monocrystalline material.

[0026] A second aspect of the invention relates to a method of manufacturing a device comprising a ferroelectric layer, comprising the steps of forming a charge trapping layer on a support to form a substrate; smoothing an exposed surface of the trapping layer so as to reduce a roughness of this exposed surface below a threshold roughness; forming a dielectric layer at least on the smoothed charge trapping layer and optionally on a donor substrate comprising a ferroelectric material, the dielectric layer having a thickness of between 150 nm and 500 nm; joining the donor substrate and the substrate via the dielectric layer;removing a portion of the donor substrate to form a ferroelectric surface layer, the threshold roughness and a nitrogen concentration in an oxide layer included in the dielectric layer being chosen so that the lithium dose in the charge trapping layer is less than 5.10; 11 at / cm 2 at the end of the manufacturing process.

[0027] According to additional non-limiting characteristics of the second aspect of the invention, considered individually or in any technically feasible combination:

[0028] - the nitrogen concentration of the dielectric layer can be between 5.10 20 at / cm 3 and 10 22 at / cm 3 ; and the surface roughness of the trapping layer may be less, in peak-valley measurement, than 800 nm, preferably less than 400 nm, and even more preferably less than 100 nm;

[0029] - the smoothing step may include chemical-mechanical polishing of the charge trapping layer;

[0030] - the charge trapping layer may comprise polycrystalline silicon;

[0031] - the manufacturing method may comprise the formation of a weakening plane by implanting light species in the donor substrate to define the surface layer therein, and the step of removing a portion of the donor substrate may comprise the detachment of the surface layer at the weakening plane. BRIEF DESCRIPTION OF THE FIGURES

[0032] Other characteristics and advantages of the invention will emerge from the detailed description of the invention which follows with reference to the appended figures in which:

[0033] Larepresents a structure which is the subject of this description;

[0034] Illustrates a manufacturing process of the structure shown in;

[0035] Schematizes a mechanism of diffusion of chemical species and the concept of peak-valley measurement in the structure according to the invention;

[0036] It represents a graph indicating a necessary thickness of oxide in the structure of the. DETAILED DESCRIPTION OF THE INVENTION

[0037] La represents a structure 1 comprising a substrate 10 integrating a support 12 and a layer 14 for trapping electric charges on the support, a surface layer 20 arranged on the substrate 10, and a dielectric layer 16 interposed between the surface layer 20 and the substrate 10, preferably in direct contact with the surface layer 20 and the charge trapping layer 14.

[0038] The surface layer 20 is a layer making it possible to give functions, for example piezoelectric, to a device developed on or in the structure 1.

[0039] Conventionally, structure 1 can be in the form of a circular plate whose diameter can be 100, 200, 300 or even 450 mm.

[0040] As presented in the documents forming the state of the art presented in the preamble, the structure 1 can be produced in multiple ways. Very generally, the structure 1 can be produced by a manufacturing method comprising the assembly of the substrate 10 and a donor substrate, the dielectric layer 16 being interposed between these two elements, followed by a step of eliminating a portion of the donor substrate to form the surface layer 20. The step of eliminating a portion of the donor substrate can be carried out by mechanical-chemical thinning of this substrate. However, the structure 1 is preferentially manufactured by applying the Smart Cut™ technology, according to which a layer intended to form the surface layer 20 is delimited by means of a weakening plane formed by implantation of light species such as hydrogen in the donor substrate.This layer is then separated from the donor substrate bonded to the support via the dielectric layer 16, by fracture at the level of the weakening plane, the surface layer 20 remaining fixed on the substrate 10 provided with the trapping layer 14, with the dielectric layer 16 interposed between them.

[0041] The fabrication of such a structure leads to the introduction of hydrogen into the layers due, for example, to hydrogen implantation during the Smart Cut process and the production of hydrogen during bonding between the surface layer and the substrate via the dielectric layer. In addition, when the surface layer is a ferroelectric layer containing lithium niobate or lithium titanate, lithium is also present in the layers. These two elements, hydrogen and lithium, can diffuse into the trapping layer, occupy the charge trapping sites and therefore passivate them, thus drastically reducing the usefulness of the trapping layer.

[0042] The substrate 10 typically has a thickness of several hundred microns. Preferably, the substrate has a high resistivity, greater than 1000 ohm.centimeter, and even more preferably, greater than 2000 ohm.centimeter. This limits the density of charges, holes or electrons, which are likely to move in the substrate. However, the invention is not limited to a substrate 10 having such a resistivity, and it also provides RF performance advantages when the substrate has a more conformal resistivity, of the order of a few hundred ohm.centimeter, for example less than 1000 ohm.cm, or 500 ohm.cm or even 10 ohm.cm.

[0043] For reasons of availability and cost, the support 12 is preferably made of monocrystalline silicon. It may, for example, be a CZ silicon substrate with a low interstitial oxygen content of between 6 and 10 ppm, or an FZ silicon substrate which in particular has a naturally very low interstitial oxygen content. It may also be a CZ silicon substrate having a high quantity of interstitial oxygen (designated by the expression “High Oi”) greater than 26 ppm. The support 12 may alternatively be formed of another material: it may, for example, be sapphire, glass, quartz, silicon carbide, etc. In certain circumstances, and in particular when the trapping layer 14 has a sufficient thickness, for example greater than 30 microns, the support 12 may have a standard resistivity of less than 1 kohm.cm.

[0044] The trapping layer 14 can be of very varied natures, as reported in the documents forming the state of the art. Generally speaking, it is a non-crystalline layer having structural defects such as dislocations, grain boundaries, amorphous zones, interstices, inclusions, pores, etc. These structural defects form traps for charges likely to circulate in the material, for example at the level of incomplete or dangling chemical bonds. This prevents or limits conduction in the trapping layer, which consequently has a high resistivity.

[0045] Advantageously, and for reasons of simplicity of implementation, this trapping layer 14 is formed of a layer of polycrystalline silicon. Its thickness, in particular when it is formed on a resistive support 12, can be between 0.3 and 3 µm. But other thicknesses lower or higher than this interval are entirely conceivable, depending on the level of RF performance expected from the structure 1.

[0046] In order to seek to preserve the polycrystalline quality of this layer during the heat treatments that the structure 1 may undergo, it is advantageous to provide an amorphous layer, made of silicon dioxide for example, on the support 12 before the deposition of the charge trapping layer 14.

[0047] Alternatively, the trapping layer 14 can be formed by implanting a heavy species, such as argon, into a surface thickness of the support 12, in order to form the structural defects constituting the electrical traps. This layer 14 can also be formed by porosification of a surface thickness of the support 12.

[0048] The dielectric layer is usually made of silicon oxide and preferably contains nitrogen, which is favorable for forming a barrier layer preventing the diffusion of species, in particular hydrogen and lithium mentioned above.

[0049] The surface layer 20 may be of any suitable nature. It is very preferably formed of a monocrystalline material. When the structure 1 is intended to receive integrated semiconductor components, the surface layer 20 may thus be composed of monocrystalline silicon, or any other semiconductor material. In such a case, lithium contamination may originate from the equipment used for the manufacture of the structure. When the structure 1 is intended to receive surface acoustic wave filters, the surface layer 20 may be composed of a piezoelectric and / or ferroelectric material, such as lithium tantalate or lithium niobate. In this case, in addition to possible contamination from the outside, the lithium contamination may also originate from the surface layer itself.The surface layer 20 may also comprise finished or semi-finished integrated components, formed on the donor substrate and transferred to the substrate 10 during the step of manufacturing the structure 1. Generally speaking, the thin layer may have a thickness of between 10 nm and 10 µm.

[0050] A method of manufacturing a structure according to that shown in the, in which the surface layer 20 is a ferroelectric layer, is now presented, for illustration purposes only.

[0051] According to this method, on a silicon support 12, a charge trapping layer 14 of polycrystalline silicon is formed by deposition, for example using an LPCVD technique carried out between 600°C and 650°C. The trapping layer 14 has a thickness of approximately 500 nm, or even 1 micron.

[0052] The trapping layer 14 is then polished by a chemical-mechanical polishing (or CMP) step leading to a removal of approximately 100 to 200 nanometers of the trapping layer, resulting in a layer with a thickness of between 500 and 1000 nanometers to have a surface roughness of less than 300 nm, preferably less than 140 nm, or even more preferably less than 100 nm, in peak-valley measurement. In a non-limiting manner, a peak-valley roughness of 800 nm can be obtained with a deposition of a polycrystalline silicon charge trapping layer of several microns (approximately 4 µm).Such roughness could make it possible to avoid parasitic modes, particularly present in a POI (Piezoelectric-On-Insulator) type structure with a thickness of the piezoelectric layer greater than the wavelength used, due to the radiation of these volume modes in the volume and their interaction with the interfaces.

[0053] Preferably, in order to reduce the hydrogen content of the trapping layer, a first annealing of this layer can be provided in a hydrogen-poor atmosphere (i.e. less than 5 ppm) at a temperature between the deposition temperature and 1000°C. Advantageously, the temperature of the first annealing is greater than 620°C and preferably less than 900°C, for at least one hour and preferably for a few hours. Under these preferential annealing conditions, the hydrogen present in the trapping layer 3 is effectively exodifused to reduce its concentration below the threshold of 10 18 at / cm 3 , preferably 10 1 7 at / cm 3 , without damaging the polycrystalline nature of the trapping layer, by recrystallization effect.

[0054] On the trapping layer 14, a dielectric layer 16 formed of a silicon oxide layer including nitrogen with a thickness of 300 nm to 1000 nm is deposited, for example by a PECVD technique carried out at a temperature between 600°C and 800°C, forming the dielectric layer 16 of the structure 1. The layer is then polished by a chemical-mechanical polishing (CMP) step leading to a removal of approximately 200 to 800 nanometers of the oxide to provide a surface having a roughness of less than 0.3 nm RMS, for example on a field of 5*5 microns or a field of 30*30 microns by measurement by atomic force microscopy. The dimensions of the measurement field are adapted by the practitioner so as to obtain a representative characterization of the layer in question. Here, the dielectric layer 16 has a thickness of between 150 nm and 500 nm, preferably between 150 nm and 250 nm, and a significant hydrogen concentration of more than 10 20 at / cm3 but preferably remaining lower than a nitrogen concentration in the dielectric layer 16.

[0055] To reduce this concentration, a second annealing, called "densification" annealing, similar to the first annealing described above, can be applied. This is therefore an annealing in a hydrogen-poor atmosphere (i.e., less than 5 ppm) and exposing the dielectric layer 16 to a temperature higher than its deposition temperature. This can be a neutral or oxidizing atmosphere. Preferably, this temperature is higher than 800°C, typically between 800°C and 900°C. The annealing is continued for at least one hour, and preferably for several hours, in order to exodiffuse the hydrogen from the dielectric layer 16, and possibly from the trapping layer 14. At the end of this densification annealing, the dielectric layer 16 has a hydrogen concentration lower than 10 20 at / cm 3and the trapping layer 14 has a hydrogen concentration lower than 10 18 at / cm 3 , preferably 10 1 7 at / cm 3 .

[0056] The presence of nitrogen in a silicon oxide layer improves its barrier effect with respect to the diffusion of chemical species such as lithium and hydrogen. The applicant has estimated by simulations and confirmed by experiments that a reduction in the roughness of the trapping layer is accompanied by a reduction in the nitrogen content necessary to obtain a satisfactory barrier effect. Thus, a nitrogen concentration of between 5.10 20 at / cm 3 and 10 22 at / cm 3 , preferably between 10 21 at / cm 3 and 6.10 21 at / cm 3, allows, in combination with a trapping layer with a roughness of less than 800 nm, preferably less than 400 nm, preferably less than 100 nm, in peak-valley measurement, to obtain a sufficient barrier effect of the dielectric layer to develop on the substrate thus obtained devices capable of operating at high frequencies. The high values ​​of the above ranges do not constitute an upper limit to the nitrogen concentration to obtain a barrier effect, but ensure a sufficiently low nitrogen concentration to be able to apply the structure according to the invention to known devices without risking negatively influencing their performance.

[0057] The importance of minimizing roughness in peak-valley measurement is empirically explained by means of: each roughness peak 310 of the trapping layer 14 creates one or more preferred paths (represented by straight arrows) for the migration of species through the dielectric layer 16 due to a local thinning of the dielectric layer 16 at these peaks 310. This is only a schematic representation used for explanatory purposes and in no way a realistic representation of the layers in a real device.

[0058] As illustrated by the, a peak-valley measurement consists of measuring the sum Sum of a maximum depth S1 of a trough (the deepest valley) in a considered surface Surf and of a maximum height S2 of a peak (the highest projection) of this surface, the depth and the height being measured relative to an average altitude Moy of this surface, for example on a given surface of the sample. In the case of a measurement by atomic force microscopy, one can for example consider an observation surface corresponding to a square of 30 µm on each side, but one could alternatively consider a square of 5 µm on each side or more to establish the peak-valley measurement.

[0059] It is possible to seek to minimize the thickness of the oxide layer forming the dielectric layer 16 as a function of its nitrogen concentration and a maximum dose of lithium considered acceptable in the charge trapping layer. The minimum thickness of the oxide layer is thus estimated as the sum of half the roughness in peak-valley measurement and a minimum oxide thickness depending on its nitrogen concentration, this minimum thickness decreasing with the increase in the nitrogen concentration. The thickness of the dielectric layer 16 is measured between the average depth of the charge trapping layer and the surface of the oxide layer.

[0060] Dose is defined as the quantity of atoms of a given chemical species over the thickness of the layer, that is, the quantity contained in a volume defined by a given surface area of ​​the layer and the projection of this surface area perpendicular to the layer. A dose can be expressed as the number of atoms per unit area of ​​the layer.

[0061] The graph illustrated by summarizes the situation. On the abscissa is the thickness Tk of the oxide layer expressed in nanometers, on the ordinate is the roughness in peak-valley measurement of the charge trapping layer indicated by PV and expressed in nanometers. For this graph, the curves identified by [N]1, [N]2, [N]3 and [N]4 represent the minimum thicknesses of the oxide layer according to PV to obtain a maximum acceptable lithium dose set at 5.10 11 lithium atoms per square centimeter in the charge trapping layer, respectively for nitrogen concentrations of about 1020 , 1.10 2 1 , 3.10 21 and 10 2 2 at / cm 3 , respectively. A PV value of 0 corresponds to a perfectly smooth charge trapping layer, which gives the minimum thickness of oxide to be deposited to sufficiently limit the diffusion of chemical species in the layer, lithium in particular, for a given nitrogen concentration of this oxide.

[0062] Preferably, the oxide layer forming the dielectric layer 16 has a proportion between the concentrations of nitrogen and hydrogen which is favorable to blocking the diffusion of hydrogen, with an excess of nitrogen relative to the quantity of hydrogen, that is to say a ratio between the concentrations of nitrogen and hydrogen which is strictly greater than 1, preferably greater than 1.5, and even more preferably greater than 3, for concentrations measured by a SIMS (Secondary Ion Mass Spectrometry) method. Thus, the hydrogen concentration in the dielectric layer is preferably less than approximately 10 22 at / cm 3 , more preferably less than about 10 21 at / cm 3 , even more preferably less than about 10 20 at / cm 3 .

[0063] It should be noted that, when the dielectric layer 16 is formed on the trapping layer 14, and these two layers have been deposited at a relatively low temperature as has just been explained, it is not necessary to apply the first and second annealing respectively after each deposition step. It is possible to carry out a single annealing, under conditions similar to the first and second annealing, after the formation of the dielectric layer 16 at low temperature on the trapping layer 14. In other words, it is not necessary in this case to apply a specific annealing of the trapping layer 14 before the deposition of the dielectric layer 16.

[0064] As illustrated by this embodiment, it is generally preferred to arrange the dielectric layer 16 on the support 12 (via the trapping layer 14) rather than on the donor substrate 200. Indeed, it is generally possible to heat treat this support 12 at the temperature of the first and / or second annealing, which is not always the case for the donor substrate 200. For example, this donor substrate may have a weakening plane, or be composed of a ferroelectric material having a relatively low Curie temperature or comprise components, which, in each of these cases, limits the thermal budget applicable to it to a few hundred degrees for a relatively short time, less than 1 hour. However, the invention does not exclude that, in certain favorable cases, the dielectric layer 16 may be formed at least in part on the donor substrate 200.

[0065] The structure obtained at this stage is illustrated in (a) of the.

[0066] In parallel with the preparation of the substrate 10, hydrogen ions are implanted into a ferroelectric lithium tantalate donor substrate 200 through a first 210 of its faces in order to form a buried weakening plane 220. In this way, a surface layer 20 is defined between this weakening plane 220 and the first face 210 of the donor substrate and a complementary layer 22 comprising the remainder of the donor substrate.

[0067] The donor substrate obtained at this stage is illustrated in (b) of the.

[0068] The donor substrate 200 is assembled to the silicon oxide layer 16 arranged on the support 12 as illustrated in (c) of the, and the donor substrate 200 is then fractured at the embrittlement plane 220 using a moderate heat treatment of the order of 400°C. The complementary layer 22 of the donor substrate is released to expose a free face 230 of this layer which can then be prepared to improve its crystalline quality and surface condition. This preparation comprises a step of thinning the first layer by chemical-mechanical polishing and a step of heat treatment at 500°C in a neutral atmosphere for 1 hour. The structure obtained, indicated in (d) of the is that of the.

[0069] The method described above is applied to a ferroelectric layer of lithium tantalate used as the surface layer 20, but other types of ferroelectric or piezoelectric materials such as lithium niobate could be employed. Furthermore, as an alternative to a ferroelectric surface layer, a semiconductor surface layer such as a silicon layer or comprising silicon such as monocrystalline silicon could be employed.

[0070] The manufacturing process detailed above therefore makes it possible to obtain a structure whose pollution of the trapping layer by damaging species, in particular hydrogen and lithium, remains sufficiently limited to develop devices capable of operating satisfactorily at high frequencies. Indeed, for example, the combination of a nitrogen content of between 5.10 20 at / cm 3 and 10 22 at / cm 3for an oxide layer of sufficient thickness placed directly on a surface of a trapping layer 14 with a roughness of less than 300 nm in peak-valley measurement results in a maintenance in the charge trapping layer 14 of lithium dose at less than 5.10 11 at / cm 2 , and hydrogen concentrations less than 10 20 at / cm 3 , preferably less than 10 19 at / cm 3 , even more preferably less than 10 18 at / cm 3 .

[0071] Of course, the invention is not limited to the embodiments described and variant embodiments can be made without departing from the scope of the invention as defined by the claims.

Claims

Device comprising:- a ferroelectric surface layer (20) containing lithium;- a dielectric layer (16) comprising an oxide and arranged in contact with the ferroelectric surface layer; and- a substrate (10) in contact with the dielectric layer, the substrate comprising a charge trapping layer (14) arranged on a support (12), the charge trapping layer (14) being arranged between the support (12) and the dielectric layer (16),the device beingcharacterized in that:the dielectric layer (16) has a thickness of between 150 nm and 500 nm, preferably between 150 nm and 300 nm;a nitrogen concentration in the dielectric layer (16) and a surface roughness of the charge trapping layer (14) are such that the charge trapping layer (14) has a lithium dose of less than 5.10 11 at / cm 2 ;the nitrogen concentration of the dielectric layer is between 5.10 20 at / cm3 and 10 22 at / cm 3 ; andthe surface roughness of the trapping layer (14) is less, in peak-valley measurement, than 800 nm, preferably less than 400 nm, and even more preferably less than 100 nm. The device according to claim 1, wherein the dielectric layer (16) has a thickness of between 150 nm and 250 nm. The device according to claim 1 or 2, wherein the nitrogen concentration of the dielectric layer (16) is between 10 21 at / cm 3 and 6.10 21 at / cm 3 . The device according to any one of claims 1 to 3, wherein the dielectric layer is a silicon oxide layer and a hydrogen concentration of the dielectric layer (16) is strictly lower than the nitrogen concentration of the dielectric layer (16). The device of claim 4, wherein a hydrogen concentration of the dielectric layer (16) is at least three times lower than the nitrogen concentration of the dielectric layer (16). The device according to any one of claims 1 to 5, wherein a hydrogen concentration in the dielectric layer (16) is less than 10 22 at / cm 3 . The device according to any one of claims 1 to 6, wherein the lithium dose in the charge trapping layer (14) is less than 10 1 1 at / cm 2 . The device of any one of claims 1 to 7, wherein the ferroelectric surface layer (20) comprises lithium niobate or lithium tantalate. The device according to any one of the preceding claims 1 to 8 wherein the charge trapping layer (14) comprises polycrystalline silicon. The device according to any one of the preceding claims wherein the ferroelectric surface layer (20) is made of a monocrystalline material. A method of manufacturing a device comprising the following steps:- forming a charge trapping layer (14) on a support (12) to form a substrate (10);- smoothing an exposed surface of the trapping layer (14) so ​​as to reduce a roughness of this exposed surface below a threshold roughness;- forming a dielectric layer (16) at least on the smoothed charge trapping layer (14) and optionally on a donor substrate (200) comprising a ferroelectric material containing lithium, the dielectric layer (16) having a thickness of between 150 nm and 500 nm;- assembling the donor substrate (200) and the substrate (10) via the dielectric layer (16);- removing a portion of the donor substrate to form a ferroelectric surface layer (20) containing lithium, the threshold roughness and a nitrogen concentration in an oxide layer included in the dielectric layer (16) being chosen so that the lithium dose in the charge trapping layer is less than 5.10; 1 1 at / cm 2 at the end of the manufacturing process; in which: - the nitrogen concentration of the dielectric layer is between 5.10 20 at / cm 3 and 10 22 at / cm 3 ; and- the surface roughness of the trapping layer (14) is less, in peak-valley measurement, than 800 nm, preferably less than 400 nm, and even more preferably less than 100 nm. The manufacturing method of claim 11, wherein the smoothing step comprises chemical-mechanical polishing of the charge trapping layer (14). A manufacturing method according to claim 11 or 12, wherein the charge trapping layer (14) comprises polycrystalline silicon. A manufacturing method according to any one of the preceding claims 11 to 13, comprising forming a weakening plane (220) by implanting light species into the donor substrate (200) to define the surface layer (20) therein, and the step of removing a portion of the donor substrate comprises detaching the surface layer (20) at the weakening plane (220).

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