Light sensor

Abstract

Light Sensor This description relates to a light sensor (1) comprising an integrated circuit chip (100) and a boost DC-DC converter (106). The chip (100) includes a pixel array (102, 104), each pixel having at least one SPAD. The converter (106) delivers a bias potential (VHV) to the SPADs (200) suitable for placing the SPADs in Geiger mode. The converter (106) includes an inductor (110), a first switch (112), a second switch (114), and a control circuit (CTRL) for switching the first switch (112). The inductor (110) and the first and second switches (112, 114) are located outside the chip (100), while the control circuit (CTRL) is located within the chip (100). Figure for the abstract: Fig. 1

Description

Title of the invention: Light sensor Technical field

[0001] The present description relates generally to electronic circuits, and, more particularly, to light sensors, for example time-of-flight sensors. Prior art

[0002] Light sensors comprising single photon avalanche diodes (SPADs) are known. Such sensors, for example time-of-flight sensors, comprise a pixel array where each pixel of the array comprises at least one SPAD and is for example referred to as a SPAD pixel or a single photon avalanche diode pixel. This pixel array is implemented in and on an integrated circuit chip, the chip being implemented from a semiconductor layer. Other circuitry of the sensor, for example pixel drive circuits and / or pixel readout circuits, are generally implemented in the same integrated circuit chip as the pixel array.

[0003] As is well known to those skilled in the art, to detect a single photon, a SPAD must first be biased by a potential greater than its breakdown voltage. This bias potential is determined so that the electric field in the PN junction of the diode is high enough so that, when a photon is received by the SPAD and results in the generation of a charge carrier, the injection of this charge carrier into the depletion zone of the SPAD triggers an avalanche phenomenon in the SPAD. This mode of operation of a diode is called Geiger mode in the literature.

[0004] There are various solutions for generating this polarization potential and supplying it to the SPADs of the sensor pixel array. However, these known solutions all have drawbacks. Summary of the invention

[0005] There is a need for a light sensor comprising an integrated circuit chip, the chip comprising a SPAD pixel array, wherein generating the bias potential of the SPADs above their breakdown voltage overcomes at least some of the disadvantages of known light sensors.

[0006] One embodiment overcomes all or part of the drawbacks of known light sensors, for example known light sensors comprising a matrix of SPAD pixels.

[0007] One embodiment provides a light sensor comprising an integrated circuit chip and a DC-DC boost converter, wherein: the integrated circuit chip comprises an array of pixels, each pixel comprising at least one single-photon avalanche diode; the converter is configured to deliver a bias potential to the diodes of the pixels, the bias potential being capable of placing said diodes in Geiger mode; and the converter comprises: - an inductor coupling a node configured to receive a first supply potential to an intermediate node; - a first switch coupling the intermediate node to a reference potential; - a second switch coupling the intermediate node to an output node of the converter, the output node being configured to deliver said bias potential; and - a control circuit configured to control switching of the first switch, the inductor, the first switch and the second switch of the converter being arranged outside the integrated circuit chip and the control circuit belonging to said integrated circuit chip.

[0008] According to one embodiment, the second switch is a diode.

[0009] According to one embodiment, the converter further comprises a first capacitance coupling the output node to the reference potential, the first capacitance being arranged outside the integrated circuit chip.

[0010] According to one embodiment, the output node of the converter is connected to an input terminal of the integrated circuit chip.

[0011] According to one embodiment, the input terminal of the integrated circuit chip is coupled, preferably connected, to an input of the control circuit.

[0012] According to one embodiment, the input terminal of the chip is coupled to the pixel array such that a potential on the input terminal is provided to each single-photon avalanche diode of the pixel array of the integrated circuit chip.

[0013] According to one embodiment, the polarization potential has a target value greater than 15 V, preferably greater than or equal to 20 V.

[0014] According to one embodiment, the sensor is configured to implement a time-of-flight capture function.

[0015] According to one embodiment, a control terminal of the first switch of the converter is connected to an output terminal of the integrated circuit chip.

[0016] According to one embodiment, an output of the control circuit is coupled, preferably connected, to the output terminal of the integrated circuit chip.

[0017] According to one embodiment, the converter further comprises a second capacitor coupling the node configured to receive the first supply potential to the reference potential, the second capacitor being disposed outside the chip. integrated circuit.

[0018] According to one embodiment, the integrated circuit chip comprises a terminal configured to receive the reference potential.

[0019] According to one embodiment, the converter further comprises a resistor connected in series with the inductor, between the node configured to receive the first supply potential and the intermediate node, the resistor being arranged outside the integrated circuit chip and the chip comprising two terminals each connected to a different end of the resistor and to the control circuit.

[0020] According to one embodiment, the sensor comprises a substrate on which the integrated circuit chip and converter components that are arranged outside the integrated circuit chip are mounted, the support comprising conductive tracks configured to connect together the chip and the converter components that are arranged outside the integrated circuit chip. The converter components that are arranged outside the chip and that are mounted on the support comprise, for example, the first and second switches and the inductor.

[0021] According to one embodiment, the sensor further comprises: - a protective housing mounted on the support; and - at least one light source mounted on the support, the chip, the inductance of the converter, the first and second switches of the converter and said at least one light source being encapsulated in said housing, and the sensor forming a ready-to-use module. Brief description of the drawings

[0022] These characteristics and advantages, as well as others, will be explained in detail in the following description of particular embodiments given without limitation in relation to the attached figures among which:

[0023] [Fig.l] represents, schematically and at least partly in the form of blocks, an embodiment of a light sensor;

[0024] [Fig.2] schematically represents an example of a pixel comprising a single-photon avalanche diode;

[0025] [Fig. 3] shows, schematically and at least partly in the form of blocks, an example of a circuit of the sensor of [Fig. 1]; and

[0026] [Fig.4] represents, schematically and at least partly in the form of blocks, an alternative embodiment of the sensor of [Fig.1]. Description of the embodiments

[0027] The same elements have been designated by the same references in the different figures. In particular, the structural and / or functional elements common to the different embodiments may have the same references and may have identical structural, dimensional and material properties.

[0028] For the sake of clarity, only the steps and elements useful for understanding the described embodiments have been shown and are detailed. In particular, the various known SPAD pixels have not all been described, the present description applying to all these known SPAD pixels. In the same way, the usual control methods of the switching switch(es) of a switching boost converter ("Switched Mode Power Supply Boost Converter" or "SMPS Boost Converter" in English) and the usual control circuits implementing these usual control methods have not all been detailed, the present description applying to these usual control methods and to these usual control circuits.

[0029] In the remainder of the description, unless otherwise indicated, each potential is, for example, referenced relative to the same reference potential, for example ground GND, and the potential of a node then has the same value as the voltage taken between this node and a node at the reference potential.

[0030] Unless otherwise specified, when referring to two elements connected to each other, this means directly connected without intermediate elements other than conductors, and when referring to two elements connected (in English "coupled") to each other, this means that these two elements can be connected or be connected by means of one or more other elements.

[0031] In the following description, when reference is made to absolute position qualifiers, such as the terms "front", "back", "top", "bottom", "left", "right", etc., or relative position qualifiers, such as the terms "above", "below", "upper", "lower", etc., or to orientation qualifiers, such as the terms "horizontal", "vertical", etc., reference is made unless otherwise specified to the orientation of the figures.

[0032] Unless otherwise specified, the expressions "about", "approximately", "substantially", and "of the order of" mean to within 10%, preferably to within 5%.

[0033] [Fig.l] represents, schematically and partly in the form of blocks, an embodiment of a light sensor 1.

[0034] The light sensor 1 is, for example, a time-of-flight sensor capable of producing a depth map of a scene captured by the sensor 1.

[0035] The light sensor 1 comprises an integrated circuit chip 100. The chip 100 comprises, for example, a portion of a semiconductor layer, for example made of silicon, in and on which all the electronic components of the chip 100 are formed.

[0036] In particular, the integrated circuit chip 100 comprises a matrix 102 of pixels 104. In [Fig.l], by way of example, the matrix 102 comprises seven columns and ten rows of pixels 104, or seventy pixels 104, a single pixel 104 being referenced in [Fig.l] so as not to overload it. The matrix 102 may however comprise a number different number of columns and / or rows of pixels 104, and therefore a different number, for example smaller or larger, of pixels 104.

[0037] Each pixel 104 comprises a single-photon avalanche diode (not shown in [Fig. 1]). In other words, each pixel 102 comprises a diode configured to receive a bias potential VHV above its breakdown voltage, so that it can be placed in Geiger mode. For example, in each pixel, the single-photon avalanche diode has its cathode coupled to the potential VHV and its anode coupled to a reference potential, for example the ground GND. For example, the potential VHV, referenced to the reference potential GND, has a value greater than 15 V, preferably greater than or equal to 20 V, for example a value substantially equal to 25 V. For example, each pixel 102 comprises a single single-photon avalanche diode.As an alternative example, a pixel may comprise several single-photon avalanche diodes, each of which may be associated with its own quenching circuit, and the assembly being, for example, called a macro-pixel.

[0038] An example of a pixel 104 that can be implemented in the matrix 102 is illustrated in [Fig. 2]. This example pixel 104 is similar to the pixel shown in Figures 1, 5, 6, 7 and 8 of patent applications EP 3806162, US 2021105427 and CN 112702546. The example pixel 104 of [Fig. 3] is, more particularly, similar to the pixel of Figure 5 of the aforementioned patent applications.

[0039] In this example, the pixel 104 comprises a single-photon avalanche diode 200. The anode of the diode 200 is coupled to the GND potential, i.e., to a node 202 configured to receive the GND potential. The cathode of the diode 200 is coupled to the VHV potential, i.e., to a node 206 configured to receive the VHV potential.

[0040] More particularly, in this example, the cathode of the diode 200 is coupled to the node 204 by a resistor 205. The resistor 205, called the quenching resistor, is configured to quench, i.e. stop, an avalanche phenomenon in the diode 200. In this example, the anode of the diode 200 is coupled to the node 202 by two MOS ("Metal Oxide Semiconductor") transistors T1 and T2. The transistor T1 is, for example, configured to quench an avalanche phenomenon in the diode 200 when it is switched to the open state. The transistor T2 is, for example, configured to deactivate the pixel 104 when it is switched to the open state.

[0041] In this example, the pixel 104 further comprises a pull-up diode 206 whose anode is connected to the anode of the diode 200 and whose cathode is connected to a node 208 configured to receive a potential V2. The potential V2 is lower than the potential VHV. For example, the potential V2 is of the order of 7 V

[0042] In this example, the pixel 104 further comprises two capacitors C1 and C2. Capacitance Cl is connected between the node 210 connecting the diode 200 to the resistor 205, and a node 212. Capacitance C2 is connected between the node 212 and the node 202. Capacitances Cl and C2 form a capacitive divider bridge configured to reproduce or transmit variations in the cathode potential of the diode 200 to the node 212

[0043] In this example, the pixel 104 further comprises a circuit 216, here an inverter, configured to switch its output following a variation in the potential on the node 212 resulting from an avalanche phenomenon in the diode 200. In other words, the circuit 216 is configured to detect an avalanche phenomenon in the diode 200.

[0044] In this example, the pixel 104 further comprises an optional MOS transistor T3. The transistor T3 couples the node 212 to a node 214 configured to receive a potential VL. The potential VI is lower than the potential VHV. The potential VI is, for example, a supply potential of the order of 1.2 V. A potential received by the gate of the transistor T3 makes it possible to modify the duration of the pulses supplied at the output of the circuit 216.

[0045] The person skilled in the art is able to provide single-photon avalanche diode pixels 104 different from that of [Fig. 2], in which, as in [Fig. 2], the single-photon avalanche diode receives the VHV potential, for example on its cathode, so that it can be placed in Geiger mode. In other words, the person skilled in the art is able to provide single-photon avalanche diode pixels 104 different from that of [Fig. 2] but which each require receiving the VHV potential in order to operate.

[0046] Referring again to [Fig.l], the sensor 1 further comprises a switching boost converter 106 (delineated by dotted lines in [Fig.l])•

[0047] The converter 106 is configured to deliver the potential VHV to the single-photon avalanche diodes of the matrix 102 of pixels 104. More particularly, the converter 106 is configured to deliver the potential VHV from a supply potential Vbat. The potentials Vbat and VHV are direct current (DC) potentials. In other words, the converter 106 is a direct-to-direct (DC-DC) converter.

[0048] By way of example, the potential Vbat is lower, for example by at least 10 V, than the potential VHV. By way of example, the potential Vbat is lower than or equal to 5 V, for example substantially equal to 3.6 V.

[0049] The converter 106 comprises an inductor 110, a switch 112, a diode 114 and a control circuit CTRL configured to control switchings of the switch 112.

[0050] The inductor 110 couples a node 116 configured to receive the potential Vbat to a intermediate node 118. In other words, one terminal of the inductor 110 is coupled, for example connected, to the node 116, the other terminal of the inductor 110 being coupled, for example connected, to the node 118.

[0051] The switch 112 couples the node 118 to the reference potential GND, that is, the switch 112 couples the node 118 to a node 122 configured to receive the reference potential GND. This switch 112 is, for example, called a low side switch. For example, the switch 112 comprises a conduction terminal coupled, for example connected, to the node 118, and another conduction terminal coupled, for example connected, to the node 122. The switch 112 receives a control signal sigCTRL on a control terminal.

[0052] By way of example, the switch 112 is implemented by an N-channel MOS transistor. For example, a first conduction terminal, for example the drain, of the transistor 112, is coupled, preferably connected, to the node 118, a second conduction terminal of the transistor 112, for example the source, is coupled, preferably connected, to the node 122, and the gate of the transistor 112 receives the signal sigCTRL. Preferably, when the signal sigCTRL is switched to a high potential equal to a supply potential of the chip 100 this is sufficient to switch the transistor 112 to the on state. Thus, the switch 112 is controlled by a signal, here a voltage, having a maximum value less than or equal to the value of the supply voltage of the chip 100.

[0053] The diode 114 couples the intermediate node 118 to an output node 124 of the converter 106. The node 124 is configured to provide the VHV potential. In other words, the converter 106 provides the VHV potential on its output node 124. The diode 114 has a first electrode, here its anode, coupled, preferably connected, to the node 118, and a second electrode, here its cathode, coupled, preferably connected, to the node 124. In practice, the diode 114 implements a switch function. In other words, the diode 114 is a (non-controllable) switch, called a high side switch. For example, the diode 114 is a Schottky diode.

[0054] The CTRL circuit is configured to control the switch 112, i.e. switchings of the switch 112, so as to maintain the potential VHV at a target value Vtarget. The target value Vtarget is, for example, greater than 15 V, preferably greater than or equal to 20 V, for example substantially equal to 25 V.

[0055] For this, the CTRL circuit is configured to receive a signal representative of the VHV potential, for example the VHV potential itself. Furthermore, the CTRL circuit is configured to provide the signal sigCTRL for controlling the switch 112. By way of example, the CTRL circuit is configured to control the switch 112 in pulse width modulation (PWM).

[0056] The CTRL circuit is part of the chip 100, unlike the inductor 110, the switch 112 and the diode 114 which are arranged outside the chip 100, that is to say they are not part of the chip 100. In particular, the node 118 is outside the chip 100.

[0057] Thus, the CTRL circuit comprises a terminal, or node or input, 126 configured to receive the signal representative of the VHV potential, and, more particularly, the VHV potential in the example of [Fig.l]. The terminal 126 of the CTRL circuit is coupled, preferably connected, to an input terminal 128 of the chip 100. The terminal 128 is configured to receive the VHV potential.

[0058] Although this is not detailed in [Fig.l], preferably, terminal 126 of the CTRL circuit corresponds, for example, to one end of a voltage divider bridge, for example a resistive voltage divider bridge, configured to divide the value of the potential VHV so as to obtain a potential representative of the potential VHV but whose value is compatible with the maximum voltages supported by the transistors of the chip 100. By way of example, this potential representative of the potential VHV has a maximum value lower than that of the power supply potential AVDD of the chip 100. The voltage divider bridge is for example part of the CTRL circuit, therefore of the chip 100.

[0059] More generally, instead of the voltage divider bridge, the CTRL circuit can comprise any usual circuit adapted to provide a potential which is representative of the VHV potential and which has a maximum value lower than that of the maximum voltage supported by the MOS transistors of the chip 100.

[0060] Terminal 128 is further coupled, preferably connected, to matrix 102 of pixels 104 of chip 100, such that the VHV potential on terminal 128 is supplied to matrix 102, more particularly to each pixel 104 of matrix 102, and even more particularly to each single-photon avalanche diode of matrix 102. Thus, each single-photon avalanche diode of matrix 102 receives the VHV potential, for example on its cathode as in the example of [Fig.2]. For example, for a potential VHV, i.e. a target value Vtarget, of the order of 25 V, the current drawn by the matrix 102 on the node 124 is of the order of 30 mA in stationary operation, and can reach, for example, at least 45 mA during transient current calls.

[0061] Further, the CTRL circuit includes a terminal, or node or output, 130 configured to provide the control signal sigCTRL. The terminal 130 is coupled, preferably connected, to an output terminal 132 of the chip 100. The output terminal 132 is configured to provide the signal sigCTRL to the switch 112 disposed externally of the chip 100. The terminal 132 is connected to the control terminal of the switch 112.

[0062] As an example, the chip 100 is powered by a potential AVDD, the chip 100 then comprising a terminal 120 configured to receive the potential AVDD, and a terminal 121 configured to receive the reference potential GND. For example, the supply potential AVDD of the chip 100 has a value substantially equal to 3.6 V.

[0063] For example, the CTRL circuit is also powered by the AVDD potential and then comprises a terminal or node 134 configured to receive the reference potential GND and a terminal 135 configured to receive the AVDD potential. For example, the terminal 134 is coupled, preferably connected, to the input terminal 121 of the chip 100. For example, the terminal 135 is coupled, preferably connected, to the input terminal 120 of the chip.

[0064] In a usual manner for switching boost converters, the converter 1 comprises a capacitor Cout coupling the nodes 124 and 122 together. For example, the capacitor Cout comprises a first electrode coupled, preferably connected, to the node 124 and a second electrode coupled, preferably connected, to the node 122.

[0065] By way of example, the converter 1 further comprises a capacitor Cin coupling the node 116 to the node 122. For example, the capacitor Cin comprises a first electrode coupled, preferably connected, to the node 124 and a second electrode coupled, preferably connected, to the node 122. This capacitor Cin may be omitted, for example when the impedance between a voltage source providing the potential Vbat and the node 116 is sufficiently low so that the voltage drops on the node 116 during current draws on the node 116 by the converter 106 are negligible.

[0066] According to one embodiment, at least the inductor 110, the switch 112 and the diode 114 of the converter 306 are arranged outside the chip 100, and at least the control circuit CTRL of the converter 106 is part of the chip 100.

[0067] Although not illustrated, the chip 100 comprises numerous MOS transistors, for example in control circuits and reading circuits of the pixels 104 of the matrix 102. These transistors are not intended to implement power applications, and are therefore not capable of withstanding high voltages, for example the voltage applied to the terminals of each single-photon avalanche diode of the matrix 102 to place this diode in Geiger mode. For example, most of the MOS transistors of the chip 100 are configured to withstand voltages lower than Vbat. For example, some transistors of the chip 100 are configured to withstand maximum voltages higher than Vbat and the other transistors are standard low voltage transistors, for example configured to withstand between their terminals voltages lower than or equal to the voltage AVDD.

[0068] According to one embodiment, the chip 100 and the components of the converter 106 which are external to the chip 100, namely the inductor 110, the switch 112, the diode 114, and, when present, the capacitors Cin and Cout are mounted on a support or substrate 140. The support 140 is part of the sensor 1. According to an alternative embodiment, the capacitors Cin and / or Cout can be arranged outside the sensor 1.

[0069] By way of example, the sensor 1, and more particularly its support 140, comprise an input terminal 108 configured to receive the potential Vbat. By way of example, the potential Vbat is supplied to the sensor 1 by a circuit external to the sensor 1.

[0070] By way of example, the sensor 1, and more particularly its support 140, comprise an input terminal 109 configured to receive the potential AVDD. By way of example, the potential AVDD is supplied to the sensor 1 by a circuit external to the sensor 1.

[0071] As an alternative example, the potentials AVDD and Vbat are merged, terminal 108 then being, for example, merged with terminal 109.

[0072] As another alternative example, the sensor 1 receives from the outside only one of the potentials AVDD and Vbat, for example the potential Vbat, and comprises a circuit configured to provide the other of the potentials AVDD and Vbat, for example the potential AVDD, from the potential received by the sensor 1.

[0073] Although this is not detailed in [Fig.l], the support 140 comprises conductive tracks, so as to implement the couplings or connections described previously between the chip 100, and, more particularly the input and output terminals of the chip 100, and the components of the converter 106 which are arranged outside the chip 100.

[0074] Although not illustrated in [Fig.l], when the sensor 1 is a time-of-flight sensor, the sensor 1 may further comprise one or more light sources, for example one or more vertical-cavity surface-emitting laser (VCSEL) diodes, and the close-control circuit(s) for these light sources. The light source(s) and the close-control circuit(s) are configured to emit a light signal towards a scene, the matrix 102 being configured to receive the corresponding signal reflected by the scene. The light source(s) and the close-control circuit(s) are preferably discrete components mounted on the support 140. Other discrete components of the sensor 1 may also be mounted on the support 140.Furthermore, the sensor 1 comprises, for example, a protective housing mounted on, or assembled with, the support 140. The housing comprises an opening facing the matrix 102 of pixels 104 and an opening facing the light source(s). All the components and the chip(s) of the sensor 1 which are mounted on the support 140 are then encapsulated in this housing. In other words, the sensor 1 then constitutes a ready-to-use module ("plug and play"). play" in English) which simply needs to be powered, for example by supplying the potentials Vbat and AVDD to the terminals 108 and 109 of the support 140, for the sensor 1 to operate. For example, the support 140 is then configured to be assembled to a motherboard of a complex electronic system, such as for example a smartphone, for example on a printed circuit board (PCB) or a flexible printed circuit board (Flex PCB).

[0075] The components of the converter 106 which are arranged outside the chip 100 are standard, readily available components.

[0076] Rather than integrating the CTRL circuit into the chip 100 of the sensor 1, that is to say into the chip 100 comprising the pixels 104 of the sensor 1, one could have thought of using a switching boost converter entirely arranged outside the chip, in the form of a discrete component which would have been mounted on the support 140. However, this would have increased the size of the support 140, and therefore the size of the sensor 1, for example when the sensor 1 is a ready-to-use module.

[0077] One could also have thought of directly supplying the VHV potential to the sensor 1 by arranging the converter 106 entirely outside the sensor 1, that is to say that the converter 106 would then not have been mounted on the same support 140 as the chip 100. However, this would have increased the distance between the converter supplying the VHV potential and the sensor 1, which would have led to increasing the losses and / or increasing the response times of the converter and / or reducing the fineness of control of the value of the VHV potential.

[0078] Furthermore, rather than providing that the converter 106 of the sensor 1 is arranged partly in the chip 100 and partly outside the chip 100, one could have considered using a charge pump entirely integrated in the chip 100. However, the efficiency of such a charge pump would have been much lower than that of the converter 106, and, in addition, the surface area occupied by the charge pump would have been much larger than that occupied by the CTRL circuit.For example, considering a charge pump whose efficiency is of the order of 25%, to provide at the output of the charge pump a maximum current of the order of 45 mA for a potential VHV substantially equal to 25 V, that is to say to provide approximately 1 W at the output of the charge pump, the power source providing the potential Vbat would have had to be capable of delivering more than 4 W of supply power, which is too high a consumption compared to that which a switching DC-DC converter would have to provide the same output power. For example, the high consumption linked to the use of a charge pump harms the autonomy of a mobile object powered by battery.

[0079] One could have thought of integrating the switch 112 into the chip 100. However, the switch 112 sees between its terminals voltages up to the value of the potential VHV, and the chip 100, in particular its MOS transistors which could have been envisaged to implement the switch 112, are not designed to withstand such voltages.

[0080] Furthermore, the provision of the CTRL circuit as an integral part of the chip 100 allows finer control of the value of the potential VHV, i.e. the target value Vtarget, necessary for the proper operation of the single-photon avalanche diodes of the matrix 102, compared to the case where this CTRL circuit would have been arranged outside the chip 100. For example, the CTRL circuit can be configured to modify the value Vtarget as a function of the operating conditions of the chip 100, for example as a function of the temperature of the chip 100, and therefore of the single-photon avalanche diodes.

[0081] More generally, the implementation of the converter 106 of the sensor 1 as described in relation to [Fig.l] allows better conversion efficiency, better efficiency of regulation of the VHV potential with a smaller footprint than if the converter 106 were replaced by a charge pump integrated into the chip 100 or by a switching boost converter completely external to the chip.

[0082] In an alternative embodiment not shown, the high-side switch of the converter 106 is implemented by a controllable switch rather than by the diode 114 which corresponds to a non-controllable switch. The controllable switch replacing the diode 14 is then controlled by the CTRL circuit. This high-side controllable switch is, for example, a P-channel MOS transistor. In this case, the control signal, typically a control voltage, of the high-side PMOS transistor has a value much higher than what the circuits of the chip 100 are capable of delivering and / or supporting. The high-side transistor is then provided with a voltage translation circuit ("level-shifter" in English) making it possible to provide a control voltage adapted to the high-side transistor from a control signal provided by the CTRL circuit.This voltage translation circuit and the high-side transistor are then in the form of one or more discrete components mounted on the support 140.

[0083] Implementing the high side switch of converter 106 with diode 114 rather than with a MOS transistor is advantageous in that it is less complex and less bulky.

[0084] [Fig. 3] shows, schematically and partly in block form, a more detailed example of the CTRL circuit of the sensor of [Fig. 1]. In this example, the CTRL circuit implements a PWM control of the switch 112. Terminal 135 of the CTRL circuit is not shown in [Fig. 3].

[0085] In the example of [Fig. 3], the CTRL circuit comprises a resistive voltage divider bridge 300, connected between the inputs, or terminals, 126 and 134 of the CTRL circuit. The voltage divider bridge 300 is configured to divide the value of the potential VHV and provide this divided value Vfb on a node 302. In other words, the divider bridge 300 receives the potential VHV and provides the potential Vfb from the potential VHV, the potential Vfb being representative of the potential VHV and being lower than the potential VHV. Preferably, the voltage Vfb is lower than the maximum voltage that the components, in particular the transistors, of the chip 100 can withstand. For example, the voltage Vfb is lower than the voltage Vbat, preferably lower than the voltage AVDD.

[0086] For example, the voltage divider bridge 300 comprises a resistor RI connected between nodes 126 and 302, and a resistor R2 connected between nodes 302 and 134.

[0087] The CTRL circuit comprises a circuit 306. The circuit 306 is configured to provide an err signal representative of the difference in value, i.e. the error, between the voltage Vfb and a voltage Vref. The voltage value Vref is determined by the value Vtarget. Thus, the err signal is representative of the difference in value, or error, between the potential VHV and its target value. The circuit 306 is configured to receive the signal Vfb, the signal Vref and to provide the err signal. For example, the circuit 306 implements a proportional integral derivative (PID) filtering function. For example, the circuit 306 comprises an operational amplifier mounted as an error amplifier, the usual passive components of this error amplifier not being shown in [Fig.3] so as not to overload the figure.For example, the signal Vref is received by one input of the circuit 306, for example the non-inverting input (+) of the operational amplifier, the signal Vfb is received by another input of the circuit 306, for example the inverting input (-) of the operational amplifier, and the signal err is available at the output of the circuit 306, for example at the output of the operational amplifier.

[0088] The CTRL circuit further comprises a circuit 308. The circuit 308 is configured to provide a periodic sawtooth signal sigl. The frequency of the signal sigl corresponds, in this example, to the switching frequency of the switch 112 (see [Fig.l]), and is, for example, of the order of 10 MHz.

[0089] The CTRL circuit further comprises a circuit 310 configured to compare the signal sigl with the signal err, and to provide a binary signal cmp whose binary state indicates the result of this comparison. For example, the signal cmp is in a first binary state when the signal err is less than the signal sigl, and in a second binary state when the signal err is greater than the signal sigl. Thus, the width of each pulse of the signal cmp is modulated according to the value of the potential VHV.

[0090] The CTRL circuit may comprise, as illustrated in [Fig.3], a circuit 312 configured to provide the sigCTRL signal from the cmp signal. The circuit 312 is configured to shape the cmp signal to generate the sigCTRL signal. For example, circuit 312 is a buffer circuit. For example, each switching of the cmp signal causes a corresponding switching of the sigCTRL signal, and each switching of the sigCTRL signal is caused by a corresponding switching of the cmp signal.

[0091] According to another example not illustrated, circuit 312 can be omitted.

[0092] Although a case has been described above, in particular in relation to [Fig. 3], where the CTRL circuit is configured to control the switch 112 ([Fig. 1]) in PWM, the present description is not limited to this example of control. Indeed, as an alternative example, the CTRL circuit can implement a pulse frequency modulation (PFM) control, or a hysteresis type control. In yet another example, the CTRL circuit can be configured to switch between at least two control modes of the switch 112, for example between a PWM control and a PFM control, these switches between these different control modes being, for example, determined by the power drawn by the chip 100 on the node 124 (see [Fig. 1]).

[0093] For example, in embodiments, the CTRL circuit may need to know the current in the inductor, e.g., whether the current is zero or not, to generate the sigCTRL signal.

[0094] In this case, the converter 106 may comprise a circuit configured to determine the current in the inductor 110, for example a circuit configured to detect when the current in the inductor 110 becomes zero.

[0095] [Fig.4] shows, schematically and at least partly in the form of blocks, an alternative embodiment of the sensor 1 of [Fig.l]. Only the differences between the converter 1 of [Fig.l] and that of [Fig.4] are highlighted here.

[0096] In this variant, the circuit CTRL is configured to generate the signal sigCTRL not only from the value of the potential VHV, that is to say from the difference in value between the potential VHV actually available on the node 124 and the intended value Vtarget of the potential VHV, but, in addition, from the value of the current IL in the inductor 110, for example from a detection that the current IL in the inductor is cancelled.

[0097] Thus, with respect to the converter 106 of [Fig.l], the converter 106 of [Fig.4] comprises a resistor Rs, for example called a measuring resistor ("shunt resistor" in English).

[0098] This resistance Rs is connected in series with the inductance 110, between the nodes 118 and 116.

[0099] For example, in [Fig.4], the resistor Rs has one end, or terminal, connected to the node 116, another end, or terminal, connected to an electrode of the inductor 110, the other electrode of the inductor 110 being connected to the node 118. As an alternative example not shown, the resistor Rs has one end, or terminal, connected to the node 118, another end, or terminal, connected to an electrode of the inductor 110, the other electrode of the inductor 110 being connected to the node 116.

[0100] Preferably, the resistor Rs is connected on the side of the node 116, so that the voltage on each terminal of the resistor Rs remains less than or equal to a maximum voltage value that the transistors of the chip 100 can withstand.

[0101] The resistor Rs is, like the elements 110, 112 and 114, and, when present, the capacitors Cin and Cout, arranged outside the chip 100.

[0102] The CTRL circuit comprises two terminals, or nodes or inputs, 402 and 406 each configured to receive the voltage on one of the terminals of the resistor Rs. Thus, the chip 100 comprises two terminals, or inputs, 400 and 408 each connected to a different end or terminal of the resistor Rs, and to the control circuit.

[0103] In the example of [Fig.4], terminal 408 of chip 100 is connected to a first end of resistor Rs, namely, in this example, node 116, and terminal 400 of chip 100 is connected to a second end of resistor Rs, namely, in this example, a connection node 404 between inductor 110 and resistor Rs. Furthermore, terminal 408 of chip 100 is connected to terminal 406 of CTRL circuit and terminal 400 of chip 100 is connected to terminal 402 of CTRL circuit.

[0104] The person skilled in the art is able to adapt the description given above in relation to [Fig.4] to the case where the potentials AVDD and Vbat are the same and / or to the case where the resistor Rs has a terminal connected to the node 118.

[0105] Various embodiments and variants have been described. Those skilled in the art will understand that certain features of these various embodiments and variants could be combined, and other variants will occur to those skilled in the art. In particular, those skilled in the art are able to provide other embodiments of a switching boost converter whose low-side switch, the high-side switch, preferably a diode, and the inductor are arranged outside an integrated circuit chip comprising a matrix of pixels each comprising a single-photon avalanche diode, and whose control circuit for the low-side switch, or in other words, the voltage and / or current feedback loop of the converter, is an integral part of this chip.In this case, according to one embodiment, the high side and low side switches of the converter, i.e. the chopping switches of the converter, the inductor, and the measuring resistor when present, are mounted on the same support as the chip, for example when the sensor forms a ready-to-use module.

[0106] Finally, the practical implementation of the described embodiments and variants is at the scope of the person skilled in the art from the functional indications given above.

Claims

Claims

1. A light sensor (1) comprising an integrated circuit chip (100) and a DC-DC boost converter (106), wherein: the integrated circuit chip (100) comprises a matrix of pixels (102, 104), each pixel (104) comprising at least one single-photon avalanche diode (200); the converter (106) is configured to deliver a bias potential (VHV) to the diodes (200) of the pixels (102), the bias potential (VHV) being capable of placing said diodes in Geiger mode; the converter (106) comprises: - an inductor (110) coupling a node (116) configured to receive a first supply potential (Vbat) to an intermediate node (118); - a first switch (112) coupling the intermediate node (118) to a reference potential (GND);- a second switch (114) coupling the intermediate node (118) to an output node (124) of the converter, the output node (124) being configured to deliver said bias potential (VHV); and - a control circuit (CTRL) configured to control switchings of the first switch (112), the inductor (110), the first switch (112) and the second switch (114) of the converter being arranged outside the integrated circuit chip (100) and the control circuit (CTRL) belonging to said integrated circuit chip (100).;

2. The light sensor of claim 1, wherein the second switch (114) is a diode.

3. The light sensor of claim 1 or 2, wherein the converter (106) further comprises a first capacitor (Cout) coupling the output node (124) to the reference potential (GND), the first capacitor being disposed external to the integrated circuit chip (100).

4. A light sensor according to any one of claims 1 to 3, wherein the output node (124) of the converter (106) is connected to an input terminal (128) of the integrated circuit chip (100).

5. A light sensor according to claim 4, wherein the input terminal (128) of the integrated circuit chip (100) is coupled, preferably connected, to an input (126) of the control circuit (CTRL).

6. A light sensor according to claim 4 or 5, wherein the input terminal (128) of the chip (100) is coupled to the pixel array (102, 104) such that a potential (VHV) on the input terminal (128) is supplied to each single-photon avalanche diode (200) of the pixel array (102, 104) of the integrated circuit chip (100).

7. Light sensor according to any one of claims 1 to 6, wherein the bias potential (VHV) has a target value greater than 15 V, preferably greater than or equal to 20 V.

8. A light sensor according to any one of claims 1 to 7, configured to implement a time-of-flight capture function.

9. A light sensor according to any one of claims 1 to 8, wherein a control terminal of the first switch (112) of the converter (106) is connected to an output terminal (132) of the integrated circuit chip (100).

10. A light sensor according to claim 9, wherein an output (130) of the control circuit (CTRL) is coupled, preferably connected, to the output terminal (132) of the integrated circuit chip (100).

11. The light sensor of any one of claims 1 to 10, wherein the converter (106) further comprises a second capacitor (Cin) coupling the node (116) configured to receive the first supply potential (Vbat) to the reference potential (GND), the second capacitor (Cin) being disposed outside the integrated circuit chip (100).

12. A light sensor according to any one of claims 1 to 11, wherein the integrated circuit chip (100) comprises a terminal (121) configured to receive the reference potential (GND).

13. A light sensor according to any one of claims 1 to 12, wherein the converter (106) further comprises a resistor (Rs) connected in series with the inductor (110), between the node (116) configured to receive the first supply potential (Vbat) and the intermediate node (118), the resistor (Rs) being arranged outside the integrated circuit chip (100) and the chip (100) comprising two terminals (408, 400) each connected to a different end of the resistor (Rs) and to the control circuit (CTRL, 402, 406).

14. A light sensor according to any one of claims 1 to 13, comprising a substrate (140) on which the circuit chip is mounted integrated (100) of the components (110, 112, 114, Rs, Cin, Cout) of the converter (106) which are arranged outside the integrated circuit chip (100), the support (140) comprising conductive tracks configured to connect together the chip (100) and the components (110, 112, 114, Rs, Cin, Cout) of the converter (106) which are arranged outside the integrated circuit chip (100).

15. The light sensor (1) of claim 14, wherein the sensor further comprises: - a protective casing mounted on the support; and - at least one light source mounted on the support (140), the chip (100), the inductance (110) of the converter, the first and second switches (114, 112) of the converter and said at least one light source being encapsulated in said housing, and the sensor forming a ready-to-use module.

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