Piezoelectric substrate on insulator (POI) and process for manufacturing a piezoelectric substrate on insulator (POI)

Abstract

The invention relates to a piezoelectric substrate on insulation (POI) (100) comprising a support substrate (102), in particular a silicon-based substrate, a piezoelectric layer (108), in particular a lithium tantalate (LTO) or lithium niobate (LNO) layer, a dielectric layer (106), in particular a silicon oxide layer, sandwiched between the piezoelectric layer (108) and the support substrate (102), and a trapping structure (104) sandwiched between the dielectric layer (106) and the support substrate (102). The substrate (100) is characterized in that the trapping structure (104) comprises at least two trapping layers (104a, 104b) made of different materials. The invention also relates to a method for manufacturing a piezoelectric substrate on insulation (POI). Figure 1 for the abstract

Description

Title of the invention: Piezoelectric-on-insulator (POI) substrate and method of manufacturing a piezoelectric-on-insulator (POI) substrate

[0001] The invention relates to a piezoelectric on insulator (POI) substrate comprising in this order a support substrate, a trapping structure, a dielectric layer and a piezoelectric layer, as well as a method of manufacturing such a POI substrate.

[0002] Such substrates are known in the state of the art, for example a POI substrate comprising a monocrystalline silicon substrate, a polycrystalline silicon trapping structure, a silicon oxide layer and a piezoelectric layer, in particular a lithium tantalate (LTO) or lithium niobate (LNO) layer. The trapping structure makes it possible to reduce losses linked to parasitic conduction effects at the interface between the support substrate and the dielectric layer. Indeed, the trapping layer, which is inserted between the support substrate and the dielectric layer, serves to reduce the lifetime of the charges in this region.

[0003] However, it is observed that, during heat treatments as part of or subsequent to the manufacture of POI substrates, metallic elements of the piezoelectric layer, such as lithium, can diffuse through the dielectric layer and the trapping structure to the interface with the support substrate. The accumulation of these metallic elements reduces the performance of the trapping structure and the suppression of parasitic currents is thus negatively affected.

[0004] It is possible to increase the thickness of the trapping layer to increase the number of available traps. However, in this case, parasitic modes appear in devices using the POI substrate, such as filters, sensors, etc.

[0005] The object of the invention is therefore to increase the number of traps with less risk of the appearance of parasitic effects.

[0006] The subject of the invention is achieved by a piezoelectric on insulator (POI) substrate comprising: a support substrate, in particular a silicon-based substrate, a piezoelectric layer, in particular a lithium tantalate (LTO) or lithium niobate (LNO) layer, a dielectric layer, in particular a silicon oxide layer, sandwiched between the piezoelectric layer and the support substrate, and a trapping structure sandwiched between the dielectric layer and the support substrate comprising a first trapping layer based on polycrystalline or amorphous or porous silicon, preferably based on polycrystalline silicon. This POI substrate is characterized in that the trapping structure comprises a second trapping layer based on a different material.

[0007] Adding a second trapping layer with a different material in the trapping structure allows the number of traps to be increased, without having to increase the total thickness of the trapping structure to the same extent as would be necessary in the case of a single-material trapping structure.

[0008] According to one embodiment, the second trapping layer may be based on silicon carbide. A second layer based on silicon carbide makes it possible to effectively reduce parasitic currents.

[0009] According to one embodiment, the second silicon carbide-based trapping layer may be thinner than the first layer. Thus, the provision of a thinner layer of silicon carbide makes it possible to increase the number of traps, while limiting the appearance of parasitic modes due to the presence of the trapping structure, in particular in comparison with a single-material silicon-based trapping layer having the same number of traps.

[0010] According to one embodiment, the second silicon carbide-based trapping layer may have a thickness less than or equal to 500 nm, in particular a thickness less than or equal to 200 nm, more in particular less than or equal to 50 nm. Even for such small thicknesses, a sufficient increase in the number of traps is observed.

[0011] According to one embodiment, the first silicon-based trapping layer may have a thickness less than or equal to 2 μm, in particular a thickness less than or equal to 1 μm. By using a second trapping layer, it becomes possible to keep the thickness of the first trapping layer sufficiently low. Thus, the parasitic modes due to this layer cannot develop, or at least their contribution remains negligible.

[0012] According to one embodiment, the second trapping layer can be directly formed on the first trapping layer. Thus, a compact structure can be maintained.

[0013] According to one embodiment, the first trapping layer is positioned between the support substrate and the second trapping layer. This facilitates the formation of the trapping structure, because a silicon carbide layer is deposited at a lower temperature than a silicon layer.

[0014] The subject matter of the invention is also achieved by a method of manufacturing a piezoelectric-on-insulator (POI) substrate as described above and comprising the steps of: providing a support substrate, in particular a silicon-based substrate, providing a substrate comprising a piezoelectric layer, in particular a substrate comprising lithium tantalate (LTO) or lithium niobate (LNO), forming a trapping structure over the support substrate, forming a dielectric layer, in particular a silicon oxide layer, over the substrate comprising a piezoelectric layer and / or over the trapping structure, assembling the piezoelectric substrate with the support substrate such that the dielectric layer and the trapping structure are sandwiched between the piezoelectric layer and the support substrate, characterized in that the formation of the trapping structure comprises the formation of a first layer based on polycrystalline or amorphous or porous silicon, preferably based on polycrystalline silicon, and the formation of a second trapping layer based on a different material.

[0015] According to one embodiment, the method for manufacturing a piezoelectric substrate may further comprise a step of: forming a weakening zone inside the piezoelectric layer, in particular before the assembly step, and performing a fracture along the weakening zone to separate a portion of the piezoelectric layer from the remainder of the substrate comprising the piezoelectric layer after the assembly step to transfer the portion of the piezoelectric layer onto the support substrate. This method makes it possible to manufacture the POI substrates according to the invention industrially.

[0016] The invention and its advantages are described in more detail hereinafter by means of advantageous exemplary embodiments and with particular reference to the following accompanying figures, in which the reference numerals identify features of the invention.

[0017] [Fig-1] schematically represents a piezoelectric substrate on insulator (POI) according to a first embodiment of the invention.

[0018] [Fig.2] schematically represents a method of manufacturing a piezo substrate electrical on insulator (POI) according to a second embodiment of the invention.

[0019] The embodiments described are merely possible configurations and it should be borne in mind that individual features as described above may be provided independently of one another, or may be omitted altogether when implementing the present invention.

[0020] [Fig.l] schematically represents a piezoelectric on insulator (POI) substrate 100 according to the first embodiment of the invention.

[0021] The piezoelectric substrate on insulator 100 comprises a support substrate 102. In this first embodiment, the support substrate 102 is a silicon-based substrate, in particular a monocrystalline silicon wafer.

[0022] A trapping structure 104 is arranged over the support substrate 102. The trapping structure 104 may be in direct contact with the support substrate 102. The trapping structure 104 has a thickness equal to or less than 2 pm, preferably equal to or less than 1 pm, even more preferably equal to or less than 600 nm.

[0023] According to the first embodiment, the trapping structure 104 comprises two layers: a first trapping layer 104a and a second trapping layer 104b having a material different from the material of the first trapping layer 104a.

[0024] The first trapping layer 104a is based on polycrystalline silicon or based on amorphous silicon or based on porous silicon. The second trapping layer 104b is based on silicon carbide (SiC). Preferably these are layers deposited by low pressure chemical vapor deposition (LPCVD) or by plasma activated chemical vapor deposition (PECVD) or by high density plasma activated chemical vapor deposition (HDP-CVD).

[0025] In this embodiment, the two trapping layers 104a, 104b have different thicknesses. The silicon-based trapping layer 104a preferably has a thickness less than or equal to 2 μm, in particular a thickness less than or equal to 1 μm. The silicon carbide-based trapping layer 104b preferably has a thickness less than or equal to 500 nm, in particular a thickness less than or equal to 200 nm, and more particularly a thickness less than or equal to 50 nm. According to an example of the invention, the first trapping layer 104a has a thickness of 500 nm and the second trapping layer 104b has a thickness of 50 nm.

[0026] A dielectric layer 106 is arranged over, in particular directly on the trapping structure 104. The dielectric layer 106 is preferably a silicon oxide-based layer. The dielectric layer 106 preferably has a thickness between 100nm and 1pm, in particular between 200nm and 700nm. The dielectric layer 106 may be formed by CVD deposition or any other suitable deposition method.

[0027] A piezoelectric layer 108 is arranged on top, in particular directly on the dielectric layer 106. It is preferably a layer of lithium tantalate (LTO) or lithium niobate (LNO). The piezoelectric layer 108 typically has a thickness of between 200nm and 1pm.

[0028] The use of a trapping structure 104 with two trapping layers 104a, 104b of different materials makes it possible to increase the number of traps without excessively increasing the thickness of the trapping structure 104.

[0029] By adding a second trapping layer 104b of a different material, and in particular thinner, it becomes possible to increase the number of traps while keeping the thickness of the trapping structure sufficiently low to limit the appearance of parasitic modes in final devices such as sensors, filters, etc.

[0030] According to a variant, the order of the first trapping layer 104a and the second trapping layer 104b can be reversed. In this case, it is the second trapping layer based on silicon carbide which is located between the support substrate 102 and the first trapping layer 104a based on polycrystalline silicon or based on amorphous silicon or based on porous silicon.

[0031] [Fig.2] schematically represents a method of manufacturing a piezo substrate electrical on insulator (POI) according to the second embodiment of the invention to obtain a POI substrate 100 according to the first embodiment as described above in relation to [Fig.l]. The reference numbers already used in reference to [Fig.l] in the context of the description of the POI substrate 100 are reused in order to describe the method of the second embodiment.

[0032] The method for manufacturing a piezoelectric-on-insulator (POI) substrate 100 begins with step I) of providing a support substrate 102, in particular a silicon-based substrate, in particular a monocrystalline silicon wafer.

[0033] According to this second embodiment of the invention, step II) provides for the formation of the trapping structure 104 on a free surface 120 of the support substrate 102.

[0034] The formation of the trapping structure 104 begins with the formation of a first trapping layer 104a made by low pressure chemical vapor deposition (LPCVD). According to variants, the formation of the first trapping layer 104a of step II) can be carried out by a thermal growth technique or by physical vapor deposition (PVD).

[0035] The trapping layer 104a formed on the support substrate 102 is a layer based on polycrystalline silicon, based on amorphous silicon or based on porous silicon.

[0036] The thickness of the trapping layer 104a is equal to or less than 2 pm, in particular equal to or less than 1 pm.

[0037] Next, a second trapping layer 104b is formed on the first trapping layer 104b. This second trapping layer 104b is based on silicon carbide. The second trapping layer 104b is formed with a thickness less than the first trapping layer, preferably with a thickness equal to or less than 500nm, in particular a thickness less than or equal to 200nm, more in particular with a thickness equal to or less than 50nm.

[0038] The second trapping layer 104b is formed by low pressure chemical vapor deposition (LPCVD) or by plasma activated chemical vapor deposition (PECVD) or by high density plasma activated chemical vapor deposition (HDP-CVD). According to variants, the formation of the second trapping layer 104b during step II) can be carried out by a thermal growth technique or by physical vapor deposition (PVD). Typically the formation of the second trapping layer 104b is carried out at a lower temperature than the first trapping layer 104a.

[0039] Before the formation of the second trapping layer, one or more treatments of the surface of the first trapping layer 104a may take place, such as polishing, in particular CMP type polishing, or activation of the surface by plasma or ozone treatment.

[0040] During step III) a dielectric layer 106a is formed on the free surface 122 of the second trapping layer 104b. The dielectric layer 106a is preferably a silicon oxide layer formed by chemical vapor deposition (CVD) or physical vapor deposition (PVD).

[0041] The dielectric layer 106a preferably has a thickness equal to or less than 1pm, in particular equal to or less than 700nm.

[0042] A heat treatment can be carried out after the deposition of the dielectric layer 106a to densify it.

[0043] In step IV), a substrate 124 comprising a piezoelectric layer 126, in particular a substrate 124 comprising lithium tantalate (LTO) or lithium niobate (LNO), is provided. The piezoelectric layer 124 is, in this embodiment, arranged on top of a base substrate 126. In an alternative, the piezoelectric layer 126 is a bulk layer and forms the entire substrate 124.

[0044] During step V) a second dielectric layer 106b, in particular a silicon oxide layer, is produced on the free surface 130 of the piezoelectric layer 126. This layer is produced in the same way as the dielectric layer 106a formed during step III). The thickness is chosen such that the sum of the thicknesses of the two dielectric layers 106a and 106b is between 100nm and 1pm, in particular between 200nm and 700nm.

[0045] According to a variant, one or more surface treatment steps of the free surface 130 of the substrate 124 comprising a piezoelectric layer may be carried out before the formation of the dielectric layer 106b. For example, a surface activation treatment may be carried out, such as a plasma treatment and / or an ozone-based treatment.

[0046] During step VI), the substrate 124 obtained after step V) is assembled with the support substrate 102 obtained in step III) to form a support substrate - substrate assembly 132 comprising a piezoelectric layer.

[0047] The assembly is implemented in such a way that the dielectric layers 106a and 106b are brought into direct contact. The assembly is preferably implemented by molecular adhesion.

[0048] Once the two substrates are assembled, a thinning step VII) of the assembly 132 is carried out to obtain the POI substrate 100 with a thinner piezoelectric layer 108, as illustrated in [Fig.l].

[0049] For example, the thinning step can be carried out by grinding, or by a step of forming a weakening zone in the piezoelectric layer 126 before the assembly step VI), so as to delimit the piezoelectric layer 108 to be transferred onto the support substrate 102, followed by fracturing. This step of forming a weakening zone is carried out by implanting atomic or ionic species in the piezoelectric layer 126. The atomic or ionic can be produced in such a way that the weakening zone is located inside the piezoelectric layer 126 and delimits a piezoelectric layer 108 to be transferred from the rest of the piezoelectric layer 126. Then, a step of fracturing the assembly 132 by a supply of thermal and / or mechanical energy at the weakening zone of the piezoelectric layer 126 is then carried out, in order to obtain the piezoelectric substrate on insulator (POI) 100.

[0050] According to variants, the bonding between the support substrate 102 and the substrate 124 can also be done between the trapping structure 104 and the dielectric layer 106b, i.e. without carrying out step III), or between the dielectric layer 106a and the piezoelectric layer 126.

[0051] Before the production of one or more of the above-mentioned layers, one or more steps of cleaning, brushing or polishing the surface directly below may be carried out to remove the presence of particles and dust.

Claims

Claims

1. Piezoelectric on insulator (POI) substrate comprising: - a support substrate (102), in particular a silicon-based substrate, - a piezoelectric layer (108), in particular a lithium tantalate (LTO) or lithium niobate (LNO) layer, - a dielectric layer (106), in particular a silicon oxide layer, sandwiched between the piezoelectric layer (108) and the support substrate (102), - a trapping structure (104) sandwiched between the dielectric layer (106) and the support substrate (102) comprising a first trapping layer (104a) based on polycrystalline or amorphous or porous silicon, preferably based on polycrystalline silicon, and, the trapping structure (104) comprises a second trapping layer (104b) based on silicon carbide characterized in that the first trapping layer (104a) is a silicon carbide-based trapping layer (104b) and the second trapping layer (104b) is a silicon carbide-based trapping layer (104b). trapping layer (104a) is positioned between the support substrate (102) and the second trapping layer (104b).

2. The piezoelectric on insulator (POI) substrate of claim 1, wherein the second trapping layer (104b) is thinner than the first trapping layer (104a).

3. A piezoelectric on insulator (POI) substrate according to claim 1 or 2, wherein the second trapping layer (104b) has a thickness less than or equal to 500nm, in particular a thickness less than or equal to 200nm, in particular a thickness less than or equal to 50nm.

4. Piezoelectric substrate on insulator (POI) according to one of claims 1 to 3, wherein the first trapping layer has a thickness less than or equal to 2 pm, in particular a thickness less than or equal to 1 pm.

5. A piezoelectric on insulator (POI) substrate according to one of claims 1 to 4, wherein the second trapping layer (104b) is directly formed on the first trapping layer (104a).

6. A method of manufacturing a piezoelectric on insulator (POI) substrate according to one of claims 1 to 5 comprising the steps of: - providing a support substrate, in particular a silicon-based substrate, - providing a substrate comprising a piezoelectric layer, in particular a substrate comprising lithium tantalate (LTO) or

7. lithium niobate (LNO), - form a trapping structure over the support substrate, - forming a dielectric layer, in particular a silicon oxide layer, over the piezoelectric substrate and / or over the trapping structure, - assembling the substrate comprising a piezoelectric layer with the support substrate such that the dielectric layer and the trapping structure are sandwiched between the piezoelectric layer and the support substrate; the formation of the trapping structure comprises the formation of a first layer based on polycrystalline or amorphous or porous silicon on the support substrate, preferably based on polycrystalline silicon, and then the formation of a second trapping layer based on silicon carbide. A method of manufacturing a piezoelectric substrate according to claim 6, further comprising a step of: - form a weakening zone inside the piezoelectric layer, and - performing a fracture along the weakening zone to separate a portion of the piezoelectric layer from the remainder of the substrate comprising the piezoelectric layer after the assembly step to transfer the portion of the piezoelectric layer onto the support substrate.

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