Display pixel including light-emitting sources

Abstract

Display Pixel Including Light-Emitting Sources This description relates to a display pixel (12i,j) for a display screen comprising a light-emitting circuit (LEDs) including at least one first light-emitting source, a controllable current source (82) for driving the light-emitting circuit with current pulses (I_LED), and a control circuit (70) for driving the current source. The control circuit is configured to receive a digital signal (Data) and to drive the current source to provide current pulses modulated by pulse-width modulation and pulse-amplitude modulation based on the bits of the digital signal. Figure for the abstract: Fig. 7

Description

Title of the invention: Display pixel comprising electroluminescent sources Technical field

[0001] The present description relates to a display pixel comprising light-emitting sources, for example light-emitting diodes, and a display screen having such display pixels. Prior art

[0002] A pixel of an image corresponds to the unit element of the image displayed by a display screen. For the display of color images, the display screen generally comprises, for the display of each pixel of the image, at least three components, also called display sub-pixels, which each emit light radiation, called image pixel color component essentially in the form of a single color (for example, red, green and blue). The superposition of the image pixel color components emitted by the three display sub-pixels provides the observer with the color sensation corresponding to the pixel of the displayed image. In this case, the assembly consisting of the three display sub-pixels used for the display of a pixel of an image is called a display pixel of the display screen. Each display sub-pixel may comprise a light source, in particular a light-emitting diode.

[0003] The display pixels may be distributed in an array, with each display pixel located at the intersection of a row (or line) and a column of the array. Typically, each row of the display pixels is successively selected and the display pixels in the selected row are programmed to display the desired image pixels.

[0004] An active array is a display control architecture that allows all rows of pixels to be kept active for the entire duration of an image, as opposed to arrays considered to be passive, in which each row is active only for a time T = Tframe / M (where Tframe is the duration of the display of the entire image and M is the number of rows on the screen). This allows the brightness of the display screen to be increased. In addition, it is possible to send low voltage or low current levels on the control lines of the array, which allows larger data streams to be displayed.

[0005] It is known to control a light-emitting source, for example a light-emitting diode, by pulse width modulation, also called PWM (acronym for the English translation "Pulse Width Modulation"). pulse width). This type of control consists of circulating successive current pulses of constant intensity in the light-emitting diode, the pulses being repeated cyclically, the duty cycle determining the light intensity emitted by the light-emitting diode. Such control advantageously makes it possible to operate the light-emitting diode at its optimum operating point at which the efficiency of the light-emitting diode, equal to the ratio between the light power emitted by the light-emitting diode and the electrical power consumed by the light-emitting diode, is maximum.

[0006] Color depth, also referred to as bit depth, is the number of bits used to encode the color for each color component of the image pixel of a single display pixel. It is generally desirable that the color depth be high. However, implementing pulse width modulation with high color depth can lead to complex display drive architectures, particularly because generating the pulse width modulation pulses can require generating many clock signals as the color depth increases. Summary of the invention

[0007] An object of an embodiment is to provide a display pixel comprising light-emitting sources and a display screen comprising such display pixels overcoming all or part of the disadvantages of existing display pixels comprising light-emitting sources and display screens comprising such display pixels.

[0008] Another object of an embodiment is to control by pulse width modulation display pixels having a high color depth.

[0009] Another object of an embodiment is to reduce the duration of a cycle of the control of the electroluminescent source.

[0010] One embodiment provides a display pixel for a display screen comprising a light emitting circuit comprising at least a first light emitting source, a controllable current source for driving the light emitting circuit with current pulses and a control circuit for controlling the current source, the control circuit being configured to receive a digital signal and to control the current source to provide the current pulses modulated by a pulse width modulation and modulated by a pulse amplitude modulation based on the bits of the digital signal. This advantageously reduces the number of clock signals required to implement the pulse amplitude modulation.

[0011] Compared to a control using pulse width modulation, the present embodiment advantageously makes it possible to reduce the duration of a control cycle of the electroluminescent source while maintaining the same color depth.

[0012] According to one embodiment, the control circuit is configured to control the current source to provide the current pulses modulated by pulse width modulation based on first bits of the digital signal and modulated by pulse amplitude modulation based on at least a second bit of the digital signal different from the first bits.

[0013] According to one embodiment, the at least one second bit comprises the most significant bit of the digital signal. This makes it possible to modify the current intensity in the light-emitting source only for high values ​​of the digital signal. In particular, when the light-emitting source comprises a three-dimensional light-emitting diode, this makes it possible to limit the wavelength shift of the light emitted by the light-emitting diode, which can occur when the intensity of the current flowing in the light-emitting diode varies, only at high values ​​of the digital signal.

[0014] According to one embodiment, the control circuit is configured to control the current source to provide the current pulses by pulse amplitude modulation based on at least two second bits of the digital signal. This advantageously makes it possible to further reduce the number of clock signals required to perform the pulse amplitude modulation and consequently to reduce the duration of a control cycle of the light-emitting source.

[0015] According to one embodiment, the control circuit is configured to control the current source to provide the current pulses by pulse amplitude modulation for three second bits of the digital signal. This advantageously makes it possible to further reduce the number of clock signals required to perform the pulse amplitude modulation and consequently to reduce the duration of a control cycle of the light-emitting source.

[0016] According to one embodiment, the control circuit comprises a first storage circuit for storing said first bits of the digital signal and the first storage circuit comprises a shift register synchronized by a pulse width modulated clock signal. The structure of the control circuit of the display pixel is advantageously simple and can occupy a reduced silicon area when the control circuit is manufactured in integrated form.

[0017] According to one embodiment, the control circuit comprises a second storage circuit for storing said at least one second bit of the digital signal and a logic circuit controlled by a control signal and configured to receive successively the first bits from the shift register synchronized by the pulse width modulated clock signal and to receive said at least one second bit from the second storage circuit and to control the controllable current source from the first bits and the second bit received successively when the control signal is in a given state. This advantageously makes it possible to control the duration of a display phase.

[0018] According to one embodiment, the controllable current source comprises: a first MOS transistor connected to the light emitting circuit and a first switch connected to the first MOS transistor; and a second MOS transistor connected to the light emitting circuit and a second switch connected to the second MOS transistor.

[0019] The structure of the controllable current source of the display pixel is advantageously simple.

[0020] According to one embodiment, the logic circuit is configured to control the first switch successively from each first bit and to control the second switch on the basis of said at least one second bit.

[0021] According to one embodiment, the control circuit is configured to control only the first switch based on some of the first bits and to control both the first switch and the second switch based on the other first bits.

[0022] According to one embodiment, the light emitting circuit comprises a first group of light emitting sources comprising a first number of light emitting sources connected to the first MOS transistor and a second group of light emitting sources comprising a second number of light emitting diodes connected to the second MOS transistor. This allows the current densities in each light emitting source to be the same.

[0023] According to one embodiment, the light emitting circuit comprises a third group of light-emitting sources comprising a third number of light-emitting diodes and in which the controllable source comprises a third MOS transistor connected to the light-emitting sources of the third group and a third switch connected to the third MOS transistor, in which the first number is equal to the second number and in which the third number is greater than the second number.

[0024] An embodiment also provides a display screen comprising an array of display pixels as defined previously.

[0025] According to one embodiment, the display screen comprises a circuit configured to modify a supply voltage of the display pixels as a function of the second bit. This advantageously reduces the display's power consumption with easy-to-use control. Brief description of the drawings

[0026] These characteristics and advantages, as well as others, will be explained in detail in the following description of particular embodiments given without limitation in relation to the attached figures among which:

[0027] [Fig.l] partially and schematically represents an example of a display screen;

[0028] [Fig.2] represents an example of a block diagram of a display pixel of the display screen of [Fig.l];

[0029] [Fig.3] shows examples of timing diagrams of a signal used by the display pixel of [Fig.2] to control a light-emitting diode by pulse width modulation and the current supplied to the light-emitting diode;

[0030] [Fig.4] represents examples of timing diagrams of a signal sent to the display pixels of two successive rows of the display screen of [Fig.l] to control light-emitting diodes by pulse width modulation;

[0031] [Fig.5] represents timing diagrams of the current supplied to a light-emitting diode for the display of successive digital color signals according to an embodiment of a method for controlling the light-emitting diode;

[0032] [Fig.6] represents timing diagrams of the current supplied to a light-emitting diode for the display of successive digital color signals according to another embodiment of a method for controlling the light-emitting diode;

[0033] [Fig.7] represents an embodiment of a block diagram of a display pixel of the display screen of [Fig.l];

[0034] [Fig.8] shows a more detailed embodiment of elements of the display pixel of [Fig.7];

[0035] [Fig.9] shows a more detailed embodiment of other elements of the display pixel of [Fig.7];

[0036] [Fig. 10] shows timing diagrams of signals during one embodiment of a method of driving the display pixel of [Fig.7];

[0037] [Fig.l 1] shows timing diagrams of signals during another embodiment of a method of driving the display pixel of [Fig.7];

[0038] [Fig. 12] shows timing diagrams of signals during another embodiment of a method of driving the display pixel of [Fig.7];

[0039] [Fig. 13] is a block diagram showing one embodiment of a method for modifying the power supply of a display screen;

[0040] [Fig. 14] shows timing diagrams of the power supply of a display screen during the display of video data;

[0041] [Fig. 15] is a figure similar to [Fig.9] and represents another embodiment of elements of the display pixel of [Fig.7];

[0042] [Fig. 16] is a top view of the display pixel shown in [Fig. 15];

[0043] [Fig. 17] shows another embodiment of a display pixel;

[0044] [Fig. 18] shows timing diagrams of signals during operation of the display pixel of [Fig. 17];

[0045] [Fig. 19] shows another embodiment of a display pixel;

[0046] [Fig.20] shows timing diagrams of signals during operation of the display pixel of [Fig.19];

[0047] [Fig.21] shows another embodiment of a display pixel;

[0048] [Fig.22] is a highly simplified cross-sectional view of an example of a display pixel;

[0049] [Fig.23] is a bottom view of the display pixel of [Fig.22]; and

[0050] [Fig.24] and [Fig.25] each represent a block diagram of the display pixel of [Fig.22], Description of the embodiments

[0051] The same elements have been designated by the same references in the different figures. In particular, the structural and / or functional elements common to the different embodiments may have the same references and may have identical structural, dimensional and material properties. For the sake of clarity, only the steps and elements useful for understanding the embodiments described have been shown and are detailed.

[0052] Unless otherwise specified, when referring to two elements connected to each other, this means directly connected without intermediate elements other than conductors, and when referring to two elements connected (in English "coupled") to each other, this means that these two elements can be connected or be linked by means of one or more other elements. Furthermore, a signal which alternates between a first stable state, for example a low state, noted "0", and a second stable state, for example a high state, noted "1", will be called a "binary signal". The high and low states of different binary signals of the same electronic circuit can be different. In practice, binary signals can correspond to voltages or currents which may not be perfectly stable in the high or low state. Furthermore, in the Following description, the source and drain of a MOS transistor are called the "power terminals" of the insulated gate field effect transistor, or MOS transistor.

[0053] Furthermore, unless otherwise specified, when we speak of a voltage at a conductive pad, we consider the difference between the potential at said conductive pad and a reference potential, for example, ground, taken as being equal to 0V.

[0054] Unless otherwise specified, the expressions "about", "approximately", "substantially", and "of the order of" mean within 10%, preferably within 5%. In addition, the expression "substantially stable" means that it varies by less than 10% over time compared to a reference value.

[0055] A pulse width modulation control of a light-emitting source, for example a light-emitting diode, consists of a circulation, in the light-emitting source, of successive current pulses having a stable intensity with variable durations. A pulse amplitude modulation control of a light-emitting source, for example, a light-emitting diode, consists of a circulation, in the light-emitting source, of successive current pulses having a stable duration with variable intensities.

[0056] In the following description, embodiments are described for display pixels comprising light emitting diodes. However, these embodiments can be implemented for display pixels comprising light emitting sources other than light emitting diodes, for example, organic light emitting diodes, field induced polymer light emitting components, laser diodes.

[0057] In the following description, embodiments are described for a color display screen comprising color display pixels, each display pixel comprising light-emitting diodes adapted to emit radiation of different colors. However, these embodiments also apply to a monochrome display screen comprising monochrome display pixels, each monochrome display pixel comprising a light-emitting diode or light-emitting diodes adapted to emit radiation of a single color.

[0058] [Fig. 1] partially and schematically represents an example of a display screen 10. The display screen 10 comprises display pixels 12^, for example, arranged in M ​​rows and N columns, M being an integer varying from 1 to 8,000 and N being an integer varying from 1 to 16,000, i being an integer varying from 1 to M and j being an integer varying from 1 to N. For example, in [Fig. 1], M and N are equal to 6. Each display pixel 1¾ is connected to a source of a low reference potential Gnd, for example, ground, via an electrode 14; and to a source of a high reference potential Vcc via an electrode 16j. For example, electrodes 14; are shown as being aligned along the rows in [Fig.l] and electrodes 16j are shown as being aligned along the columns in [Fig.l], the reverse structure being possible. The supply voltage of the display screen corresponds to the voltage between the high reference potential Vcc and the low reference potential Gnd. The supply voltage depends in particular on the arrangement of the light-emitting diodes and the technology by which the light-emitting diodes are manufactured. For example, the supply voltage may be in the order of 4 V to 5 V.

[0059] For each row, the display pixels 12;j of the row are connected to at least one row electrode 18;. For each column, the display pixels 12;j of the column are connected to at least one column electrode 20j. The display screen 10 comprises a selection circuit 22 connected to the row electrodes 18; and adapted to provide signals on the row electrodes 18;. The display screen 10 comprises a data supply circuit 24 connected to the column electrodes 20j and adapted to provide data on the column electrodes 20j. The selection circuit 22 and the control circuit 24 are controlled by a circuit 26, for example comprising a microprocessor.

[0060] [Fig. 2] represents an example of a block diagram of a display pixel 12;j of the display screen 10. For a color display screen, the display pixel 12i j comprises a light-emitting circuit LEDS comprising at least three light-emitting diodes emitting radiation of different colors, a single light-emitting diode LED being represented in [Fig. 2]. Each light-emitting diode LED is connected in series to a controllable current source CS, comprising for example a MOS transistor. In the present example, for each light-emitting diode LED, the anode of the light-emitting diode LED receives a high reference potential Vcc and the cathode of the light-emitting diode LED is for example connected to one terminal of the controllable current source CS, the other terminal of the controllable current source CS receiving the reference potential Gnd.

[0061] The display pixel 12;j further comprises a control circuit 40 for controlling a controllable current source CS. The control circuit 40 may in particular comprise electronic components such as MOS transistors. The control circuit 40 comprises a storage circuit 48 (Color Data registers) synchronized by a clock signal Clk configured to store digital color signals R, G, B based on received digital data Data. The digital color signals R, G, B each comprise a number NB of bits and are representative of the color components of the image pixel to be displayed. The control circuit 40 comprises a circuit 50 (LED driver) configured to control the controllable current sources CS connected to the light-emitting diodes LED with signals I_red, I_green and I_blue, obtained from the digital color signals R, G, B, and from a PWM signal.

[0062] [Fig. 3] represents a timing diagram of the PWM signal and the signals I_red_1, I_red_2, I_red_3 and I_red_4 corresponding to the signal I_red supplied by a circuit 50 of the display pixel 1¾ of [Fig. 2] for the display of four different color signals R. According to one embodiment, the light-emitting diodes LED of the display pixel 1¾ are controlled by pulse width modulation. To do this, during a display phase, the PWM signal presents the succession of pulses at the logic state level "1" which regulates the operation of the circuit 50 for controlling the light-emitting diodes LED by pulse width modulation. The number of pulses in the succession of pulses corresponds to the number NB of bits of each digital color signal R, G and B.

[0063] For example, when the current source CS corresponds to a MOS transistor, this transistor is on or off, at the frequency of the pulses of the PWM signal, depending on the logic value "0" or "1" of each bit of the color signal R, G or B, starting with the most significant bit, this transistor being kept on or off until the next pulse of the PWM signal. The duration between two successive pulses of the PWM signal is divided by two each time, so that the total duration for which the light-emitting diode is on depends on the value of the color signal R, G or B. The succession of pulses of the PWM signal can be repeated until another image pixel is displayed. In this case, the succession of pulses of the PWM signal constitutes a display cycle and the display phase comprises more than one display cycle.

[0064] In [Fig.3], as an example, the number of pulses in a display cycle of the PWM signal is equal to 7 and only one display cycle is shown. The signal I_red_l is obtained for displaying a color component of an image pixel corresponding to a color signal R equal to "1010101". The signal I_red_2 is obtained for displaying a color component of an image pixel corresponding to a color signal R equal to "0101010". The signal I_red_3 is obtained for displaying a color component of an image pixel corresponding to a color signal R equal to "1111111". The signal I_red_4 is obtained for displaying a color component of an image pixel corresponding to a color signal R equal to "0000000".

[0065] The PWM signal can be generated from periodic clock signals. The number of clock signals required to generate the PWM signal increases with the number NB of bits of R, G and B color signals. Generating a large number of Clock signals can lead to complex circuits. In addition, the image pixels of a new image to be displayed are successively displayed from the first row to the last row of the display screen.

[0066] [Fig.4] represents a timing diagram of PWM signals received by the display pixels of a first row (signal PWMj) and a second following row (signal PWMj+i) of the display screen. The signal PWMj+i corresponds to the signal PWMj which is shifted by a duration H equal to Tframe / M where Tframe is the duration of the display of the entire image and M is the number of rows of the display screen. The shift H of the PWM signal from a first row to a second following row can be obtained by supplying the signal PWMj to flip-flops before supplying it to the second row.

[0067] In addition, the electrical power consumed by the display screen 10 when the light-emitting diodes of each display pixel 12ij are controlled by pulse width modulation does not depend on the brightness of the image being displayed. It would be desirable for the electrical power consumed by the display screen to decrease when the brightness of the displayed image decreases.

[0068] According to one embodiment, each display pixel of the display screen is configured, for displaying an image pixel color component corresponding to a digital color signal, to control the light emitting circuit by pulse amplitude modulation (PAM) for some bits of the digital color signal and by pulse width modulation (PWM) for the other bits of the digital color signal. According to one embodiment, pulse amplitude modulation is used for at least the most significant bit (MSB) of the digital color signal, and optionally for one or more successive bits directly adjacent to the MSB.

[0069] According to one embodiment, the duration of the pulse of the pulse amplitude modulation is equal to the total duration Tcycle of a display phase cycle of the pulse width modulation. According to one embodiment, each time during the display cycle of the pulse width modulation, the intensity of the current supplied to the light emitting circuit is equal to the sum of the intensity of the current resulting from the pulse amplitude modulation and the intensity of the current resulting from the pulse width modulation.

[0070] According to one embodiment, pulse amplitude modulation is used for the MSB of the digital color signal and the second most significant bit (MSB-1) of the digital color signal, which is the bit following the MSB, and pulse width modulation is used for the other bits of the digital color signal. According to one embodiment, the intensity of the current supplied to the light emitting circuit, when only the MSB of the digital color signal is equal to "1", is twice the current supplied to the light emitting circuit when only MSB-1 of the digital color signal is equal to "1". According to one embodiment, the current supplied to the light emitting circuit when only MSB-1 of the digital color signal is equal to "1" is equal to the current supplied to the light emitting circuit for one pulse of the pulse width modulation when the MSB, MSB-1 and MSB-2 are equal to "0".

[0071] According to one embodiment, pulse amplitude modulation is used for the MSB of the digital color signal, the MSB-1 of the digital color signal, and the third most significant bit (MSB-2) of the digital color signal, which is the bit following the MSB-1, and pulse width modulation is used for the other bits of the digital color signal. According to one embodiment, the current supplied to the light emitting circuit, when only the MSB of the digital color signal is equal to "1", is twice the current supplied to the light emitting circuit when only the MSB-1 of the digital color signal is equal to "1" and is equal to four times the current supplied to the light emitting circuit when only the MSB-2 of the digital color signal is equal to "1".According to one embodiment, the current supplied to the light emitting circuit, when only the MSB-2 of the digital color signal is equal to "1", is equal to the current supplied to the light emitting circuit for a pulse of the pulse width modulation when the MSB, MSB-1 and MSB-2 are equal to "0".

[0072] Figures 5 and 6 each show exemplary timing diagrams of an I_LED current supplied to the light emitting circuit of an embodiment of a display pixel for displaying an image pixel color component encoded on a digital color signal having 10 bits for three different digital color signals. Reference I_MSB denotes the portion of the intensity of the I_LED current due to pulse amplitude modulation when the MSB is equal to "1". Reference I_MSB-1 denotes the portion of the intensity of the I_LED current due to pulse amplitude modulation when the MSB-1 is equal to "1". Reference I_MSB-2 denotes the portion of the intensity of the I_LED current due to pulse amplitude modulation when the MSB-2 is equal to "1". Reference I_PWM denotes the portion of the intensity of the I_LED current due to pulse width modulation.For Figures 5 and 6, the pulse duration of the pulse amplitude modulation is equal to the complete duration of one display phase cycle Tcycle of the pulse width modulation.

[0073] In [Fig.5], pulse amplitude modulation is used for the MSB, MSB-1 and MSB-2 of the digital color signal, and pulse width modulation is used for the other 7 bits of the digital color signal. The first digital color signal is equal to "1110101010". The second digital color signal is equal to "0010101010". The third digital color signal is equal to "0000101010".

[0074] In [Fig.6], pulse amplitude modulation is used for the MSB and MSB-1 of the digital color signal, and pulse width modulation is used for the other 8 bits of the digital color signal. The first digital color signal is equal to "1101010100". The second digital color signal is equal to "0101010100". The third digital color signal is equal to "0001010100".

[0075] [Fig.7] represents an embodiment of a block diagram of the display pixel 1¾ of [Fig.l] configured to implement the control of the light-emitting diodes described previously in relation to Figures 5 and 6.

[0076] The display pixel 12ij comprises all the elements described previously in relation to [Fig. 2] except that the control circuit 40 and the controllable current source CS are replaced by a control circuit 70 and a current control circuit 82, respectively. The control circuit 70 may in particular comprise electronic components such as MOS transistors. According to one embodiment, the control circuit 70 comprises two storage circuits 72 and 74 configured to store, for each image pixel color component, the bits of the digital color signal representative of the image pixel color component to be displayed on the basis of received data Data. The first storage circuit 72 (Shift register for lower bits (PWM)) is a shift register in which a number LB of bits of the digital color signal for which a pulse width modulation is implemented are stored.The second storage circuit 74 (Shift register for higher bits (PAM)) is a shift register in which a number HB of bits of the digital color signal for which pulse amplitude modulation is implemented are stored. According to one embodiment, for each image pixel color component, the digital color signal comprises NB bits, among which LB bits, starting from the least significant bit (LSB), which are stored in the first storage circuit 72 and which are used for pulse width modulation and HB bits, starting from the MSB, which are stored in the second storage circuit 74 and which are used for pulse amplitude modulation.

[0077] The control circuit 70 further comprises a first shift circuit 76 (Switch circuit) which receives the successive data bits Data, a write clock signal Clk_wr and a PWM signal and which supplies the data bits Data and either the write clock signal Clk_wr or the PWM signal to the first storage circuit 72. The first shift circuit 76 is controlled by a binary signal Line. The Control circuit 70 further comprises a second shift circuit 78 (Switch circuit) which receives the write clock signal Clk_wr and data bits from the first storage circuit 72 and which provides the write clock signal Clk_wr and the data bits to the second storage circuit 74. The second shift circuit 78 is controlled by the binary signal Line.

[0078] The control circuit 70 further comprises a logic circuit 80 (AND gate (HB + 1)) which receives a binary signal CP WM from the first storage circuit 72 and a digital signal CPAM from the second storage circuit 74, the digital signal CPAM having the number HB of bits. The logic circuit 80 is controlled by a binary signal Ctrl.

[0079] The current control circuit 82 provides the current I_LED to the light emitting circuit LEDS. The logic circuit 80 is configured to provide a binary signal CPWM' and a digital signal CPAM' to the current control circuit 82. Under the control of the Ctrl signal, the binary signal CPWM' may be equal to the binary signal CPWM and the digital signal CPAM' may be equal to the digital signal CPAM. The current control circuit 82 may include a digital to analog converter (DAC).

[0080] [Fig.8] shows a more detailed embodiment of the control circuit 70 of [Fig.7] in the case where HB is equal to three as an example.

[0081] The first storage circuit 72 comprises successive D flip-flops FFi to FFlb. The number of D flip-flops FFi to FFLB is equal to LB. The Q output of flip-flop FFlb provides the signal CPWM. The second storage circuit 74 comprises successive HB flip-flops, three flip-flops FFMSB . 2, FFMSB . 1 and FFMSB being shown as an example in [Fig. 8]. The Q output of flip-flop FFMSB . 2 provides a binary signal CPAMmsb . 2* The Q output of flip-flop FFMSB . 1 provides a binary signal CPAMmsb 1. The Q output of flip-flop FFMSB provides a binary signal CPAMmsb. The binary signals CPAMmsb . 2, CPAMmsb . 1 and CPAMmsb constitute the digital signal CPAM shown in [Fig. 7].

[0082] The first shift circuit 76 comprises a first 2-to-1 multiplexer MUXi and a second 2-to-1 multiplexer MUX2 and the second shift circuit 78 comprises a third 2-to-1 multiplexer MUX3 and a fourth 2-to-1 multiplexer MUX4. Each of the first multiplexer MUXb, the second multiplexer MUX2, the third multiplexer MUX3 and the fourth multiplexer MUX4 is controlled by the Line signal and comprises a first input, a second input and an output which is connected to the first input when the Line signal is at a first value, for example "0", and which is connected to the second input when the Line signal is at a second value, for example "1".

[0083] The first input of the first multiplexer MUXi is connected to the Q output of the FFLB flip-flop of the first storage circuit 72. The second input of the first multiplexer MUXi receives the Data signal and the output of the first multiplexer MUXi is connected to the D input of the FFi flip-flop of the first storage circuit 72. The first input of the second multiplexer MUX2 receives the PWM signal. The second input of the second multiplexer MUX2 receives the write signal Clk_wr, and the output of the second multiplexer MUX2 is connected to the clock input of each FFi to FFlb flip-flop of the first storage circuit 72.

[0084] The first input of the third multiplexer MUX3 receives the reference potential Gnd. The second input of the third multiplexer MUX3 is connected to the Q output of the FFLB flip-flop of the first storage circuit 72 and the output of the third multiplexer MUX3 is connected to the D input of the FFMSB flip-flop. 2 of the second storage circuit 74. The first input of the fourth multiplexer MUX4 receives the reference potential Gnd. The second input of the fourth multiplexer MUX 4 receives the write clock signal Clk_wr, and the output of the fourth multiplexer MUX4 is connected to the clock input of each FFMSB flip-flop. 2, FFMSB. i and FFMSB of the second storage circuit 74.

[0085] The logic circuit 80 comprises HB+1 logic gates of the AND type ANDPWM, ANDMSB - 2- ANDMsb -1 and ANDMsb. Each ANDPwm, ANDmsb - 2- ANDmsb - 1 and ANDmsb gate has a first input which receives the Ctrl signal. The second input of the ANDPWM gate is connected to the Q output of the FFLB flip-flop of the first storage circuit 72. The second input of the ANDMSB - 2- ANDMSB -1 and ANDMSB gates is connected to the Q output of the FFMSB - 2- FFMSB - 1 and FFMSB flip-flops, respectively, of the second storage circuit 74.

[0086] [Fig.9] shows a more detailed embodiment of the current control circuit 82 of [Fig.7] in a case where HB is equal to three as an example. The LEDS light emitting circuit is represented in [Fig.9] by a single LED. However, the LEDS light emitting circuit may comprise several LEDs connected in parallel.

[0087] The current control circuit 82 comprises HB+1 MOS transistors, for example of the N type, among which a TPWM transistor used for pulse width modulation and HB transistors TMSB - 2, TMSB -1 and TMSB used for pulse amplitude modulation. The drain of each transistor TPWM, TMSB 2, TMSB 1 and TMSB is connected to the cathode of the light-emitting diode LED. The anode of the light-emitting diode LED receives a high reference potential Vcc. The gate of each transistor TPWM, TMSB - 2, TMSB -1 and TMSB receives a Bias signal. The width of the transistor Tmsb 2 is equal to the width of the TPWM transistor. The width of the transistor TMSB -1 is equal to twice the width of the TMSB transistor - 2- The width of the TMSB transistor is equal to four times the width of the TMSB transistor. 2.

[0088] The current control circuit 82 comprises HB+1 switches among which a switch SWPWM used for pulse width modulation and HB switches SWMsb 2, SWMsb 1 and SWMsb used for pulse amplitude modulation. A first terminal of each switch SWPWM, SWMSB . 2, SWmsb 1 and SWmsb receives the low reference potential Gnd. The second terminal of the switch SWPWm is connected to the source of the transistor TPWM. The second terminal of each switch SWMSB 2, SWMSB 1 and SWMSB is connected to the source of the transistor TMSB 2, TMSB 1 and TMSB, respectively. The switch SWPWm is controlled by the binary signal CPWM'. The switch SWMSB 2, SWMSB 1 and SWMsb is controlled by a binary signal CPAM'msb _ 2, CPAM'msb _ 1 and CPAM'msb, respectively.

[0089] [Fig. 10] shows examples of timing diagrams of the Line, Clk_wr, Ctrl and PWM signals during operation of the display pixel having the structure shown in Figures 8 and 9.

[0090] The Line signal is set to a logic level "1" during write phases WP in order to perform a write operation in the first storage circuit 72 and in the second storage circuit 74. More precisely, when the Line signal is at a logic level "1", the multiplexer MUXi provides at its output the Data signal, the multiplexer MUX2 provides at its output the clock signal Clk_wr, the multiplexer MUX3 provides at its output the signal provided by the Q output of the FFLB flip-flop, and the multiplexer MUX4 provides at its output the clock signal Clk_wr. Successive bits of Data data are stored in the first storage circuit 72 and the second storage circuit 74 synchronized by the clock signal Clk_wr. According to one embodiment, the data bits Data are successively supplied, from the MSB to the LSB of the digital color signal, to the first flip-flop FFi of the storage circuit 72.The bits shift, at the frequency of the clock signal Clk_wr, through the first storage circuit 72 and possibly through the second storage circuit 74. In particular, the MSB of the digital color signal shifts from the flip-flop FFi to the flip-flop FFLB of the first storage circuit 72 and then from the flip-flop FFMSB . 2 to the flip-flop FFMSB of the second storage circuit 74. When the MSB of the digital color signal has reached the flip-flop FFmsb, the LSB of the digital color signal has reached the flip-flop FFi. .

[0091] The Line signal is set to a logic level "0" in a display phase DP between two successive write phases WP. During a display phase DP, the Ctrl signal is set to a logic level "1" for at least one display cycle DC for the display of the color component of the image pixel by the light-emitting diode LED. When the Line signal is at a logic level "0", the multiplexer MUXi provides at its output the Q output of the flip-flop FFLB, the multiplexer MUX2 provides at its output the PWM signal, the multiplexer MUX3 provides at its output the low reference potential Gnd and the multiplexer MUX4 provides at its output the low reference potential Gnd. In addition, since the Ctrl signal is at a logic level "1", each gate ANDPWM, ANDMSB _ 2, ANDmsb _ i and ANDmsb provides at its output the bit present at its second input. Therefore, the gate ANDPWM provides at its output the bit present at the output of the flip-flop FFlb, and each gate ANDMSB . 2, ANDMSB . i and ANDMSB provides at its output the MSB-2, MSB-1 and MSB, respectively, of the color signal data.The flip-flops FFi to FFlb of the first storage circuit 72 are synchronized by the PWM signal and the bits of the digital color signal stored in the first storage circuit 72 are shifted from one flip-flop to the next flip-flop at each pulse of the PWM signal, so that the bit present at the output of the flip-flop FFLB successively corresponds to the LB bits of the color data signal, the last bit supplied being the LSB of the color data signal.

[0092] [Fig. 11] shows another embodiment in which the PWM signal and the Clk_wr signal are merged into a single binary signal Clk_PWM. According to this variant, the multiplexer MUX2 may not be present.

[0093] In the timing diagrams shown in Figures 10 and 11, there is only one display cycle DC during the display phase DP between two successive write phases WP. According to a variant, a display phase DP between two successive write phases WP may comprise more than one display cycle DC.

[0094] [Fig. 12] is similar to [Fig. 10] and represents examples of timing diagrams of the Line, Clk_wr, Ctrl and PWM signals during operation of the display pixel having the structure shown in Figures 8 and 9. In [Fig. 12], each display phase DP between two successive write phases WP comprises the repetition of four identical display cycles DC.

[0095] [Fig. 13] is a block diagram illustrating an embodiment of a method for modifying the Vcc power supply of the display screen 10. The method comprises the following steps: - the video data to be displayed is received by the circuit 26 of the display screen 10 (step 100); - the maximum gray level of the image to be displayed is determined (step 102). To simplify the calculation of the gray level of the image, for each image pixel color component of each image pixel, only the bits of the digital color signal used for the pulse amplitude modulation are taken into account; - the current intensity required for displaying the image is determined on the basis of the maximum gray level of the image (step 104); and - The supply voltage Vcc is adjusted (step 106) so that the desired current intensity can be supplied to the light-emitting diodes of the display pixels during image display.

[0096] The level of the supply voltage Vcc can be reduced for an image having dark tones because, in this case, only a low current is required to display the image. The level of the supply voltage Vcc can be increased for an image having bright tones because, in this case, a high current is required to display the image. Therefore, this embodiment makes it possible to reduce the electrical power consumed by the display screen.

[0097] [Fig. 14] shows an example of the evolution of the Vcc power supply during the display of video data. In this example, the bits used for pulse amplitude modulation are the MSB and MSB-1 of the digital color signals. As an example, [Fig. 14] shows four successive phases PI, P2, P3 and P4 with different maximum gray levels. In phases PI and P4, the maximum gray level corresponds to the MSB and MSB-1 which are in the logic state "1". In phase P2, the maximum gray level corresponds to the MSB which is in the logic state "0" and to the MSB-1 which is in the logic state "1". In phase P3, the maximum gray level corresponds to the MSB and MSB-1 which are in the logic state "0". As will be noted in [Fig. 14], in each phase PI, P2, P3 and P4, the potential Vcc is set to a stable level.The variation of the potential Vcc from a stable level to another stable level can be implemented with a given variation rate in order to avoid sudden variations on the displayed images.

[0098] In some cases, the wavelength of the radiation emitted by a light-emitting diode may vary depending on the intensity of the current flowing through the light-emitting diode. This may not be desirable.

[0099] [Fig. 15] is a figure similar to [Fig. 9] and represents another embodiment of the display pixel 1¾. The display pixel 1¾ shown in [Fig. 15] comprises all the elements of the display pixel 1¾ shown in [Fig. 9] except that it comprises a light emitting circuit LEDS comprising several light emitting diodes LED for each image pixel color component, only the light emitting diodes LED of one image pixel color component being shown in [Fig. 15]. This embodiment can advantageously be easily implemented when each light emitting diode comprises a nanoscale or microscale three-dimensional element, for example a microwire, a nanowire or a nanoscale or microscale three-dimensional element having a pyramidal, conical or frustoconical shape, the nanoscale or microscale three-dimensional element micrometer being covered by the active region of the light-emitting diode, which is the region from which most of the electromagnetic radiation provided by the light-emitting diode is emitted.

[0100] For each image pixel color component, the LEDs of the light emitting circuit LEDS are distributed into HB+1 LEDPWM groups, LEDmsb 2, LEDmsb i and LEDmsb of LEDs, HB being equal to 3 as an example in [Fig.9] and each LED PWM group, LEDmsb - 2, LEDmsb -1 and LEDmsb being represented by the electrical symbol of a single LED in [Fig. 15]. The anode of each LED of each LEDPWM group, LEDMsb 2- LEDMSB . i and LEDMSB receives the high reference potential Vcc. The cathode of each LED of the LEDPWM group is connected to the drain of the TPWM transistor.The cathode of each light-emitting diode in the LEDMsb group 2 is connected to the drain of the transistor TMsb 2- The cathode of each light-emitting diode in the LEDMsb group 1 is connected to the drain of the transistor Tmsb i- The cathode of each light-emitting diode in the LEDMsb group is connected to the drain of the transistor TMsb- The number of light-emitting diodes in each LEDPWM, LEDmsb 2, LEDmsb 1 and LEDmsb group is chosen so that, when it is on, the luminous intensity emitted by the LEDMsb group 2 is equal to the luminous intensity emitted by the LEDPWM group, the luminous intensity emitted by the LEDMsb group 1 is equal to twice the luminous intensity emitted by the LEDMsb group 2- and the luminous intensity emitted by the LEDMsb group is equal to twice the luminous intensity emitted by the LEDmsb group 1.Therefore, the current density for each LED in each group LEDpwm, LEDMsb 2- LEDMsb 1 and LEDMsb is advantageously the same. In the case where the LEDs all have the same structure, the number of LEDs in group LEDmsb 2 is equal to the number of LEDs in group LEDPWM, the number of LEDs in group LEDMsb 1 is equal to twice the number of LEDs in group LEDmsb 2, and the number of LEDs in group LEDmsb is equal to twice the number of LEDs in group LEDMsb i- Therefore, the current density for each LED in each group LEDpwm, LEDmsb 2, LEDmsb 1 and LEDmsb is advantageously the same. .

[0101] [Fig. 16] is a top view of an embodiment of the display pixel 1¾ shown in [Fig. 15] showing an arrangement of the light-emitting diodes of the light-emitting circuit LEDS. Each light-emitting diode LED is represented by a circle in which the letter "R" is indicated for the diodes light-emitting diodes emitting red radiation, the letter "G" for light-emitting diodes emitting green radiation and the letter "B" for light-emitting diodes emitting blue radiation. In [Fig. 16], the LEDMSB group includes four light-emitting diodes for each image pixel color component, the LEDMSb i group includes two light-emitting diodes for each image pixel color component, the LEDMSB - 2 group includes one light-emitting diode for each image pixel color component and the LEDpWM group includes one light-emitting diode for each image pixel color component.

[0102] It may be desirable to reduce the storage capacity of the digital signals of the display pixel 1¾.

[0103] [Fig. 17] is a figure similar to [Fig. 15] and represents another embodiment of the display pixel 12^. The display pixel 1¾ shown in [Fig. 17] includes all the elements of the display pixel 1¾ shown in [Fig.15], except that, for the LEDS light emitting circuit, the LEDPWM group is referenced LED 1, the LEDMSB group . 2 is referenced LED2, the LEDMSB group . 1 is referenced LED3, the LEDMSB group is referenced LED4, the TPWM transistor is referenced Th, the Tmsb transistor 2 is referenced T2, the TMSB transistor - 1 is referenced T3, the TMSB transistor is referenced T4, the SWPWm switch is referenced SWi, the SWMsb switch 2 is referenced SW2, the SWMSB switch 1 is referenced SW3, the SW msb switch is referenced SW4, and except that the gates of the Tb transistors T2, T3, T4 are controlled by a control circuit 110.

[0104] [Fig. 18] shows timing diagrams of Vsync and Clk_wr signals and CLED control signals of the light-emitting diodes for an embodiment of a display screen comprising the 1¾ display pixels shown in [Fig. 17]. In this embodiment, for displaying an image pixel color component, the bits of the digital color signal are sent to each display pixel in successive write phases WP separated by display phases DP. Four write phases WP and four display phases DP are shown as an example in [Fig. 18] for displaying an image pixel and 2 bits of the digital color signal are stored in the display pixel during each write phase WP, the image pixel color signal comprising 8 bits.

[0105] Each display phase DP is divided into a first sub-phase DP_1 and a second sub-phase DP_2. The total duration of the display phase DP, the duration of the first sub-phase DP_1 and the duration of the second sub-phase DP_2 are the same for all the display phases DP. The duration of the first sub-phase DP_1 is equal to a multiple of the duration of the second sub-phase DP_2. In the present example, the duration of the first sub-phase DP_1 is equal to sixteen times the duration of the second sub-phase DP_2. For each display phase DP, the light-emitting diodes of different groups among the groups LEDi, LED2, LED3 and LED4 are turned on or off based on a first stored bit of the digital color signal during the first sub-phase DP_1 and based on a second stored bit of the digital color signal during the second sub-phase DP_2.

[0106] In [Fig. 18], the LEDi, LED2, LED3 and LED4 groups of light-emitting diodes that can be used during a DP display phase are indicated under the DP display phase. In the present embodiment, the light-emitting diodes of the LEDi group are used during the first and second sub-phases DP_1 and DP_2 of all the DP display phases. The light-emitting diodes of the LED2 group are used during the first and second sub-phases DP_1 and DP_2 of three of the DP display phases and are systematically blocked in the other DP display phase. The light-emitting diodes of the LED3 group are used during the first and second sub-phases DP_1 and DP_2 of two of the DP display phases and are systematically blocked in the other DP display phases.The light-emitting diodes of the LED4 group are used during the first and second sub-phases DP_1 and DP_2 of one of the DP display phases and are systematically blocked in the other DP display phases. The four successive display phases are equivalent to a single display phase for which the light-emitting diodes would be controlled by pulse width modulation and by pulse amplitude modulation.

[0107] [Fig. 19] shows another embodiment of a 1¾ display pixel. The 1¾ display pixel shown in [Fig. 19] includes all the elements of the 1¾ display pixel shown in [Fig.8], except that the second storage circuit 74, the second shift circuit 78 and the logic circuit 80 are not present. In addition, the 1¾ display pixel includes the light emitting circuit LEDS shown in [Fig. 17] with two groups LEDi and LED2 of light emitting diodes. The number of flip-flops of the first storage circuit 72 is equal to 4 as an example in [Fig. 19]. The flip-flops FFi to FF4 are synchronized by the binary signal Clk_PWM. In addition, the first shift circuit 76 includes only the first multiplexer Muxi. The first input of the first multiplexer MUX receives the low reference potential Gnd.The second input of the first multiplexer MUXi receives the Data signal and the output of the first multiplexer MUXi is connected to the D input of the FFi flip-flop of the first storage circuit 72.

[0108] The control circuit 70 further comprises an additional D-type flip-flop FFCi which is synchronized by the binary signal Clk_PWM. The D input of the flip-flop FFa is connected to the QB output of the flip-flop FFa. The control circuit 70 further comprises an inverter INV and a NOR logic gate of the NOR type. The input of the inverter INV is connected to the Q output of the flip-flop FFa. The inverter INV provides the binary signal CLED. The QB output of the flip-flop FF4 is connected to a first input of the NOR gate. The output of the inverter INV is connected to a second input of the NOR gate. In the present embodiment, the display pixel 1¾ comprises only the LEDi and LED2 groups of light-emitting diodes.

[0109] [Fig. 20] shows timing diagrams of the Vsync and Clk_PWM signals and the CLED signal during an embodiment of a display screen of the display pixel 1¾ shown in [Fig. 18]. The binary signal Clk_PWM includes the write clock Clk_wr and the PWM signal. In this embodiment, the bits of the digital color signal are sent to the first storage circuit 72 of the display pixel 12i j in a write phase WP. During a display phase DP that follows the write phase WP, the signal Clk_PWM includes first, second, third, fourth and fifth pulses Pb P2, P3, P4 and P5. The first pulse Pi indicates the start of the display phase DP and the fifth pulse P5 indicates the end of the display phase DP. The storage circuit 72 is synchronized by the successive pulses PH P2, P3, P4 to successively supply to the output Q of the flip-flop FF4 the bits stored in the storage circuit 72.

[0110] The duration between the first pulse Pi and the second pulse P2 is equal to the duration between the second pulse P2 and the second pulse P3. The duration between the third pulse P3 and the fourth pulse P4 is equal to the duration between the fourth pulse P4 and the fifth pulse P5 and is equal to four times the duration between the first pulse Pi and the second pulse P2. The CLED signal provided by the inverter INV alternates between the logic states "0" and "1" at each pulse of the Clk_PWM signal so that CLED is in the logic state "0" between the first pulse Pi and the second pulse P2 and between the third pulse P3 and the fourth pulse P4 and the CLED signal is in a stable state "1" between the second pulse P2 and the third pulse P3 and between the fourth pulse P4 and the fifth pulse P5.

[0111] In [Fig.20], the LEDi group of light-emitting diodes can be used during the entire display phase DP while the LED2 group of light-emitting diodes can be used only between the second pulse P2 and the third pulse P3 and between the fourth pulse P4 and the fifth pulse P5. Therefore, between the first pulse Pi and the second pulse P2 and between the third pulse P3 and the fourth pulse P4, only the light-emitting diodes of the group LEDi are on or off based on the bit provided by flip-flop FF4 and, between the second pulse P2 and the third pulse P3 and between the fourth pulse P4 and the fifth pulse P5, the light-emitting diodes of the two groups LEDi and LED2 are on or off based on the bit provided by flip-flop FF4. Therefore, the current density for each light-emitting diode of each group LEDi and LED2 is advantageously the same.

[0112] [Fig.21] shows another embodiment of a 1¾ display pixel . The 1¾ display pixel shown in [Fig. 21] includes all the elements of the 1¾ display pixel shown in [Fig. 18] except that it includes, for each image pixel color component, a single LEDi group of light-emitting diodes, the cathode of the light-emitting diodes of the LEDi group being connected to the drain of transistor Ti and to the drain of transistor T2. The operation of the 1¾ display pixel shown in [Fig. 21] is the same as the operation of the 1¾ display pixel shown in [Fig. 19].

[0113] As will be described below, to limit the number of conductive pads Gnd, P_Vcc, P_Col, P_Row per display pixel 12ij, the data signals Dataj validate both the determination, by each display pixel 12^, of a clock signal and the color signals R, G, B representative of the desired light intensities for the radiation at the first, second and third wavelengths. As a variant, the data signals Dataj can be used only for the determination, by each display pixel 12ij, of the color signals R, G, B and the clock signal is received by each pixel 12^, on a separate conductive pad.

[0114] According to an embodiment of the display screen 10 shown in [Fig. 1], for each row, the display pixels 12ij of the row are connected to a single row electrode 18;. For each column, the display pixels 1¾ of the column are connected to a single column electrode 20j. The display screen 10 comprises a selection circuit 22 connected to the row electrodes 18; and adapted to provide a selection and synchronization signal Corn; on each row electrode 18;. The display screen 10 comprises a data supply circuit 24 connected to the column electrodes 20j and adapted to provide a data signal Dataj on each column electrode 20j. The selection circuit 22 and the control circuit 24 are controlled by a circuit 26, comprising for example a microprocessor.

[0115] [Fig.22] is a very simplified cross-sectional view of an example known from a 1¾ display pixel and [Fig.23] is a bottom view of the 1¾ display pixel. Each 1¾ display pixel comprises a driver circuit 30 covered by a display circuit 32. The display circuit 32 comprises at least one light-emitting diode LED, preferably at least three diodes LED light-emitting diodes. The display pixel comprises a lower surface 34 and an upper surface 35 opposite the lower surface 34, the surfaces 34 and 35 preferably being planar and parallel. The control circuit 30 further comprises conductive pads P_Gnd, P_Vcc, P_Col, P_Row on a lower surface 34. The control circuit 30 may correspond to an integrated circuit comprising electronic components, in particular insulated gate field effect transistors, also called MOS transistors, or thin film transistors, also called TFTs. Preferably, the display circuit 32 comprises only LED light-emitting diodes and the conductive elements of these LED light-emitting diodes, and the control circuit 30 comprises all the electronic components necessary for controlling the LED light-emitting diodes of the display circuit 32.Alternatively, the display circuit 32 may also include other electronic components in addition to the LEDs. The LEDs may be 2D LEDs, also known as planar LEDs, comprising a stack of planar layers, or 3D LEDs, each comprising a three-dimensional semiconductor element covered with an active region. In [Fig. 22], the LEDs are shown as being connected with a common anode. However, it may be desirable to arrange the LEDs in accordance with another configuration. For example, the LEDs may be connected with a common cathode or be connected independently of each other.

[0116] According to one embodiment, the display pixel 1¾ comprises three display sub-pixels emitting light at the first, second and third wavelengths. According to one embodiment, the first wavelength corresponds to blue light and is in the range of 430 nm to 490 nm. According to one embodiment, the second wavelength corresponds to green light and is in the range of 510 nm to 570 nm. According to one embodiment, the third wavelength corresponds to red light and is in the range of 600 nm to 720 nm. Alternatively, the display pixel 1¾ may comprise a single light source emitting light at the first, second or third wavelength or only two light sources emitting light at two of the first, second and third wavelengths.

[0117] Each conductive pad P_Gnd, P_Vcc, P_Col, P_Row is intended to be connected to one of the electrodes 14;, 16j, 18;, 20j shown schematically in [Fig.22]. The first conductive pad P_Gnd is connected to the source of the low reference potential Gnd. The second conductive pad P_Vcc is connected to the source of the high reference potential Vcc. The third conductive pad P_Row is connected to the row electrode 18; and receives the selection and synchronization signal Com;. The fourth conductive pad P_Col is connected to the column electrode 20j and receives the data signal Dataj.

[0118] [Fig.24] represents a known example of a block diagram of a display pixel 12ij of the display screen 10. In [Fig.24], above each block, the supply voltage used to power the electronic components of the blocks has been indicated.

[0119] The display pixel 1¾ comprises the control circuit 70 for controlling the controllable current source 82. The control circuit 70 may in particular comprise electronic components such as MOS transistors. It may be desirable to use a reduced supply voltage, less than 4 V, for example of the order of 1 V or 1.8 V, to power the electronic components of the control circuit 70, this reduced supply voltage corresponding for example to the voltage likely to be applied between the power terminals of the MOS transistors. To do this, the display pixel 1¾ comprises a circuit 42 (Vdd Generation) for providing, from the supply voltage Vcc, a reduced supply voltage Vdd used in particular to power the control circuit 40. The circuit 42 comprises for example a voltage divider.

[0120] According to one embodiment, the detection and synchronization signal Com;, received at the conductive pads P_Row of each display pixel 12^, is a binary signal alternating between a low state "0" and a high state "1", the low state corresponding to the low reference potential Gnd and the high state "1" corresponding to a low voltage, for example approximately 1 V, lower than the reduced supply voltage Vdd. The data signal Dataj, received at the conductive pads P_Col of each display pixel 12^, is a binary signal alternating between a low state "0" and a high state "1", the low state corresponding to the low reference potential Gnd and the high state "1" corresponding to a low voltage, for example approximately 1 V, lower than the reduced supply voltage Vdd.

[0121] The display pixel 1¾ comprises a circuit 44 (Clk & data separation) connected to the conductive pad P_Col receiving the data signal Dataj and providing, from the data signal Dataj, a clock signal Clk and the data. The display pixel 12ij comprises a circuit 46 (Selection mode) receiving the signals Clk and Data, connected to the conductive pad P_Row receiving the selection and synchronization signal Com; , and configured to provide the signals Clk_wr and Data or to provide a PWM signal to the control circuit 70 to control the controllable current source 82 associated with each light-emitting diode LED.

[0122] As will be described below, to limit the number of conductive pads Gnd, P_Vcc, P_Col, P_Row per display pixel 12^, the data signals Dataj validate both the determination, by each display pixel 12ij, of a clock signal and the color signals R, G, B representative of the desired light intensities for the radiation at the first, second and third wavelengths. As a variant, the data signals Dataj can be used only for the determination, by each display pixel 12ij, of the color signals R, G, B and the clock signal is received by each pixel 12^, on a separate conductive pad.

[0123] [Fig. 25] shows a block diagram of an embodiment of a 1¾ display pixel. The 1¾ display pixel of [Fig. 25] has the same structure as the 1¾ display pixel of [Fig. 24], except that the circuit 42 for providing the reduced supply voltage Vdd is replaced by a circuit 60 for providing the reduced supply voltage Vdd receiving the communication and synchronization signal Com; and the data signal Dataj. In this embodiment, the reduced supply voltage Vdd is provided from the communication and synchronization signal Com; and the data signal Dataj.

[0124] In one embodiment, for each display pixel 12^, the circuit 44 determines the clock signal Clk and the data Data based on the pulses of the data signal Dataj. For example, each pulse of the data signal Dataj may have a first duration or a second duration, longer than the first duration. The signal Clk may correspond to a sequence of pulses of the same durations having their rising edges which coincide, to within a possible stable offset, with the rising edges of the pulses of the data signal Dataj. The data Data may correspond to a binary signal at a state "0" when the pulse of the data signal Dataj has the first duration and at the state "1" when the pulse of the signal Dataj has the second duration.Circuit 46, selected by the signal Com; in state "1", provides, at the frequency of the clock signal Clk, the data Data which are stored in circuit 70 in the form of digital color signals R, G, B having their bits provided by the successive values ​​of the signal Data.

[0125] Various embodiments and variations have been described. Those skilled in the art will understand that certain features of these various embodiments and variations could be combined, and other variations will occur to those skilled in the art. In particular, in the embodiments described above, the light-emitting diodes have a common anode, i.e., the anodes of the light-emitting diodes receive the high reference voltage and the cathodes of the light-emitting diodes are connected to the controllable current source. However, these embodiments also apply to the display pixels in which the LEDs have a common cathode, i.e. the cathodes of the LEDs receive the low reference voltage and the anodes of the LEDs are connected to the controllable current source.

[0126] Finally, the practical implementation of the embodiments and variants described is within the reach of those skilled in the art from the functional indications given above.

Claims

Claims

1. Display pixel (1¾) for a display screen (10) comprising a light emitting circuit (LEDS) comprising at least one first light emitting source (LED), a controllable current source (82) for driving the light emitting circuit with current pulses (I_LED) during a display phase having display cycles, and a control circuit (70) for controlling the current source, the control circuit being configured to receive a digital signal (Data) comprising first bits and at least one second bit, the second bit being different from the first bits, and to control the current source to provide the current pulses modulated by a pulse width modulation based on the first bits of the digital signal and modulated by a pulse amplitude modulation based on said at least one second bit of the digital signal,wherein the control circuit (70) is configured to control the current source (82) to provide, each time during the display cycle of the pulse width modulation, a current whose intensity is equal to the sum of the intensity of the current resulting from the pulse amplitude modulation and the intensity of the current resulting from the pulse width modulation, the duration of the pulse of the pulse amplitude modulation being equal to the total duration of a display cycle of the pulse width modulation.,

2. The display pixel of claim 1, wherein the at least one second bit comprises the most significant bit of the digital signal (Data).

3. A display pixel according to claim 1 or 2, wherein the control circuit (70) is configured to control the current source (82) to provide the current pulses (I_LED) by pulse amplitude modulation based on at least two second bits of the digital signal.

4. The display pixel of claim 3, wherein the control circuit (70) is configured to control the current source (82) to provide the current pulses (I_LED) by pulse amplitude modulation based on three second bits of the digital signal.

5. A display pixel according to any one of claims 1 to 4, wherein the control circuit (70) comprises a first storage circuit (72) for storing said first bits of the digital signal and wherein the first storage circuit (72) comprises a shift register synchronized by a pulse width modulation (PWM) clock signal.

6. A display pixel according to claim 5, wherein the control circuit (70) comprises a second storage circuit (72) for storing said at least one second bit of the digital signal and a logic circuit (80) controlled by a control signal (Ctrl) and configured to successively receive the first bits from the shift register (72) synchronized by the pulse width modulation (PWM) clock signal and to receive said at least one second bit from the second storage circuit (74) and to control the controllable current source (82) from the first bits and the second bit successively received when the control signal is in a given state.

7. A display pixel according to any one of claims 1 to 6, wherein the controllable current source (82) comprises: a first MOS transistor (TPWM; TJ) connected to the light emitting circuit (LEDS) and a first switch (SWPWm; SWi) connected to the first MOS transistor; and a second MOS transistor (TMSB_2, TMSB i, TMSB; T2, T3, T4) connected to the light emitting circuit and a second switch (SWmsb-2, SWmsb-i, SWBmsb; SW2, SW3, SW4) connected to the second MOS transistor.

8. A display pixel according to claim 7, wherein the logic circuit (80) is configured to control the first switch (SWPWM; SWi) successively from each first bit and to control the second switch (SWMSB2, SWMSB.i, SWBmsb) based on said at least one second bit.

9. The display pixel of claim 7, wherein the control circuit (70) is configured to control only the first switch (SWi) based on some of the first bits and to control both the first switch (SWi) and the second switch based on the other first bits.

10. A display pixel according to claim 7 or 8, wherein the light emitting circuit (LEDS) comprises a first group (LEDPWM; LEDi) of light emitting sources comprising a first number of light emitting sources connected to the first MOS transistor (TPWM; Ti) and a second group (LEDMSB 2, LEDMSB i, LEDMSB; LED2, LED3, LED4) of light emitting sources comprising a second number of light emitting sources connected to the second MOS transistor (TMSB 2 -, Tmsb-h Tmsb; t2, t3, t4).

11. The display pixel of claim 10, wherein the light emitting circuit (LEDS) comprises a third group (Tmsb 2, TMSB-i, TMSB; T2, T3, T4) of light emitting sources having a third number of light emitting sources and wherein the control source (82) comprises a third MOS transistor (TMsb 2, TMsb 1, TMsb; T2, T3, T4) connected to the light emitting sources of the third group (LEDS) and a third switch (SWMSB-2, SWMSB-i, SWBmsb; SW2, SW3, SW4) connected to the third MOS transistor, wherein the first number is equal to the second number and wherein the third number is greater than the second number.

12. A display screen (60) comprising a display pixel array (1¾) according to any one of claims 1 to 11.

13. A display screen according to claim 12, comprising a circuit (26) configured to modify a supply voltage (Vcc) of the display pixels as a function of the second bit.

Images