Microelectronic device with two field-effect transistors

Abstract

Title: Microelectronic Device with Two Field-Effect Transistors The invention relates to a microelectronic device (1) comprising an n-MOS field-effect transistor (100), a first N-doped region (110), one of the drain and one of the source of the n-MOS transistor, and a second N-doped region (120), the other of the drain and one of the source of the n-MOS transistor. The device according to the invention further comprises a p-MOS field-effect transistor (200), a first P-doped region (210), one of the drain and one of the source of the p-MOS transistor, a second P-doped region (220), the other of the drain and one of the source of the p-MOS transistor, a dielectric layer (300) in contact with the doped regions, and a back gate (400). The n-MOS transistor and the p-MOS transistor are separated by a PN junction (1000). Figure for the abstract: Fig. 2A

Description

Title of the invention: Microelectronic device with two field effect transistors Technical field

[0001] The present invention relates to the field of microelectronics and more particularly to advanced CMOS (Complementary Metal Oxide Semiconductor) technologies. It finds particularly advantageous applications in low-power electronics and devices for protection against electrostatic discharges. STATE OF THE ART

[0002] Different types of transistors are currently used in electronic circuits to perform numerous functions (logic circuits, amplification, signal modulation, etc.).

[0003] One of the most widely used structures currently is the FDSOI transistor (from the English "Fully Depleted Silicon On Insulator"), represented in [Fig.l]. This technology consists of placing a thin insulating layer under the semiconductor layer, for example silicon, so as to create a barrier which in particular prevents current leaks. FDSOI transistors are preferred in low-power applications.

[0004] Z2FET transistors are used in particular for memory applications and protection against electrostatic discharges (ESD). It is a forward-biased pin diode whose intrinsic channel is only partially covered by a front gate.

[0005] An objective of the present invention is to propose an alternative to existing devices while presenting at least equivalent performances and / or making it possible to carry out functions for which all current devices cannot be used. SUMMARY

[0006] To achieve this objective, a first aspect concerns a microelectronic device comprising: • an n-MOS field effect transistor comprising a first drain, a first source, a first gate and a first gate oxide, • a first N-doped zone, constituting one of the first drain and the first source, • a second N-doped zone, constituting the other of the first drain and the first source.

[0007] The device further comprises: • a p-MOS field effect transistor comprising a second drain, a second source, a second gate and a second gate oxide, • a first P-doped zone, constituting the second source if the first N-doped zone constitutes the first drain, or the second drain, if the first N-doped zone constitutes the first source, • a second P-doped zone, constituting the other of the second drain and the second source, • a dielectric layer having an upper face in contact with the first N-doped zone, the second N-doped zone, the first P-doped zone and the second P-doped zone, • a rear gate in contact with a lower face of the dielectric layer.

[0008] It also has the particularity that the second N-doped zone and the second P-doped zone form a PN junction.

[0009] The object thus defined constitutes a microelectronic device which can replace the transistors currently used in many applications. This device can also have improved performance. Advantageously, it makes it possible to generate abrupt switching thanks to the PN junction, which can be used, for example, for devices with a high slope. The current levels used can remain low, so that this technique is well suited to electronic systems with very low power consumption.

[0010] A second subject relates to a method for controlling the device in which the first control voltage Vno is applied to the first N-doped zone and the second control voltage V2io is applied to the first P-doped zone, and in which: • The first control voltage V110 constitutes a source voltage Vs of the device and the second control voltage V2io constitutes a drain voltage VD of the device, or • The second control voltage V2i0 constitutes the source voltage Vs of the device and the first control voltage V110 constitutes the drain voltage VD of the device. BRIEF DESCRIPTION OF THE FIGURES

[0011] The aims, objects, as well as the characteristics and advantages of the invention will emerge more clearly from the detailed description of an embodiment thereof which is illustrated by the following accompanying drawings in which:

[0012] [Fig.l] [Fig.l] represents an FDSOI transistor as known from the prior art.

[0013] [Fig.2A] Figures 2A and 2B each represent the mapping of the doping within the device according to an embodiment of the invention.

[0014] [Fig.2B]

[0015] [Fig.3A] Figures 3A and 3B represent current-voltage characteristics of the device according to one of the embodiments of the invention obtained by simulation.

[0016] [Fig.3B]

[0017] [Fig.3C] [Fig.3C] is a table summarizing the parameters applied during the simulations of Figures 3A and 3B.

[0018] [Fig.4A] Figures 4A and 4B represent the distribution of charges within the device respectively in a blocked configuration (VBG=1.7V) and in a passing configuration (VBG=L8V).

[0019] [Fig.4B]

[0020] [Fig.4C] [Fig.4C] is a table summarizing the parameters applied during the simulations of Figures 4A and 4B.

[0021] [Fig.5A] Figures 5A and 5B represent the distribution of the electrostatic potential within the device in blocked (VBG=L7V) and passing (VBG=L8V) configurations.

[0022] [Fig.5B]

[0023] [Fig.5C] [Fig.5C] is a table summarizing the parameters applied during the simulations of Figures 5A and 5B.

[0024] [Fig.6A] Figures 6A and 6B represent simulations of the level of the conduction and valence bands of the device in blocked (VBG=L7V) and passing (VBG=L8V) configurations.

[0025] [Fig.6B]

[0026] [Fig.6C] [Fig.6C] is a table summarizing the parameters applied during the simulations of Figures 6A and 6B.

[0027] [Fig.7A] Figures 7A and 7B represent the distribution of the electric field in the direction of transport within the device in blocked (VBG=L7V) and passing (VBG=L8V) configurations.

[0028] [Fig.7B]

[0029] [Fig.7C] [Fig.7C] is a table summarizing the parameters applied during the simulations of Figures 7A and 7B.

[0030] [Fig.8A] Figures 8A and 8B represent the distribution of the current density of the electrons within the device in blocked (VBG=L7V) and passing (VBg =1.8V) configurations.

[0031] [Fig.8B]

[0032] [Fig.8C] [Fig.8C] is a table summarizing the parameters applied during the simulations of Figures 8A and 8B.

[0033] [Fig.9A] Figures 9A, 9C and 9E show current-voltage characteristics of the device obtained respectively by increasing a second gate voltage V G2 and setting a first gate voltage VGi to a value of -0.5V, by increasing the first gate voltage VGi and setting the second gate voltage VG2 to a value of -0.5V, and by decreasing the second gate voltage.

[0034] [Fig.9B] Figures 9B and 9D are tables summarizing the parameters applied during the simulations of Figures 9A, 9C and 9E.

[0035] [Fig.9C]

[0036] [Fig.9D]

[0037] [Fig.9E]

[0038] The drawings are given as examples and are not limiting of the invention. They constitute schematic representations of principle intended to facilitate the understanding of the invention and are not necessarily on the scale of practical applications. In particular, the dimensions are not representative of reality. DETAILED DESCRIPTION

[0039] Before beginning a detailed review of embodiments of the invention, optional features which may possibly be used in combination or alternatively are set out below:

[0040] According to one example, the device further comprises a first electrode and a second electrode, the first N-doped zone is in contact with the first electrode which is configured to receive a first control voltage Vn0 and the first P-doped zone is in contact with the second electrode which is configured to receive a second control voltage V2io.

[0041] According to an example: • The first control voltage Vno constitutes a source voltage Vs of the device and the second control voltage V2io constitutes a drain voltage VD of the device, or • The second control voltage V2io constitutes the source voltage Vs of the device and the first control voltage Vno constitutes the drain voltage VD of the device.

[0042] According to an example, the device further comprises a first gate electrode and a second gate electrode, the first gate is in contact with the first gate electrode which is configured to receive the application of a first gate voltage VGi and the second gate is in contact with the second gate electrode which is configured to receive the application of a second gate voltage V G2*

[0043] According to one example, the device comprises a back gate electrode and the gate rear is in contact with the rear gate electrode which is configured to receive the application of a rear gate voltage VBG.

[0044] According to one embodiment, the device further comprises a control circuit configured to apply: • the first control voltage Vno on the first electrode, • the second control voltage V2io on the second electrode, • the first grid voltage VG1 on the first electrode, • the second grid voltage VG2 on the second electrode, • the back gate voltage VBG on the back gate electrode, the first control voltage Vno, the second control voltage V2io, the first gate voltage VGi, the second gate voltage VG2 and the rear gate voltage VBG being able to take different values ​​and at least values ​​between -5 and 5 V.

[0045] According to one example, the control circuit is configured to be able to switch the device from an on configuration, in which the PN junction is in an on state, to a blocked configuration in which the PN junction is in a blocked state, or vice versa, by varying the rear gate voltage VBG between an open rear gate voltage Vbg,on and a blocked rear gate voltage V bg.off distinct from the open rear gate voltage Vbg,on-

[0046] According to an example, VGi = VG2 + AVG with AVG between - IV and +1V.

[0047] According to one example, VGi<0.

[0048] According to one example, VG2<0.

[0049] According to one example, VGi>0 and VG2>0.

[0050] According to an example, VG1 = VG2-

[0051] According to one example, the PN junction has a diffusion voltage Vbi, and in which the drain-source voltage, defined by VD-VS, is greater than the diffusion voltage Vbi.

[0052] According to one example, the back gate voltage VBG is between -1 and 2 V.

[0053] According to one example, the n-MOS transistor and the p-MOS transistor are separated by a distance L greater than 10 nm, preferably greater than 50 nm, and / or less than 500 nm.

[0054] A second object of the invention relates to a method for controlling the device. According to one example, the method provides for varying the rear gate voltage VBG between an open rear gate voltage Vbg,on and a blocked rear gate voltage Vbg,off distinct from the open rear gate voltage VBGjon, so as to switch the device from an on configuration, in which the PN junction is in an on state, to a blocked configuration in which the PN junction is in a blocked state.

[0055] According to one example, the method provides for the application of the voltages VG1 and VG2 so that VGi = VG2 + AVG with A VG between - IV and +1 V.

[0056] According to one example, the method provides for the application of the voltages VG1 and VG2 so that VGi>0 and VG2>0.

[0057] According to one example, the method provides for the application of the voltage VG1 such that VG1 <0.

[0058] According to one example, the method provides for the application of the voltage VG2 so that VG2 <0.

[0059] According to one example, the method provides for the application of the voltages VG1 and VG2 so that VG1 = VG2.

[0060] According to one example, the method provides for the application of voltages V110 and V2i0 so that the drain-source voltage, defined by VD-VS, is greater than a diffusion voltage Vbi of the PN junction.

[0061] According to one example, the method provides for the application of a back gate voltage VBG of between -1 and 2 V.

[0062] It is specified that, in the context of the present invention, the terms "on", "overcomes", "covers", "underlying", "facing" and their equivalents do not necessarily mean "in contact with". Thus, for example, the deposition, transfer, bonding, assembly or application of a first layer on a second layer does not necessarily mean that the two layers are in direct contact with each other, but means that the first layer at least partially covers the second layer by being either directly in contact with it or by being separated from it by at least one other layer or at least one other element.

[0063] A layer may also be composed of several sub-layers of the same material or of different materials.

[0064] A substrate, a layer, a device, “based” on a material M, is understood to mean a substrate, a layer, a device comprising this material M only or this material M and possibly other materials, for example alloying elements, impurities or doping elements. Thus a material based on a III-N material may comprise a III-N material with added dopants. Similarly, a GaN-based layer typically comprises GaN and AlGaN or InGaN alloys.

[0065] The term "III-V material" refers to a semiconductor composed of one or more elements from column III and column V of Mendeleev's periodic table. Elements in column III include boron, gallium, aluminum, and indium. Column V contains, for example, nitrogen, arsenic, antimony, and phosphorus.

[0066] A reference frame, preferably orthonormal, comprising the axes x, y, z is represented in [Fig.2A]. This reference frame is applicable by extension to the other figures.

[0067] In the present patent application, we will preferably speak of thickness for a layer and of height for a structure or a device. The thickness is taken along a direction normal to the main extension plane of the layer, and the height is taken perpendicular to the base plane XY. Thus, a layer typically has a thickness along z, when it extends mainly along an XY plane, and a projecting element, for example an isolation trench, has a height along z. The relative terms “on”, “under”, “underlying” preferably refer to positions taken along the z direction.

[0068] The terms “substantially”, “approximately”, “of the order of” mean “to within 10%, preferably to within 5%”.

[0069] The device according to different embodiments of the invention will now be described with reference to Figures 2A and 2B.

[0070] The device 1 comprises two field effect transistors: one of the n-MOS 100 type, and the other of the p-MOS 200 type. Preferably, it does not comprise other transistors or at least not other transistors joined to one or the other of the first two by a PN junction.

[0071] The n-MOS transistor 100 comprises a first drain, a first source, a first gate 101 and a first gate oxide 102.

[0072] The first gate oxide 102 extends under the first gate 101. The first N-doped zone 110 and the second N-doped zone 120 are each in contact with a first channel 103, called a conduction channel but which can also be a carrier-free zone, separating them. This first channel 103 is in contact with the lower face of the first gate oxide 102. The first channel 103 advantageously has a thickness in the z direction of between 5 and 10 nm, typically substantially equal to 7 nm.

[0073] The n-MOS transistor 100 further typically comprises spacers 104 making it possible to isolate the first gate 101 from the first drain on the one hand and from the first source on the other hand. These spacers 104 typically cover the lateral flanks of the first gate 101. They are intended, among other things, to limit the parasitic capacitive coupling between the first gate 101 and the first source on the one hand and the first drain on the other hand.

[0074] The p-MOS transistor 200 comprises a second drain, a second source, a second gate 201, a second gate oxide 202 and a second channel 203 also called a conduction channel but which can also be a carrier-free zone. The characteristics of the n-MOS transistor 100 can be transposed mutatis mutandis to the p-MOS transistor 200.

[0075] The n-MOS transistor 100 and the p-MOS transistor 200 are separated by a distance L measured in the XY plane and defined as the distance between a flank 106 of the transistor n-MOS transistor 100 and a flank 206 of the p-MOS transistor 200 facing it. The flanks 106, 206 of the transistors 100, 200 typically correspond to the flanks of the spacers 104, 204. The distance L is preferably, for reasons of technological limitations during the manufacture of the device, greater than 50 nm. However, it would be possible in the intended applications for the distance L to be set to values ​​as low as 10 nm. With the aim of optimizing the density of devices that can be integrated on a chip, it is preferably less than 500 nm.

[0076] The device further comprises a first N-doped zone 110 and a second N-doped zone 120. The first N-doped zone 110 and the second N-doped zone 120 may constitute the first drain and the first source respectively, or vice versa.

[0077] Similarly, the device comprises a first P-doped zone 210 and a second P-doped zone 220 which can respectively constitute the second drain and the second source, or vice versa.

[0078] The second N-doped zone 120 and the second P-doped zone 220 are in contact and thus form a PN junction 1000. The PN junction 1000 has a diffusion voltage, commonly referred to by the English term “built-in” voltage, noted V bi and the value of which depends in particular on the doping level of the zones 120, 220 constituting it.

[0079] The doped zones 110, 120, 210, 220 are preferably all located in an active layer 10. The active layer 10 is preferably based on at least one IV-IV material. It may also be based on at least one III-V material, preferably based on at least one III-N material. For example, this material is based on GaN. This material may also be based on silicon. It may be a homogeneous layer, typically formed from a single material. The active layer 10 typically has an upper face 11 and a lower face 12 both extending mainly in the XY plane of the orthogonal reference frame XYZ. It has a thickness ei0 along the z direction. The thickness ei0 of the active layer 10 is advantageously between 20 and 30 nm, typically substantially equal to 25 nm.

[0080] Certain elements constituting the transistors 100, 200 may have been at least partially formed from a continuous layer called the fabrication layer. For example, certain regions of the fabrication layer may have been oxidized to form the gate oxides 102, 202 and / or the spacers 104, 204. The fabrication layer may also have been etched and then various deposits may have been made on this fabrication layer in order to form the gate oxides 102, 202, spacers 104, 204 and / or gates 101, 201. The untransformed or etched regions of the fabrication layer then form part of the active layer 10. The active layer 10 may further comprise areas having been epitaxially grown from the fabrication layer.

[0081] In order to produce a functional PN 1000 junction, in the case where the second N-doped zone 120 constitutes the first drain, the second P-doped zone 220 constitutes the second source. Consequently, the first N-doped zone 110 then constitutes the first source and the first P-doped zone 220 constitutes the second drain. In this case, the first N-doped zone 110 constitutes the source and the first P-doped zone 220 the drain of the device 1.

[0082] Conversely, in the case where the second N-doped zone 120 constitutes the first source, the second P-doped zone 220 constitutes the second drain. Consequently, the first N-doped zone 110 then constitutes the first drain and the first P-doped zone 220 constitutes the second source. In this case, the first N-doped zone 110 constitutes the drain and the first P-doped zone 220 the source of the device 1.

[0083] The device 1 further comprises a dielectric layer 300 having an upper face 301 and a lower face 302 both extending mainly in planes parallel to the XY plane of the orthogonal reference frame. The upper face 301 of the dielectric layer 300 is in contact with the first N-doped zone 110, the second N-doped zone 120, the first P-doped zone 210 and the second P-doped zone 220. The dielectric layer 300 thus constitutes a buried dielectric common to the two transistors 100, 200 and therefore generally a buried dielectric for the device 1. It has, along the z direction, a thickness e300 typically equal to 25 nm. This value corresponds to the standards of the microelectronics industry. The invention can, however, function perfectly for other values ​​of e300.The value of the back gate voltage VBg will be adjusted according to the value of e300: the thicker the dielectric layer 300, the higher the back gate voltage to be applied.

[0084] The device 1 further comprises a rear grid 400 in contact with the lower face 302 of the dielectric layer 300.

[0085] The device 1 may comprise the following electrodes or contact connections: • a first electrode 115 in contact with the first N-doped zone 110, • a second electrode 215 in contact with the first P-doped zone 210, • a first grid electrode 105 in contact with the first grid 101, • a second grid electrode 205 in contact with the second grid 201, • a rear grid electrode 405 in contact with the rear grid 400, each of these electrodes being configured to be able to receive the application of a voltage. These electrodes are typically metal layers deposited in contact with each of the doped zones 110, 210 and grids 101, 201, 400.

[0086] More specifically, it is provided in particular that the following may be applied: • a first control voltage Vno on the first electrode 115, • a second control voltage V2io on the second electrode 215, • a first gate voltage VG1 on the first electrode 105, • a second gate voltage VG2 on the second electrode 205, • a rear gate voltage VBG on the rear gate electrode 405.

[0087] Preferably, all the electrodes 115, 215, 105, 205 and 405 are accessible - that is to say that voltages can be applied to them - from the same face called the front face of the device 1. In this regard, the rear gate 400 advantageously projects relative to the dielectric layer 300 so as to allow a contact resumption of said rear gate 400 from the front face of the device 1. The dielectric layer 300 may furthermore, at the level of this contact resumption, have an excess thickness. This excess thickness typically corresponds to the sum of the thickness e300 of the dielectric layer 300 and the thickness ei0 of the active layer 10. The rear gate electrode 405 is then level in the z direction with the first electrode 115 and the second electrode 215. This makes it easier to manufacture them simultaneously.Advantageously, the presence of at least one shallow isolation trench (commonly referred to as STI, the English acronym for “Shallow Trench Isolation”) is then provided, making it possible to electrically isolate the rear grid 400 from the active layer 10.

[0088] Thus, the behavior of the device 1 can be controlled at five control points. FDSOI transistors, commonly used in the microelectronics industry, which have a single gate on the front face, can only be controlled at four control points (drain, source, front gate, back gate, visible in [Fig.l]). Thanks to this additional control point, it is possible to more finely control the electrical behavior of the device 1 compared to a conventional FDSOI transistor. This also gives the device 1 additional functionalities and allows it to be used for other applications, as will be detailed later.

[0089] The first control voltage Vno and the second control voltage V2io constitute for the device 1 respectively a drain voltage VD and a source voltage Vs, or vice versa. More precisely: • If the first N-doped zone 110 constitutes the first source and the first P-doped zone 210 the second drain, then the first control voltage Vue constitutes the source voltage Vs of device 1 and the second control voltage V2io constitutes the drain voltage VD of device 1. This scenario is considered in [Fig.2A]. • If the first N-doped zone 110 constitutes the first drain and the first P-doped zone 210 the second source, then the first control voltage Vue constitutes the drain voltage VD of device 1 and the second control voltage V2i0 constitutes the source voltage Vs of device 1. This case of figure is considered in [Fig.2B].

[0090] In the first case, the source of device 1 is located at an N-doped area and the drain at a P-doped area. In this configuration, device 1 in operation will therefore have an overall n-MOS type behavior. Conversely, in the second case, the source of device 1 is located at a P-doped area and the drain at an N-doped source. Device 1 in operation will therefore have an overall p-MOS type behavior this time.

[0091] It should be noted that the source or drain function of the zones 110, 120, 210 and 220 depends on the voltages applied to them, and more precisely on the sign of the voltages V110-V120 and V2io-V22o- Thus, it is possible to switch the device 1 from n-MOS behavior to p-MOS behavior, and vice versa, by simply changing the sign of these voltage differences. The device 1 thus constitutes a vertical switching device (often referred to by the English term “sharp switch”).

[0092] The rear gate voltage plays a major control role in device 1.

[0093] The device 1 in operation may be in a so-called on-line configuration or in a so-called off-line configuration.

[0094] In the blocked configuration, the PN junction 1000 is in a blocked state. It has a space charge region, or depletion region, comprising fixed charges but in which free charges cannot flow. A potential barrier thus separates the n-MOS transistor 100 and the p-MOS transistor 200 and prevents the flow of current between the source and the drain of the device 1. This blocked configuration of the device 1 can also be called the “OFF state” of the device 1.

[0095] In the on-configuration of the device 1, the PN junction 1000 is in an on-state. There is therefore no potential barrier between the n-MOS transistor 100 and the p-MOS transistor 200. Consequently, the assembly formed by the first conduction channel 103, the PN junction 1000 and the second conduction channel 203 is crossed by charges circulating freely between the source and the drain of the device. The current can therefore flow in the device 1. This on-configuration of the device 1 can be designated the “ON state” of the device 1.

[0096] The transition from the blocked configuration to the on configuration of the device 1, or vice versa, is done by switching the PN junction 1000. Such a junction is characterized in particular by its switching speed, which gives the device 1 itself excellent efficiency in transitioning from the ON state to the OFF state and vice versa. This is what will subsequently be characterized with reference to FIGS. 3A to 8C.

[0097] The fact that a small variation in voltage allows the device to pass from one state to another ensures high energy efficiency. Device 1 can therefore be used in electronic applications with very low energy consumption. This also improves its performance in terms of speed of response to external requests. This characteristic is thus the origin of several important advantages of device 1.

[0098] All the simulations presented in Figures 3A to 8C which will now be described were carried out for a device 1 in which the first N-doped zone 110 constitutes the source of the n-MOS transistor 100 and the first P-doped zone 210 constitutes the drain of the p-MOS transistor 200 (n-FET type behavior). The drain-source voltage VDs=VD-Vs of the device 1 is therefore defined by V2io-Vno. It should be noted that simulations relating to a device 1 exhibiting p-FET behavior would make it possible to draw similar lessons on its efficiency.

[0099] Figures 3A and 3B show the current-voltage characteristics ID=f(VBG), respectively in logarithmic and linear scales, obtained by TCAD (Technology Computer Aided Design) simulation of the device 1. During this simulation: • the first gate voltage VGi and the second gate voltage VG2 were set to the same positive value. The simulation was carried out for several values ​​of VGi=VG2, varying from - IV to 0V. These different simulations correspond to the different curves in Figures 3A and 3B. • the drain-source voltage VDS was set to a value of IV. This value is notably higher than the built-in voltage, or diffusion voltage, of the PN 1000 junction. • the back gate voltage VBG varies from - IV to 2V. • we note the evolution of the drain-source current IDS circulating in device 1 as a function of VBG.

[0100] These elements are summarized in the table presented in [Fig.3C].

[0101] These figures demonstrate abrupt current switching (behavior sometimes referred to as "steep slope"). A variation in the back gate voltage VBG of only a few mV (lmV=103V) ​​allows a variation of up to eight decades of current. This corresponds to a subthreshold slope that can have values ​​as low as ImV / dec. For comparison, the subthreshold slope of FDSOI transistors commonly used in industry is generally of the order of 80mV / dec. The device 1 according to the invention therefore makes it possible to achieve performances that are much higher than those of conventional FDSOI transistors.

[0102] For example, for VGi=VG2=-0.9V, a variation of a current of approximately 10 5A at a current of approximately 10 13A is obtained for a variation of VBg of less than 50mV.

[0103] It should be noted that the back gate voltage at which the device 1 switches V bg,commutation can be adjusted over a wide voltage range, here from approximately -0.5 V to nearly 1.5 V, by adjusting the voltage applied to the first gate 101 and the second gate 201. Thus, the device 1 can be used for different applications by simply setting the voltages VGi and VG2-

[0104] Figures 4A and 4B are maps representing the distribution of charges within the device 1 in blocked ([Fig.4A]) and passing ([Fig.4B]) configurations.

[0105] During this simulation: • the first gate voltage VGi and the second gate voltage VG2 were set to the same value of -IV. • the drain-source voltage VDS was set to a value of IV. • the rear gate voltage VBg is set a first time at 1.7V ([Fig.4A]) and once at 1.8V ([Fig.4B]). • the volumetric charge density, expressed in C.m3, is recorded at any point in the device.

[0106] These elements are summarized in the table presented in [Fig.4C].

[0107] These maps make it possible in particular to observe the evolution of the space charge zone of the PN junction 1000. It is observed that this creates a potential barrier over the entire height of the junction when VBG=1.7V ([Fig.4A]), which gives way when the rear gate voltage reaches a value of 1.8V ([Fig.4B]). In fact, in [Fig.4B], against the upper face 301 of the dielectric layer 300, a continuous zone with a charge density of the order of 1019C / m3 can be observed. It is in particular through this zone that the drain-source current IDS flows once the device has been switched. These two figures thus illustrate the switching of the PN junction 1000 and consequently that of the device 1.

[0108] Figures 5A and 5B show maps representing the distribution of the electrostatic potential within the device 1 in blocked ([Fig.5A]) and on-configurations ([Fig.5B]). The simulation parameters are identical to those of the simulations illustrated in Figures 4A and 4B, as indicated in [Fig.5C]. In [Fig.5A] we observe a very strong difference in electrostatic potential between the second N-doped zone 120 and the second P-doped zone 220 forming the PN junction 1000, testifying to the potential barrier prevailing in the PN junction 1000. After switching and transition to the on-configuration, this potential difference disappears, which allows the current to flow between the source and the drain of the device.

[0109] It should be noted that Figures 5A and 5B demonstrate that switching can be achieved by varying VBG by 100 mV, but it has been shown that a variation of less than 10 mV may be sufficient to observe the same phenomenon.

[0110] Figures 6A and 6B represent simulations of the level of the conduction bands ([Fig.6A]) and valence bands ([Fig.6B]) between the source and the drain of the device 1 in blocked (dark gray curves) and on-conversion (light gray curves) configurations. The simulation parameters are identical to those of the simulations illustrated in Figures 4A and 4B, as indicated in [Fig.6C]. It is observed that in the blocked configuration, the conduction band has, at the level of the second N-doped zone 120, a potential barrier blocking the passage of electrons from the source to the drain. For a value of V bg corresponding to the on-conversion configuration of the device 1, this barrier is lowered and the current can flow. A similar phenomenon occurs for the valence band: in the blocked configuration, the valence band presents, at the level of the second P 220 doped zone, a potential barrier blocking the passage of the holes from the drain to the source of device 1.After switching from the blocked configuration to the conducting configuration, the potential barrier is lowered and current can flow. These figures again demonstrate that abrupt switching of device 1 is enabled by the sudden transition of the PN 1000 junction from the blocked state to the conducting state, or vice versa.

[0111] Figures 7A and 7B show maps representing the distribution of the electric field along the Y direction within the device 1 in blocked ([Fig.7A]) and passing ([Fig.7B]) configurations. The simulation parameters are identical to those of the simulations illustrated in Figures 4A and 4B, as indicated in [Fig.7C]. The switching results in a strong lateral electric field at the PN junction 1000 in the OFF state and a practically zero electric field in the ON state of the device 1.

[0112] Figures 8A and 8B show maps representing the distribution of the electron current density within the device 1 in blocked ([Fig.8A]) and passing ([Fig.8B]) configurations. A very strong increase in the current density takes place after switching the device 1 from the OFF state to the ON state.

[0113] The characteristics just studied with reference to FIGS. 3A to 8C were obtained by fixing the value of the gate voltages VGi and VG2 and by varying the back gate voltage VBG. They made it possible to show that abrupt switching could be obtained for the current-voltage characteristic IDs=f(VBG). However, abrupt switching can also be obtained for the current-voltage characteristic IDs=f(VDS). This is what is illustrated in FIGS. 9A to 9D. First, [Fig.9A] shows a study of the current-voltage characteristic IDS =f(VDs) as a function of the second gate voltage VG2. During this simulation: • the first gate voltage VGi is set to -0.5V. • the drain-source voltage VDs varies from 0V to 2V. • the back gate voltage VBG has been set to 0.4V. • we note the evolution of the drain-source current IDS circulating in device 1 as a function of VDS and this for different values ​​of VG2 between - IV and IV corresponding to as many curves on [Fig.9A].

[0114] It is observed that an abrupt switching of the drain-source current IDS is obtained around a switching voltage VDs, switching = 1-05V, and this whatever the voltage VG2 applied to the gate of the p-MOS transistor.

[0115] [Fig.9C] then shows a study of the current-voltage characteristic IDs=f(VDS) as a function of the first gate voltage VGi. During this simulation: • the second gate voltage VG2 is fixed at -0.5V. • the drain-source voltage VDS varies from 0V to 2V. • the back gate voltage VBG has been set to 0.4V. • we note the evolution of the drain-source current IDS circulating in the device 1 as a function of VDS and this for different values ​​of VGi between - IV and IV corresponding to as many curves on [Fig.9C].

[0116] It is observed that an abrupt switching of the drain-source current IDS is obtained on the condition that the first gate voltage VGi is in the correct range of values. In the present case, it is necessary that VGi < ​​-0.3V. Above this threshold, i.e. for VGi > -0.3V, the first gate voltage is not sufficient to form the potential barrier at the PN junction 1000 between the drain of the n-MOS transistor 100 and the source of the p-MOS transistor 200. The device 1 then does not exhibit abrupt switching and has a behavior similar to that of a PIN diode. For VGi < ​​-0.3V, the first gate voltage is sufficient to form the potential barrier at the PN junction 1000. An abrupt switching is observed and takes place for a drain-source voltage VDS that is all the stronger as the first gate voltage VGi is low.In fact, the lower VGi, the greater the potential barrier, the higher the drain-source voltage needed to make it disappear and therefore the higher the switching voltage VDS.

[0117] [Fig.9E] illustrates the current-voltage characteristic IDs=f(VDS) obtained by a simulation similar to that used to obtain [Fig.9C], but during which the drain-source voltage VDS varies from 2 V to 0V and not from 0V to 2V. This is therefore a characteristic commonly called “backward” or “reverse”, while the characteristic shown in [Fig.9C] constitutes its “forward” counterpart.

[0118] It is noted that, for each of the values ​​of first gate voltage VGi studied, the switching voltage VDs .commutation is different in “backward” mode and in “forward” mode. The switching voltage VDs,commutation,bw in backward mode is notably here lower than the switching voltage VDs,commutation,fw in forward mode. These two figures therefore highlight a hysteresis phenomenon, which can be used to advantage in memory applications.

[0119] According to one embodiment, the device 1 comprises a control circuit making it possible to apply the previously mentioned voltages to each of these electrodes. The control circuit also makes it possible to vary the voltages V110, V2io, VGi, VG2 and Vbg, for example in a given range such as [-5V, 5V].

[0120] The control circuit is advantageously configured to be able to switch the device 1 from the on configuration to the off configuration and vice versa.

[0121] The invention is not limited to the embodiments previously described and extends to all embodiments covered by the invention.

Claims

Claims

1. Microelectronic device (1) comprising: • an n-MOS field effect transistor (100) comprising a first drain, a first source, a first gate (101) and a first gate oxide (102), • a first N-doped area (110), constituting one of the first drain and the first source, • a second N-doped area (120), constituting the other of the first drain and the first source, characterized in that it further comprises: • a p-MOS field effect transistor (200) comprising a second drain, a second source, a second gate (201) and a second gate oxide (202), • a first P-doped area (210), constituting the second source if the first N-doped area (110) constitutes the first drain, or the second drain, if the first N-doped area (110) constitutes the first source, • a second P-doped area (220), constituting the other of the second drain and the second source,• a dielectric layer (300) having an upper face (301) in contact with the first N-doped zone (110), the second N-doped zone (120), the first P-doped zone (210) and the second P-doped zone (220), • a rear gate (400) in contact with a lower face (302) of the dielectric layer (300), and in that the second N-doped zone (120) and the second P-doped zone (220) form a PN junction (1000).,

2. Device (1) according to the preceding claim comprising a first electrode (115) and a second electrode (215), and in which the first N-doped zone (110) is in contact with the first electrode (115) which is configured to receive a first control voltage V110 and the first P-doped zone (210) is in contact with the second electrode (215) which is configured to receive a second control voltage V2i0.

3. Device (1) according to the preceding claim in which: • The first control voltage V110 constitutes a source voltage Vs of the device (1) and the second control voltage V2io constitutes a drain voltage VD of the device (1), or • The second control voltage V2io constitutes the source voltage Vs of the device (1) and the first control voltage V110 constitutes the drain voltage VD of the device (1).

4. Device (1) according to any one of the preceding claims comprising a first gate electrode (105) and a second gate electrode (205), and wherein the first gate (101) is in contact with the first gate electrode (105) which is configured to receive the application of a first gate voltage VG1 and the second gate (201) is in contact with the second gate electrode (205) which is configured to receive the application of a second gate voltage VG2.

5. Device (1) according to any one of the preceding claims comprising a back gate electrode (405) and wherein the back gate (400) is in contact with the back gate electrode (405) which is configured to receive the application of a back gate voltage VBG

6. Device (1) according to claims 2 to 5 in combination further comprising a control circuit configured to apply: • the first control voltage Vi i0 on the first electrode (115), • the second control voltage V2i0 on the second electrode (215), • the first gate voltage VG1 on the first electrode (105), • the second gate voltage VG2 on the second electrode (205), • the back gate voltage VBG on the back gate electrode (405), the first control voltage Vno, the second control voltage V2io, the first gate voltage VGi, the second gate voltage VG2 and the rear gate voltage VBG being able to take different values ​​and at least values ​​between -5 and 5 V.

7. Device (1) according to the preceding claim in which the control circuit is configured to be able to switch the device (1) from an on configuration, in which the PN junction (1000) is in an on state, to a blocked configuration in which the PN junction (1000) is in a blocked state, or vice versa, by varying the rear gate voltage VBG between an open rear gate voltage VBGj0N and a blocked rear gate voltage VBGjOff distinct from the open rear gate voltage VBGj0N.

8. Device (1) according to the preceding claim in which VGi = VG2 + AVG with AVG between -IV and +1V.

9. Device (1) according to any one of the two preceding claims in which VGi<0.

10. Device (1) according to any one of the three preceding claims, wherein VG2<0.

11. Device (1) according to any one of claims 7 and 8, in which VGi>0 and VG2>0.

12. Device (1) according to any one of claims 7 to 11, in which VGi = VG2.

13. Device (1) according to any one of claims 7 to 12, in which the PN junction has a diffusion voltage Vbi, and in which the drain-source voltage, defined by VD-VS, is greater than the diffusion voltage Vbi.

14. Device (1) according to any one of claims 7 to 13, wherein the back gate voltage VBG is between -1 and 2 V.

15. Device (1) according to any one of the preceding claims in which the n-MOS transistor (100) and the p-MOS transistor (200) are separated by a distance L greater than 10 nm, preferably greater than 50 nm, and / or less than 500 nm.

16. Method for controlling the device (1) according to any one of claims 2 to 15 in which the first control voltage Vno is applied to the first N-doped zone (110) and the second control voltage V2i0 is applied to the first P-doped zone (210), and in which: • The first control voltage Vno constitutes a source voltage Vs of the device (1) and the second control voltage V2io constitutes a drain voltage VD of the device (1), or • The second control voltage V2io constitutes the source voltage Vs of the device (1) and the first control voltage Vno constitutes the drain voltage VD of the device (1).

17. Method for controlling the device (1) according to the preceding claim wherein the device comprises a rear gate electrode (405), the rear gate (400) is in contact with the rear gate electrode (405) which is configured to receive the application of a rear gate voltage VBG, and wherein the rear gate voltage VBg varies between an open rear gate voltage VBGjon and a blocked rear gate voltage Vbg,off distinct from the open rear gate voltage VBGjon, so as to switch the device (1) from an on configuration, in which the PN junction (1000) is in an on state, to a blocked configuration in which the PN junction (1000) is in a blocked state.

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