Method for manufacturing a substrate for a power electronic or radio frequency device

Abstract

The invention relates to a method for manufacturing a substrate (15) for a power electronic or radio frequency device, comprising the formation of a support substrate (10) comprising the deposition of at least one layer (100) of polycrystalline silicon carbide by chemical vapor deposition (CVD) under conditions chosen to form carbon inclusions (1) in said silicon carbide layer, and the assembly of the support substrate (10) and a surface layer (20) into a single-crystal material. Figure for the abstract: Fig 2A

Description

Title of the invention: Method for manufacturing a substrate for a power electronic or radio frequency device. Technical field

[0001] The present invention relates to a substrate for an electronic device, particularly for application in power electronics or radio frequency. The invention also relates to an electronic device comprising such a substrate, and to a method for manufacturing such a substrate. State of the art

[0002] Silicon carbide (SiC) is widely used for the manufacture of power electronic or radio frequency components.

[0003] A substrate for fabricating such components typically comprises a support substrate, which may be made of polycrystalline SiC (p-SiC), and a surface layer of monocrystalline SiC (m-SiC) extending over the support substrate. Electronic components are fabricated in or on the monocrystalline SiC layer. The structure is cut into chips, each comprising one or more electronic components. Each chip is soldered onto a heat dissipation stack, comprising metallic layers, a heat-conducting ceramic, and a heat sink.

[0004] The heat is thus dissipated mainly by the thermal dissipation stack, implying significant thermal stresses on the filler material bonding by brazing the electronic component and the upper metallic layer of the thermal dissipation stack.

[0005] However, the coefficient of thermal expansion (CTE) and the Young's modulus of SiC and the thermal stack, particularly copper, are very different. Temperature variations therefore cause deformations of unequal magnitude in the different layers above and below the brazing. In particular, since the Young's modulus of SiC is high compared to that of the other materials, the stresses are concentrated in these materials, and especially in the filler material.

[0006] Thus, the filler material is under considerable stress, which leads to cracks, delamination, or crumbling at the brazing interface, resulting in a shortened lifespan of the device.

[0007] To reduce these mechanical stresses, it is known to thin the layers of the composite structure, particularly the polycrystalline SiC base substrate. However, the abrasion of such a base substrate is lengthy and laborious, resulting in a high cost for the electronic component. Furthermore, thinning carries a risk of breakage, rendering the composite structure unusable.

[0008] Another solution is to modify the materials used to carry out the brazing, which is difficult to implement, in particular while preserving the mechanical strength and the electrical and thermal conductivity of the brazing. Description of the invention

[0009] An object of the invention is to propose a composite structure for the production of electronic devices, exhibiting better resistance to temperature cycles, avoiding cracks, delaminations and crumbling at the soldering interface.

[0010] To this end, the invention proposes a method for manufacturing a substrate for a power electronic or radio frequency device, comprising • the formation of a support substrate comprising a deposit of at least one layer of polycrystalline silicon carbide by chemical vapor deposition (CVD), under conditions chosen to form carbon inclusions in said silicon carbide layer, and • the assembly of the supporting substrate and a surface layer into a single-crystal material.

[0011] The gaseous atmosphere CVD process is an alternative to the known sintering process. The CVD process allows control over the composition and morphology of the deposited layer. In particular, it can create a concentration gradient of inclusions in a single deposition process.

[0012] The elongated silicon carbide grains are likely to generate anisotropic electrical and thermal resistivity that is lower in a direction perpendicular to the substrate surface. This improves heat dissipation and electrical conduction towards the back surface of the substrate. The presence of carbon inclusions does not impair the operation of the electronic device fabricated in or on the surface single-crystal layer, which is free of such inclusions.

[0013] Preferably, the surface layer is made of a semiconductor material, preferably silicon carbide or gallium nitride or diamond.

[0014] Advantageously, at least a first phase of the chemical vapor deposition is carried out at a temperature above 1200 °C, preferably above 1400 °C.

[0015] Advantageously, a first temperature at the start of chemical vapor deposition is higher than a second temperature at the end of chemical vapor deposition.

[0016] The invention also relates to a substrate for a power electronic or radio frequency device, comprising • a polycrystalline silicon carbide support substrate having a front face and a back face, and • a surface layer of a single-crystal material extending over the front face of said supporting substrate,

[0017] said substrate being characterized in that at least a portion of said substrate support comprises a plurality of silicon carbide grains having an elongated shape oriented in a direction perpendicular to the surface of the substrate and a plurality of carbon inclusions located between said grains.

[0018] Preferably, the surface layer is made of a semiconductor material, preferably silicon carbide or gallium nitride or diamond.

[0019] Advantageously, the ratio between the length and width of the silicon carbide grains in the support substrate is greater than or equal to 1:1.2, advantageously greater than 1:10 and more advantageously greater than 1:20.

[0020] The ratio between the length and width of the silicon carbide grains further facilitates polishing. Thus, if polishing causes the removal of an elongated silicon carbide grain in a direction perpendicular to the substrate surface, the resulting cavity has smaller horizontal dimensions compared to the removal of a grain in an isotropic structure. Furthermore, removal is made more difficult since the grain is more deeply embedded in the matrix formed by the other grains.

[0021] Advantageously, the carbon inclusions are discontinuous.

[0022] Preferably, the ratio between the width and the length of the carbon inclusions is 1:1.2, advantageously greater than 1:20 and more advantageously greater than 1:30.

[0023] Advantageously, the supporting substrate has a concentration gradient of carbon inclusions, so that the density of carbon inclusions increases from the front face towards the back face.

[0024] In certain embodiments, only a portion of the support substrate includes said carbon inclusions and the support substrate (30) further includes a portion devoid of carbon inclusions between the surface layer of single-crystal SiC and the portion including the carbon inclusions.

[0025] Preferably, the volumetric rate of carbon inclusions in the supporting substrate is between 1% and 40%, preferably between 1% and 20%.

[0026] The invention also relates to an electronic device comprising a substrate as described above and at least one power electronic or radio frequency component formed in or on the surface layer, and a heat dissipation device, the substrate being brazed to the heat dissipation device via a filler material such that the filler material is in solid contact with at least a portion of the portion comprising carbon inclusions on the rear face of the supporting substrate. Brief description of the figures

[0027] Other features and advantages of the invention will become apparent from the detailed description that follows, with reference to the accompanying drawings, in which:

[0028] Fig. 1 illustrates a device comprising two electronic components made from a substrate according to the invention and a heat dissipation stack.

[0029] Fig. 2A illustrates a substrate according to a first embodiment.

[0030] Figure [Fig.2B] illustrates a substrate according to a second embodiment.

[0031] Fig. 2C illustrates a substrate according to a third embodiment.

[0032] Figures 3A to 3D illustrate the steps for producing a support substrate according to the invention.

[0033] Figures 4A to 4C illustrate the assembly steps of the support substrate with the surface layer.

[0034] Fig. 5 is a graph of the different phases of silicon carbide obtained during a CVD process as a function of temperature and gas composition in the deposition chamber. Detailed description of implementation methods

[0035] Figure 1 illustrates a power electronic or radio frequency device comprising one or more electronic chips 11, 12 made from a substrate according to the invention. The chips may be linked by interconnections. In the case of a radio frequency device, the electronic chip may carry a gallium nitride lateral device.

[0036] The electronic chips 11, 12 are mounted on a heat-dissipating structure by means of solder joints 22, 23. This heat-dissipating structure (DBC, an acronym for the English term "Direct Bonded Copper") comprises two copper metallizations 17, 19 and a substrate 18 made of a heat-conducting and electrically insulating ceramic, for example, aluminum nitride. Electrical connections 27, 28 are fixed to the copper metallization 17 by means of solder joints 25, 26.

[0037] A solder joint 29 fixes the device onto a heat sink 34 and a base plate 32. A layer of thermal grease 31 ensures thermal contact between the heat sink 34 and the base plate 32. The power electronic or radio frequency device is encapsulated in a housing 39 which is typically made of plastic.

[0038] Each chip is formed from a substrate comprising a silicon carbide support substrate and a surface layer of a single-crystal material in or on which is formed at least one power electronic component or one radio frequency electronic component. Substrate presentation

[0039] Figures 2A to 2C illustrate substrates 15 for a power electronic or radio frequency device according to different embodiments. Each substrate 15 comprises, from its rear face to its front face, a support substrate 10 and a surface layer 20. The rear face 105, 106 of the support substrate 10 is intended to be fixed to the thermal stack 17, 18, 19 of [Fig. 1] by a solder joint 22. One or more electronic components 11, 12 can be formed in or on the surface layer 20.

[0040] The substrate 10 is made of polycrystalline silicon carbide. At least a portion of the substrate 10 comprises carbon inclusions 1. The silicon carbide is in the form of a plurality of elongated grains 2. The width-to-length ratio of the grains 2 is greater than or equal to 1:1.2, and preferably greater than 1:10. In preferred embodiments, the width-to-length ratio of the grains is greater than 1:20. The grains 2 are oriented along a Z direction perpendicular to the surface 220 of the substrate and bonded together. The measurement and variation of the grain size can be evaluated by counting the number of intersections between a line parallel to the base of the substrate and the grain boundaries. Such a measurement is, for example, performed by a technical observation of electron microscopy such as backscattered electron microscopy (BSE).

[0041] The carbon inclusions 1 are dispersed discontinuously between the silicon carbide grains 2. The width-to-length ratio of the carbon inclusions 1 is greater than or equal to 1:1.2, and preferably greater than 1:10. In preferred embodiments, the width-to-length ratio of the carbon inclusions 1 is greater than 1:30.

[0042] The elongated geometry of the silicon carbide grains 2 and the carbon inclusions 1 results in improved electrical and / or thermal conductivity in a Z direction perpendicular to the substrate surface 220 compared to conductivity perpendicular to Z, because the number of grain boundaries to be crossed between the two faces is limited. Such thermal conductivity particularly promotes efficient heat dissipation to a thermal stack bonded to the back face 105 of the substrate by brazing.

[0043] With reference to [Fig. 2A], the carbon inclusions 1 can be distributed throughout the entire surface of the support substrate 10. The distribution of the inclusions can be homogeneous. Alternatively, the support substrate may exhibit a concentration gradient of carbon inclusions. In this case, the density of the carbon inclusions decreases from the back face towards the front face. The gradient can be continuous or successive in several layers with decreasing carbon content from the back face towards the surface.

[0044] In some cases, with reference to [Fig.2B], a portion 10A extending from the front face is devoid of carbon inclusions and a second portion 10B includes inclusions, which may be distributed homogeneously or according to a gradient.

[0045] Such a configuration presents a front face of homogeneous composition, which facilitates the preparation of the substrate for bonding a single-crystal SiC layer. In particular, grinding and / or polishing steps are easier to perform on a homogeneous front face, because carbon inclusions are more friable than SiC grains. These inclusions are therefore more easily destroyed or removed during polishing, which can lead to an increase in surface roughness.

[0046] For example, the portion 10B containing the inclusions may be a so-called thin layer, having a thickness of between 100 nm and 3 pm. In this case, the layer containing the inclusions has very little impact on the thermal and electrical conductivity.

[0047] Alternatively, the portion 10B comprising the inclusions is a so-called thick layer, having a thickness of, for example, approximately 350 pm. Such a layer allows the substrate to be thinned from its back side after the fabrication of the electronic components on its front side. For example, the layer can be thinned to a final thickness of between 100 and 180 pm. This reduces the overall resistance to the passage of a current flowing along a Z-axis perpendicular to the base of the substrate.

[0048] For all thicknesses of the portion including the inclusions, also for intermediate thicknesses between 3 and 100 pm, a starting portion 10B can be prepared with a thickness greater than the thickness envisaged for the final application, and thinning can be carried out in a subsequent step.

[0049] In other embodiments, the substrate may comprise additional layers. With reference to [Fig. 2C], the substrate may include a porous silicon carbide layer 60 extending from its rear face 106. The substrate may include other layers having a different porosity than layer 60, or one or more layers comprising inclusions obtained by a different method such as sintering, or made of another material.

[0050] A high carbon content reduces the Young's modulus of silicon carbide, thus bringing the Young's modulus closer to that of the substrate supporting the Young's modulus of a thermal stack onto which the electronic component will be soldered. This avoids mechanical and thermal stresses in the substrate, particularly on the back side of the substrate, and in the solder joint. The reduction of stresses increases the component's lifespan.

[0051] The volumetric rate of carbon inclusions in the supporting substrate is between 1% and 40%.

[0052] The thickness of the layer including the inclusions after CVD deposition is typically between 500 pm and 4 mm, with thickness variations (TTV, acronym for the Anglo-Saxon term "Total Thickness Variation") which are typically between 50 pm and 1.5 mm.

[0053] After thinning, the final thickness of the silicon carbide layer formed by CVD can vary depending on the intended application. For example, for a substrate diameter of 150 mm, the thickness of the layer including the inclusions is typically 350 µm ±25 µm, and for a substrate diameter of 200 mm, the thickness of the layer including the inclusions is approximately 500 µm ±25 µm.

[0054] The surface layer 20 is made of a single-crystal material, for example, a semiconductor such as silicon carbide or gallium nitride, or another IILV-type semiconductor. In some cases, the surface layer is made of diamond. In a preferred embodiment, the surface layer is made of single-crystal silicon carbide. In another variant, the surface layer 20 may be a discontinuous layer, for example, a layer composed of an array of tiles, each made of a single-crystal material. This variant can be used for materials not available in dimensions corresponding to the diameter of the supporting substrate. For example, the surface layer may be composed of a plurality of juxtaposed diamond tiles.

[0055] The function of the substrate support is to provide mechanical support for the component to be manufactured and to efficiently dissipate heat to the thermal stack. Furthermore, due to the anisotropy of the grains and carbon inclusions, the electrical conductivity perpendicular to the substrate surface is maximized because the number of grain boundaries to be crossed along the path is reduced. Manufacturing process

[0056] We will now describe the steps of a process for manufacturing such a substrate 15. We begin by providing a support 80 for the fabrication of the substrate support 10. Typically, a graphite support 80 is used, which is easy to remove or burn after the substrate support has been fabricated. The support 80 is introduced into a chemical vapor deposition (CVD) chamber, and the chamber is heated to a first temperature TL. The first temperature Tl is above 1200°C, preferably above 1400°C. A high temperature Tl promotes the formation of carbon inclusions in the substrate support to be formed.

[0057] Simultaneously, a gas mixture is introduced into the deposition chamber. The gas mixture comprises a carrier gas, typically argon, and a deposition precursor fluidized by another gas, which is typically hydrogen.

[0058] With reference to [Fig.3A], a layer 100 of silicon carbide comprising carbon inclusions is deposited on the support 80.

[0059] In the case where a top layer free of inclusions or an inclusion gradient is targeted ([Fig.2B]), the temperature in the enclosure is progressively lowered during the vapor phase deposition process to reach an end-of-deposition temperature T2 lower than Tl and / or the ratio of the Ar / (Ar+H2) gas is lowered.

[0060] In the case where a layer with a homogeneous distribution of inclusions is deposited ( [Fig.2A]), these parameters are kept constant.

[0061] The deposition of the silicon carbide layer is continued in this way in order to obtain a thickness greater than the thickness of the substrate to be manufactured. Typically, a thickness of between 500 µm and 2 mm is targeted.

[0062] At the beginning of the growth of the silicon carbide layer 100, the grain size is often variable and then becomes more homogeneous. By promoting the growth of a thick layer, the portion in which the grain size varies greatly can be removed later, and the portion in which the grain size is homogeneous and of good crystalline quality can be used. During and after deposition, the surface 110 of the layer 100 exhibits high roughness due to the vertical orientation of the grains.

[0063] With reference to [Fig.3B], once the envisaged thickness of the silicon carbide layer 100 is reached, the carbon support 80 is removed mechanically or by combustion.

[0064] With reference to [Fig. 3C], the lower portion 13 of the silicon carbide layer, in which the grain size is inhomogeneous and the crystalline quality is lower than in the upper portion produced at the end of the CVD deposition, is then removed. A surface portion 14 exhibiting high roughness or a significant local variation in thickness on a scale larger than the roughness is also removed.

[0065] The removal of these excess portions 13, 14 is typically achieved by grinding followed by chemical polishing to obtain a flat surface 120 that is sufficiently smooth for bonding a surface layer. Such polishing uses a slurry containing abrasive particles in a chemically active mixture. Typically, after the removal steps, the thickness of the silicon carbide substrate 10 is between 150 and 500 µm and can vary depending on the intended application. After subsequent thinning steps, the thickness is typically between 100 µm and 180 µm.

[0066] With reference to [Fig.3D], the support substrate 10 thus prepared is assembled with a surface layer 20 in a single-crystal material, typically by a Smart Cut™ type process.

[0067] With reference to [Fig.4A], a single-crystal donor substrate 200 is prepared to create the surface layer 20. A cleaning and / or surface treatment can be applied to the surface of the donor substrate 200.

[0068] A weakening zone 21 is then formed in the donor substrate 200, so that to delimit a single-crystal layer 20. The embrittlement zone 21 is formed in the donor substrate 200 at a predetermined depth that corresponds substantially to the thickness of the single-crystal layer intended to form the surface layer of the substrate supporting the power electronic or radio frequency device to be formed. Preferably, the embrittlement zone 21 is created by implanting hydrogen and / or helium atoms into the donor substrate.

[0069] With reference to [Fig.4B], the donor substrate 200 is then glued onto the silicon carbide layer 10.

[0070] With reference to [Fig.4C], a detachment of the donor substrate 200 is caused along the embrittlement zone 21, so as to transfer the single-crystal layer 20 onto the silicon carbide layer containing the carbon inclusions.

[0071] Before or after assembly with the single-crystal silicon carbide layer 20, the support substrate 10 can be assembled with other layers, for example with a porous silicon carbide layer 60 as illustrated in [Fig.2C].

[0072] From the finished substrate, power electronic or radio frequency components can be formed in or on the single-crystal surface layer. The substrate is brazed onto a heat dissipation device. The brazing is performed by adding a material, for example silver, a silver-filled epoxy, gold-silicon, gold-tin, lead-tin, or a liquid-phase sintered material, in solid contact with the underside of the substrate. Thus, the filler material is in thermal contact with the carbon inclusions arranged on the back side of the substrate, which allows heat to be efficiently dissipated from the substrate to the heat dissipation device. Grain formation during the CVD process

[0073] The use of a CVD process promotes grain formation in silicon carbide and the formation of carbon inclusions. Furthermore, unlike a layer produced by sintering, CVD deposition generally results in anisotropic grain growth, such that their axis of maximum elongation extends parallel to the Z-axis perpendicular to the base of the substrate. Strong anisotropy is desirable to promote thermal and / or electrical conductivity along the Z-axis.

[0074] Figure 5 represents the different chemical compositions deposited as a function of temperature and gas composition in the deposition chamber. When the temperature and the Ar / (Ar+H2) gas ratio are relatively low, silicon carbide and pure silicon are deposited. For intermediate values ​​of these two parameters, only silicon carbide is deposited. At high temperatures and a high Ar / (Ar+H2) gas ratio, silicon carbide and carbon are deposited. In the temperature ranges shown, the amount of carbon is lower than the amount of silicon carbide deposited, and carbon is present in the form of inclusions within the silicon carbide layer. The ideal rate for the formation of silicon carbide grains and carbon inclusions therefore depends on the temperature and atmosphere within the deposition chamber, particularly the ratio of carrier gas to fluidizing gas flow. The geometry and size of the inclusions also depend on these parameters.

[0075] The CVD process for obtaining a biphasic silicon carbide deposit with carbon inclusions is explained in detail in R. Liu et al.

[0076] In addition to obtaining an anisotropic structure, CVD deposition offers other advantages compared to the formation of a two-phase structure by sintering. It avoids the use of a binder that can be polluting, particularly in cleanrooms. Furthermore, the control of gas flow and mixing is easy to manage.

[0077] By lowering the temperature during CVD deposition with an adjustment of the Ar / (Ar+H2) gas ratio, an inclusion concentration gradient is achieved in a single deposition process. The temperature decrease can be carried out as a continuous ramp to achieve a continuous gradient for the inclusion concentration. Alternatively, the temperature can be lowered in steps to create layers in the substrate in which the inclusion rate decreases in discrete increments. References

[0078] R. Liu et al.: Experimental phase diagram of SiC in CH3SiCl3-Ar-H2 System, Journal of Materials Research August 2016-1(17):1-11.

Claims

Demands

1. A method for manufacturing a substrate (15) for a power electronic or radio frequency device, comprising • the formation of a support substrate (10) comprising a deposition of at least one layer (100) of polycrystalline silicon carbide by chemical vapor deposition (CVD) in an atmosphere comprising a mixture of argon and a deposition precursor fluidized in hydrogen, said chemical vapor deposition being carried out under conditions of Ar / (Ar+H2) ratio and temperature adapted to form carbon inclusions (1) in said silicon carbide layer, and • the assembly of the support substrate (10) and a surface layer (20) into a single-crystal material.

2. A method according to claim 1, wherein the surface layer (20) is made of a semiconductor material, preferably silicon carbide or gallium nitride or diamond.

3. A process according to claim 1 or claim 2, wherein at least a first phase of the chemical vapor deposition is carried out at a temperature above 1200 °C, preferably above 1400 °C.

4. A method according to any one of the preceding claims, wherein a first temperature (T1) for the start of chemical vapor deposition is greater than a second temperature (T2) for the end of chemical vapor deposition.

5. A process according to any one of the preceding claims, wherein the ratio of Ar / (Ar+H2) decreases during the chemical vapor deposition step.

6. A method according to any one of the preceding claims, wherein the formation of the support substrate further comprises a step of assembling said at least one silicon carbide layer comprising the carbon inclusions (1) with a porous silicon carbide base layer.

7. Substrate for power electronic or radio frequency device, comprising • a support substrate (10) of polycrystalline silicon carbide having a front face (410) and a back face, and • a surface layer (20) of a monocrystalline material extending over the front face (410) of said support substrate (10), said substrate being characterized in that at least a portion of said support substrate (10) comprises a plurality of silicon carbide grains having an elongated shape oriented in a direction perpendicular to the surface of the substrate and a plurality of carbon inclusions located between said grains.

8. Substrate according to claim 7, wherein the surface layer (20) is made of a semiconductor material, preferably silicon carbide or gallium nitride or diamond.

9. Substrate according to claim 7 or claim 8, wherein the supporting substrate has a concentration gradient of carbon inclusions (1), such that the density of carbon inclusions (1) increases from the front face towards the back face.

10. Substrate according to any one of claims 7 to 9, wherein only a portion of the supporting substrate comprises said carbon inclusions (1) and the supporting substrate (30) further comprises a portion devoid of carbon inclusions (1) between the surface layer (20) of single-crystal SiC and the portion comprising the carbon inclusions (1).

11. Electronic device comprising a substrate according to any one of claims 7 to 10 and at least one power electronic or radio frequency component formed in or on the surface layer (20), and a heat dissipation device, the substrate being brazed onto the heat dissipation device via a filler material such that the filler material is in solid contact with at least a portion of the portion comprising carbon inclusions (1) on the rear face of the support substrate (10).

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