Quantum device for forming an array of quantum dots and associated manufacturing process

Abstract

Quantum device for forming a matrix of quantum dots and associated manufacturing method. One aspect of the invention relates to a quantum device (QD) configured to be able to form a matrix of quantum dots (QD), the device (QD) comprising for this purpose: an active layer (AL) made of a semiconductor material; a plurality of first grids (G1) arranged along a plurality of rows (RL); a plurality of second grids (G2) arranged along a plurality of columns (CO) perpendicular to the rows (RL) of the plurality of rows (RL);a plurality of third grids (G3), each third grid (G3) of the plurality of third grids (G3) being arranged at the intersection of a row of the plurality of rows (LI) and a column of the plurality of columns (CO), each third grid (G3) being separated from the nearest third grids (G3), on a row (LI) by a first grid (G1) and on a column (CO) by a second grid (G2); the active layer (CA) comprising openings (OU) throughout the thickness of the active layer (CA) arranged between the rows (LI) of the plurality of rows (LI) and the columns (CO) of the plurality of columns (CO). Figure to be published with the abbreviation: Figure 1;

Description

Title of the invention: Quantum device for forming a matrix of quantum dots and associated manufacturing process. TECHNICAL FIELD OF THE INVENTION

[0001] The technical field of the invention is that of quantum computing.

[0002] The present invention relates to a semiconductor device comprising means for forming an array of quantum dots and, in particular, a device for controlling the chemical potential within each quantum dot and the coupling between adjacent quantum dots, this control being localized while ensuring the absence of charged particles outside the quantum dots. The present invention also relates to a manufacturing method for obtaining such a device. TECHNOLOGICAL BACKGROUND OF THE INVENTION

[0003] In the field of quantum computing, it is known to use quantum dots in which one or more charged particles can be trapped for manipulation. For this, the confinement of the charged particles must be achieved in all three dimensions of space. In the prior art, such confinement can be obtained in two ways (which can be used in combination): structurally (by alternating materials in at least one dimension of space) and / or electrostatically by applying a potential to a portion of conductive material (for example, using a gate electrode). Generally, quantum dots are arranged in the form of a matrix of quantum dots, which allows for better interconnectivity between quantum dots and therefore, for example, more efficient execution of quantum error correction algorithms (see, for example, Fowler, Phys. Rev. A, 2012).

[0004] A quantum dot matrix was, for example, proposed in the paper Li et al., Science, 2018. In this paper, the authors propose a structure comprising three grid levels: along the rows, columns, and diagonals of the quantum dot matrix, these grid levels allow control of the chemical potential in each quantum dot as well as the potential barriers (or tunneling coupling) between adjacent quantum dots. However, the device does not allow complete control of the position of charged particles and, in particular, does not prevent their presence outside the quantum dots, i.e., between the rows and columns of the quantum dot matrix. Moreover, the use of three grid levels implies screening of the higher grid levels by the lower grid levels, which leads to a significant disparity between the different grid levels (the first level grid appears continuous while the second and third level grids take the form of a dotted line).

[0005] Another architecture was proposed in document FR3066297. In this architecture, the active layer of the quantum dot matrix is ​​structured to prevent the presence of charged particles outside the quantum dots, i.e., between the rows and columns of the quantum dot matrix. Furthermore, the proposed device also includes a plurality of grids for controlling the potential barriers between adjacent quantum dots in the quantum dot matrix. However, given the difficulty of implementation, the proposed device does not include a grid for local control of the chemical potential within each quantum dot.Furthermore, grid control is achieved using vias, which allows for good homogeneity between grids, but on the other hand imposes very strict constraints in terms of relative alignment of the different grid levels, thus making the manufacturing process complex to implement.

[0006] There is therefore a need for a device that provides both homogeneous electrostatic control, local control (i.e., by means of a grid located above the element to be controlled) of the chemical potential within each quantum dot, and a means of ensuring the absence of electrical charge between the rows and columns of the matrix. Furthermore, there is a need for a process that enables such a device to be obtained without imposing very strict alignment constraints during manufacturing. Summary of the invention

[0007] The invention offers a solution to the problems mentioned above by providing a device that enables both homogeneous electrostatic control, local control (i.e., by a grid located directly above the element to be controlled) of the chemical potential within each quantum dot, and a means of guaranteeing the absence of charged particles between the rows and columns of the matrix. This is achieved in particular through the implementation of a process that allows the grids and the patterns between the rows and columns of the quantum dot matrix to be produced in a self-aligned manner and on a single lithography level.

[0008] To this end, a first aspect of the invention relates to a quantum device configured to form an array of quantum dots, the device comprising: • An active layer made of a semiconductor material; • A plurality of first grids arranged along a plurality of lines; • A plurality of second grids arranged according to a plurality of columns perpendicular to the lines of the plurality of lines; • A plurality of third grids, each third grid of the plurality of third grids being arranged at the intersection of a row of the plurality of rows and a column of the plurality of columns, each third grid being separated from the nearest third grids, on a row by a first grid and on a column by a second grid;

[0009] the active layer comprising openings throughout the thickness of the active layer arranged between the rows of the plurality of rows and the columns of the plurality of columns.

[0010] Thanks to the device according to the invention, it is possible to obtain a device enabling homogeneous electrostatic control, local control (by a grid located directly above the element to be controlled) of the chemical potential within each quantum dot, and a means of guaranteeing the absence of electrical charge between the rows and columns of the matrix. More particularly, in the device according to the invention, a quantum dot can be formed below each third grid so as to form a matrix of quantum dots. Indeed, each first grid of the plurality of first grids allows, when an electrical potential is applied to it, the modification of the potential barrier separating two parts of the active layer located below two adjacent third grids along the rows.Similarly, each second grid in the plurality of second grids, when an electric potential is applied, allows modification of the potential barrier separating two parts of the active layer located beneath two adjacent third grids along the columns. Furthermore, the first and second grids allow this modification to be performed locally, as they are not "screened" by a conductive layer (in other words, there is no conductive layer between the oxide of the first and second grids and the active layer). Therefore, thanks to the control of the potential barriers exerted by the first and second grids, it is possible to achieve electrostatic confinement of charged particles beneath the third grids of the plurality of third grids, forming a quantum dot beneath each third grid.This electrostatic confinement is further complemented by structural confinement achieved through the openings present in the active layer, since no charged particle can be located at the level of these openings.

[0011] Furthermore, in each quantum dot, the charged particle or particles present are associated with a chemical potential. Now, since each third grid is not "screened" by a conductive layer (in other words, there is no conductive layer between the oxide of the third grids and the active layer), each third grid of the plurality of third grids allows, when an electrical potential is applied to it, to modify the chemical potential of the charged particles present in the quantum dot associated with the third grid considered.

[0012] In addition to the characteristics mentioned in the preceding paragraph, the device according to the first aspect of the invention may have one or more additional characteristics from among the following, considered individually or according to all technically possible combinations.

[0013] In one embodiment, the device is made from a "silicon on insulator" (or SOI for Silicon On Insulator) type substrate, the active layer being made in the silicon layer of the substrate located above the oxide.

[0014] In one embodiment, the device is made from a bulk silicon substrate. Advantageously, the substrate comprises an epitaxial silicon layer coated with a thermal oxide. In this embodiment, the active layer is formed within the silicon layer, preferably epitaxial.

[0015] In one embodiment, the device is made from a Si / SiGe heterostructure, the active layer being made in the Si layer.

[0016] In one embodiment, the device is made from a Ge / SiGe heterostructure, the active layer being made in the Ge layer.

[0017] In one embodiment, the device includes spacers arranged so as to separate each first grid, second grid and third grid from the first, second grids and third grids adjacent.

[0018] In one embodiment, each first grid, second grid and third grid comprises a grid electrode and a grid oxide, and the material of the electrode and the grid oxide of the first, second and third grids are identical.

[0019] In one embodiment, the oxide of the first, second and / or third grids is chosen from SiO2, HfO2 or Al2O3.

[0020] In one embodiment, the thickness of the oxide of the first grids, second grids and / or third grids is between 5 nm and 10 nm.

[0021] In one embodiment, the electrodes of the first grids, second grids and / or third grids are made of a conductive material chosen from Ti, TiN, poly-Si or even W.

[0022] A second aspect of the invention relates to a method for manufacturing a semiconductor device from a substrate comprising a semiconductor layer, called the active layer, on a first surface of said substrate (i.e., on a first surface of said substrate or near the first surface of said substrate), the method comprising: • A step of depositing a first dielectric layer on the first surface; A step of depositing a support layer on the first dielectric layer; A step of etching the support layer so as to form a matrix of first pillars forming a plurality of rows and a plurality of columns; A conformal deposition step of a second dielectric layer on the matrix of first pillars, the deposited thickness being chosen so as to fill the space between each first pillar and its nearest neighbors; An etching step of the second dielectric layer so as to expose the first dielectric layer between each first pillar of the first pillar matrix along the diagonals of said first pillar matrix; A step of depositing a first conductive layer so as to fill the openings made during the etching step of the second dielectric layer; a mechano-chemical polishing step of the structure obtained at the end of the previous step so as to obtain a matrix of second conductive pillars at the level of the openings made during the etching step of the second dielectric layer, the polishing being stopped on the support layer so that the second conductive pillars are no longer in contact with each other at the end of this step and form the third grids; A selective removal step of the second dielectric layer so as to retain on the first dielectric layer only the first pillar matrix and the second pillar matrix; A conformal deposition step of a third dielectric layer on the first pillar matrix and the second pillar matrix, the deposited thickness being chosen so as to fill the space between each first pillar and the nearest second pillars of said first pillar; An etching step of the third dielectric layer so as to expose the first dielectric layer between each first pillar of the first pillar matrix along the rows and columns of said first pillar matrix; A step of depositing a second conductive layer so as to fill the openings made during the etching step of the third dielectric layer; a mechano-chemical polishing step of the structure obtained at the end of the previous step, so as to obtain a matrix of conductive third pillars at the openings made during the etching step of the third dielectric layer, the polishing stopping at the support layer so that the conductive third pillars are no longer in contact between them at the end of this stage and form the first grids and the second grids; • A step of selectively removing the first pillars from the plurality of first pillars so as to expose the first dielectric layer at the location of said first pillars; • A selective etching step of the first dielectric layer and the active layer over their entire thickness at the location of said first pillars removed during the previous step so as to obtain a plurality of openings in the active layer.

[0023] Thanks to the method according to the invention, it is possible to obtain a device according to the invention by self-alignment using only a single lithography level. The method is thus greatly simplified compared to prior art methods in which several lithography levels (and therefore for which precise alignment is necessary) and / or partial screening of the grids are present.

[0024] In addition to the characteristics mentioned in the preceding paragraph, the method according to the second aspect of the invention may have one or more complementary characteristics from among the following, considered individually or according to all technically possible combinations.

[0025] In one embodiment, the substrate is a "silicon on insulator" type substrate and the active layer is made in the silicon layer of the substrate located above the oxide.

[0026] In one embodiment, the material of the first dielectric layer is chosen from SiO2, HfO2 or Al2O3.

[0027] In one embodiment, the material of the support layer is a dielectric material.

[0028] In one embodiment, the distance d separating two first neighboring pillars and the height h of the first pillars at the end of the step of etching the support layer so as to form a matrix of first pillars are chosen such that h> d / 2.

[0029] In one embodiment, the process includes, after the step of etching the second dielectric layer, a step of mechano-chemical polishing of the structure obtained after the previous step.

[0030] In one embodiment, the process includes, before the step of etching the third dielectric layer, a mechano-chemical polishing step of the structure obtained at the end of the previous step.

[0031] In one embodiment, the process includes, after the mechano-chemical polishing step of the structure obtained at the end of the step of deposition of a second conductive layer, a mechano-chemical over-polishing step of the structure obtained at the end of the previous mechano-chemical polishing step.

[0032] In one embodiment, the process comprises, after the step of selectively etching the first dielectric layer and the active layer, a step of depositing a fourth dielectric layer followed by a step of mechano-chemical polishing of said layer, the polishing being stopped on the second and third pillars.

[0033] The invention and its various applications will be better understood upon reading the following description and examining the accompanying figures. BRIEF DESCRIPTION OF THE FIGURES

[0034] The figures are presented by way of illustration and in no way limit the invention.

[0035] [Fig. 1] shows a schematic representation of a device according to the invention.

[0036] [Fig. 2A] to [Fig. 2C] show a schematic representation of different substrates that can be used in a device or method according to the invention.

[0037] Fig. 3 shows a schematic representation of an SOI-type substrate used in a process according to the invention and used in the illustrations of the different stages of the process.

[0038] Figures [Fig.4A] to [Fig.4K] show a schematic representation of the steps of the process according to the invention (the step or steps associated with each figure are noted in parentheses). DETAILED DESCRIPTION

[0039] Unless otherwise specified, the same element appearing on different figures has a unique reference.

[0040] Quantum device for forming a matrix of quantum dots

[0041] A first aspect of the invention, illustrated in [Fig. 1], relates to a quantum dot device (QD) configured to form an array of quantum dots (QDs). For this purpose, the QD comprises an active layer (CA) made of a semiconductor material. Preferably, this CA layer is a layer of silicon (Si) or germanium (Ge), but other semiconductor materials can be considered. The QDs are formed within this active layer (CA). As a reminder, a QD is formed by an electrostatic potential well in which it is possible to trap one or more charged particles, for example, one or more holes or one or more electrons.

[0042] The QD device according to the invention also comprises a plurality of first grids G1 arranged along a plurality of LI lines, above the active layer CA. The device according to the invention also comprises a plurality of second grids G2 arranged along a plurality of CO columns perpendicular to the LI lines of the plurality of LI lines, above the active layer CA. The DQ device according to the invention further comprises a plurality of third grids G3, each third grid G3 of the plurality of third grids G3 being arranged at the intersection of a a LI line of the plurality of LI lines and a CO column of the plurality of CO columns, above the active layer CA, each third grid G3 being separated from the nearest third grids G3, on an LI line by a first grid G1 and on a CO column by a second grid G2. Finally, in the DQ device according to the invention, the active layer CA comprises OR apertures throughout the thickness of the active layer CA, said apertures being arranged between the LI lines of the plurality of LI lines and the CO columns of the plurality of CO columns (thus the OR apertures also form a matrix shifted with respect to the matrix of quantum dots QD).

[0043] Thus, in the DQ device according to the invention, a quantum dot QD can be formed below each third grid G3 so as to form an array of quantum dots QD. Indeed, each first grid G1 of the plurality of first grids G1 allows, when an electrical potential is applied to it, the modification of the potential barrier separating two parts of the active layer CA located under two adjacent third grids G3 along the rows. Similarly, each second grid G2 of the plurality of second grids G2 allows, when an electrical potential is applied to it, the modification of the potential barrier separating two parts of the active layer CA located under two adjacent third grids G3 along the columns CO.Furthermore, the first grids G1 and the second grids G2 allow this modification to be performed locally, as the latter, Gl and G2, are above the active layer CA (in other words, there is no conductive layer between the oxide of the first grids Gl and the second grids G2 and the active layer CA). Also, thanks to the control of the potential barriers exerted by the first grids Gl and the second grids G2, it is possible to achieve electrostatic confinement of charged particles below the third grids G3 of the plurality of third grids G3 to form a quantum dot (QD) under each third grid G3. This electrostatic confinement is further complemented by structural confinement obtained thanks to the OR openings present in the active layer, since no charged particle can be located at said OR openings.

[0044] Furthermore, in each quantum dot QD, the charged particle or particles present are associated with a chemical potential. Now, since each third grid G3 is above the part of the active layer CA in which a quantum dot is formed (in other words, there is no conductive layer between the oxide of the third grids G3 and the active layer CA), each third grid G3 of the plurality of third grids G3 allows, when an electrical potential is applied to it, the chemical potential of the charged particles present in the quantum dot QD associated with the third grid G3 considered to be modified.

[0045] In one embodiment, the oxide of the first Gl, second G2 and / or third grids G3 is selected from SiO2, HfO2 or Al2O3. In one embodiment, the thickness of the oxide of the first grids Gl, second grids G2 and / or third grids G3 is between 5 nm and 10 nm. In one embodiment, the electrodes of the first grids Gl, second grids G2 and / or third grids G3 are made of a conductive material selected from Ti, TiN or W.

[0046] In one embodiment, the device according to the invention is made in a SOI-type substrate and the active layer is a silicon layer. In this embodiment, the first, second, and third gates Gl, G2, G3 are in direct contact with the active layer CA.

[0047] In an alternative embodiment, the device is made from a bulk silicon substrate. Advantageously, the substrate comprises an epitaxial silicon layer (denoted 28Si in the figure) coated with a thermal oxide (denoted SiO2 in the figure), this epitaxial silicon layer being deposited on the intrinsic silicon layer (denoted 'Si in the figure) of the bulk silicon substrate. Such a substrate is illustrated in [Fig. 2A]. In this embodiment, the active CA layer is formed within the silicon layer, advantageously the epitaxial silicon layer. The dimensions shown in the figure are, of course, given for illustrative purposes only.

[0048] In an alternative embodiment, the device is made from a Si / SiGe heterostructure. A substrate comprising such a heterostructure is illustrated in [Fig. 2B]. The latter comprises a layer whose Ge concentration varies linearly (denoted Sii_xGex in the figure) on which rests a SiGe layer (denoted Sio.7Geo.3), a quantum well for electrons formed in a Si layer (denoted 28Si in the figure), a SiGe spacer (denoted Si0.7Ge0.3 in the figure) located on the Si layer, and a silicon layer (denoted Si Cap in the figure). In this embodiment, the active layer is made in the Si layer. The dimensions shown in the figure are, of course, given for illustrative purposes only.

[0049] In an alternative embodiment, the device is made from a Ge / SiGe heterostructure. A substrate comprising such a heterostructure is illustrated in [Fig. 2C]. The latter comprises a layer whose Si concentration varies linearly (denoted Sii_xGex in the figure) on which rests a SiGe layer (denoted Sio.2Geo.8), a quantum well for holes formed in a Ge layer (denoted Ge in the figure), a SiGe spacer (denoted Si0.2Ge0.8 in the figure) located on the Ge layer, and a silicon layer (denoted Si Cap in the figure). In this embodiment of In its construction, the active layer is made within the Ge layer. The dimensions shown in the figure are, of course, given for illustrative purposes only.

[0050] Method for manufacturing a quantum device comprising an island matrix

[0051] A second aspect of the invention, illustrated in [Fig. 3] to [Fig. 4K], relates to a method for manufacturing a semiconductor device according to the invention from a substrate SB comprising a semiconductor layer, called the active layer CA, on a first surface of said substrate SB or near the first surface. "Near the first surface" means that the distance separating the active layer from the first surface is less than the distance separating the active layer from the second surface of the substrate opposite the first surface. Preferably, the distance separating the active layer CA from the first surface of the substrate SB is less than 500 nm, preferably less than 200 nm, or even less than 100 nm. In one embodiment, the thickness of the active layer CA is between 5 and 20 nm, for example, 10 nm.

[0052] In one embodiment, the active layer CA is made of silicon, the substrate preferably being a SOI (Silicon-On-Insulator) type substrate. In an alternative embodiment, the substrate is a SiMOS type substrate as described above. In an alternative embodiment, the substrate comprises a Si / SiGe heterostructure as described above at its first surface. In an alternative embodiment, the substrate comprises a Ge / SiGe heterostructure as described above at its first surface.

[0053] The process according to the invention comprises a step E1 of depositing a first dielectric layer DI onto the first surface. When the active layer CA is at the level of this first surface (as illustrated in [Fig. 3] to [Fig. 4K]), then this deposition is carried out on the active layer CA. In one embodiment, the material of the first dielectric layer DI is chosen from SiO2, HfO2, or Al2O3. In another embodiment, the first dielectric layer DI is made of a high-permittivity dielectric material. In another embodiment, the first dielectric layer DI comprises several dielectric sublayers. For example, it comprises a first sublayer of SiO2 ensuring good interface quality with the layer on which it is deposited (for example, the active layer of Si), and then a second sublayer of HfO2 or Al2O3. This is, of course, only an example, and other combinations can be considered.

[0054] The process then includes a step E2 of depositing a support layer SP on the first dielectric layer DI. In one embodiment, the material of the support layer SP is a dielectric material, for example silicon nitride.

[0055] As illustrated in [Fig. 4B], the process then comprises a step E3 of etching the support layer so as to form a matrix of first pillars PI forming a plurality of rows and a plurality of columns. Preferably, the distance d separating two adjacent first pillars PI and the height h of the first pillars PI are chosen such that h > d / 2. Preferably, the height h of the first pillars is between 50 nm and 500 nm, for example equal to 200 nm.

[0056] The process also includes a step E4 of conformal deposition of a second dielectric layer D2 onto the matrix of first pillars PI, the deposited thickness being chosen so as to fill the space between each first pillar PI and its nearest neighbors. In one embodiment, the dielectric layer D2 is made of SiO2. In another embodiment, the second dielectric layer D2 comprises several dielectric sublayers.

[0057] The process then comprises a step E5 of etching the second dielectric layer D2 so as to expose the first dielectric layer DI between each first pillar PI of the first pillar matrix PI along the diagonals of said first pillar matrix PI, the first dielectric layer DI serving as a stop layer for the etching. In one embodiment, the second dielectric layer D2 is a SiO2 layer and the first dielectric layer DI (serving as a stop layer) is an HfO2 or Al2O3 layer. The structure obtained after these two steps is illustrated in [Fig. 4C], the exposed areas of the first dielectric layer DI being marked by a dashed circle in the top-to-bottom representation of the figure.

[0058] In one embodiment, the process also includes a chemical-mechanical polishing step E6 of the structure obtained after the preceding step E5. Although optional, this step E6 flattens the surface of the structure and thus improves the quality of the conductive layer Cl deposition described below. Furthermore, performing the chemical-mechanical polishing in two steps avoids any selectivity issues with the chemical-mechanical polishing carried out after the conductive layer Cl deposition described below.

[0059] The process according to the invention then comprises a step E7 of depositing a first conductive layer Cl so as to fill the openings made during step E5 of etching the second dielectric layer D2. Thus, at these openings, the conductive layer Cl is in direct contact with the first dielectric layer DI. In one embodiment, the material of the conductive layer Cl is chosen from Ti, TiN or even W.

[0060] The process according to the invention further comprises a mechano-chemical polishing step E8 of the structure obtained at the end of the preceding step E7 so as to obtain a matrix of conductive PCI second pillars at the openings made During step E5, the etching of the second dielectric layer D2 occurs. In step E8, the polishing is stopped on the support layer SP, so that the second PCI pillars are no longer in contact with each other after this step E8. The structure obtained after these two or three steps (when the optional mechano-chemical polishing step E6 is implemented) is illustrated in [Fig. 4D]. In the final structure obtained after the process according to the invention, the second conductive PCI pillars will form the third grids G3 of [Fig. 1], allowing control of the chemical potential of the charged particles at the quantum dots QD.

[0061] As illustrated in [Fig. 4E], the process then includes a step E9 of selective removal of the second dielectric layer D2 so as to retain on the first dielectric layer (Dl) only the first pillar matrix PI and the second pillar matrix PCI. During this removal step, the first dielectric layer Dl is preserved and serves as a stop layer.

[0062] The process then includes a step E10 of conformal deposition of a third dielectric layer D3 on the matrix of first pillars PI and on the matrix of second pillars PCI, the deposited thickness being chosen so as to fill the space between each first pillar PI and the second pillars PC2 nearest neighbors of said first pillar PI.

[0063] The process also includes a step El 1 of etching the third dielectric layer D3 so as to expose the first dielectric layer Dl between each first pillar PI of the first pillar matrix PI along the rows and columns of said first pillar matrix PI. The structure obtained after these two steps is illustrated in [Fig. 4F], the exposed areas of the first dielectric layer Dl being marked by a dashed circle.

[0064] In one embodiment, the process includes a chemical-mechanical polishing step of the structure obtained after the preceding step E1 (not shown in the figures). Although optional, this step flattens the surface of the structure and thus improves the quality of the deposition of the conductive layer C2 described below. Furthermore, performing the chemical-mechanical polishing in two steps avoids any selectivity problems with the chemical-mechanical polishing carried out after the deposition of the conductive layer C2 described below.

[0065] As illustrated in [Fig. 4G], the process then includes a step E12 of depositing a second conductive layer C2 so as to fill the openings made during the step El 1 of etching the third dielectric layer D3. Thus, at the level of these openings, the second conductive layer C2 is in direct contact with the first dielectric layer DL. In one embodiment, the material of the second conductive layer C2 is chosen from Ti, TiN or even W.

[0066] The process then comprises a step E13 of mechano-chemical polishing of the structure obtained at the end of the previous step, so as to obtain a matrix of conductive third pillars PC2, said conductive third pillars PC2 being in direct contact with the first dielectric layer DI at the openings made during step E1 of etching the third dielectric layer D3. During this step E13, the polishing is stopped at the support layer SP so that the third pillars PC2 are no longer connected to each other at the end of this step E13. In one embodiment, in order to ensure the proper disconnection of the third pillars from each other, a step E14 of mechano-chemical over-polishing of the structure obtained at the end of step E13 is carried out. "Over-polishing" means continuing the polishing after the stop layer has been reached.Indeed, the detection of the arrest layer's contact by polishing is done automatically by physically detecting a polishing signal from the arrest layer. However, if there are non-uniformities in thickness across the wafer, the signal may be detected even though the arrest layer has not been contacted across the entire wafer, but only in a portion. "Over-polishing" therefore allows polishing to continue long enough after the signal has been detected so that all areas of the wafer are sufficiently polished. The structure obtained at the end of this step E13, or these two steps (when the optional over-polishing step E14 is implemented), is illustrated in [Fig. 4H]. In the final structure, the third conductive pillars PC2 will form the first grids G1 and the second grids G2 of [Fig. 1], allowing control of the potential barrier between two adjacent QD quantum dots.

[0067] As illustrated in [Fig.4I], the process then includes a step E15 of selective removal of the first pillars PI from the plurality of first pillars PI so as to expose the first dielectric layer DI at the location of said first pillars PL. When the material of the first pillars is a dielectric, for example SiN, this removal step can be carried out by a selective wet etching process, for example based on H3PO4.

[0068] As illustrated in [Fig.4J], the process also includes a step E16 of selective etching (with respect to the conductive materials of the conductive pillars PCI, PC2) of the first dielectric layer DI and a part of the substrate comprising the active layer CA over the entire thickness of the active layer CA at the location of the first pillars PI removed during the previous step E15 so as to form OU openings in the active layer CA.

[0069] When the substrate is of the SOI type, then the active Si layer is etched through its entire thickness during this step E16. When the substrate is of the SiMOS type, then the SiO2 layer and the Si layer (active layer) are etched through their entire thickness. During this step E16, when the substrate comprises a Si / SiGe heterostructure, the Si cap layer, the SiGe spacer, and the Si layer (CA active layer) are etched to their full thickness. When the substrate comprises a Ge / SiGe heterostructure, the Si cap layer, the SiGe spacer, and the Ge layer (CA active layer) are etched to their full thickness.

[0070] By removing the active CA layer (and the layers above it where necessary), it is ensured that charged particles cannot be located in this area, which facilitates their confinement within the quantum dots formed below the second conductive PCI pillars. In the final structure, the openings thus created correspond to the OU openings of [Fig. 1], ensuring the absence of charged particles between the LI rows and the CO columns.

[0071] In one embodiment, the process comprises a step E17 of depositing a fourth dielectric layer followed by a step El8 of mechano-chemical polishing of said layer, the polishing being stopped on the second and third pillars PCI, PC2. The structure obtained at the end of these two steps is illustrated in [Fig.4K].

[0072] As shown in [Fig. 1] and [Fig. 4K], in the arrangement thus obtained, the third grids G3 preferably exhibit central symmetry, and the distribution of the first grids G1 and second grids G2 adjacent to each third grid G3 follows this symmetry. Similarly, the first, second, and third grids G1, G2, G3 are preferentially distributed symmetrically with respect to the axis associated with each row LI and the axis associated with each column CO.

Claims

15 Demands

1. A method for manufacturing the quantum device from a substrate (SB) comprising a semiconductor layer, called the active layer (CA), on a first surface of said substrate (SB), the method comprising: A step (El) of deposition of a first dielectric layer (Dl) on the first surface; A step (E2) of depositing a support layer (SP) on the first dielectric layer (Dl); A step (E3) of etching the support layer (SP) so as to form a matrix of first pillars (PI) forming a plurality of rows and a plurality of columns; A conformal deposition step (E4) of a second dielectric layer (D2) on the matrix of first pillars (PI), the deposited thickness being chosen so as to fill the space between each first pillar (PI) and its nearest neighbors; A step (E5) of etching the second dielectric layer (D2) so as to expose the first dielectric layer (Dl) between each first pillar (PI) of the first pillar matrix (PI) along the diagonals of said first pillar matrix (PI); A step (E7) of depositing a first conductive layer (Cl) so as to fill the openings made during the step (E5) of etching the second dielectric layer (D2); a mechano-chemical polishing step (E8) of the structure obtained at the end of the previous step so as to obtain a matrix of second conducting pillars (PCI) at the openings made during the step (E5) of etching the second dielectric layer (D2), the polishing being stopped on the support layer (SP) so that the second conducting pillars (PCI) are no longer in contact with each other at the end of this step (E8) and form the third grids (G3); A step (E9) of selective removal of the second dielectric layer (D2) so as to retain on the first dielectric layer (Dl) only the matrix of first pillars (PI) and the matrix of second pillars (PCI); A step (E10) of conformal deposition of a third dielectric layer (D3) onto the first pillar matrix

2. (PI) and the second pillar matrix (PCI), the deposited thickness being chosen so as to fill the space between each first pillar (PI) and the second pillars (PC2) nearest neighbors of said first pillar (PI); - A step (El 1) of etching the third dielectric layer (D3) so as to expose the first dielectric layer (Dl) between each first pillar (PI) of the first pillar matrix (PI) according to the rows and columns of said first pillar matrix (PI); - A step (El2) of depositing a second conductive layer (C2) so as to fill the openings made during the step (El 1) of etching the third dielectric layer (D3); - a mechano-chemical polishing step (E13) of the structure obtained at the end of the previous step, so as to obtain a matrix of third pillars (PC2) conductive at the openings made during the step (El 1) of etching the third dielectric layer (D3), the polishing being stopped on the support layer (SP) so that the third pillars (PC2) conductive are no longer in contact with each other at the end of this step (E13) and form the first grids (G1) and the second grids (G2); - A step (El5) of selective removal of the first pillars (PI) of the plurality of first pillars (PI) so as to expose the first dielectric layer (Dl) at the location of said first pillars (PI); - A step (El6) of selective etching of the first dielectric layer (Dl) and of the active layer (CA) over their entire thickness at the location of said first pillars (PI) removed during the previous step (E15) so as to obtain a plurality of openings (OU) in the active layer (CA). A method according to the preceding claim in which the substrate (SB) is a "silicon on insulator" type substrate and the active layer (CA) is made in the silicon layer of the substrate (SB).

3. A method according to any one of the preceding claims wherein the material of the first dielectric layer (Dl) is chosen from SiO2, HfO2 or FA12O3.

4. A method according to any one of the preceding claims wherein the support layer (SP) material is a dielectric material.

5. A method according to any one of the preceding claims wherein the distance d separating two adjacent first pillars (PI) and the height h of the first pillars (PI) at the end of step (E3) of etching the support layer (SP) so as to form a matrix of first pillars (PI) are chosen such that h> d / 2.

6. A method according to any one of the preceding claims comprising, after the step (E5) of etching the second dielectric layer (D2), a step (E6) of mechano-chemical polishing of the structure obtained after the preceding step (E5).

7. A method according to any one of the preceding claims comprising, before the step (El 1) of etching the third dielectric layer (D3), a step (E12) of mechano-chemical polishing of the structure obtained at the end of the preceding step (El 1).

8. A method according to any one of the preceding claims comprising, after the step (E15) of mechano-chemical polishing of the structure obtained at the end of the step of deposition of a second conductive layer (C2), a step (E16) of mechano-chemical over-polishing of the structure obtained at the end of the preceding mechano-chemical polishing step (E15).

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