Electronic circuit comprising a cell of transistors

Abstract

Electronic circuit comprising a transistor cell The present description relates to an electronic circuit (40) comprising at least one transistor cell (402), each transistor cell comprising: - a plurality of transistors (430) arranged in and on a semiconductor substrate, each transistor comprising an active area (436); - first isolation regions (440) located at least partially around the transistors and extending to a first depth in the semiconductor substrate; - second isolation regions (442) positioned so as to isolate from each other the active areas (436) of all or part of the transistors of the plurality of transistors, the second isolation regions extending to a second depth in the semiconductor substrate, the second depth being greater than the first depth. Figure for abstract: Fig. 4A

Description

Title of the invention: Electronic circuit comprising a transistor cell Technical field

[0001] The present description relates generally to electronic circuits, and in particular to electronic circuits comprising one or more transistor cells, such as metal oxide semiconductor field effect transistors, or MOSFETs, from the English "Metal Oxide Semiconductor Field Effect Transistor". Prior art

[0002] An EEPROM memory is typically composed of a memory plane organized into rows and columns of memory words, each memory word comprising memory cells.

[0003] An EEPROM memory generally further comprises control circuits adapted to carry out operations, for example writing and / or reading, in the memory cells of the memory plane.

[0004] An EEPROM memory cell typically comprises a transistor cell including a state transistor having a floating gate surmounted by a control gate, and a selection transistor connected in series with the state transistor to be able to transmit a voltage to it, for example transmit a voltage to the drain region of said state transistor.

[0005] An EEPROM memory generally further comprises circuits for switching the control gates of the state transistors. A switching circuit generally comprises one or more switching transistor cells. A switching transistor is adapted to transmit a voltage to the control gate of the state transistor of a memory cell, and may be designated by the term "CG Switch", for "control gate switch" in English. For example, a switching circuit is provided for each memory word. The switching circuits may be integrated in the memory plane, for example between memory words.

[0006] Typically, a memory cell write comprises an erasure followed by a programming. During erasure, a high positive erasure voltage is applied to the control gate of the state transistor and a substantially zero voltage is applied to the drain region of the state transistor, so as to inject by Fowler-Nordheim effect an electron charge from the drain region to the floating gate. The source region of the state transistor is, for example, grounded. During programming, a high positive programming voltage is applied to the drain region of the state transistor, for example through the transistor selection, and a substantially zero voltage is applied to the control gate, so as to extract by Fowler-Nordheim effect the electron charge potentially stored in the floating gate.

[0007] The high programming voltage applied to the drain region via the selection transistor, and / or the high erasure voltage applied to the control gate via the switching transistor, is, for example, between approximately 10 and 20 V, for example of the order of 13 V, or of the order of 15 V. Thus, the switching transistor and the selection transistor must be sufficiently robust to transmit this high voltage, which may be a cause of the bulkiness of the memory cells and / or the switching circuits.

[0008] However, an objective in the field of EEPROM memories may be on the contrary to reduce the surface area of ​​the memory cells. However, there is generally a limit in the reduction of the surface area of ​​the memory cells, in particular in the reduction of the surfaces of the transistors of the memory cells, especially with the high voltages applied.

[0009] In EEPROM memories, smaller memory cells, for example comprising more compact high-voltage transistors, can make the driving circuits, in particular the switching circuits, more complex, and increase their surface areas, which can cancel out the benefit of the reduction in size of the memory cells. For example, so-called shared voltage techniques, using a combination of positive and negative potentials to generate programming voltages, allow a shrinking of the memory cells at the expense of more complex switching circuits, such as inverters, which consequently require wells with complementary doping, which increases the surface area occupied by these circuits.

[0010] There is a need to address the area overhead to achieve a real advantage in reducing the overall size and cost of EEPROM memories, without degrading other performance. Summary of the invention

[0011] More generally, there is a need to reduce the surface area of ​​transistor cells, in particular for transistor cells intended to operate at high voltages.

[0012] Embodiments of the present description relate in particular to transistor cells of which at least certain transistors are adapted to operate at a high voltage, typically greater than or equal to 10 volts, or even greater than or equal to 15 volts, and of which at least certain high voltage transistors can be positioned at a short distance from each other, typically less than 1 μm.

[0013] Embodiments of the present disclosure also relate to non-volatile memories ("NVM", for "Non Volatile Memory" in English), such as electrically erasable and programmable non-volatile memories, known by the acronym "EEPROM" from the English "Electrically Erasable and Programmable Read Only Memory", comprising several transistor cells, for example produced on an integrated circuit.

[0014] One embodiment overcomes all or part of the drawbacks of known transistor cells.

[0015] One embodiment provides an electronic circuit comprising at least one transistor cell, each transistor cell comprising: - a plurality of transistors arranged in and on a semiconductor substrate, each transistor comprising an active area; - first isolation regions located at least partially around the transistors and extending to a first depth in the semiconductor substrate; - second isolation regions positioned so as to isolate from each other the active zones of all or part of the transistors of the plurality of transistors, the second isolation regions extending to a second depth in the semiconductor substrate, the second depth being greater than the first depth.

[0016] According to one embodiment, each transistor cell comprises first transistors among the plurality of transistors having active areas separated by a first distance and isolated from each other by at least one of the first isolation regions, and second transistors among the plurality of transistors having active areas separated by a second distance less than the first distance and isolated from each other by at least one of the second isolation regions.

[0017] According to one embodiment, the first distance is greater than or equal to 400 nm and / or the second distance is less than 350 nm.

[0018] According to one embodiment, the first isolation regions are first isolation trenches, for example shallow isolation trenches, and the second isolation regions are second isolation trenches, for example deep isolation trenches.

[0019] According to one embodiment, the second insulation regions extend in a first direction substantially parallel to the longitudinal direction of the active zones.

[0020] According to one embodiment, the electronic circuit further comprises third isolation regions positioned so as to isolate the active areas of the plurality of transistors from other transistor cells, the third isolation regions extending to a third depth in the semiconductor substrate, the third depth being greater than the first depth, e.g. example substantially equal to the second depth, the third isolation regions being, for example, deep isolation trenches.

[0021] According to one embodiment, the third isolation regions extend in a second direction substantially parallel to the transverse direction of the active zones.

[0022] According to one embodiment, at least some of the first and second isolation regions surround the active areas of all or part of the transistors of the plurality of transistors.

[0023] According to one embodiment, the transistors of the plurality of transistors are intended to operate at voltages greater than or equal to 10 volts, for example greater than or equal to 15 volts.

[0024] According to one embodiment, the transistor cell further comprises a gate structure, for example of the double gate type, extending above the active areas of the plurality of transistors, between a source region and a drain region of each active area.

[0025] According to one embodiment, the transistors of the plurality of transistors are P-channel MOS transistors and / or N-channel MOS transistors.

[0026] According to one embodiment, the electronic circuit is included in a non-volatile memory, for example an electrically erasable and programmable non-volatile memory.

[0027] According to one embodiment, the transistors of the plurality of transistors form switching transistors of a switching circuit coupled to memory cells of a non-volatile memory, for example of an electrically erasable and programmable non-volatile memory.

[0028] One embodiment provides a method of manufacturing an electronic circuit comprising at least one transistor cell, each transistor cell comprising a plurality of transistors formed in and on a semiconductor substrate, each transistor comprising an active area, the method comprising: - the formation of first isolation regions located at least partially around the transistors and extending to a first depth in the semiconductor substrate; and - the formation of second isolation regions positioned so as to isolate from each other the active zones of all or part of the transistors of the plurality of transistors, the second isolation regions extending to a second depth in the semiconductor substrate, the second depth being greater than the first depth.

[0029] According to one embodiment, the method further comprises: - forming third isolation regions positioned to isolate the active areas of the plurality of transistors from other transistor cells, the third isolation regions extending to a third depth in the semiconductor substrate, the third depth being greater than the first depth, for example substantially equal to the second depth.

[0030] The following embodiments may be applied to an electronic circuit or manufacturing method.

[0031] According to one embodiment, the first depth is between 250 and 450 nm, for example between 300 and 400 nm, and the difference between the third depth and the first depth is greater than or equal to 100 nm, for example between 100 and 200 nm.

[0032] According to one embodiment, the first depth is between 250 and 450 nm, for example between 300 and 400 nm, and the difference between the second depth and the first depth is greater than or equal to 100 nm, for example between 100 and 200 nm.

[0033] One embodiment provides an integrated circuit comprising any of the electronic circuits described above. Brief description of the drawings

[0034] These characteristics and advantages, as well as others, will be explained in detail in the following description of particular embodiments given without limitation in relation to the attached figures among which:

[0035] [Fig.l] is a simplified electrical diagram representing a detail of a memory plane of an EEPROM memory;

[0036] [Fig.2] represents, in a top view, a detail of a memory plane of an EEPROM memory;

[0037] [Fig.3A] represents, in a top view, an electronic circuit comprising a cell of switching transistors coupled with memory cells, corresponding to a portion of a memory plane of an EEPROM memory;

[0038] [Fig.3B] represents, by a sectional view, the electronic circuit of [Fig.3A];

[0039] [Fig.4A] represents, by a top view, an electronic circuit according to a mode embodiment comprising a cell of switching transistors coupled with memory cells, corresponding to a portion of a memory plane of an EEPROM memory;

[0040] [Fig.4B] represents, by a sectional view AA, the electronic circuit of [Fig.4A];

[0041] [Fig.4C] represents, by a sectional view BB, the electronic circuit of [Fig.4A];

[0042] [Fig.5] illustrates curves representing a junction leakage current of a transistor as a function of an applied drain voltage, and this for several examples of transistor cells; and

[0043] [Fig.6A], [Fig.6B], [Fig.6C], [Fig.6D] and [Fig.6E] are sectional views partially and schematically illustrating structures obtained following successive steps of a simplified example of a method for manufacturing isolation trenches of a transistor cell of an electronic circuit according to one embodiment. Description of the embodiments

[0044] The same elements have been designated by the same references in the different figures. In particular, the structural and / or functional elements common to the different embodiments may have the same references and may have identical structural, dimensional and material properties.

[0045] For the sake of clarity, only the steps and elements useful for understanding the described embodiments have been shown and are detailed. In particular, the steps for manufacturing the transistor cells have not been described, being achievable with the usual microelectronics methods. Similarly, all the details of the transistor cells, the transistors, as well as the memories, have not been described, being within the reach of the person skilled in the art in the field of microelectronics. Furthermore, not all the applications that the described electronic circuits may have have been given.

[0046] Unless otherwise specified, when referring to two elements connected to each other, this means directly connected without intermediate elements other than conductors, and when referring to two elements connected (in English "coupled") to each other, this means that these two elements can be connected or be connected by means of one or more other elements.

[0047] In the following description, when reference is made to absolute position qualifiers, such as the terms "front", "back", "top", "bottom", "left", "right", etc., or relative position qualifiers, such as the terms "above", "below", "upper", "lower", etc., or to orientation qualifiers, such as the terms "horizontal", "vertical", etc., reference is made unless otherwise specified to the orientation of the figures.

[0048] Unless otherwise specified, the expressions "about", "approximately", "substantially", and "of the order of" mean to within 10%, preferably to within 5%.

[0049] When referring to an "active region", reference is made to a semiconductor region of a transistor, for example delimited by isolation regions. An active region typically comprises a source region, a drain region and a channel forming region, or channel region, between the source region and the drain region. The active region may be formed in a semiconductor substrate or in a well formed in a semiconductor substrate.

[0050] When referring to a "transistor cell", reference is made to a set of several transistors formed in and on the same semiconductor substrate.

[0051] In the following description, a length (for example of a transistor cell, of a transistor, or of a transistor active zone) corresponds to a dimension in a first direction, corresponding to the X direction identified in the figures, of a main plane XY. The main plane generally corresponds to the main plane of a semiconductor substrate in and on which the transistor is formed. The first direction is parallel to the conduction direction of the transistor. Thus, a channel length of the transistor corresponds substantially to the distance between a source region and a drain region of the transistor. A width (for example of a transistor cell, of a transistor, or of a transistor active zone) corresponds to a dimension in a second direction of the main plane, orthogonal to the X direction, corresponding to the Y direction identified in the figures.A thickness or depth corresponds to a dimension in the direction perpendicular to the principal plane, for example a vertical direction, corresponding to the Z direction marked in the figures. The term "longitudinal" or "lateral" refers to the direction of the transistor length (X direction), and the term "transverse" refers to the direction of the transistor width (Y direction).

[0052] In the following description, a MOSFET may be referred to as a MOS transistor. An NMOS transistor is an N-channel MOS transistor, i.e., a transistor whose source and drain regions are N-type doped. A PMOS transistor is a P-channel MOS transistor, i.e., a transistor whose source and drain regions are P-type doped.

[0053] [Fig.l] is a simplified electrical diagram representing a detail of a memory plane 10 of an EEPROM memory.

[0054] [Fig.l] represents an intersection between a column COL; and two rows RGj, RGj i of the memory plane 10. In the following, the indices "i" in the references will indicate membership in the respective column COL;, and the indices "j" in the references will indicate membership in the respective row RGj.

[0055] A memory word MWij, MWij i is located at the intersection of a column COL; and a row RGj, RGj i.

[0056] Each memory word MWij comprises several memory cells 101 (CEU j bCEL ij i ... CELij k), each comprising a state transistor 110 and a selection transistor 120.

[0057] The state transistor 110 is adapted to store binary data and in this respect comprises a gate structure comprising a floating gate 112 surmounted by a control gate 114, the gate structure being between a source region and a drain region of the state transistor. The state transistor 120 comprises a gate structure 122 between a source region and a drain region.

[0058] The state and selection transistors are, for example, NMOS type transistors.

[0059] Each memory cell CELlj k is coupled to a dedicated and individual bit line BLk. For example, the bit line extends in the direction of the columns of the memory plane.

[0060] Each memory cell CELlj k is coupled to a word line WLj which may be common for all the cells of the same row RGj. For example, the word line extends in the direction of the rows of the memory plane.

[0061] The memory cells CEL1 | k of the same memory word MWLJ can be coupled to the same source line SL, which can be common to other memory words.

[0062] The state transistor 110 and the selection transistor 120 of a memory cell 101 are connected in series, the drain region of the state transistor 110 being, for example, coupled to the source region of the selection transistor 120. For example, the drain region of the selection transistor 120 is coupled to the bit line BLk of the memory cell CELijjk, while the source region of the state transistor 110 is coupled to the source line SL, and the gate structure 122 of the selection transistor 120 is coupled to the word line WLj of its row RGj.

[0063] The memory cells CELijjk, CELij.i,k of the same memory word MWij, MWij i are coupled to a common control gate line CGij, CGLJ ।, adapted to send a signal to the control gates 114 of the state transistors 110 of these memory cells. For example, each control gate line CG^ is exclusively dedicated to a memory word MWij of a column COL; and of a row RGj.

[0064] Access to the control gate line CGij in the memory plane 10 is made by means of a control gate switching circuit 102 (CGSWjj) located in a region CGSW of the memory plane 10, preferably near the associated memory word MWij. For example, the control gate line CG^ carries a signal from the switching circuit 102 to the control gates 114 of the state transistors 110 of the memory cells 101 of the associated memory word MW^.

[0065] Each switching circuit 102 may comprise one (or more) inverter circuit(s) each comprising a PMOS transistor 130 in series with an NMOS transistor 140, controlled by a control signal on their gates.

[0066] [Fig.2] represents, in a top view, a detail of a memory plane 20 of an EEPROM memory.

[0067] For example, the X direction shown corresponds to the direction of the rows of the memory plane, and the Y direction shown corresponds to the direction of the columns of the memory plane.

[0068] [Fig.2] represents a detail of the memory plane 20, this detail making it possible to schematically visualize a memory word 21, comprising four memory cells 201, associated with a switching circuit 202 of control gates. Each cell memory 201 comprises a state transistor 210 whose active area 216 can be continuous with the active areas of other state transistors in the X direction, in series with a selection transistor 220 whose active area 226 can be continuous with the active areas of other selection transistors in the X direction.

[0069] In the switching circuit 202, several switching transistors 230 are shown, organized in columns, each column comprising several switching transistors, for example PMOS type transistors, i.e. MOSFET transistors whose source and drain regions are P-type doped. Each column of the switching circuit 202 comprises a gate structure comprising a first gate 232 surmounted by a second gate 234, for example longer (in the X direction) and narrower (in the Y direction) than the first gate 232. The first and second gates are preferably connected to each other. The gate structure 232, 234 is common to the transistors of the same column, and delimits a drain region D and a source region S in an active zone 236 of each transistor 230 of the column.

[0070] A switching transistor 230 is isolated from the other switching transistors and from the memory cell 201 by shallow isolation regions 240, for example shallow trench isolation, or "STI" for "Shallow Trench Isolation".

[0071] Although not shown, the switching circuit may include NMOS type transistors in series with PMOS type transistors, to form inverter circuits.

[0072] A switching transistor 230 (or an inverter circuit) is, for example, dedicated to one or more cells 201 of the memory plane 21, or to one or more cells of other memory planes (not shown in [Fig.2]). The memory word 21 could comprise fewer, or more, than four memory cells 201, for example six or eight memory cells 201.

[0073] [Fig.3A] represents, in a top view, an electronic circuit 30 comprising a cell of switching transistors coupled with memory cells, corresponding to a portion of a memory plane of an EEPROM memory. [Fig.3B] represents, in a sectional view along plane AA, the electronic circuit of [Fig.3A].

[0074] The memory plane of Figures 3A and 3B is for example similar to the memory plane 20 of [Fig.2], in more detail. Three memory cells, a switching transistor and partially another switching transistor are shown, although the switching circuit comprises more than two switching transistors, and the memory plane comprises more than three memory cells.

[0075] Each memory cell 301 comprises a state transistor 310 and a selection transistor 320 in series with the state transistor. The state and selection transistors are, for example, NMOS type transistors, i.e. MOS transistors whose source and drain regions are N-type doped. The state transistors 310 and selection transistors 320 are formed in and on a semiconductor substrate 304, for example of the P type, with a deep well 306, for example of the N type, formed in the semiconductor substrate, under each memory cell 301 and between each memory cell 301 and the switching transistor 330 described below.

[0076] The state transistor 310 comprises an active area 316 formed in the semiconductor substrate 304 as well as a gate structure surmounting the active area 316 and comprising a floating gate 312 surmounted by a control gate 314, the gate structure 312, 314 being between a first source region SI and a first drain region DI of the active area 316. This gate structure is common to several state transistors in the Y direction.

[0077] The floating gate 312 is, for example, electrically insulated from the control gate 314 by an inter-gate dielectric layer 313, and from the semiconductor substrate 304 by a dielectric layer 311, for example made of silicon dioxide (SiO2). The control gate 314 is, for example, coupled with the switching transistor 330 described below.

[0078] The selection transistor 320 comprises an active area 326 formed in the semiconductor substrate 304, as well as a gate structure 322, 324 overlying the active area 326, the gate structure 322, 324 being between a second source region S2 and a second drain region D2 of the active area 326. This gate structure is common to several selection transistors in the Y direction.

[0079] For example, for reasons of simplification of the manufacturing process of the memory cell, the gate structure of the selection transistor can be of the double gate type, as shown in [Fig.3B], the two gates being connected together so as to form only one gate.

[0080] The first drain region DI of the state transistor 310 is coupled to the second source region S2 of the selection transistor 320.

[0081] In the example shown in Figures 3A and 3B, each switching transistor 330 is positioned on the same semiconductor substrate 304 as the state transistor 310 and the selection transistor 320 of each memory cell 301. Unlike the memory cell 301, there is no deep well formed in the semiconductor substrate under the switching transistor 330.

[0082] The switching transistor 330 shown is an NMOS type transistor, i.e. a transistor whose source and drain regions are N-type doped.

[0083] The switching transistor 330 includes an active area 336 formed in the semiconductor substrate 304 and a gate structure 332, 334, similar to the gate structure 232, 234 of [Fig. 2], overlying the active area 336, the gate structure gate 332, 334 being between a third source region S3 and a third drain region D3 of the active area 336. This gate structure is common to several switching transistors in the Y direction.

[0084] For example, for reasons of simplification of the manufacturing process, the gate structure of the switching transistor may be of the double gate type, as shown in [Fig.3B], the two gates being connected together so as to form only one gate.

[0085] The switching transistor 330 is isolated from the other switching transistors of the switching circuit 302 and from the memory cells 301 by shallow isolation regions 340, for example STIs. The memory cells 301 are also isolated from each other by shallow isolation regions 340, for example STIs.

[0086] As can be seen from the figures described above, the control gate switching circuits occupy a significant area in a memory plane.

[0087] One way to reduce the area occupied by the control gate switching circuits could be to reduce the width W of the active area 236, 336 of the switching transistor 230, 330, but this may have the consequence of reducing the breakdown voltage of the transistor, which may be incompatible with high operating voltages.

[0088] Another way could be to reduce the SP spacing between two adjacent switching transistors in the Y direction, but this may result in increasing the leakage current between the transistors.

[0089] The inventors propose a transistor cell making it possible to meet the improvement needs described above, and to overcome all or part of the drawbacks of transistor cells, such as the switching transistor cells and / or the memory cells described above. In particular, the inventors propose a transistor cell with reduced bulk.

[0090] Embodiments of transistor cells will be described below. The embodiments described are non-limiting and various variants will become apparent to those skilled in the art from the indications of the present description.

[0091] In particular, in the embodiments described below, a transistor cell is included in an EEPROM type memory, for example in a memory plane. A transistor cell may compose all or part of a switching circuit and / or a memory cell of an EEPROM type memory. However, this application is not limiting, and a transistor cell could compose or be included, for example, in a FLASH memory of the NOR and NAND flash type, or in a split-gate type memory.

[0092] [Fig.4A] represents, in a top view, an electronic circuit 40 according to a embodiment comprising a cell of switching transistors coupled with memory cells 401, corresponding to a portion of a memory plane of an EEPROM memory. [Fig.4B] represents, by a sectional view along plane AA, the electronic circuit of [Fig.4A]. [Fig.4C] represents, by a sectional view along plane BB, the electronic circuit of [Fig.4A].

[0093] Similar to Figures 3A and 3B, Figures 4A, 4B and 4C show memory cells 401 associated with switching transistors 430 of a switching circuit 402. Figures 4A, 4B and 4C show three memory cells, although the memory plane comprises more than three memory cells. The switching circuit 402 comprises several switching transistors, although not all of them are shown in Figures 4A, 4B and 4C.

[0094] Each memory cell 401 comprises a state transistor 410 and a selection transistor 420 in series with the state transistor. The state and selection transistors are, for example, NMOS type transistors, i.e. transistors whose source and drain regions are N-type doped. The state and selection transistors are, for example, formed in and on a semiconductor substrate 404, for example of the P type. A deep well 406, for example of the N type, is formed in the semiconductor substrate, under each memory cell 401 and between each memory cell 401 and the switching transistors 430 described below.

[0095] The state transistor 410 comprises an active area 416 formed in the semiconductor substrate 404, as well as a gate structure surmounting the active area 416 and comprising a floating gate 412 surmounted by a control gate 414, the gate structure 412, 414 being between a first source region SI and a first drain region DI of the active area 416 of the state transistor. This gate structure is common to several state transistors in the Y direction. The active area 416 may be continuous with active areas of other state transistors in the X direction.

[0096] The floating gate 412 is electrically insulated from the control gate 414 by an inter-gate dielectric layer 413, for example a multilayer called "ONO" for oxide-nitride-oxide, and from the semiconductor substrate 404 by a dielectric layer 411, for example made of silicon dioxide (SiO2). The floating gate 412 can store electric charges in a non-volatile manner. The injection of charges into the floating gate 412 is obtained by Fowler-Nordheim effect through the dielectric layer 411. The control gate 414 is coupled with the switching circuit 402, for example, with one of the switching transistors 430.

[0097] The selection transistor 420 comprises an active area 426 formed in the semiconductor substrate 404 as well as a gate structure 422, 424 surmounting the active area 426, the gate structure 422, 424 being between a second source region S2 and a second drain region D2 of the active area 426. This gate structure is common to several selection transistors in the Y direction. The active area 426 may be continuous with active areas of other selection transistors in the X direction.

[0098] For example, for reasons of simplification of the manufacturing method of the memory cell, the gate structure of the selection transistor may be of the double gate type, as shown in [Fig.4B], the two gates preferably being connected together so as to form only one gate. Alternatively, the gate structure of the selection transistor may be single gate.

[0099] The first drain region DI of the state transistor 410 is coupled to the second source region S2 of the selection transistor 420.

[0100] In the example shown in Figures 4A, 4B and 4C, each switching transistor 430 is positioned on the same semiconductor substrate 404 as the state transistor 410 and the selection transistor 420 of each memory cell 401. Unlike the memory cell 401, there is no deep well formed in the semiconductor substrate under the switching transistors 430.

[0101] Each switching transistor 430 is, for example, an NMOS type transistor, i.e. a transistor whose source and drain regions are N-type doped. Alternatively, each switching transistor could be a PMOS type transistor, i.e. a transistor whose source and drain regions are P-type doped. The switching circuit 402 may also comprise several inverter circuits each comprising a PMOS transistor in series with an NMOS transistor.

[0102] The switching transistor 430 comprises an active area 436 formed in the semiconductor substrate 404, as well as a gate structure 432, 434 overlying the active area 436, the gate structure 432, 434 being between a third source region S3 and a third drain region D3 of the active area 436. The gate structure of the switching transistor may be of the double-gate type, as shown in [Fig.4B], the two gates preferably being connected together so as to form only one gate. Alternatively, the gate structure of the switching transistor may be a single-gate. This gate structure is common to several switching transistors in the Y direction. The active area 436 may be continuous with active areas of other switching transistors in the X direction.

[0103] In the semiconductor substrate 404, first isolation regions 440 are formed, which are, in the example shown, shallow isolation trenches. These first isolation regions 440 make it possible in particular to isolate each switching transistor 430 from other switching transistors of the switching circuit 402 as well as from the memory cells 401, and to isolate all or part of the memory cells 401 from each other. The first isolation regions 440 extend to a first PI depth in the semiconductor substrate 404.

[0104] The memory plane 40 of FIGS. 4A, 4B and 4C is distinguished from the memory plane 30 of FIGS. 3A and 3B, in that, between the active areas 436 of the switching transistors 430 adjacent in the Y direction, second isolation regions 442 are formed (visible in FIGS. 4A and 4C), deeper than the first isolation regions 440. In other words, the second isolation regions 442 extend to a second depth P2 in the semiconductor substrate 404, the second depth P2 being greater than the first depth P1.

[0105] These second isolation regions 442 make it possible to further isolate the active zones 436 of the switching transistors 430 from each other. In the example shown, the second isolation regions 442 are deep isolation trenches.

[0106] For example, the first isolation regions 440 have a depth PI of between 250 and 450 nm, or even between 300 and 400 nm, for example equal to approximately 400 nm, and the difference between the second depth P2 and the first depth PI is greater than or equal to 100 nm, for example between 100 and 200 nm. For example, the second isolation regions have a depth of between 500 and 600 nm.

[0107] These second isolation regions 442 make it possible to reduce the spacing SP between the active zones 436 of the adjacent switching transistors 430, without increasing the leakage current between these transistors, or even by reducing this leakage current, as can be seen in [Fig.5] described later. Indeed, having deeper isolation regions located between the active zones of the switching transistors makes it possible to limit the passage of charge carriers from one active zone to another.

[0108] Depending on the distance between the active areas of adjacent transistors, and, for example, also depending on the operating voltage, it may be chosen to form between said active areas either one of the first isolation regions or one of the second isolation regions. Thus, a cell of transistors may comprise at least two adjacent first transistors having active areas separated by a first distance and isolated from each other by at least one of the first isolation regions, and adjacent second transistors having active areas separated by a second distance less than the first distance and isolated from each other by at least one of the second isolation regions. The first distance is, for example, greater than or equal to 400 nm and the second distance is, for example, less than 350 nm.

[0109] The inventors determined that the presence of the second isolation regions could make it possible to reduce the distance between two adjacent active areas, up to approximately 30%, without increasing the leakage current, and thus could make it possible to reduce the width (dimension in the Y direction) of the switching circuit.

[0110] Furthermore, targeting the location of these second isolation regions makes it possible not to increase the depth of all the isolation regions, in particular the first isolation regions, which are formed in the semiconductor substrate. For example, this makes it possible to avoid impacting the operation of other electronic components of the electronic circuit, for example other transistors, or even to call into question the entire design strategy of an electronic circuit. On the contrary, the embodiments propose to locate the second isolation regions only between the active zones of the transistors whose isolation is to be reinforced, or even around these active zones.

[0111] As shown in Figures 4A and 4B, third isolation regions 444, also deeper than the first isolation regions 440, may be formed in the semiconductor substrate 404 between the switching transistors 430 and the memory cells 401, for example near the active areas 436 of the switching transistors. The third isolation regions 444 extend to a third depth P3 in the semiconductor substrate 404, the third depth P3 being greater than the first depth P1, for example substantially equal to the second depth P2. These third isolation regions 444 are not mandatory, but they may be advantageous, for example if it is desired to reinforce the isolation between the switching transistors and the memory cells, for example between the switching transistors and the memory cell selection transistors.

[0112] For example, the first isolation regions 440 have a depth PI of between 250 and 450 nm, or even between 300 and 400 nm, for example equal to approximately 400 nm, and the difference between the third depth P3 and the first depth PI is greater than or equal to 100 nm, for example between 100 and 200 nm. For example, the third isolation regions have a depth of between 500 and 600 nm.

[0113] In the example shown, the third isolation regions 444 are deep isolation trenches.

[0114] For example, the active areas of all or part of the switching transistors may be surrounded by second and / or third isolation regions, for example by deep isolation trenches.

[0115] More generally, the active areas of all or part of the transistors of a transistor cell according to one embodiment may be partially or entirely surrounded by second and / or third insulation regions.

[0116] The second isolation regions, and the optional third isolation regions, are described in relation to switching transistors forming a transistor cell, but this could apply to other transistor cells of a memory plane, for example to memory cells of the memory plane, or to a set memory cells-switching circuit, for example to isolate switching transistors from memory cell transistors.

[0117] More broadly, the presence of the second isolation regions, and optionally of the third isolation regions, between the active zones of all or part of the transistors of a transistor cell can make it possible to reduce the dimensions of this cell, without increasing the leakage current.

[0118] [Fig.5] illustrates curves representing a junction leakage current (leakage under STI), as a function of an applied drain voltage, and this, for several transistor cells. In other words, the curves represent current leakage measurements between two active zones isolated by an STI, all in the same semiconductor substrate, in the example a P-type substrate.

[0119] Curve 501 corresponds to a cell of switching transistors spaced 0.2 pm apart, with only first isolation regions. Curve 502 corresponds to a cell of switching transistors spaced 0.5 pm apart, with only first isolation regions. It can be seen that reducing the spacing SP between the active areas of transistors which are isolated only by first isolation regions increases the leakage current, which means that we can be in a strong leakage current operation (STRONG LEAKAGE).

[0120] Curve 503 corresponds to a cell of switching transistors spaced 0.2 pm apart, with first and second isolation regions, according to one embodiment. It can be seen that adding second isolation regions makes it possible to reduce the leakage current, so as to be in a low leakage current operation (LOW LEAKAGE), even when the spacing SP between the active zones of the transistors is smaller.

[0121] [Fig.6A], [Fig.6B], [Fig.6C], [Fig.6D] and [Fig.6E] represent structures obtained following steps of a simplified example of a method for forming isolation trenches of a transistor cell of an electronic circuit according to one embodiment.

[0122] [Fig.6A] represents a starting structure comprising first isolation trenches 640, of a first depth PI, formed in a semiconductor layer 604 (semiconductor substrate). In addition, an etch stop layer 651, for example a silicon nitride layer, is positioned on the semiconductor layer 604, the first isolation trenches 640 passing through this etch stop layer. A resin layer 652 is positioned on the etch stop layer 651, said resin layer comprising openings 652A corresponding to the positioning of the future second isolation trenches.

[0123] In Figures 6A to 6E, the semiconductor layer 604 is for example a silicon (Si) layer, for example a silicon layer of an SOI type stack, for "Silicon on insulator" in English.

[0124] [Fig.6B] represents a structure obtained at the end of the etching of the semiconducting layer 604 through the openings 652A of the resin layer 652, and this, over a second depth P2, greater than the first depth PI, so as to form second trenches 653 deeper than the first insulation trenches 640.

[0125] [Fig.6C] represents a structure obtained after the deposition of a dielectric layer 654, for example a silicon oxide such as SiO2, on the structure of [Fig.6B]. The dielectric material fills the second trenches 653 so as to form second isolation trenches 642, and overflows above the semiconductor layer 604 and the isolation trenches.

[0126] [Fig.6D] represents a structure obtained at the end of a planarization step, for example by chemical-mechanical polishing, known by the English acronym "CMP" (Chemical Mechanical Polishing), so as to remove the dielectric material which overflows above the semiconductor layer and the insulation trenches.

[0127] [Fig.6E] represents a structure obtained at the end of a step of removing the etching stop layer 651, for example by etching.

[0128] The fabrication of second isolation trenches has been described, knowing that the third isolation trenches can be fabricated similarly to the second isolation trenches, by etching third trenches to a third depth P3.

[0129] As a variant of the described manufacturing method example, the second isolation trenches, and / or the third isolation trenches, can be formed from certain first isolation trenches which will then be etched more deeply.

[0130] These examples of manufacturing method show that it is possible to produce second and / or third isolation regions, for example second and / or third isolation trenches, next to the first isolation regions, for example next to the first isolation trenches, in the same semiconductor substrate.

[0131] Various embodiments and variations have been described. Those skilled in the art will understand that certain features of these various embodiments and variations could be combined, and other variations will occur to those skilled in the art. In particular, the embodiments have been described in relation to an EEPROM memory. More generally, the embodiments may be applied to electronic circuits, or integrated circuits, comprising transistor cells. In particular, the embodiments may be applied to transistor cells intended to receive a high voltage, typically greater than 10 V, for example. example equal to approximately 13 V, or even greater than or equal to 15 V, in particular when the aim is to bring two adjacent transistors intended to operate at these high voltages closer together. For example, the embodiments can be applied to a FLASH memory of the NOR and NAND flash type, or in a split-gate type memory.

[0132] Finally, the practical implementation of the embodiments and variants described is within the reach of those skilled in the art from the functional indications given above.

Claims

Claims

1. An electronic circuit (40) comprising at least one transistor cell (402), each transistor cell comprising: - a plurality of transistors (430) arranged in and on a semiconductor substrate (404), each transistor comprising an active area (436); - first isolation regions (440) located at least partially around the transistors and extending to a first depth (PI) in the semiconductor substrate (404); - second isolation regions (442) positioned so as to isolate from each other the active areas (436) of all or part of the transistors of the plurality of transistors, the second isolation regions extending to a second depth (P2) in the semiconductor substrate (404), the second depth being greater than the first depth;wherein each transistor cell comprises first transistors among the plurality of transistors having active areas separated by a first distance and insulated from each other by at least one of the first insulating regions, and second transistors among the plurality of transistors having active areas separated by a second distance less than the first distance and insulated from each other by at least one of the second insulating regions, the first distance being greater than or equal to 400 nm, and the second distance being less than 350 nm; and wherein the first depth (PI) is between 250 and 450 nm, and the difference between the second depth (P2) and the first depth is between 100 and 200 nm.;

2. An electronic circuit according to claim 1, wherein the first isolation regions (440) are first isolation trenches, for example shallow isolation trenches, and the second isolation regions (442) are second isolation trenches, for example deep isolation trenches.

3. Electronic circuit according to claim 1 or 2, in which the second insulation regions (442) extend in a first direction (X) substantially parallel to the longitudinal direction of the active zones (436).

4. An electronic circuit (40) according to any one of claims 1 to 3, further comprising third isolation regions (444) posi- data so as to isolate the active areas (436) of the plurality of transistors (430) from other transistor cells (401), the third isolation regions extending to a third depth (P3) in the semiconductor substrate (404), the third depth being greater than the first depth (PI), for example substantially equal to the second depth (P2), the third isolation regions being, for example, deep isolation trenches.

5. Electronic circuit (40) according to claim 4, in which the third isolation regions (444) extend in a second direction (Y) substantially parallel to the transverse direction of the active zones (436).

6. An electronic circuit according to claim 4 or 5, wherein at least some of the first and second isolation regions surround the active areas of all or some of the transistors of the plurality of transistors.

7. An electronic circuit according to any one of claims 1 to 6, wherein the transistors of the plurality of transistors are intended to operate at voltages greater than or equal to 10 volts, for example greater than or equal to 15 volts.

8. An electronic circuit (40) according to any one of claims 1 to 7, wherein the transistor cell further comprises a gate structure (432, 434), for example of the double gate type, extending above the active areas (436) of the plurality of transistors (430), between a source region (S3) and a drain region (D3) of each active area.

9. An electronic circuit (40) according to any one of claims 1 to 8, wherein the plurality of transistors are P-channel MOS transistors and / or N-channel MOS transistors.

10. An electronic circuit (40) according to any one of claims 1 to 9, said electronic circuit being comprised in a non-volatile memory, for example an electrically erasable and programmable non-volatile memory.

11. An electronic circuit (40) according to any one of claims 1 to 10, wherein the transistors (430) of the plurality of transistors form switching transistors of a switching circuit (402) coupled to memory cells (401) of a non-volatile memory, for example of an electrically erasable and pro- grammable.

12. Electronic circuit according to any one of claims 1 to 11 in combination with claim 4, wherein the first depth (PI) is between 250 and 450 nm, for example between 300 and 400 nm, and the difference between the third depth (P3) and the first depth is greater than or equal to 100 nm, for example between 100 and 200 nm.

13. Electronic circuit according to any one of claims 1 to 12, in which the first depth (PI) is between 300 and 400 nm

14. llili. Integrated circuit comprising an electronic circuit selected according to any one of claims 1 to 13.

15. A method of manufacturing an electronic circuit comprising at least one transistor cell, each transistor cell comprising a plurality of transistors formed in and on a semiconductor substrate (604), each transistor comprising an active area, the method comprising: - forming first isolation regions (640) located at least partially around the transistors and extending to a first depth (PI) in the semiconductor substrate (604); and - forming second isolation regions (642) positioned to isolate from each other the active areas of all or some of the transistors of the plurality of transistors, the second isolation regions extending to a second depth (P2) in the semiconductor substrate (604), the second depth being greater than the first depth;wherein each transistor cell comprises first transistors among the plurality of transistors having active areas separated by a first distance and insulated from each other by at least one of the first insulating regions, and second transistors among the plurality of transistors having active areas separated by a second distance less than the first distance and insulated from each other by at least one of the second insulating regions, the first distance being greater than or equal to 400 nm, and the second distance being less than 350 nm; and wherein the first depth (PI) is between 250 and 450 nm, and the difference between the second depth (P2) and the first depth is between 100 and 200 nm.;

16. A manufacturing method according to claim 15, further comprising: - forming third isolation regions positioned to isolate the active areas of the plurality of transistors from other transistor cells, the third isolation regions extending to a third depth (P3) in the semiconductor substrate, the third depth being greater than the first depth (PI), for example substantially equal to the second depth (P2).

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