Electronic circuit

Abstract

Electronic Circuit This description concerns an electronic circuit having an impedance matching circuit (230) comprising: a first inductor (330) connecting a first node (N3) to a second node (N4); and a second inductor (340) connecting the second node to a third node (N5), the third node being connected to ground; the first and second inductors (330, 340) being configured to form a positive magnetic coupling between them. Figure for the abbreviation: Fig. 3

Description

Title of the invention: Electronic circuit Technical field

[0001] The present description relates generally to electronic circuits and devices comprising these electronic circuits, in particular radiofrequency communication devices. Prior art

[0002] Many electronic circuits and devices, particularly radio frequency communication devices, require impedance matching circuits between a bias circuit, connected to a matching circuit, and an antenna. In some cases, such as in test circuits, the bias circuit is connected to the antenna. As a result, the impedance matching circuit must then be modified to limit signal losses and costs. Summary of the invention

[0003] There is a need to provide a wideband impedance matching circuit that limits signal losses and costs.

[0004] One embodiment overcomes all or part of the drawbacks of known electronic circuits.

[0005] One embodiment provides an electronic circuit having an impedance matching circuit comprising: a first inductor connecting a first node to a second node; and a second inductor, connecting the second node to a third node, the third node being connected to ground; the first and second inductors being configured to form a positive magnetic coupling therebetween.

[0006] According to one embodiment, the third node is connected to ground via a capacitor.

[0007] According to one embodiment, the first and second inductances are constituted by planar conductive windings.

[0008] According to one embodiment, the second node is intended to be polarized by a test device.

[0009] According to one embodiment, the third node is intended to be polarized by a power supply of the electronic circuit.

[0010] According to one embodiment, the first node is intended to be connected to an amplifier.

[0011] According to one embodiment, the magnetic coupling is greater than 0.5.

[0012] According to one embodiment, the first and second inductors are configured so that a current can flow through them in the same direction.

[0013] According to one embodiment, the first inductor and the second inductor are stacked.

[0014] According to one embodiment, the second inductor has a number of windings greater than the number of windings of the first inductor.

[0015] According to one embodiment, one or more first conductive tracks, insulated from the second inductor, surround in whole or in part an external region of the winding of the second inductor.

[0016] According to one embodiment, one or more second conductive tracks, insulated from the second inductor, are arranged between a central part of the second inductor not covered by a winding and an internal region of the winding of the second inductor.

[0017] According to one embodiment, one or more third conductive tracks, insulated from the first inductor, surround in whole or in part an external region of the winding of the first inductor.

[0018] According to one embodiment, one or more fourth conductive tracks, insulated from the first inductor, are arranged between a central part of the winding of the first inductor not covered by a winding and an internal region of the winding of the first inductor.

[0019] According to one embodiment, the value of the capacitance is configured to limit the occurrence of a current loop.

[0020] According to one embodiment, the impedance matching circuit comprises another capacitor connecting the first and second nodes.

[0021] According to one embodiment, the electromagnetic field generated by the first inductance and the electromagnetic field generated by the second inductance are superimposed in the same direction.

[0022] One embodiment provides an electronic device comprising: - the electronic circuit as described above; and - an amplifier connected to the first node.

[0023] In one embodiment, the device further comprises a test device configured to bias the second node.

[0024] In one embodiment, the test device is configured to bias the second node with a bias tee.

[0025] In one embodiment, the device further comprises an antenna connected to said polarization tee.

[0026] In one embodiment, the amplifier comprises a bipolar type transistor and in which the first node is connected to a collector of said transistor.

[0027] One embodiment provides a 5G radio frequency communication system comprising the electronic device as described above. Brief description of the drawings

[0028] These characteristics and advantages, as well as others, will be explained in detail in the following description of particular embodiments given without limitation in relation to the attached figures among which:

[0029] [Fig.l] very schematically represents an example of an electronic device

[0030] [Fig.2] represents very schematically an electronic device according to a embodiment;

[0031] [Fig.3] represents the electronic device of [Fig.2] according to one embodiment;

[0032] [Fig.4] represents a top view of a part of the electronic device of [Fig.3] according to one embodiment;

[0033] [Fig.5] represents a top view of another part of the electronic device of [Fig.3] according to one embodiment;

[0034] [Fig. 6] represents a combined sectional view of the embodiments of Figures 4 and 5; and

[0035] [Fig.7] represents simulations of operation of the device of [Fig.3]. Description of the embodiments

[0036] The same elements have been designated by the same references in the different figures. In particular, the structural and / or functional elements common to the different embodiments may have the same references and may have identical structural, dimensional and material properties.

[0037] For the sake of clarity, only the steps and elements useful for understanding the described embodiments have been shown and are detailed.

[0038] Unless otherwise specified, when referring to two elements connected to each other, this means directly connected without intermediate elements other than conductors, and when referring to two elements connected (in English "coupled") to each other, this means that these two elements can be connected or be electrically connected by means of one or more other elements. When two elements are magnetically coupled without contact, it will be specified "magnetic coupling".

[0039] In the following description, when referring to absolute position qualifiers, such as the terms "front", "back", "top", "bottom", "left", "right", etc., or relative position qualifiers, such as the terms "above", "below", "upper", "lower", etc., or to orientation qualifiers, such as the terms "horizontal", "vertical", etc., it is made reference unless otherwise specified to the orientation of the figures.

[0040] Unless otherwise specified, the expressions "about", "approximately", "substantially", and "of the order of" mean to within 10%, preferably to within 5%.

[0041] [Fig.l] very schematically represents an example of an electronic device 100. The device 100 is for example a device used in a system processing radio frequencies.

[0042] The electronic device 100 comprises an amplification block 110 (AMPLIFIER) which comprises for example a CMOS or bipolar transistor. In the example shown, a biasing block 120 (POLARIZATION) connects the amplification block 110 at a node NI to an impedance matching circuit 130 (IMPEDANCE MATCHING) at a node N2. The impedance matching circuit 130 is itself connected, preferably connected, to a load 140 (LOAD). The load 140 is for example a circuit comprising an antenna. In the case where the amplification block 110 comprises a bipolar transistor, the biasing block 120 is for example connected, preferably connected, to the collector of this transistor. The bias block 120 is for example formed of a bias tee comprising an inductance connecting a supply voltage rail to the node NI and a capacitor connecting the node NI to the node N2.

[0043] The bias tee is for example used to supply voltage or current to the device while allowing high speed and ultra-wideband signals to flow, with minimal signal degradation.

[0044] The impedance matching circuit 130 has the function of matching the output impedance of the amplification block 110, which is for example 17 Ohms with a capacitance of 1 to 3 pF to an impedance of the load which is for example 50 Ohms without degrading the signal level.

[0045] [Fig.2] very schematically represents an electronic device 200 according to one embodiment.

[0046] The device 200 is similar to the device 100 except that an impedance matching circuit 230 is connected, preferably connected, to the amplification block 110 at a node N3 and to the biasing block 120 at a node N4. The biasing block 120 this time connects the load 140 to the node N4 so as to allow biasing of the second node N4.

[0047] The architecture of the device 200 is for example obtained when the polarization block 120 and possibly the load 140 are arranged on a circuit whose substrate is different from the impedance matching circuit 230 and / or the amplification block 110. In one example, the polarization block 120 and possibly the load 140 are arranged on a test circuit. In another example, the impedance matching circuit 130 and / or the amplification block 110 are formed in a semi-solid substrate. conductor, for example a silicon substrate.

[0048] Compared to the example of [Fig.l], the device 200 requires redefining a new architecture of the impedance matching circuit 230 without series capacitance or short-circuit inductance while limiting the surface area used. The constraints in terms of performance remain the same, such as, for example, adapting the output impedance of the amplification block 110, which is for example 17 Ohms with a capacitance of 1 to 3 pF to an impedance of the load which is for example 50 Ohms without degrading the signal and this over a bandwidth for example greater than 1 GHz.

[0049] The described embodiments provide an impedance matching circuit comprising: a first inductor connecting a first node to a second node; and a second inductor, connecting the second node to a third node which is connected to ground; the first and second inductors being configured to form a positive magnetic coupling therebetween.

[0050] In other words, the first and second inductors are configured so that the electromagnetic field generated by the first inductor and the electromagnetic field generated by the second inductor are superimposed in the same direction. This creates the positive magnetic coupling between the two inductors.

[0051] The described embodiments make it possible to avoid the use of series capacitors and short-circuit inductances ("shunt inductance" in English) while limiting the space used. The wideband transformation impedance is relatively flat and with low losses over a band of several GHz.

[0052] [Fig.3] represents the electronic device 200 of [Fig.2] according to one embodiment.

[0053] More specifically, [Fig. 3] describes in detail an exemplary embodiment of the impedance matching circuit 230 and the polarization block 120.

[0054] In the example shown, the polarization block 120 is for example formed of a polarization tee comprising an inductor 360 connecting a supply voltage rail VBAT to the node N4 and a capacitor 350 connecting the node N4 to the load 140.

[0055] The impedance matching circuit 230 comprises a first inductor 330 connecting the node N3 to the node N4; and a second inductor 340, connecting the node N4 to a node N5. The first and second inductors 330, 340 are therefore connected at the node N4.

[0056] In the example shown, where the polarization (that of the polarization block 120) is external to the circuit 230, a capacitor 320 can be incorporated by connecting the node N5 to ground. The capacitor 320 is for example chosen to limit the appearance of a current loop, it has a value of several tens of picoFarads for example. In a case not illustrated where the polarization is generated by a power supply internal to the circuit 230, for example referenced to ground and applied to node N5, the capacitor 320 may be absent or of smaller size. In this case, the block 120 will for example be absent.

[0057] In one example, the impedance matching circuit further comprises an optional capacitor 310 connecting the nodes N3 and N4. The capacitor 310 makes it possible to obtain a flatter response over the entire bandwidth, for example between 1 and 5 GHz. The capacitor 310 has a value of the order of pFarad, for example.

[0058] In the example shown, the first and second inductances 330, 340 are configured to form a positive magnetic coupling between them. To do this, the currents i1 and i2 flowing respectively through the two inductances 330, 340 go in the same direction (i.e. towards the node N4). The electromagnetic fields generated by the first inductance and the second inductance can therefore add up if they are emitted at the same location.

[0059] Positive coupling is advantageous over negative coupling because it limits bandwidth and losses in the matching network.

[0060] A positive coupling as close as possible to 1 makes it possible to limit losses and gain efficiency while limiting the size of the inductances relative to the circuit. For this purpose, it may be advantageous for the first and second inductances 330, 340 to be stacked on top of each other with, for example, maximum overlap between the windings of the first inductance 330 and those of the second inductance 340. This also makes it possible to limit the encroachment of the inductances in the circuit.

[0061] [Fig. 4] represents a top view of a portion of the electronic device of [Fig. 3] according to one embodiment. More particularly, [Fig. 4] represents the magnetically coupled lines of the inductor 330 which constitute a primary portion of the magnetic coupling.

[0062] [Fig. 5] represents a top view of another part of the electronic device of [Fig. 3] according to one embodiment. More particularly, [Fig. 5] represents the magnetically coupled lines of the inductor 340 which constitute a secondary part of the magnetic coupling.

[0063] More particularly, figures 4 and 5 illustrate respectively, in top view, the first and second inductors 330, 340. The inductors 330 and 340 are shown separately for reasons of clarity but it is advantageous to stack them with maximum overlap.

[0064] In the examples shown, the first inductor 330 comprises two windings 430 and the second inductor 340 comprises four windings 530. The length of the windings defines the value of the inductances. In one example, the windings 430 have a width of approximately 30 μm and the windings have a width of about 10 pm. The difference in width between windings 430 and 530 allows the two windings to be superimposed over most of their length despite a large difference between their respective lengths. The innermost winding of the first inductor 330 is configured to have a track width that can overlap with the two innermost windings of the second inductor 340. The outermost winding of the first inductor 330 is configured to have a track width that can overlap with the two outermost windings of the second inductor 340.

[0065] In an example shown in [Fig.5], one or more conductive tracks 510, insulated from the second inductor 340, surround in whole or in part an outer region of the winding of the second inductor 340.

[0066] In another example shown in [Fig. 5], one or more conductive tracks 520, insulated from the second inductor 340, are arranged between a central portion 540 of the second inductor 340 not covered by a winding and an internal region 542 of the internal winding of the second inductor.

[0067] In an example not illustrated, one or more insulated conductive tracks of the first inductor 330 surround in whole or in part an outer region of the winding of the first inductor 330.

[0068] In another example not illustrated, one or more conductive tracks, insulated from the first inductor, are arranged between a central portion 440 of the winding of the first inductor 330 not covered by a winding and an internal region of the winding of the first inductor.

[0069] The tracks 510 and 520 are for example connected to the first inductance 330 by vias.

[0070] Tracks 510 and 520 are, in another example, connected to the tracks surrounding the windings of the first inductor by vias.

[0071] Tracks 510 and 520 make it possible to increase the positive magnetic coupling between inductors 330 and 340.

[0072] In one example, the first and second inductors 330, 340 are for example connected via vias.

[0073] [Fig. 6] represents a combined AA sectional view of the embodiments of FIGS. 4 and 5. More particularly, the AA section is made on a stack of the first and second inductors 330, 340. The AA section intersects one of the tracks 510, and one of the tracks 520 as well as three windings 530 of the second inductor located between these tracks 510 and 520. The AA section further represents the windings 430 of the first inductor 330 which are superimposed above the windings of the inductor 340 shown in the section.

[0074] In the example shown, the windings 530 of the second inductor 340 and the tracks 510, 520 are made by a metal deposit made for example on a semiconductor substrate. The windings 530 of the second inductor 340 and the tracks 510, 520 are covered for example by an insulator 620. The windings 430 of the first inductor 330 are for example made by a metal deposit formed in and / or on the insulator 620.

[0075] In the example shown, the tracks 510 and 520 are for example connected to the first inductance 330 by vias 630 formed through the insulator 620. The positive magnetic coupling between the first and second inductances 330, 340 is thus reinforced.

[0076] By superimposing the first and second inductances 330 and 340, and by circulating a current in the same direction in these two inductances 330, 340, it is possible to obtain a positive magnetic coupling greater than 0.5 or even of the order of 0.9 with the use of the tracks 510, 520.

[0077] [Fig.7] represents simulations of operation of the device of [Fig.3].

[0078] More particularly [Fig.7] is a graph representing the impedance (IMPEDANCE) expressed in Henry, at the level of the node N3 as a function of the frequency between 2.3 and 5 GHz, with (curve 720) and without (curve 710) the optional capacitance 310. In the example of figures 7 and 8, the capacitance 310 is of the order of 1 pF and the inductances 330, 340 are similar to those of figures 4 and 5 with a footprint, once stacked and in top view, of 330 pm by 230 pm.

[0079] With the 310 capacitor, the impedance decreases slightly at high frequencies towards which it is possible to keep a flatter output response from the amplifier block than without the 310 capacitor.

[0080] Various embodiments and variants have been described. Those skilled in the art will understand that certain features of these various embodiments and variants could be combined, and other variants will occur to those skilled in the art. In particular, the number of windings of the first and second inductors 330, 340 as well as their width may be modified to optimize the positive magnetic coupling or adapt to the constraints of the circuit.

[0081] Finally, the practical implementation of the embodiments and variants described is within the reach of the person skilled in the art from the functional indications given above. In particular, as regards the overlap of the first and second inductances, it may be adjusted by the person skilled in the art in order to maximize the positive magnetic coupling between the two inductances 330 and 340.

[0082] The embodiments presented could for example be integrated into a 5G radiofrequency communication system comprising the electronic device 200.

Claims

Claims

1. An electronic circuit having an impedance matching circuit (230) comprising: a first inductor (330) connecting a first node (N3) to a second node (N4); and a second inductor (340), connecting the second node to a third node (N5), the third node being connected to ground; the first and second inductors (330, 340) being configured to form a positive magnetic coupling therebetween.

2. The circuit of claim 1, wherein (320) the third node (N5) is connected to ground via a capacitor (320).

3. The circuit of claim 1, wherein the first and second inductors (330, 340) are formed by planar conductive windings.

4. A circuit according to any one of claims 1 to 3, wherein the second node (N4) is intended to be biased by a test device.

5. Circuit according to any one of claims 1 to 3, in which the third node (N5) is intended to be biased by a power supply of the electronic circuit.

6. according to any one of claims 1 to 5, wherein the first node (N3) is intended to be connected to an amplifier (110).

7. A circuit according to any one of claims 1 to 6, wherein the magnetic coupling is greater than 0.

5.

8. A circuit according to any one of claims 1 to 7, wherein the first and second inductors (330, 340) are configured so that a current can flow through them in the same direction.

9. A circuit according to any one of claims 1 to 8, wherein the first inductor and the second inductor (330, 340) are stacked.

10. A circuit according to any one of claims 3 to 8, wherein the second inductor (340) has a number of windings (530) greater than the number of windings (430) of the first inductor.

11. A circuit according to any one of claims 3 to 10, wherein one or more first conductive tracks (510), insulated from the second inductor, surround in whole or in part an outer region of the winding of the second inductor.

12. A circuit according to any one of claims 3 to 11, wherein one or more second conductive tracks (520), insulated from the second inductance, are arranged between a central portion (540) of the second inductance not covered by a winding and an internal region of the winding of the second inductance (340).

13. A circuit according to any one of claims 3 to 12, wherein one or more third conductive tracks, insulated from the first inductor (330), surround in whole or in part an outer region of the winding of the first inductor (330).

14. A circuit according to any one of claims 3 to 13, wherein one or more fourth conductive tracks, insulated from the first inductor (330), are arranged between a central portion (440) of the winding of the first inductor not covered by a winding and an internal region of the winding of the first inductor (330).

15. A circuit according to any one of claims 2 to 14, wherein the value of the capacitance (320) is configured to limit the occurrence of a current loop.

16. A circuit according to any one of claims 1 to 15, wherein the impedance matching circuit (230) comprises a further capacitor (310) connecting the first and second nodes (N3, N4).

17. Circuit according to any one of claims 1 to 16, in which the electromagnetic field generated by the first inductance (330) and the electromagnetic field generated by the second inductance (340) are superimposed in the same direction.

18. Electronic device (200) comprising: - the electronic circuit according to any one of the preceding claims; and - an amplifier (110) connected to the first node (N3).

19. Device according to the preceding claim, further comprising a test device (120) configured to bias the second node (N4).

20. Device according to the preceding claim, in which the test device is configured to polarize the second node (N4) with a polarization tee (120).

21. Device according to the preceding claim, further comprising an antenna (140) connected to said polarization tee.

22. Device according to any one of claims 18 to 21, wherein the amplifier (110) comprises a bipolar type transistor and wherein the first node (N3) is connected to a collector of said transistor.

23. A 5G radio frequency communication system comprising the electronic device (200) according to any one of claims 18 to 22.