Memory device comprising RRAM memory cells with optimized active area

Abstract

Memory device comprising RRAM memory cells with optimized active area. This description relates to a memory device (100) comprising, in a first metallization level: - first electrical interconnection lines (102) parallel to each other, - metallic portions (104) parallel to each other and each electrically coupling two adjacent first electrical interconnection lines, and wherein an OxRAM or CBRAM type memory point is disposed at each interface between one of the metallic portions and one of the first electrical interconnection lines, and each memory point comprises a first electrode disposed against said first electrical interconnection line, a second electrode disposed against said one of the metallic portions, and a memory layer disposed between the first and second electrodes. Figure for the abbreviation: Fig. 1

Description

Title of the invention: Memory device comprising RRAM memory cells with optimized active area. Technical field

[0001] This description relates generally to the field of non-volatile memories of the resistive type (RRAM or ReRAM) based on oxide (OxRAM) or metallic electrolyte (CBRAM). Prior art

[0002] The main block of a memory is formed of an array of memory cells, or "bitcells". Each memory cell includes at least one selection transistor and at least one memory point that performs the storage of information for the memory cell. The memory cells are electrically coupled to electrical connection elements formed by superimposed metallic layers corresponding to the BEOL ("Back End Of Line") of the circuit.

[0003] In an OxRAM type memory, each memory cell is generally formed by a vertical mesa, or island, structure in which a portion of oxide is arranged between upper and lower electrodes in the form of a vertical stack. The paper P. Polakowski et al., "Ferroelectric deep trench capacitors based on Al:HfO2 for 3D nonvolatile memory applications", 2014 IEEE 6th International Memory Workshop (IMW), Taipei, Taiwan, 2014, pp. 1-4, describes such a configuration.

[0004] Other memory point architectures have been considered, for example in the form of a cylindrical 3D structure as described in the paper G. Piccolboni et al., "Investigation of the potentialities of Vertical Resistive RAM (VRRAM) for neuromorphic applications", 2015 IEEE International Electron Devices Meeting (IEDM), Washington, DC, USA, 2015, pp. 17.2.1-17.2.4.

[0005] In an OxRAM type memory cell, the active area, which corresponds to the contact area between the oxide portion and the electrodes, determines a large part of the memory cell's electrical characteristics. For the various vertical memory cell architectures mentioned above, this active area is, however, limited by the total area available for the cell in the plane of the memory cell array. A reduction in the total area available for the memory cell is therefore accompanied by a reduction in the active area of ​​the memory cell, which leads to several problems: an increase in the voltage required to store information in the memory cell, an increase in the variability of the electrical parameters (current, voltage) of the memory cells, and a loss of efficiency.

[0006] Similar problems are also found for CBRAM type memories. Summary of the invention

[0007] There is therefore a need to propose a resistive memory structure allowing a reduction in the surface area occupied by memory cells while limiting or eliminating the problems previously mentioned.

[0008] One embodiment proposes a solution to all or part of the drawbacks of known solutions and proposes a memory device comprising, in a first level of metallization:

[0009] - the first parallel electrical interconnection lines,

[0010] - metallic portions parallel to each other and electrically coupling each of the first two adjacent electrical interconnection lines,

[0011] and wherein an OxRAM or CBRAM type memory point is disposed at each interface between one of the metallic portions and one of the first electrical interconnection lines, and each memory point comprises a first electrode disposed against said one of the first electrical interconnection lines, a second electrode disposed against said one of the metallic portions, and a memory layer disposed between the first and second electrodes.

[0012] According to a particular embodiment, each memory point further comprises a portion of getter material disposed between the memory layer and one of the first and second electrodes.

[0013] According to a particular embodiment, the memory device further comprises, in a second level of metallization, second lines of electrical interconnection parallel to each other and electrically coupled to the metallic portions or to the first lines of electrical interconnection.

[0014] According to a particular embodiment, the memory device further comprises first electrically conductive vias electrically coupling the second electrical interconnection lines to the metallic portions or to the first electrical interconnection lines.

[0015] According to a particular embodiment, when the second electrical interconnection lines are electrically coupled to the metallic portions, the first electrical interconnection lines are source lines of the memory device and the second electrical interconnection lines are bit lines of the memory device.

[0016] According to a particular embodiment, the first metallization level is disposed between the second metallization level and a substrate of the memory device.

[0017] According to a particular embodiment, the substrate comprises a layer of semi conductor in which transistors are formed, one of the source or drain electrodes of each of the transistors being electrically coupled to one of the first electrical interconnect lines or to one of the metallic portions by a second electrically conductive via extending between the semiconductor layer and said one of the first electrical interconnect lines or between the semiconductor layer and said one of the metallic portions.

[0018] According to a particular embodiment, the device comprises, in a third metallization level such that the first metallization level is disposed between the second and third metallization levels, third electrical interconnection lines parallel to each other and perpendicular to the first electrical interconnection lines, and the third electrical interconnection lines are electrically coupled to the gates of the transistors.

[0019] According to a particular embodiment, each of the first two adjacent electrical interconnection lines is electrically coupled to memory points which are electrically coupled to different second electrical interconnection lines.

[0020] According to a particular embodiment, the first electrical interconnection lines extend in a plane perpendicular to larger-dimension faces of the memory layer and of the first and second electrodes.

[0021] According to a particular embodiment, a method for implementing a memory device is proposed, comprising at least:

[0022] - realization, in a first level of metallization, of first lines of parallel electrical interconnections, and of parallel metallic sections, each electrically coupling two adjacent first electrical interconnection lines,

[0023] - realization, at each interface between one of the metallic portions and one of the first lines of electrical interconnection, of a memory point of type OxRAM or CBRAM comprising a first electrode disposed against said one of the first lines of electrical interconnection, a second electrode disposed against said one of the metallic portions, and a memory layer disposed between the first and second electrodes.

[0024] According to a particular embodiment, the first electrical interconnection lines, the metallic portions and the memory points are made by implementing the following steps:

[0025] - etching, in a first dielectric layer, of first trenches defining locations for the first electrical interconnection lines,

[0026] - depositing at least one first metallic material in the first trenches, forming the first electrodes of the memory points, and at least a second metallic material forming the first lines of electrical interconnection,

[0027] - etching, in the first dielectric layer, of first holes defining em placements for metal components and memory points,

[0028] - successive deposits of several materials in the first holes, forming the points memory and metallic portions.

[0029] According to a particular embodiment, the method further comprises, after the construction of the first electrical interconnection lines, metallic portions and memory points:

[0030] - deposition of at least a second dielectric layer on the first lines electrical interconnection, metallic portions and memory points,

[0031] - engraving, through a first part of the thickness of the second layer di electrical, second trenches parallel to each other and defining locations for second electrical interconnection lines,

[0032] - engraving, through a second part of the thickness of the second layer di electrical, under the second trenches and directly above the metallic sections or the first electrical interconnection lines, second holes defining locations for first electrically conductive vias,

[0033] - depositing at least one other metallic material in the second holes and in the second trenches, forming the second electrical interconnection lines and the first electrically conductive vias electrically coupling one of the second electrical interconnection lines to the metallic portions or to the first electrical interconnection lines.

[0034] According to a particular embodiment, the method further comprises, prior to the realization of the first electrical interconnection lines, the metallic portions and the memory points, the realization, from a semiconductor layer of a substrate, of transistors in which one of the source or drain electrodes of each of the transistors is electrically coupled to one of the first electrical interconnection lines or to one of the metallic portions by a second electrically conductive via extending between the semiconductor layer and said one of the first electrical interconnection lines or between the semiconductor layer and said one of the metallic portions.

[0035] According to a particular embodiment, the realization of the transistors includes the realization of gates electrically coupled to third lines of electrical interconnection parallel to each other and perpendicular to the first lines of electrical interconnection. Brief description of the drawings

[0036] These features and advantages, as well as others, will be described in detail in the The following is a description of specific examples of implementation, provided for informational purposes only, in relation to the attached figures, among which:

[0037] Figure 1 schematically represents part of an example of a memory device

[0038] Figure 2 schematically represents a memory cell of a memory device according to a particular embodiment;

[0039] [Fig.3] schematically represents the memory points of a memory cell of the memory device according to a particular embodiment;

[0040] [Fig.4] represents an electrical diagram of several memory cells of the memory device according to a particular embodiment;

[0041] [Fig.5] schematically represents a top view of the arrangement of two memory cells of the memory device according to a particular embodiment;

[0042] [Fig.6] schematically represents part of a memory cell matrix of a memory device according to a particular embodiment;

[0043] [Fig.7] represents geometric characteristics of the memory points of a memory device;

[0044] Figures 8, 9, 10, 11, 12, and 13 represent some of the steps in a process for manufacturing a memory device. Description of embodiments

[0045] The same elements have been designated by the same reference numerals in the different figures. In particular, the structural and / or functional elements common to the different embodiments may have the same reference numerals and may have identical structural, dimensional and material properties.

[0046] For the sake of clarity, only the steps and elements useful for understanding the described embodiments have been shown and are detailed. In particular, various elements (read circuit, row decoder, column decoder, etc.) of the memory device are not detailed. A detailed implementation of these elements is within the capabilities of a person skilled in the art using the functional description given below.

[0047] In the different figures, the visible elements are not represented at the same scale relative to each other to facilitate understanding of these figures.

[0048] Unless otherwise specified, when referring to two elements connected together, this means directly connected without intermediate elements other than conductors, and when referring to two elements linked or coupled together, this means that these two elements can be connected or linked through one or more other elements.

[0049] In the following description, when referring to positional qualifiers absolute, such as the terms "front", "back", "up", "down", "left", "right", etc., or relative, such as the terms "above", "below", "superior", "inferior", etc., or to orienting qualifiers, such as the terms "horizontal", "vertical", etc., refers, unless otherwise specified, to the orientation of the figures in a normal operating position of the device.

[0050] Unless otherwise specified, the expressions "approximately", "roughly", and "in the order of" mean within 10%, preferably within 5%.

[0051] Throughout this document, the terms "first," "second," and "third," used to designate and distinguish the different metallization levels of the device, do not imply their order of realization or their arrangement relative to the device substrate. Thus, the "first metallization level" does not necessarily correspond to the M1 metallization level of the circuit. Similarly, the "second metallization level" and "third metallization level" do not necessarily correspond to the M2 and M3 metallization levels of the circuit.

[0052] The description below of oxide-based resistive memories (OxRAM) can be applied in the same way to CB RAM type resistive memories, by replacing the constituent elements of these OxRAM memories with their equivalent in CBRAM memories, namely in particular the lower and upper electrodes with respectively a chemically inert electrode and a chemically active electrode, and the resistive layer with a solid electrolyte.

[0053] An example of a memory device 100 according to a particular embodiment is described below with reference to Figures 1 to 5. Figure 1 schematically represents a part of the device 100. Figure 2 schematically represents a memory cell of the device 100. Figure 3 schematically represents the memory points of a memory cell of the device 100. Figure 4 schematically represents an electrical diagram of several memory cells of the device 100. Figure 5 schematically represents a top view of the layout of two memory cells of the device 100.

[0054] The memory device 100 comprises a memory cell array extending in a plane parallel to the (X,Y) plane shown in [Fig. 1]. The device 100 is, for example, implemented as an integrated circuit comprising a substrate on and / or in which components, including the memory cell transistors, are fabricated. The circuit also includes several metallization layers fabricated above the substrate, forming the BEOL of the circuit, in which the memory points of the memory cells are fabricated.

[0055] The device 100 comprises, in a first metallization level corresponding for example to the M4 metallization level of the circuit, first electrical interconnection lines 102 parallel to each other (parallel to the X axis (visible in [Fig. 1]). According to one embodiment, the first 102 lines comprise at least one of the following metallic materials: tungsten, copper, cobalt. Furthermore, the first 102 lines are made of a dielectric layer not visible in [Fig. 1] and comprising, for example, SiO2. The thickness (dimension parallel to the Z-axis) of the first 102 lines is, for example, between 50 nm and 500 nm. Each of the first 102 lines can be common to all the memory cells arranged on the same row of the memory cell array.

[0056] The device 100 also includes, in the first metallization level, parallel metallic portions 104, each electrically coupling two adjacent first lines 102. In the example of [Fig. 1], each of the metallic portions 104 extends between two adjacent first lines 102 parallel to the Y-axis. According to one embodiment, the metallic portions 104 comprise at least one of the following metallic materials: copper, tungsten, cobalt. The metallic portions 104 are made of the same dielectric layer as the first lines 102. The thickness of the metallic portions 104 is similar to that of the first lines 102.

[0057] In the device 100, an OxRAM type memory point 105 is disposed at each interface of one of the metallic portions 104 and one of the first lines 102. Two examples of these memory points 105 are visible in [Fig.3].

[0058] Each of the memory points 105 comprises a first electrode 106 disposed against one of the first lines 102, and a second electrode 108 disposed against one of the metallic portions 104. According to one embodiment, the first and second electrodes 106, 108 comprise, for example, TiN, which has the advantage of being a chemically stable material providing electro-chemical neutrality to the electrodes 106, 108. Alternatively, the first and second electrodes 106, 108 may comprise TaN or WN.

[0059] Each of the memory points 105 also includes a memory layer 110 disposed between the first and second electrodes 106, 108, in which the information of the memory point 105 is intended to be stored. In the case of an OxRAM-type memory point 105, the memory layer 110 corresponds to a resistive layer, for example, an oxide portion. According to one embodiment, the oxide portion 110 comprises HfO2.

[0060] In the particular embodiment described, each memory point 105 further comprises a portion of getter material 112 disposed between the memory layer 110 and one of the first and second electrodes 106, 108. In the example of [Fig. 3], for each memory point 105, the portion 112 is disposed between the memory layer 110 and the second electrode 108 (i.e., the electrode disposed against the metallic portion 104 of the memory point 105). The portion 112 contributes, in this example, to the creation of one or more electrically conductive filaments in the memory layer 110 during the operation of the device 100. According to an example embodiment, portion 112 comprises titanium, or tantalum, or hafnium, or any other material having an electro-chemical affinity with oxygen.

[0061] The dimension along the Z axis of layer 110 and portion 112 is for example similar to the thickness of the first lines 102.

[0062] In the example described above, each memory point 105 is formed by the stacking of the electrodes 106, 108, of the layer 110 and of the portion 112, this stacking being arranged "horizontally", that is to say extending between one of the first rows 102 and one of the portions 104 in a direction belonging to the plane in which the first rows 102 and the portions 104 are located. In the example described, the direction of the stacking (parallel to the Y axis in Figures 1 to 3) forming each memory point 105 is perpendicular to the direction in which the first rows 102 extend.

[0063] In the particular embodiment described, the first lines 102 extend in a plane perpendicular to larger faces of the memory layer 110 and of the first and second electrodes 106, 108.

[0064] Furthermore, in each memory point 105, the active area is defined by the dimension along the X-axis of the metallic portion 104 and the thickness of the first line 102 and the metallic portion 104. Thus, a reduction in the total area of ​​the memory cell in the plane of the memory cell matrix does not directly impact the active area of ​​each memory point 105 and can be compensated by an increase in the thickness of the lines 102 and the portions 104.

[0065] In the described embodiment, the device 100 also includes, in a second metallization level of the device 100 corresponding, for example, to the M5 metallization level of the circuit, second electrical interconnection lines 114 parallel to each other. In the embodiment described here, the second electrical interconnection lines 114 are also parallel to the first lines 102.

[0066] In the particular embodiment described, the device 100 may also include electrically conductive vias 116 extending between the first and second metallization levels of the device 100, each electrically coupling one of the second lines 114 to one of the metal portions 104. In another embodiment, the second lines 114 may be directly electrically coupled to the metal portions 104 without intermediate vias. In another configuration not shown in the figures, the second lines 114 may be arranged perpendicular to the first lines 102 and electrically coupled to the metal portions 104 by the vias 116. The second lines 114 and / or the vias 116 comprise one or more metallic materials, for example similar to that or those of the metallic portions 104. The second lines 114 and the vias 116 may be arranged in at least one dielectric layer not visible in figures 1 to 5 and comprising, for example, SiO2.

[0067] The second lines 114 and the vias 116 electrically couple together the portions 104 arranged on the same line of the memory cell matrix, i.e. arranged between the same two first lines 102. Within the memory cells of the device 100, electrical access to the first electrodes 106 of the memory points 105 can therefore be achieved via the first lines 102 and electrical access to the second electrodes 108 can be achieved via the second lines 114, the vias 116 and the metallic portions 104.

[0068] The device 100 further comprises a substrate including a semiconductor layer 118 in which transistors 120 are formed. The arrangement of the substrate is such that the first metallization level is disposed between the second metallization level and the substrate.

[0069] In the described embodiment, the transistors 120 correspond to memory cell selection transistors. One of the source or drain electrodes (depending on the conductivity of the transistors) of each of the transistors 120 is electrically coupled to one of the first rows 102 by an electrically conductive via 122 extending between the semiconductor layer 118 and this first row 102. The other source or drain electrode is electrically coupled to a control circuit of the device 100.

[0070] The device 100 comprises, in a third metallization level such that the first metallization level is arranged between the second and third metallization levels, and corresponding, for example, to the M3 metallization level of the circuit, third electrical interconnection lines 124 parallel to each other and perpendicular at least to the first lines 102 and possibly to the second lines 114 depending on their orientation. In the example shown in Figures 1 and 2, the third lines 124 are parallel to the Y-axis. The third lines 124 are electrically coupled to the gates of the transistors 120 and allow, for example, the selection of a column of transistors.

[0071] According to one embodiment, the third lines 124 comprise at least one of the following metallic materials: copper, titanium nitride, tantalum nitride. Furthermore, the third lines 124 and the vias 122 are made of a dielectric layer not visible in Figures 1 to 5 and comprising, for example, SiO2. The thickness (dimension parallel to the Z-axis) of the third lines 124 is, for example, between 40 nm and 500 nm depending on the CMOS technology node used. Each of the third lines 124 may be common to all the transistors. arranged in the same column of the memory cell matrix.

[0072] According to one embodiment, the first lines 102 can correspond to source lines of the device 100 and the second lines 114 can correspond to bit lines of the device 100. In addition, it is possible that the third lines 124 form word lines of the device 100.

[0073] The electrical diagram of several memory cells of the device 100 is visible in [Fig.4]. In this embodiment, each of the first two adjacent lines 102 (between which the metallic portions 102 extend) is electrically coupled to memory points 105 which are electrically coupled to different second lines 114.

[0074] Each memory cell of the device 100 therefore comprises, in this embodiment, two memory points 105 coupled to the same bit line, i.e. the same second line 114. In addition, each source line, i.e. each first line 102, is shared by two neighboring memory cells.

[0075] Fig. 5 schematically represents a top view (view in the (X,Y) plane) of the arrangement of two memory cells of the device 100. In this figure, the regions designated by reference 126 represent parts of the active areas of the transistors 120 of the memory cells of the device 100, and the dotted lines designated by reference 128 symbolically delimit the surfaces occupied by the two memory cells visible in this figure.

[0076] Examples of memory cell programming signals of device 100 are given below in connection with [Fig.6] schematically representing part of the memory cell matrix, some of which are intended to be programmed by these signals.

[0077] The first table below gives examples of voltages applied to the first rows 102 and the second rows 114 to program the two memory locations 105 of the memory cell coupled to the first rows 102, to which the SL2 and SL3 signals are applied, and coupled to the second row 114, to which the BL2 signal is applied, into the high state ("set"). The voltage Vset corresponds to the desired voltage across a memory location 105 intended to be programmed into the high state.

[0078] [Tables] BLl=Vset / 2 BL2=0 BL3=Vset / 2 BL4=0 SLl=0 -Vset / 2 0 -Vset / 2 0 SL2=Vset Vset / 2 Vset Vset / 2 0 SL3=Vset Vset / 2 Vset Vset / 2 0 SL4=0 -Vset / 2 0 -Vset / 2 0

[0079] The second table below gives examples of voltages applied to the first rows 102 and the second rows 114 to reset these two memory locations 105 of the memory cell coupled to the first rows 102, to which the SL2 and SL3 signals are applied, and coupled to the second row 114, to which the BL2 signal is applied, to a low state. The Vreset voltage corresponds to the desired voltage across a memory location 105 intended to be reset to a low state. During this reset, the WL2 and WL3 signals, applied to the third rows 124 forming the gates of the transistors 120 that are coupled to the first rows to which the SL2 and SL3 signals are applied, are such that these transistors 120 are in a conducting state.

[0080] [Tables2] BLl=0 BL2=Vreset BL3=0 BL4=0 SLl=Vreset / 2 Vreset / 2 -Vreset / 2 -Vreset / 2 0 SL2=0 0 Vreset 0 0 SL3=0 0 Vreset 0 0 SL4=Vreset / 2 Vreset / 2 -Vreset / 2 -Vreset / 2 0

[0081] In this particular embodiment, the memory cells of the device 100 can be viewed as being of type 1T2R. The memory cells of the device 100 can be programmed independently of each other by means of a suitable crossbar read / write protocol.

[0082] Regardless of the embodiment of the device 100, since each memory point 105 is formed by stacking the electrodes 106, 108, the layer 110, and the portion 112 arranged "horizontally," that is, extending between one of the first rows 102 and one of the portions 104 in a direction belonging to the plane in which the first rows 102 and the portions 104 are located, that is, parallel to the plane of the memory cell matrix of the device 100, the voltage value for programming the memory cells, the variability of the electrical parameters, and the efficiency of the memory cells depend on the dimensions H and W of the Memory points 105 are located in the plane parallel to the (X,Z) plane, as seen in [Fig. 7], and not in the (X,Y) plane. Therefore, reducing the dimensions of the memory cells in the plane of the memory cell matrix of device 100 can be compensated for by increasing the dimension perpendicular to this plane (i.e., the dimension along the vertical Z axis), thus avoiding the problems previously mentioned and encountered with vertically arranged memory points.

[0083] In all embodiments of the device 100, the arrangement of the memory points at the interfaces between the metallic portions 104 and the first lines 102 makes it possible to double the surface area of ​​the memory point for a given bitcell size and therefore to double the memory density for a given wafer area.

[0084] For example, for a memory cell surface of the order of 0.05 pm2, the total active surface of the memory points 105 of the cell can be of the order of 0.015 pm2, this surface being able to be further increased by increasing the thickness H of the first lines 102 and of the metallic portions 104.

[0085] An example of a method for making a memory device 100 is described below, figures 8 to 13 representing part of these steps.

[0086] In this example, the process first involves the realization, from the semiconductor layer 118 of the substrate, of the various semiconductor components of the device 100, and in particular the transistors 120 for selecting the memory cells of the device 100.

[0087] The various metallization levels intended to form the BEOL of the circuit are then carried out. One of the metallization levels is in particular carried out such that it includes the third lines 124 forming the gates of the transistors 120. These third lines 124 are for example produced by the implementation of etching and deposition steps through a previously deposited dielectric layer.

[0088] The process is then carried out so as to make the first lines 102 parallel to each other, the metallic portions 104 parallel to each other and electrically coupling each two first lines 102 adjacent, and also making, at each interface of one of the metallic portions 104 and one of the first lines 102, a memory point 105 of OxRAM type comprising the first and second electrodes 106, 108, the memory layer 110 and the portion of getter material 112.

[0089] For this purpose, according to one example, initial trenches 130 defining locations for the first lines 102 are etched into a first dielectric layer 132 comprising, for example, SiO2 (see [Fig. 8]). The thickness (dimension parallel to the Z-axis) of the first dielectric layer 132 is, for example, equal to the desired height H for the first lines 102.

[0090] A so-called "Damascene" process is, for example, implemented to form the first lines 102 and the first electrodes 106. For this purpose, the first trenches 130 are filled with at least one first metallic material intended to form the first electrodes 106 and at least one second metallic material intended to form the first lines 102 (see [Fig. 9]). According to one example, this filling of the first trenches 130 may involve depositing a layer of TiN against the walls of the first trenches 130, intended to form the first electrodes 106, and then filling the remaining volume of the first trenches 130 with tungsten intended to form the first lines 102. The portion or portions of metallic material deposited outside the first trenches 130 can then be removed by implementing chemical-mechanical planarization (CMP) with a stop on the first dielectric layer 132.Alternatively, the first electrodes 106 can be formed by depositing a layer of tungsten, cobalt, or copper nitride.

[0091] First holes 138 defining locations for the metallic portions 104 and the memory points 105 are then engraved in the first dielectric layer 132 ([Fig. 10]).

[0092] The materials intended to form the memory layers 110, the getter material portions 112, the second electrodes 108, and the metallic portions 104 are then successively deposited in the first holes 138 ([Fig. 11]). The portions of these materials deposited outside the first holes 138 can be removed by implementing a CMP with a stop on the first dielectric layer 132.

[0093] As an alternative to the example above, it is possible that the first electrodes 106 are not made by depositing a first metallic layer in the first trenches 130, but by depositing a first metallic layer in the first holes 138 implemented before the deposit of the material intended to form the memory layers 110.

[0094] The process is then carried out so as to achieve, in a level of metallization located above that comprising the first lines 102, the second lines 114 and the vias 116.

[0095] For this purpose, at least a second dielectric layer 140 is deposited on the first dielectric layer 132, the first lines 102, the metallic portions 104 and the memory points 105.

[0096] A process called "double Damascene" can be implemented to form the second lines 114 and the vias 116.

[0097] In this case, second trenches 142 parallel to each other and defining locations for the second lines 114 are then engraved through a first part of the thickness of the second dielectric layer 140. Second holes 144 defining locations for vias 116 are then engraved through a second part of the thickness of the second dielectric layer 140 and under the second trenches 142, vertically below the metallic portions 104 ([Fig.12]).

[0098] At least one other metallic material is then deposited in the second holes 144 and in the second trenches 142, forming the second lines 114 and the first vias 116 electrically coupling the second lines 114 to the metallic portions 114 ([Fig. 13]).

[0099] As an alternative to the example above, it is possible to first produce the vias 116 by etching and deposition steps through a second dielectric layer deposited on the first dielectric layer 132, the first lines 102, the metallic portions 104 and the memory points 105. The second lines 114 can then be produced by etching and deposition steps through a third dielectric layer deposited on the second dielectric layer and the vias 116.

[0100] Alternatively, the construction of the vias 116 can be avoided by directly connecting the second lines 114 and the metal portions 104 in pairs at each intersection.

[0101] As an alternative to the embodiments described above in which the transistors 120 are electrically coupled to the first lines 102 by the second vias 122, it is possible that one of the source or drain electrodes of each of the transistors 120 is electrically coupled to one of the metal portions 104 by one of the second vias 122. In this case, each second via 122 can extend between the semiconductor layer 118 and one of the metal portions 104. Furthermore, in this variant, the second lines 114 forming the bit lines can be arranged perpendicular to the first lines 102 and be electrically coupled to the first lines 102 possibly by the first vias 116, and the source lines of the device 100 can be coupled to the metal portions 104.

[0102] Various embodiments and variants have been described. A person skilled in the art will understand that certain features of these various embodiments and variants could be combined, and other variants will become apparent to a person skilled in the art.

[0103] Finally, the practical implementation of the described embodiments and variants is within the reach of a person skilled in the art, based on the functional indications given above. For example, the precise nature of the deposition and engraving steps implemented can be chosen according to, in particular, the material(s) to be deposited or engraved, as well as the thicknesses of the material to be deposited or engraved.

Claims

Claims

1. Memory device (100) comprising, in a first metallization level: - first electrical interconnection lines (102) parallel to each other, - metal portions (104) parallel to each other and each electrically coupling two neighboring first electrical interconnection lines (102), and in which a memory point (105) of the OxRAM or CBRAM type is arranged at each interface between one of the metal portions (104) and one of the first electrical interconnection lines (102), and each memory point (105) comprises a first electrode (106) arranged against said one of the first electrical interconnection lines (102), a second electrode (108) arranged against said one of the metal portions (104), and a memory layer (110) arranged between the first and second electrodes (106, 108).

2. The memory device (100) of claim 1, wherein each memory point (105) further comprises a portion of getter material (112) disposed between the memory layer (110) and one of the first and second electrodes (106, 108).

3. Memory device (100) according to one of the preceding claims, further comprising, in a second metallization level, second electrical interconnection lines (114) parallel to each other and electrically coupled to the metal portions (104) or to the first electrical interconnection lines (102).

4. The memory device (100) of claim 3, further comprising first electrically conductive vias (116) electrically coupling the second electrical interconnect lines (114) to the metal portions (104) or the first electrical interconnect lines (102).

5. The memory device (100) of claim 3 or 4, wherein when the second electrical interconnection lines (114) are electrically coupled to the metal portions (102), the first electrical interconnection lines (102) are source lines of the memory device (100) and the second lines electrical interconnection (114) are bit lines of the memory device (100).

6. The memory device (100) of one of claims 3 to 5, wherein the first metallization level is disposed between the second metallization level and a substrate of the memory device (100).

7. The memory device (100) of claim 6, wherein the substrate comprises a semiconductor layer (118) in which transistors (120) are formed, one of the source or drain electrodes of each of the transistors (120) being electrically coupled to one of the first electrical interconnection lines (102) or to one of the metal portions (104) by a second electrically conductive via (122) extending between the semiconductor layer (118) and said one of the first electrical interconnection lines (102) or between the semiconductor layer (118) and said one of the metal portions (104).

8. The memory device (100) of claim 7, comprising, in a third metallization level such that the first metallization level is disposed between the second and third metallization levels, third electrical interconnection lines (124) parallel to each other and perpendicular to the first electrical interconnection lines (102), and wherein the third electrical interconnection lines (124) are electrically coupled to the gates of the transistors (120).

9. Memory device (100) according to one of claims 3 to 8, wherein each of the two neighboring first electrical interconnection lines (102) is electrically coupled to memory points (105) which are electrically coupled to different second electrical interconnection lines (114).

10. Memory device (100) according to one of the preceding claims, wherein the first electrical interconnection lines (102) extend in a plane perpendicular to larger faces of the memory layer (110) and the first and second electrodes (106, 108).

11. Method for producing a memory device, (100) comprising at least: - producing, in a first metallization level, first parallel electrical interconnection lines (102) to each other, and of metal portions (104) parallel to each other and each electrically coupling two first neighboring electrical interconnection lines (102), - production, at each interface between one of the metal portions (104) and one of the first electrical interconnection lines (102), of a memory point (105) of the OxRAM or CB RAM type comprising a first electrode (106) arranged against said one of the first electrical interconnection lines (102), a second electrode (108) arranged against said one of the metal portions (104), and a memory layer (110) arranged between the first and second electrodes (106, 108).

12. Method according to claim 11, in which the first electrical interconnection lines (102), the metal portions (104) and the memory points (105) are produced by implementing the following steps: - etching, in a first dielectric layer (132), first trenches (130) defining locations for the first electrical interconnection lines (102), - deposition of at least one first metallic material in the first trenches, forming the first electrodes (106) of the memory points (105), and of at least one second metallic material forming the first electrical interconnection lines (102), - etching, in the first dielectric layer (132), first holes (138) defining locations for the metal portions (104) and the memory points (105), - successive deposits of several materials in the first holes (138), forming the memory points (105) and the metal portions (104).

13. Method according to one of claims 11 or 12, further comprising, after the production of the first electrical interconnection lines (102), metal portions (104) and memory points (105): - depositing at least a second dielectric layer (140) on the first electrical interconnection lines (102), the metal portions (104) and the memory points (105), - etching, through a first part of the thickness of the second dielectric layer (140), second trenches (142) parallel to each other and defining locations for second electrical interconnection lines (114), - etching, through a second part of the thickness of the second dielectric layer (140), under the second trenches (142) and directly above the metal portions (104) or the first electrical interconnection lines (102), second holes (144) defining locations for first electrically conductive vias (116), - depositing at least one other metallic material in the second holes (144) and in the second trenches (142),forming the second electrical interconnection lines (114) and the first electrically conductive vias (116) electrically coupling one of the second electrical interconnection lines (114) to the metal portions (104) or to the first electrical interconnection lines (102).,

14. Method according to one of claims 11 to 13, further comprising, prior to the production of the first electrical interconnection lines (102), the metal portions (104) and the memory points (105), the production, from a semiconductor layer (118) of a substrate, of transistors (120) of which one of the source or drain electrodes of each of the transistors (120) is electrically coupled to one of the first electrical interconnection lines (102) or to one of the metal portions (104) by a second electrically conductive via (122) extending between the semiconductor layer (118) and said one of the first electrical interconnection lines (102) or between the semiconductor layer (118) and said one of the metal portions (104).

15. The method of claim 14, wherein providing the transistors (120) includes providing gates electrically coupled to third electrical interconnect lines (124) parallel to the to each other and perpendicular to the first electrical interconnection lines (102).

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