Method of manufacturing an integrated circuit and corresponding integrated circuit

Abstract

The manufacturing method comprises forming lateral isolation regions (STI) delimiting active regions (ACT) in a semiconductor substrate (SUB), and etching a trench (GRTR) extending vertically deep into the substrate (SUB) through said lateral isolation regions (STI) and said active regions (ACT), wherein said forming of the lateral isolation regions (STI) is configured to form at the location of said etching of the trench (TR) widened portions of the lateral isolation regions (STIw+) delimiting thinned portions of the active regions (ACTw-). In the integrated circuit obtained by the method, the bottom of the trench has a shape presenting variations in depth (p1, p11) with low portions (PTB) opposite the location of the trench which crosses the lateral isolation regions (STI), and high portions (PTH) opposite the location of the trench which crosses the active regions (ACT).Figure for abstract: Fig 6A.

Description

Title of the invention: Method for manufacturing an integrated circuit and corresponding integrated circuit

[0001] Implementations and embodiments relate to integrated circuits, in particular integrated circuits comprising a trench extending vertically deep into the substrate, such as integrated circuits incorporating a buried transistor with a vertical gate, for example access transistors for non-volatile memory cells.

[0002] Indeed, an advantageous non-volatile memory technology comprises memory cells CEL1, CEL2 provided with a floating-gate state transistor TE in series with a buried access transistor TA with vertical gate.

[0003] Figures 1A, 1B and 1C illustrate an example of a memory plane incorporating memory cells CEL1, CEL2 in this non-volatile memory technology.

[0004] [Fig.1A] illustrates the arrangement of the memory cells in a top view of the memory plane (in the semiconductor part, usually designated “FEOL” for “Front End Of Line” in English).

[0005] [Fig. 1B] illustrates a sectional view in the BB plane of [Fig. 1A], the BB plane passing through gate regions of the state transistors and the vertical gate region in width.

[0006] [Fig.lC] illustrates a sectional view in the plane CC of [Fig.lA], crossing the vertical grid region lengthwise.

[0007] Briefly, the state transistor TE makes it possible to store a charge representative of a binary data item in its floating gate FG, and the access transistor TA makes it possible to selectively access the memory cell CEL1, CEL2 in writing and reading for example.

[0008] Furthermore, to access the memory cells CEL1, CEL2, the drain region D of the state transistor TE is typically connected to a bit line, while the source region of the access transistor TA is accessed by a NISO region implanted deep in the substrate, which can be called the source plane.

[0009] Typically, the bottom of the vertical gate TRG of the access transistor TA does not come into contact with the source plane NISO in depth, and a source region Simp (also called source implant) is implanted in the substrate between the bottom of the vertical gate TRG and the source plane. The implantation of the source region Simp is done from the bottom of the trench which has been etched to form the vertical gate TRG. The source implant Simp is thus provided to ensure electrical continuity with the source plane NISO.

[0010] It has been noticed by the inventors that a limitation of performance and a loss of efficiency in this non-volatile memory technology could be linked to a low access current in the memory cell, caused by a high resistance of the access transistor TA.

[0011] Indeed, if the trench comprising the vertical gate TRG has an effective depth pl1 less than a nominal depth pl0, then it is possible that the electrical continuity between the source implant Simp and the source plane NISO is poorly established, which causes said increase in the resistance of the access transistor TA.

[0012] The inventors have further established a correlation between the increase in the resistance of the access transistor TA and the depth of lateral isolation regions STI, typically shallow isolation trenches.

[0013] Indeed, the trench containing the vertical gate is etched in particular in lateral isolation regions STI at the surface of the substrate, typically in silicon oxide, then in the substrate typically in monocrystalline silicon. However, the etching of the trench is much faster in silicon oxide than in the monocrystalline substrate.

[0014] Accordingly, for an equal etch time, the depth of the trench p11 will be smaller if the depth of the lateral isolation region p21 is smaller, and the depth of the trench p10 will be larger (or at a nominal value) if the depth of the lateral isolation region p20 is larger (or at a nominal value).

[0015] Finally, a depth p21 of the STI lateral isolation regions smaller than a nominal depth p20 provided in the design, can be caused by a phenomenon of stopping the etching of the shallow STI trenches, usually called "STI etch stop" in English.

[0016] This undesirable phenomenon is summarily caused by a saturation of etched material (reagent) or of products of the etching reaction, in an etched space that is too narrow w21. This phenomenon can occur with so-called random variations in the manufacturing processes, in particular with respect to the position on the semiconductor wafer (usually "wafer" in English), and is difficult to control.

[0017] Thus, embodiments and implementations of the aspects defined below propose forming lateral isolation regions comprising widened portions under the trench, and thinned portions outside the trench.

[0018] In other words, it is proposed to form active regions with a double width, the active regions comprising thinned portions under the trench, and widened portions outside the trench; given that the lateral isolation regions delimit the active regions in a superficial region of the semiconductor substrate.

[0019] It will be noted in particular that the solutions proposed in the embodiments and implementations defined below advantageously do not provide for modifying the chemical reaction used in the etching of the shallow isolation trenches STI, which would be costly and difficult to put into practice in existing processes; nor for globally modifying the nominal width w20 of the lateral isolation regions, which would globally affect the performance of the active regions; nor for increasing the etching time of the trench, which would also have an impact on other device formations using the same etching step of the vertically gated buried transistor.

[0020] Thus, according to one aspect, there is provided a method of manufacturing an integrated circuit, comprising forming lateral isolation regions, for example shallow isolation trenches, delimiting active regions in a semiconductor substrate, and etching a trench extending vertically deep into the substrate through said lateral isolation regions and said active regions. The formation of the lateral isolation regions is configured to form, at the location of said etching of the trench, widened portions of the lateral isolation regions delimiting thinned portions of the active regions.

[0021] As a result of this particular arrangement of widened portions of the lateral isolation regions delimiting thinned portions of the active regions at the location of said etching of the trench, the bottom of the trench will have a shape presenting variations in depth with low portions facing the lateral isolation regions thus etched, and high portions facing the active regions thus etched.

[0022] The lower portions reach a sufficient depth to ensure electrical continuity between the source implant and the source plane.

[0023] Thus, implementing the method according to this aspect in the context of manufacturing a memory having a buried access transistor with a vertical gate in the trench makes it possible to improve the performance and efficiency of the memory, in particular by reducing the resistance of the access transistor.

[0024] According to one embodiment, said formation of the lateral isolation regions delimits the active regions extending lengthwise in a first direction while said trench extends lengthwise in a second direction perpendicular to the first direction, said widened and thinned portions being larger and respectively smaller in width in the second direction at the location of the etching of the trench, than outside the location of the etching of the trench.

[0025] According to one embodiment, the formation of the lateral isolation regions comprises the production of a volume of dielectric material, for example silicon oxide, in the substrate, while the active regions of the substrate are made of a monocrystalline semiconductor material, for example silicon; dynamics of trench etching being faster in dielectric material than in single-crystal semiconductor material.

[0026] According to one embodiment, a gate of a buried access transistor with a vertical gate is formed in said trench etched deep in the substrate, and a stack of a floating gate and a control gate of a state transistor is formed covering at least in part said active regions in the vicinity of the trench.

[0027] According to another aspect, there is also provided an integrated circuit comprising lateral isolation regions delimiting active regions in a semiconductor substrate, and a component arranged in a trench extending vertically deep into the substrate through said lateral isolation regions and said active regions. The bottom of the trench has a shape having variations in depth with low portions facing the location of the trench which crosses the lateral isolation regions, and high portions facing the location of the trench which crosses the active regions.

[0028] For example, the depth variations have an amplitude greater than 50 nm.

[0029] According to one embodiment, the lateral insulation regions delimit the active regions extending lengthwise in a first direction, while said trench extends lengthwise in a second direction perpendicular to the first direction, the depth variations in the bottom of the trench having successive alternations in the direction of the second direction.

[0030] According to one embodiment, said lower portions are located in planes directed by the vertical direction and the first direction and crossing the lateral isolation regions, and said upper portions are located in planes directed by the vertical direction and the first direction and crossing the active regions.

[0031] According to one embodiment, the integrated circuit comprises a buried access transistor with a vertical gate, the vertical gate being the component arranged in said trench, and a state transistor comprising a stack of a floating gate and a control gate at least partially covering said active regions in the vicinity of the trench.

[0032] According to one embodiment, the bottom of the trench has a substantially hypo-trochoidal appearance, i.e. a shortened trochoid, in the second direction.

[0033] According to another aspect, there is also provided a semiconductor device, comprising lateral isolation regions defining active regions in a semiconductor substrate, wherein widened portions of the lateral isolation regions define thinned portions of the active regions.

[0034] The semiconductor device according to this aspect corresponds for example to the integrated circuit being manufactured in the process defined above, before the etching of said trench.

[0035] Thus, according to one embodiment, the semiconductor device is capable of being shaped by etching a trench as defined above; that is to say in particular a trench extending vertically in depth in the substrate through said lateral isolation regions and said active regions, at the location of the widened portions of the lateral isolation regions delimiting thinned portions of the active regions.

[0036] Other advantages and characteristics of the invention will appear on examining the detailed description of modes of implementation and embodiment, which are in no way limiting, and the appended drawings, in which the figures:

[0037] [Fig.lA] ;

[0038] [Fig.lB] ;

[0039] [Fig. IC] previously described, illustrate an example of memory technology non-volatile;

[0040] [Fig.2A];

[0041] [Fig.2B];

[0042] [Fig.2C];

[0043] [Fig.2D];

[0044] [Fig.3A];

[0045] [Fig.3B];

[0046] [Fig.3C];

[0047] [Fig.3D];

[0048] [Fig.4A];

[0049] [Fig.4B];

[0050] [Fig.4C];

[0051] [Fig.4D];

[0052] [Fig.5A];

[0053] [Fig.5B];

[0054] [Fig.5C];

[0055] [Fig.5D];

[0056] [Fig.6A];

[0057] [Fig.6B];

[0058] [Fig.6C];

[0059] [Fig.6D] illustrate modes of implementation and realization of the invention.

[0060] Figures 2A, 2B, 2C and 2D illustrate the result of a formation step of STI lateral isolation regions in a semiconductor substrate SUB of an integrated circuit manufacturing process, more particularly in a memory plane of the integrated circuit, intended to include memory cells.

[0061] An orthogonal reference frame XYZ is defined which is common to figures 2A-2D, as well as to figures 3A-3D, 4A-4D, 5A-5D, 6A-6D described below.

[0062] The first direction X and the second direction Y are located in the plane of the front face FA (see below), and the third direction Z is vertical.

[0063] [Fig.2A] illustrates a top view of the front face FA of the substrate SUB (see below).

[0064] [Fig.2B] illustrates a sectional view in the plane BB of [Fig.2A]. The plane BB directed by the first direction X and the vertical direction Z, and is positioned in the length of the active region ACT (see below).

[0065] [Fig.2C] illustrates a sectional view in the CC plane of [Fig.2A]. The CC plane is directed by the second Y direction and the vertical Z direction, and is positioned through the widened portions of the lateral isolation regions STIw+ and the thinned portions of the active regions ACTw- (see below).

[0066] [Fig.2D] illustrates a sectional view in the DD plane of [Fig.2A]. The DD plane is directed by the second Y direction and the vertical Z direction, and is positioned through lateral isolation regions STI having a nominal width STIw and active regions ACT having a nominal width ACTw (see below).

[0067] The front face FA of the substrate SUB is the face from which the devices of the semiconductor part are made, usually designated “FEOL” for “Front End Of Line” in English.

[0068] Before or after the formation of the lateral isolation regions STI, a deep implanted NISO region in the semiconductor substrate SUB has been formed. The deep implanted NISO region, of a dopant type opposite to the dopant type of the substrate SUB, will be able to provide the function of a source plane of memory cells. Conventionally, almost no other step is implemented prior to the formation of the lateral isolation regions STI.

[0069] The lateral isolation regions STI are formed in a superficial region of the semiconductor substrate SUB from the front face FA, i.e. a shallow region, for example of substantially 250 nm or between 150 nm and 350 nm.

[0070] The lateral isolation regions STI are obtained by a shallow isolation trench technique, i.e. they are obtained by etching shallow trenches (substantially 200 nm to 250 nm) opened in the surface region of the substrate SUB, and by filling the trenches with a dielectric material, typically silicon oxide.

[0071] The lateral isolation regions STI delimit active regions ACT of the substrate, which extend in length in the first direction X.

[0072] The step of forming the lateral isolation regions STI is configured to form enlarged portions of the lateral isolation regions STIw+ delimiting thinned portions of the ACTw- active regions.

[0073] The widened portions of the lateral isolation regions STIw+ delimiting thinned portions of the active regions ACTw- are positioned at the location of the subsequent etching GRTR of a trench extending vertically deep into the substrate SUB (Figures 3A-3D).

[0074] On the other hand, that is to say outside the location of the subsequent etching GRTR, the lateral isolation regions STI of this part of the semiconductor substrate have a nominal width STIw so as to define active regions ACT having a nominal width ACTw.

[0075] Thus, the widened portions STIw+ of the lateral isolation regions STI are larger (in width) in the second direction Y than the nominal width STIw; and respectively the thinned portions ACTw- of the active regions ACT are smaller (in width) in the second direction Y than the nominal width ACTw.

[0076] Figures 3A, 3B, 3C and 3D illustrate the memory plane during the start of a trench GRTR etch step extending deep into the SUB substrate.

[0077] [Fig.3A] illustrates a top view of the front face FA of the substrate SUB.

[0078] [Fig.3B] illustrates a sectional view in plane BB of [Fig.3A] (identical to plane BB of [Fig.2A]).

[0079] [Fig.3C] illustrates a sectional view in plane CC of [Fig.3A] (identical to plane CC of [Fig.2A]).

[0080] [Fig.3D] illustrates a sectional view in the DD plane of [Fig.3A] (identical to the DD plane of [Fig.2A]).

[0081] The GRTR etching of the TR trench is positioned so as to extend lengthwise in the second direction Y and to cross perpendicularly to its length, a succession of widths of lateral isolation regions STI and active regions ACT.

[0082] Thus, the etching of the trench GRTR vertically crosses said widened portions STIw+ of the lateral isolation regions STI and said thinned portions ACTw- of the active regions ACT.

[0083] The GRTR etching technique of the TR trench is typically a dry etching of the reactive ion type, usually "RIE" for "Reactive Ion Etching". This type of etching conventionally presents rapid dynamics in the dielectric material of the lateral isolation regions STI, typically silicon oxide, than in the semiconductor material of the active regions ACT, typically monocrystalline silicon.

[0084] Accordingly, by the time the GRTR etch reaches the bottom of the shallow isolation trenches STI, the portions opposite the position of the shallow isolation regions STI are more deeply etched than the portions opposite the position of the shallow isolation regions STI. with regard to the position of the active ACT regions.

[0085] Thus, the bottom of the trench TR being etched has a shape presenting variations in depth with low portions at the location of the trench crossing lateral isolation regions STI, and high portions at the location of the trench crossing active regions ACT.

[0086] Figures 4A, 4B, 4C and 4D illustrate the memory plane at the end of the GRTR etching step of the TR trench extending deep into the SUB substrate.

[0087] [Fig.4A] illustrates a top view of the front face FA of the substrate SUB.

[0088] [Fig.4B] illustrates a sectional view in plane BB of [Fig.4A] (identical to plane BB of Figures 2A and 3A).

[0089] [Fig.4C] illustrates a sectional view in the plane CC of [Fig.4A] (identical to the plane CC of Figures 2A and 3A).

[0090] [Fig.4D] illustrates a sectional view in the DD plane of [Fig.4A] (identical to the DD plane of Figures 2A and 3A).

[0091] Between the state of the GRTR etching illustrated in Figures 3A-3D and the end of the etching, only the semiconductor material of the substrate is etched, i.e., the monocrystalline silicon. Thus, the shape of the bottom of the trench does not change significantly until the end of the GRTR etching, only the depth pl, pl increases.

[0092] Thus, the bottom of the trench TR thus obtained has a shape presenting variations in depth with low portions PTB, at the depth pl, opposite the old lateral isolation regions STI before etching; and high portions PTH, at the depth pl 1, opposite the old active regions ACT before etching.

[0093] Furthermore, a Simp source region, also called a Simp source implant, is implanted in the substrate SUB, from the bottom of the TR trench, between the bottom of the TR trench and the NISO source plane. The Simp source implant is thus provided to ensure electrical continuity with the NISO source plane.

[0094] Figures 5A, 5B, 5C and 5D illustrate the memory plane after formation of a TRG gate structure in the TR trench extending deep into the SUB substrate.

[0095] [Fig.5A] illustrates a top view of the front face FA of the substrate SUB.

[0096] [Fig.5B] illustrates a sectional view in plane BB of [Fig.5A] (identical to plane BB of Figures 2A, 3A, 4A).

[0097] [Fig.5C] illustrates a sectional view in the plane CC of [Fig.5A] (identical to the plane CC of Figures 2A, 3A, 4A).

[0098] [Fig.5D] illustrates a sectional view in the DD plane of [Fig.5A] (identical to the DD plane of Figures 2A, 3A, 4A).

[0099] On the one hand, a gate dielectric layer was formed on the bottom and the sides of the trench TR thus opened in the semiconductor substrate SUB, typically by oxidation.

[0100] On the other hand, a gate conductive region was formed in the trench volume, typically by deposition of excess polycrystalline silicon overflowing over the FA front face, and a chemo-mechanical planarization step up to the FA front face.

[0101] The TRG gate structure thus arranged in the TR trench comprises the gate dielectric envelope on the sides and the bottom of the trench, and the gate conductive region in the volume delimited by the envelope and the front face FA.

[0102] We thus formed in the TR trench, a Simp source region, NISO, and the vertical gate structure TRG, of a buried access transistor TA, for memory cells of the memory plane.

[0103] Figures 6A, 6B, 6C and 6D illustrate the memory plane at the end of steps finalizing the formation of memory cells CEL1, CEL2, in particular the formation of state transistors TE.

[0104] [Fig.6A] illustrates a top view of the front face FA of the substrate SUB.

[0105] [Fig.ôB] illustrates a sectional view in plane BB of [Fig.ôA]. Plane BB is identical to plane BB of figures 2A, 3A, 4A, 5A and through the gate regions CG, FG of the state transistors TE in length and the vertical gate region TRG in width.

[0106] [Fig. 6C] illustrates a sectional view in the CC plane of [Fig. 6A]. The CC plane is identical to the CC plane of Figures 2A, 3A, 4A, 5A and passes through the vertical grid region lengthwise.

[0107] [Fig. 6D] illustrates a sectional view in the DD plane of [Fig. 6A]. The DD plane is identical to the DD plane of Figures 2A, 3A, 4A, 5A and crosses the gate regions of the state transistors in width.

[0108] The steps completing the formation of the memory cells CEL1, CEL2, comprise the formation of state transistors TE comprising a floating gate FG surmounted by a control gate CG.

[0109] The conduction regions of the state transistor TE are implemented in the active regions ACT. The drain region D is connected to a respective bit line BL1, BL2, while the source region (not shown) of the state transistor TE is also the drain region of the access transistor TA, and makes the series connection between the state transistor TE and the access transistor TA.

[0110] The bit lines BL1, BL2 are for example formed in a metal level extending above the memory plane in the first direction X.

[0111] The control grids CG can be made so as to extend in the second direction Y, being able to form control grid lines used to selectively access the memory cells, belonging to the same group called row.

[0112] The access transistor TA is also made so as to extend in the second direction Y, and can form a word line used to selectively access the memory cells, belonging to the same group called memory word.

[0113] The floating gates FG are formed so as to cover the active regions ACT of nominal width ACTw, specific to each memory cell CEL1, CEL2, on either side of the vertical gate TRG in the direction of the first direction X.

[0114] In particular, the interface between each floating gate FG and the underlying active region ACT is designed to implement charge injections by “tunnel effect” through a tunnel oxide layer, typically by Fowler-Nordheim effect and / or by injection of hot carriers resulting from impact ionizations.

[0115] The reliability and cycling performance of the memory cells CEL1, CEL2 are determined in particular by the width of the tunnel injection interface, i.e. by the nominal width ACTw of the active regions ACT. The greater the nominal width ACTw of the active regions ACT, the greater the reliability of the memory cells.

[0116] Thus, it will be possible to provide for the formation of the enlarged active regions ACT opposite the floating gates FG, that is to say with a width ACTw (here called nominal width) greater than the conventional nominal widths of active regions.

[0117] Indeed, it is possible to improve the reliability of the memory cells CEL1, CEL2, by widening the active regions ACT opposite the tunnel injection zones; without however causing the problem relating to the resistance of the access transistor TA, because the active regions ACT comprise thinned portions ACTw- at the location of the etching of the trench TR of the access transistor TA.

[0118] In practice, a compromise between increasing the nominal width ACTw and reducing the width of the thinned portions ACTw- will be found, depending on the design and drawing possibilities.

[0119] Furthermore, from the point of view of the final device obtained by the method described previously in relation to FIGS. 2A-D to 6A-D, the bottom of the trench TR containing the vertical grid TRG, has a shape presenting variations in depth with low portions PTB at a depth pl, and high portions HTB at a depth pl 1. The variations in depth pl-Pl 1 have for example an amplitude greater than 50 nm.

[0120] The lower portions PTB are located at the location of the trench TR which crosses lateral isolation regions STI, i.e. at the intersection between the trench TR (extending in the second direction Y) and the lateral isolation regions STI (extending in the first direction X).

[0121] The upper PTH portions are located at the location of the TR trench which crosses ACT active regions, i.e. at the intersection between the TR trench (extend in the second Y direction) and the ACT active regions (extend in the first X direction).

[0122] In other words, this structure can also be defined geometrically in that the low portions PTB are located in planes XZ_STI directed by the vertical direction Z and the first direction X and at a position crossing the lateral isolation regions STI (in the length X); and in that the high portions PTH are located in planes XZ_ACT directed by the vertical direction Z and the first direction X and crossing the active regions ACT.

[0123] In the sectional view of the plane CC, that is to say along the second direction Y, the shape of the bottom of the trench has a substantially hypo-trochoidal appearance, that is to say a shortened trochoid. A trochoid is a curve obtained by tracing the movement described by a point linked to a rolling disc without sliding on a straight line, a trochoid in which the point describing the curve is located on the circumference of the disc is called a cycloid, the point describing a shortened trochoid being located between the center of the center and the circumference of the circle (on the radius of the disc).

[0124] In summary, a non-volatile memory has been described having a double width of active regions, with a wider ACTw width in the tunnel injection areas, and a narrower ACTw- width at the location of the trench TR of the access transistor TA.

[0125] This configuration greatly improves the trade-off between cycling performance and the issue of etching stoppage of STI shallow isolation trenches; with improved uniformity of STI shallow isolation trench depth; without loss of pitch density; without requiring modification of the STI shallow isolation trench manufacturing process; and compatible with downscaling of potential technological development.

Claims

Claims

1. A method of manufacturing an integrated circuit, comprising forming lateral isolation regions (STI) delimiting active regions (ACT) in a semiconductor substrate (SUB), and etching a trench (GRTR) extending vertically deep into the substrate (SUB) through said lateral isolation regions (STI) and said active regions (ACT), wherein said forming of the lateral isolation regions (STI) is configured to form at the location of said etching of the trench (TR) widened portions of the lateral isolation regions (STIw+) delimiting thinned portions of the active regions (ACTw-).

2. Method according to claim 1, wherein said formation of the lateral isolation regions (STI) delimits the active regions extending in length in a first direction (X), while said trench (TR) extends in length in a second direction (Y) perpendicular to the first direction (X), said widened (STIw+) and thinned (ACTw-) portions being larger and respectively smaller in width in the second direction (Y) at the location of the etching of the trench (TR), than outside the location of the etching of the trench.

3. Method according to one of claims 1 to 2, in which the formation of the lateral isolation regions (STI) comprises a production of a volume of dielectric material in the substrate (SUB), while the active regions (ACT) of the substrate are made of a monocrystalline semiconductor material; the dynamics of the etching (GRTR) of the trench being faster in the dielectric material than in the monocrystalline semiconductor material.

4. Method according to one of claims 1 to 3, in which a gate of a buried access transistor (TA) with a vertical gate (TRG) is formed in said trench (TR) etched deep in the substrate, and a stack of a floating gate (FG) and a control gate (CG) of a state transistor (TE) is formed, at least partly covering said active regions (ACT) in the vicinity of the trench.

5. Integrated circuit comprising lateral isolation regions (STI) delimiting active regions (ACT) in a semiconductor substrate (SUB), and a component arranged in a trench (TR) extending vertically deep into the substrate (SUB) through said regions lateral isolation regions (STI) and said active regions (ACT), in which the bottom of the trench has a shape presenting variations in depth (pl, pl 1) with low portions (PTB) opposite the location of the trench which crosses the lateral isolation regions (STI), and high portions (PTH) opposite the location of the trench which crosses the active regions (ACT).

6. Integrated circuit according to claim 5, in which the depth variations (pl, fold) have an amplitude greater than 50 nm.

7. Integrated circuit according to one of claims 5 or 6, in which the lateral insulation regions (STI) delimit the active regions extending lengthwise in a first direction (X), while said trench (TR) extends lengthwise in a second direction (Y) perpendicular to the first direction (X), the variations in depth in the bottom of the trench having successive alternations in the direction of the second direction (Y).

8. Integrated circuit according to claim 7, wherein said low portions (PTB) are located in planes (XZ_STI) directed by the vertical direction (Z) and the first direction (X) and crossing the lateral isolation regions (STI), and said high portions (PTH) are located in planes (XZ_ACT) directed by the vertical direction (Z) and the first direction (X) and crossing the active regions (ACT).

9. Integrated circuit according to one of claims 5 to 8, comprising a buried access transistor (TA) with vertical gate (GV), the vertical gate (TRG) being the component arranged in said trench (TR) a state transistor (TE) comprising a stack of a floating gate (FG) and a control gate (CG) at least partly covering said active regions (ACT) in the vicinity of the trench (TR).

10. Integrated circuit according to one of claims 5 to 9, in which the bottom of the trench (TR) has a substantially hypo-trochoidal shape.

11. A semiconductor device, comprising lateral isolation regions (STI) defining active regions (ACT) in a semiconductor substrate (SUB), wherein widened portions of the lateral isolation regions (STIw+) define thinned portions of the active regions (ACTw-).

12. A semiconductor device according to claim 11, capable of being shaped by etching a trench (GRTR) as defined in one of claims 1 to 4.

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