NON-VOLATILE MEMORY STRUCTURE WITH STACK IN VIA LOCATION AND CONDUCTIVE LINE ON THIS VIA

Abstract

Non-volatile memory (NVM) structure formed from a stack (190, 60) comprising a lower electrode (63, 193) and an upper electrode (67, 67') and at least one active material (65, 65', 66, 195) between the lower electrode and the upper electrode, said stack (190, 60) of the non-volatile structure (NVM) lining side walls as well as a bottom of a trench (174) and a hole (176) located in the extension of this trench, the hole and the trench being arranged in said insulating thickness 123a-125b), the stack being arranged at the bottom of the hole (176) on a first conductive line (111). Figure for abstract: 7

Description

Title of the invention: NON-VOLATILE MEMORY STRUCTURE WITH STACK IN VIA LOCATION AND CONDUCTIVE LINE ON THIS VIA Technical field

[0001] The present invention relates to the field of non-volatile memories formed from a stack of layers and comprising at least one layer of active material between two electrodes. It relates more particularly to that of FeRAM ferroelectric memories, OxRAM resistive memories and ferroelectric tunnel junction (FTJ) memories.

[0002] The present invention provides a microelectronic device with a non-volatile memory structure having an improved arrangement and an improved method of manufacturing such a device. PREVIOUS ART

[0003] Ferroelectric memories or FeRAM memories have the quality of being non-volatile, that is to say of being able to retain stored information even when their power supply is cut off, of consuming little energy, of having low writing and reading times, of being able to be integrated on chips in a massive way with low operating voltages and of having a low latency in accessibility and good immunity to radiation. In addition, this type of memory has a very high endurance in writing. These memories have an operation based on the ferroelectric properties of their active material placed between two electrodes.By applying a potential difference between the two electrodes creating an electric field of a value greater than the positive coercive field, the ferroelectric memory is placed in a state of high remanent polarization and by applying a potential difference creating an electric field of a value lower than the negative coercive field, the ferroelectric memory is placed in a state of low remanent polarization. The high remanent polarization state then corresponds to a first given logic state, for example '0' and the low remanent polarization state to a complementary logic state, for example '1', which allows the storage of the information.

[0004] Another type of memory called resistive such as OxRAM memories for "Oxide Resistive RAM" is based on an active material between two electrodes having at least two resistive states, corresponding to a highly resistive state ("HRS" state for "High Resistance State") and a weakly resistive state ("LRS" state for "Low Resistance State"), under the application of a voltage. The main qualities of OxRAM memories are that they are non-volatile, have write times and low read rates, to be able to be integrated on chips in a massive way, and to have low latency in accessibility and good immunity to radiation and temperature. OxRAM memories typically have a MIM (Metal-Insulator-Metal) structure comprising an active material of variable electrical resistance, generally a transition metal oxide, arranged between two metal electrodes. The transition from the "HRS" state to the "LRS" state is governed by the formation and rupture of at least one conductive filament between the two electrodes. This conductive filament is created thanks to the presence of oxygen vacancies present in the active layer of the memory. By modifying the potentials applied to the electrodes, it is possible to modify the distribution of the filament and thus modify the electrical conduction between the two electrodes.In the active layer, the electrically conductive filament is either broken or, on the contrary, reformed to vary the resistance level of the memory cell, during write cycles then resetting of this cell (SET operations, when the filament is reformed resulting in the LRS state, and RESET operations resulting in the HRS state, when the filament is broken again by respective application of a SET, VSET or RESET, VRESET voltage to the terminals of the electrodes).

[0005] Ferroelectric tunnel junction (FTJ) memories are memories that use the change in electrical resistance of a ferroelectric active material arranged between two electrodes to store information, with low volatility and high information density.

[0006] The aforementioned memories have in common that they are formed from a stack of layers comprising at least one active material arranged between two electrodes.

[0007] Nowadays, this type of memory stack is mainly achieved in a final metal interconnection level.

[0008] An example of implementation in an ultimate metallic interconnection level is given in the document entitled “16kbit HfO2:Si-based 1T-1C FeRAM Arrays De-monstrating High Performance Operation and Solder Reflow Compatibility”, François, 2021 IEDM. This document provides in particular a “2D” (in other words planar) arrangement of such a stack.

[0009] In order to increase the developed surface area of ​​the stack and improve performance, so-called "3D" arrangements have appeared. The document: “Ferroelectric deep trench capacitors based on Al:HfO2 for 3D non-volatile memory Applications”, Polakowski, 2014 IEEE International Memory Workshop (IMW) presents for example such a type of arrangement, in which the arrangement extends into a particular region in which a plurality of juxtaposed trenches have been formed.

[0010] The realization of such an arrangement may require dedicating a particular area of ​​a microelectronic device to the memory structure and additional and specific photolithography steps. It also poses difficulties in terms of making contact on the lower or upper electrode.

[0011] There is therefore a need to overcome one or more of the drawbacks mentioned above. Statement of the invention

[0012] According to one aspect the present invention provides a microelectronic device comprising:

[0013] - a substrate comprising a plurality of metallic interconnection levels su perposed,

[0014] - a non-volatile memory structure arranged on a first conductive line of a first metallic interconnection level, the non-volatile memory structure comprising a stack comprising a lower electrode and an upper electrode and at least one layer of active material between the lower electrode and the upper electrode, the device further comprising:

[0015] - the first conductive line of the first interconnection level, and a second conductive line of said first metallic interconnection level, the second conductive line being distinct from the first conductive line, the first conductive line and the second conductive line being arranged in the same first plane parallel or substantially parallel to a main plane of the substrate,

[0016] - a third conductive line belonging to a second metallic level interconnection level higher than said first level of interconnections, the third conductive line being arranged in a second plane parallel to the main plane of the substrate and above the first plane so that the first plane is arranged between the second plane and the main plane of the substrate, the third conductive line being connected to the second conductive line by means of a conductive via, the conductive via extending in an intermediate region between said first plane and said second plane, the lower electrode, the upper electrode and said at least one layer of active material of said stack of the non-volatile structure extending in the upper metal interconnection level and in said intermediate region.

[0017] With such a configuration, it is possible to implement a memory stack with a large developed surface area while limiting the space requirement in the plane of the memory structure and moving away from a so-called "front-end" area corresponding to the level in which components such as transistors are formed.

[0018] The non-volatile memory (NVM) structure may advantageously comprise a upper part of given cross-section and a lower part of cross-section different from the given cross-section.

[0019] Advantageously, the third conductive line and the conductive via pass through an insulating thickness, the insulating thickness extending over the first conductive line and the second conductive line, said stack of the non-volatile structure lining side walls as well as a bottom of a trench and a hole located in the extension of this trench, the hole and the trench being arranged in said insulating thickness, the stack being arranged at the bottom of the hole on the first conductive line.

[0020] Advantageously, the hole is provided with a width W1 and the trench is provided with a width W2 such that W2 > W1, so that the non-volatile structure comprises a lower portion and an upper portion widened relative to the lower portion. Such a configuration facilitates contact on the upper part of the memory structure.

[0021] According to one possible implementation, the cumulative height H of the hole and the trench is substantially equal to the cumulative height hc of the conductive via and the third conductive line.

[0022] Such a configuration contributes to the implementation of a memory structure integrated into the standard / conventional interconnection levels and having a large developed surface area but without having to provide specific design rules to design it.

[0023] According to one possible implementation, the lower electrode, the upper electrode and the at least one layer of active material of said stack of the non-volatile structure (NVM) extend in the form of a fourth conductive line, distinct from the third conductive line and belonging to the second metallic interconnection level and in the form of at least one other conductive via in the extension of the fourth conductive line and to contact the first conductive line.

[0024] In this case, advantageously, the fourth conductive line and said other via have a transverse profile (or a transverse section) substantially identical to that (resp. that) of the third conductive line and said conductive via.

[0025] Advantageously, the device may also be provided with an additional conductive via arranged on and in contact with an upper portion of the memory structure.

[0026] Preferably, the upper electrode is provided or coated with an area of ​​conductive material for filling the hole and the trench, the additional conductive via being disposed on and in contact with the upper portion of the memory structure without being disposed in contact with the active material or the lower electrode.

[0027] Similarly, advantageously another additional conductive via can be provided on the third conductive line.

[0028] Thus, according to one implementation possibility, one or more additional conductive or metallic interconnection levels may be provided on or above the non-volatile memory structure.

[0029] According to a first particular implementation, the non-volatile memory structure may be of the FeRAM type, the active material then being formed from a layer of ferroelectric dielectric.

[0030] According to an implemented variant, the non-volatile memory structure may be of the OXRAM type, the active material being formed from at least one layer of dielectric oxide.

[0031] According to another implemented variant, the non-volatile memory structure may be of the FTJ type, the active material being formed from at least one layer of ferroelectric dielectric in contact with a layer of another dielectric material.

[0032] According to another implemented variant, the non-volatile memory structure may be of the CB RAM type, the active material being formed from at least one layer of electrolyte.

[0033] According to another aspect, the present invention provides the implementation of a method for producing a microelectronic device as defined above.

[0034] According to another aspect, the present invention relates to a method of manufacturing a microelectronic device provided with a non-volatile memory (NVM) structure formed from a stack comprising at least one lower electrode and at least one upper electrode and at least one active material between the lower electrode and the upper electrode, the method comprising the following steps:

[0035] - providing a substrate coated with at least one insulating layer, a first line conductive and a second conductive line of a given interconnection level (Mx-1) extending in the insulating layer and in the same first plane parallel to a principal plane of the substrate,

[0036] - forming an insulating thickness on the first conductive line, the second line conductive and said insulating layer,

[0037] - forming in said insulating thickness, a hole revealing the first line conductive and a trench in the extension of this hole,

[0038] - deposit in the trench and in the hole a stack comprising at least at least one lower electrode layer, at least one active material layer and at least one upper electrode layer, said stack lining sidewalls and a bottom of the hole and the trench.

[0039] Such a method makes it possible to reconcile the large developed surface area of ​​the memory structure and the size of this structure.

[0040] Such a method also makes it possible to produce the memory structure without necessarily providing specific design rules.

[0041] In addition to the aforementioned advantages, carrying out the stack at a level remote from the components formed in a semiconductor layer of the substrate makes it possible to preserve it from steps with a high thermal budget.

[0042] Advantageously, the deposition in the trench and in the hole of said stack is followed by the filling of the trench and the hole by deposition of a metallic material, so as to fill the hole and the trench.

[0043] The deposition of the stack is typically a conformal deposition and can advantageously be carried out by ALD.

[0044] According to one possible implementation, the method may further comprise the formation in the insulating thickness of a conductive via in contact with the second conductive line and of a third conductive line on the conductive via.

[0045] According to a first possibility of implementing the method, the production of the conductive via and the third conductive line can comprise steps of:

[0046] - carrying out a first masking opposite the first conductive line and comprising at least one opening opposite the second conductive line,

[0047] - etching through the opening of the first masking of another trench and a another hole in the extension of the other trench and having a bottom revealing the second conductive line,

[0048] - filling the other trench and the other hole using at least one material driver,

[0049] the method further comprising:

[0050] - removal of the first masking and formation of a second masking comprising at minus an opening opposite the first conductive line, etching the insulating thickness through the opening of the second masking to form the trench and the hole.

[0051] According to a second possibility of implementing the method, the production of the conductive via and the third conductive line may comprise the formation of another trench and another hole in the extension of the other trench, the other hole having a bottom revealing the second conductive line, the hole revealing the first conductive line and the other hole revealing the second conductive line being formed concomitantly.

[0052] Advantageously, the trench, the other trench, the hole and the other hole may be formed by etching the insulating thickness through one or more openings of a first masking. The method may then further comprise steps of:

[0053] - filling the trench, the other trench, the hole and the other hole using of at least one conductive material,

[0054] - removal of the first masking and formation of a second masking opposite the second conductive line and the third conductive line, the second masking comprising at least one opening opposite the first conductive line,

[0055] the method further comprising steps of:

[0056] - removal of conductive material from the trench and hole by etching through opening the second masking, so as to free the trench and the hole again,

[0057] - formation of the stack in the trench and the hole.

[0058] According to one implementation possibility, the layer(s) of active material may be formed:

[0059] - of a ferroelectric dielectric, in particular an oxide such as Si-doped HfO2 or HfZrO2, or

[0060] - of a dielectric oxide such as HfO2, or

[0061] - of an electrolyte layer, in particular based on a metal oxide such as HfO2 or Al2O3 or Ta2O5 or based on a chalcogenide such as GeSe or GeTe or GeSbTe,

[0062] - of a stack of a ferroelectric dielectric and another dielectric.

[0063] Preferably, the other dielectric is chosen so as to have a large gap (i.e. a significant difference between its valence band and its conduction band) in order to have significant tunnel resistance at low thickness.

[0064] According to one possible implementation, the lower electrode and the lower electrode can be formed:

[0065] - of a layer of a first material chosen in particular from one or more of the following materials: Ti, TiN, W

[0066] - of a layer of a metallic material chosen in particular from one or more of the following materials: W, Cu, Al, AlCu, AlSi. Brief description of the drawings

[0067] The present invention will be better understood upon reading the description of exemplary embodiments given, for purely indicative and non-limiting purposes, with reference to the appended drawings in which:

[0068] [Fig.lA]

[0069] [Fig. IB] illustrate a particular arrangement of a non-volatile memory structure formed from a stack and integrated at the same level as that of a conductive via and a conductive interconnection line respectively.

[0070] [Fig.2A]

[0071] [Fig.2B]

[0072] [Fig.2C] illustrate different examples of stacks from which the non-volatile memory structure is likely to be formed.

[0073] [Fig.3] illustrates a possible starting structure for the implementation of a microelectronic device according to the invention.

[0074] [Fig.4A]

[0075] [Fig.4B]

[0076] [Fig.4C]

[0077] [Fig.4D]

[0078] [Fig.4E]

[0079] [Fig.4F] illustrate a first example of a method of manufacturing a structure of non-volatile memory formed from a stack in an insulating thickness in which one or more conductive vias and one or more conductive lines of a metallic interconnection level are also formed.

[0080] [Fig.5A]

[0081] [Fig.5B]

[0082] [Fig.5C]

[0083] [Fig.5D] illustrate a second example of a method for manufacturing a non-volatile memory structure for which the location of the stack in the form of a hole and a trench in an insulating thickness is made at that of a conductive via and a conductive line in this same thickness.

[0084] [Fig.6A]

[0085] [Fig.6B] illustrate stacking arrangements which are not part of the claimed invention.

[0086] [Fig.7] illustrates an exemplary embodiment in which the non-memory structure volatile is formed from a stack of layers and is connected to a conductive via arranged on this stack.

[0087] [Fig.8] illustrates a particular arrangement of a non-volatile memory structure with an upper part that forms a conductive line.

[0088] Identical, similar or equivalent parts of the different figures bear the same numerical references so as to facilitate the transition from one figure to another.

[0089] The different parts represented in the figures are not necessarily on a uniform scale, in order to make the figures more readable.

[0090] DETAILED DESCRIPTION OF PARTICULAR EMBODIMENTS

[0091] We first refer to figures 1A and 1B giving respectively, in a top view and in a perspective view, an example of a non-volatile memory structure NVM formed in a level Mx (with x greater than or equal to 1 and typically at least equal to 3) of interconnections of a microelectronic device.

[0092] The non-volatile memory structure NVM is here implemented in a level commonly called "back end" of the device, above an underlying "front-end" level and in which the semiconductor components and in particular the transistors are provided.

[0093] The non-volatile memory structure NVM may be for example of the FeRAM, or OxRAM or FTJ or CBRAM type and is provided with a lower portion 192A arranged on and in contact with a first conductive line 111, here a metal line of a given interconnection level Mx-1 among a plurality of metal interconnection levels of the microelectronic device.

[0094] This lower portion 192A may have the shape of a conductive via and is located at the same level as another conductive via 161. By “conductive via” is meant a conductive element called “vertical” and extending between two conductive lines of different levels and located in distinct planes.

[0095] The conductive via 161 here provides the connection between a second conductive line 112 of the same given level Mx-1 as the first line 111 and a third conductive line 163 of a level Mx higher than the given level. The first conductive line 111 and the second conductive line 112 are thus arranged in the same first plane Pb. The first conductive line 111 and the second conductive line 112 are distinct and preferably not connected and / or not intersecting.

[0096] The non-volatile memory structure NVM also comprises an upper portion 192B arranged at the same level Mx as the third conductive line 163. The third conductive line 163 is here arranged in the same second plane P2, parallel to the first plane PI, as the upper portion 192B of the NVM structure.

[0097] Preferably, the Mx level does not correspond to the last “back-end” level of the device so that there are one or more metal levels higher than the Mx level. Thus one or more additional levels (not shown) of conductive lines can be provided above the third conductive line 163. The NVM non-volatile memory structure is therefore advantageously provided here between the “front end” part of the device and the ultimate “back-end” level on which contact pads or bumps are typically arranged.

[0098] The upper portion 192B of the NVM memory structure may here be provided with a width W2 or critical dimension greater than the width or critical dimension Wi of the upper portion 192A (Wi and W2 being dimensions measured parallel to the x axis in [Fig.1B] and which correspond to the smallest dimension of a pattern measured parallel to the plane [O;x;y]). The width W2 may advantageously be provided of the order of that of a conductive line 163 located at the same level, for example between 20 nm and 60 nm.

[0099] The cumulative height H of the lower portion 192A and the upper portion 192B can be provided to be of the order of the cumulative height of the conductive via 161 and the conductive line 163. Thus, the arrangement of the NVM memory structure here does not necessarily induce any modification of design rules or loss of density.

[0100] The non-volatile memory structure NVM is formed of a stack 190 comprising at least one lower electrode and one upper electrode as well as at least one active material arranged between the lower electrode and the upper electrode. The lower electrode, the upper electrode and the active material of this memory stack extend here both in the upper interconnect metal level Mx and in an intermediate region Rn located between the first plane PI and the second plane P2.

[0101] Different stacking compositions can be considered depending on the type of NVM memory structure implemented.

[0102] A particular example of stack 60 is given in [Fig.2A] for a FeRAM type structure. It is provided with a lower electrode layer 63, coated with a ferroelectric dielectric layer 65, itself coated with an upper electrode layer 67. Advantageously, the lower electrode layer 63 can be arranged on and in contact with a metal layer 61. Similarly, a metal layer 69 can be advantageously arranged on and in contact with the upper electrode layer 67. The ferroelectric dielectric layer 65 can be for example based on HfO2 doped in particular with Si or based on HfZrO2, possibly doped, for example with lanthanum (La), or with aluminum (Al). The lower and upper electrode layers 63, 67 may be formed, for example, from TiN or W or from a stack of Ti and TiN for the lower electrode layer 63. 61.The metal layers 61, 69 can for example be provided based on W, Cu, Al, AlCu, AlSi.

[0103] A particular example of a stack for implementing an OxRAM type NVM structure is given in [Fig.2B]. It differs in particular from the stack described previously by the composition of at least one of its electrodes, here by the upper electrode layer 67', preferably containing an oxidizable conductive material such as for example Ta or Ti or Hf. The active layer arranged between the electrodes is a dielectric 65' of the dielectric oxide type, in particular an oxide of one of the oxidizable conductive materials mentioned previously, for example HfO2.

[0104] Another example of stacking is given in [Fig.2C] to form this time a non-volatile memory structure of the FTJ type. The active layer located between the electrodes here has the particularity of being formed of a stack of dielectric layers 65, 66 based on distinct dielectric materials. A first dielectric layer 65 corresponds in this particular example to a ferroelectric dielectric for example HfO2 doped with Si or HfZrO2, this first dielectric layer is coated here with a second dielectric layer 66 for example based on A12O3.

[0105] For the sake of simplification, one or other of the stacks of the figures shown in [Fig.2A], 2B, 2C are arranged in planar form. However, as can be seen in [Fig.1B], a particular stacking arrangement distributed in 3D on several distinct and non-parallel planes is provided here so as to give the structure NVM memory a large developed surface while limiting the size in the plane (in other words in a direction parallel to the plane [O;x;y] on [Fig.lB]

[0106] An improvement in the developed surface area of ​​the NVM memory structure makes it possible, in particular when it is a FeRAM, to increase its memory window and to better separate its memory states. Such an improvement makes it possible, in particular when it is an FTJ, to obtain a reduction in the total resistance of the structure and to be able, at constant current density, to increase the injected current. When the NVM structure is of the OxRAM type, an increase in the developed surface area makes it possible to reduce the so-called "forming" voltage necessary for the modification of its conductive state by creating conductive filaments and therefore to limit consumption.

[0107] As a variant of the examples described previously, it is possible to provide an NVM structure formed from a CB RAM type memory stack, comprising between a lower electrode and an upper electrode, at least one layer of electrolyte.

[0108] One of the electrodes may be for example made of Cu or Ag, while the other electrode is provided in Pt or TiN or TaN or W. The active material forming the electrolyte may be for example a chalcogenide for example GeSe, or GeTe, or GeSbTe or a metal oxide such as HfO2, or Al2O3, or Ta2O5.

[0109] Reference is now made to [Fig.3] which illustrates an example of a possible structure S from which a device as described above can be formed.

[0110] This structure S comprises a substrate 10 on which one or more electronic components, in particular transistors Tu, Tn, are arranged. The transistors Tu, Tn have a channel region arranged in a superficial semiconductor layer 11 of the substrate 10. The substrate 10 may be, for example, a solid substrate or a substrate of the semiconductor-on-insulator type, and in particular of the SOI (“Silicon On Insulator” or “silicon on insulator”) type.

[0111] The transistors Tu, Tn are here covered with one or more insulating layers 12, 13 through which one or more conductive elements 14 passing through, connected to the transistor(s) are provided. Manufacturing steps of the type commonly called “front-end-of-line” (FEOL) where components (transistors, capacitors, resistors) are formed from a semi-semiconductor layer of the substrate have thus been carried out here to produce such a device.

[0112] The assembly can then be advantageously covered with a part, represented schematically by a block 20 in broken lines, formed of one or more insulating layers and at least one metallic interconnection stage or level formed of vias and horizontal conductive lines in this or these insulating layers.

[0113] A first example of a method for producing a microelectronic device such as that previously described will now be given in connection with Figures 4A-4F.

[0114] The structure S described previously serves here in this example as a starting structure for the method.

[0115] This structure S is first coated with one or more insulating layers, here for example a stack of an insulating layer 103 made of a first material such as for example silicon nitride and another insulating layer 105 made of a second material such as for example silicon oxide.

[0116] A first conductive line 111 of an x-th (with x greater than or equal to 2) interconnection level Mx-1 and a second conductive line 112 of the same metallic interconnection level Mx-1 are then formed. For this, trenches are typically made in the insulating layers 103, 105 which are then filled with at least one conductive material, for example Cu.

[0117] The first conductive line 111 and the second conductive line 112 formed ([Fig.4A]) are arranged in the same first plane parallel or substantially parallel to a main plane of the substrate (i.e. a plane passing through the substrate 10 in the structure S and which is parallel to the plane [O;x;y] of the reference [O;x;y;z] given in [Fig.4A]).

[0118] One or more insulating layers are then formed covering the first conductive line 111 and the second conductive line 112 and the insulating layer 105. In the embodiment illustrated in [Fig.4B], a stack formed of an alternation of layers 123a, 123b made of a first insulating material such as for example silicon nitride and layers 125a, 125b made of a second insulating material such as silicon oxide is produced.

[0119] At least one trench 134 and at least one hole 136 located in the extension of this trench 134 are then formed in the insulating thickness 123a-125b thus created. The trench 134 here has a critical dimension (smallest dimension measured parallel to the main plane of the substrate) larger than that of the hole 136. Typically, the trench 134 extends mainly in a horizontal direction, in other words parallel to the main plane of the substrate, while the hole 136 extends mainly in a direction making a non-zero angle with that of the trench 134 and preferably vertical, in other words orthogonal to the main plane of the substrate.

[0120] To make the trench 134 and the hole 136 in its extension, one can proceed in different ways.

[0121] One method commonly referred to as a "via-first" method involves making an opening through the entire insulating thickness 123a-125a to form the hole 136 and then forming the trench 134 in the insulating layers 123b-125b. Another method commonly referred to as a "line-first" method involves making an opening through the upper insulating layers 125b-123b to form the trench 134 then, etch the bottom of the trench 134 in order to make the hole 136 in the insulating layers 123a-125a and in the extension of this trench 134.

[0122] The etching(s) of the insulating thickness 123a-125a to form the hole 136 and the trench 134 are typically carried out through at least one opening of a masking 148 arranged opposite the first conductive line 111. The masking 148 may be a resin mask, in particular a photosensitive resin mask, or a hard mask, for example made of amorphous carbon. For example, a dry etching based on CF4 may be implemented.

[0123] Then, the trench 134 and the hole 136 are filled using at least one conductive material 150, which can be formed from a stack of several metal layers, for example a stack of TaN, Ta, and Cu. Such filling is typically carried out as in [Fig.4D], after removing the first masking 148, by deposition then CMP planarization (CMP for “Chemical Mechanical Polishing”, i.e. chemical mechanical polishing).

[0124] The trench 134 filled with conductive material 150 forms a third horizontal conductive line 163, while the hole 136 filled with conductive material 150 forms a conductive via 161, in other words a vertical conductive element. The third conductive line 163 produced thus belongs to an xth level Mx of conductive or metallic lines.

[0125] A hole 176 is then formed in the insulating layer(s) 123a-125a having a bottom revealing the first conductive line 111 and a trench 174 in the insulating layer(s) 123b-125b. Similarly, for this purpose, a sequence of steps of the “line first” or “via first” type can be carried out. The trench 174 here has a critical dimension W2 (smallest dimension measured parallel to the main plane of the substrate) larger than that W1 of the hole 176 and typically extends mainly in a horizontal direction. The hole 176 extends in a typically vertical direction.

[0126] A memory stack 190 is then formed comprising at least one lower electrode layer, at least one active material layer and at least one upper electrode layer, the active material layer being arranged between the lower electrode layer and the upper electrode layer. The stack is made so as to line the side walls 174a and the bottom 174b of the trench 174 and to line the side walls 176a and the bottom 176b of the hole 176. In the case of a FeRAM stack, the lower electrode layer may be, for example, based on W, or TiN or formed from a Ti / TiN stack. The upper electrode layer may be, for example, based on W, or TiN. The active material layer may be a ferroelectric dielectric layer such as, for example, silicon-doped HfO2 or HfZrO2.

[0127] According to a particular embodiment illustrated in [Fig.4F], to form the lower electrode, the hole 176 and the trench 174 are first covered with a stack of layers 181, 183, for example based on Ti and TiN and with a thickness of, for example, between 5 nm and 20 nm. A layer 185 of ferroelectric dielectric, for example based on HfZrO2, is then deposited and has a thickness that may be, for example, between 5 nm and 15 nm. Then, a layer 187, for example based on TiN and with a thickness that may be, for example, between 5 nm and 20 nm, is deposited. The layers 181, 183, 185, 187 can be formed for example by an ALD (for “Atomic Layer Deposition”) type deposition process in order to obtain a conformal distribution on the side walls of the trench 174 and the hole 176 as well as at the bottom of the hole 176. The filling of the trench 174 and the hole 176 can then be completed by deposition of a metallic material 189, for example such as W.The trench 174 and the hole 176 are then preferably completely filled. The central region of the memory structure is thus mainly formed of this metallic material 189.

[0128] In the embodiment example which has just been described, the conductive via 161 and the third conductive line 163 are formed before even making the hole 176 and the trench 174 in which the NVM non-volatile memory stack is provided.

[0129] An alternative embodiment provides for concomitantly forming the holes 136, 176 for receiving the conductive via and the memory stack respectively. Preferably, the production of the trenches 174, 184 for receiving the third conductive line 163 and the memory stack respectively is also carried out concomitantly.

[0130] Thus, in the embodiment illustrated in [Fig.5A], after having formed the conductive lines 111, 112 and then covered these lines with the thickness 123a-125b of insulating layers, the holes 176, 136 and the trenches 174, 134 are formed by a “line first” or “via first” type method by carrying out one or more concomitant etchings in the insulating thickness 123a-125b. The etching can be implemented through a masking 248.

[0131] Then ([Fig.5B]), the holes 136, 176 and trenches 134, 174 are filled by means of at least one conductive material 150, typically deposited concomitantly in the holes 176, 136 and in the trenches 174, 134 and for example formed from a stack of TaN, Ta, and copper.

[0132] Then, a masking 186 is formed opposite the second conductive line 112 and the third conductive line 163. This masking 186, typically in the form of photosensitive resin or a hard mask, does not extend opposite the first conductive line 111 and thus comprises an opening opposite the first line driver 111.

[0133] The conductive material 150 is then removed ([Fig.5C]) from the hole 176 and from the trench 174 not protected by the masking 186. Etching, for example using wet etching, typically using HNO3 or NH4OH, can be implemented for this.

[0134] Then, after having removed the masking 186 for example using a plasma, the hole 176 and the trench 134 are then filled again using this time a memory stack. A memory stack of layers 181, 183, 185, 187, 189 as described previously can for example be used or a stack as described previously in connection with one or other of FIGS. 2A to 2C.

[0135] As a variant of one or other of the embodiments described previously, it is possible to form the NVM structure, starting from a structure different from that described in [Fig. 3]. For example, one can start from a structure such as illustrated in [Fig. 4A] and in which the conductive lines 111, 112 have already been produced or from a structure such as in [Fig. 4B] and in which the conductive lines 111, 112 have already been produced and covered with an insulating thickness.

[0136] The NVM memory structure whose embodiment has just been described has, due to the configuration of the trench and the hole in which it is formed, in particular the particularity of having at its upper face FS an area occupied by the upper electrode and the metallic material(s) in contact with this electrode which is much larger than that of the layer(s) of active material and the lower electrode. This makes it easier to make contact on the upper electrode and to avoid short circuits.

[0137] In an alternative embodiment illustrated in [Fig.6A], which is not part of the present invention and where a MEM memory stack is formed only in a portion of hole between two portions of conductive vias Vx+1, Vx, there is a risk, unlike the arrangement proposed for the NVM structure, of creating a short circuit in the event of misalignment.

[0138] Similarly, in another alternative embodiment illustrated in [Fig.6B] (which is not part of the present invention) where a MEM memory stack is formed only in a via hole between two conductive lines 211, 213 of distinct levels, a short circuit is created, unlike the arrangement proposed for the NVM structure.

[0139] Once the NVM memory structure is formed, other additional interconnect metal levels can then be made on the Mx level in which the third conductive line 163 and the upper part of the NVM structure are located.

[0140] Thus, it is possible to provide for forming in particular a conductive element or a via conductor 221 on the NVM structure whose embodiment has just been described. In the particular embodiment illustrated in [Fig.7], this conductive via 221 makes contact on the enlarged upper portion 192A of the stacked memory structure and in particular on a layer or on the metallic filling material 199 forming the electrode or arranged on the upper electrode of the NVM memory structure. The shape of this upper portion and the configuration of the stack of layers 181, 183, 185, 187, 189 forming the NVM structure here makes it possible to avoid any risk of short circuit.

[0141] The conductive via 221 can be arranged at the same via level Vx as another conductive via 231 making contact on the third conductive line 163 of level Mx of metal lines.

[0142] To form these conductive vias 221, 231, it is possible to start from a device such as described previously in connection with [Fig.4F] or [Fig.5D], which is coated with one or more insulating layers, for example an insulating layer 223a of silicon nitride and an insulating layer 223a of silicon oxide.

[0143] Holes are then made in the insulating layers 223a, 223a which are then filled with at least one conductive material.

[0144] Other metal levels and in particular one or more additional conductive lines on and in contact with the conductive vias 221, 231 (not shown in [Fig.7]) may then be optionally formed.

[0145] In a particular exemplary embodiment illustrated in [Fig.8], an upper portion of the non-volatile structure (NVM) forms a fourth conductive line 194 of the same interconnect metal level Mx as the third conductive line 163 and extends into another conductive via 191 to contact the first conductive line 111.

[0146] The assembly formed by the fourth conductive line 194 extended by the other conductive via 191 may have, in a transverse section plane (plane parallel to the plane [O; x; z] in [Fig. 8] and passing through the fourth conductive line 194 and the other conductive via 191) a profile substantially identical to that of the assembly formed by the third conductive line 163 and the conductive via 161. The NVM structure in the form of a fourth conductive line 194 and the conductive via 191 may thus advantageously have a total cross-section (section taken parallel to the plane [O; x; z]) substantially identical to the cross-section of the third conductive line 163 and the conductive via 161.Again, the NVM structure can be integrated with a metal Mx level and an inter-level R12 region, following similar design rules to those adopted to form the Mx level conductive lines and Vx vias without having to provide specific dimensions for this structure.

Claims

Claims

1. A microelectronic device comprising: a substrate (10) comprising a plurality of superimposed metal interconnection levels, - a non-volatile memory (NVM) structure arranged on a first conductive line (111) of a first metal interconnection level (Mx-1), the non-volatile memory (NVM) structure comprising a stack (190, 60) comprising a lower electrode (63, 193) and an upper electrode (67, 67') and at least one layer of active material (65, 65', 66, 195) between the lower electrode and the upper electrode, the device further comprising: - a second conductive line (112) of said first metal interconnection level (Mx-1), the second conductive line being distinct from the first conductive line, the first conductive line and the second conductive line being arranged in the same first plane parallel or substantially parallel to a main plane of the substrate,- a third conductive line (163) belonging to a second metallic interconnection level (Mx) higher than said first interconnection level (Mx-1), the third conductive line (163) being arranged in a second plane parallel to the main plane of the substrate and above the first plane so that the first plane is arranged between the second plane and the main plane of the substrate, the third conductive line (163) being connected to the second conductive line (112) via a conductive via (161), the conductive via (161) extending in an intermediate region (R 12) located between said first plane (PI) and said second plane (P2), the lower electrode (63, 193), the upper electrode (67, 67') and said at least one layer of active material (65, 65', 66, 195) of said stack (190, 60) of the structure non-volatile (NVM) extending into the upper interconnect metal level (Mx) and into said intermediate region (R 12).,

2. The microelectronic device of claim 1, wherein the non-volatile memory (NVM) structure comprises an upper portion (192B) of given cross-section and a lower portion (192A) of different cross-section than the given cross-section.

3. Microelectronic device according to one of claims 1 or 2, the third conductive line (163) and the conductive via (161) passing through an insulating thickness (123a-125b), the insulating thickness extending over the first conductive line (111) and the second conductive line (112), said stack (190, 60) of the non-volatile structure (NVM) lining side walls as well as a bottom of a trench (174) and a hole (176) located in the extension of this trench, the hole and the trench being arranged in said insulating thickness 123a-125b), said stack being arranged at the bottom of the hole (176) on the first conductive line (111).

4. Microelectronic device according to claim 3, in which the cumulative height H of the hole (176) and the trench (174) is substantially equal to the cumulative height hc of the conductive via (161) and the third conductive line (163).

5. Microelectronic device according to one of claims 3 or 4, wherein said hole (16) is provided with a width W1 and wherein the trench (14) is provided with a width W2 such that W2 > W1, so that the non-volatile structure (NVM) comprises a lower portion (192A) and an upper portion (192B) widened relative to the lower portion.

6. Microelectronic device according to one of the preceding claims, the lower electrode (63, 193), the upper electrode (67, 67') and the at least one layer of active material (65, 65', 66, 195) of said stack (190, 60) of the non-volatile structure (NVM) extend in the form of a fourth conductive line (194) distinct from the third conductive line (163) and belonging to the second metallic interconnection level (Mx) and in the form of at least one other conductive via (191) in the extension of the fourth conductive line (194), said other conductive via (191) being provided to make contact on the first conductive line (111).

7. A microelectronic device according to claim 6, wherein the fourth conductive line (194) and said other via (191) have a cross-section substantially identical to the cross-section of the third conductive line (163) and said conductive via (161).

8. Microelectronic device according to one of claims 1 to 7, further comprising an additional conductive via (221) arranged on and in contact with an upper portion (192B) of the memory structure.

9. A microelectronic device according to claim 8, wherein the upper electrode layer is provided or coated with a region of

10.

11. conductive material (189) for filling the hole (176) and the trench (174), said additional conductive via (221) being disposed on and in contact with said upper portion (192B) of the memory structure without being disposed in contact with the active material or the lower electrode. Microelectronic device according to one of the preceding claims, in which the non-volatile memory (NVM) structure is: - of the FeRAM type, the active material being formed of at least one layer of ferroelectric dielectric, or - of the OXRAM type, the active material being formed of at least one layer of dielectric, or - CBRAM type, the active material being formed of at least one layer forming an electrolyte, - of FTJ type, the active material being formed of at least one layer of ferroelectric dielectric in contact with a layer of another dielectric material. Method for manufacturing a microelectronic device provided with a non-volatile memory (NVM) structure formed from a stack comprising at least one lower electrode and at least one upper electrode and at least one active material between the lower electrode and the upper electrode, the method comprising the following steps: - providing a substrate (10) coated with at least one insulating layer, a first conductive line and a second conductive line of a given interconnection level (Mx-1) extending in the insulating layer and in the same first plane parallel to a principal plane of the substrate, - forming an insulating thickness (123a-125b) on the first conductive line (111), the second conductive line (112) and said insulating layer (103-105), - forming in said insulating thickness (123a-125b), a hole (176) revealing the first conductive line (111) and a trench (174) in the extension of this hole (174), - depositing in the trench (174) and in the hole (176) a stack comprising at least one lower electrode layer (191, 193, 61, 63), at least one layer of active material (195, 65, 65', 66) and at least one upper electrode layer (197, 199, 67, 69), said stack lining side walls (174a, 176a) and a bottom (176b, 177b) of the hole (176) and of the trench (174).

12. The method of claim 11, further comprising forming in said insulating thickness (123a-125b) a conductive via (161) in contact with the second conductive line (112) and a third conductive line (163) on said conductive via (161).

13. Method according to claim 12, wherein the production of the conductive via (161) and the third conductive line (163) comprises steps of: - producing a first masking (148) opposite the first conductive line (111) and comprising at least one opening opposite the second conductive line (112), - etching through said opening of the first masking (148) another trench (134) and another hole (136) in the extension of said other trench (134) and having a bottom revealing the second conductive line (112), - filling the other trench (134) and the other hole (136) using at least one conductive material, the method further comprising: - removing said first masking and forming a second masking comprising at least one opening opposite the first conductive line,etching the insulating thickness (123a-125b) through said opening of said second masking to form said trench (174) and said hole (176).,

14. The method of claim 12, wherein the production of the conductive via (161) and the third conductive line (163) comprises the formation of another trench (134) and another hole (136) in the extension of said other trench (134), said other hole (136) having a bottom revealing the second conductive line (112), said hole (176) revealing the first conductive line (111) and said other hole (136) revealing the second conductive line (112) being formed concomitantly.

15. The method of claim 13, wherein said trench (174), said further trench (134), said hole (176) and said further hole (136) are formed by etching the insulating thickness (123a-125b) through one or more openings of a first masking), the method comprising steps of: - filling said trench (174), said further trench (134), said hole (176) and said further hole (136) with at least one conductive material (150), - removing said first masking (248) and forming a second masking (186) opposite the second conductive line (112) and the third conductive line (163), the second masking (186) comprising at least one opening opposite the first conductive line (111), the method further comprising steps of: - removing said conductive material (150) from said trench (174) and said hole (176) by etching through the opening of said second masking (186), so as to release again said trench (174) and said hole (176), - forming said stack in said trench (176) and said hole (174).

16. Method according to one of claims 11 to 15, the deposition of the stack (190) being a conformal deposition carried out in particular by ALD.

17. Method according to one of claims 11 to 16, wherein said at least one layer of active material (195, 65, 65', 66) is formed: - of a ferroelectric dielectric, in particular an oxide such as Si-doped HfO2 or HfZrO2, or - of a dielectric oxide such as HfO2, or - of a metal oxide such as HfO2 or Al2O3 or Ta2O5 or a chalcogenide such as GeSe or GeTe or GeSbTe, - of a stack of a ferroelectric dielectric and another dielectric.

18. Method according to claim 17, in which the lower electrode and the lower electrode are formed: - of a layer of a first material chosen from one or more of the following materials: Ti, TiN, W - of a layer of a metallic material chosen from one or more of the following materials: W, Cu, Al, AlCu, AlSi.

19. Manufacturing method according to one of claims 11 to 18, in which the deposition in the trench (174) and in the hole (176) of said stack is followed by the filling of the trench (174) and the hole (176) by deposition of a metallic material (189), so as to fill the hole (176) and the trench (174).

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