Method of manufacturing an electronic device

Abstract

Method for manufacturing an electronic device The present description relates to a method for manufacturing an electronic device comprising:- forming a silicon nitride layer (105) of a first thickness on a dielectric layer (102);- doping by ion implantation a first portion (105A) of the silicon nitride layer, a second portion (105B) of said silicon nitride layer being protected from said ion implantation; and- partially etching the silicon nitride layer such that the first portion is etched to a first depth (p1) less than or equal to the first thickness and the second portion is etched to a second depth (p2) less than the first depth, said partial etching forming an etched silicon nitride layer (105') comprising a cavity (111) in all or part of the first portion. Figure for abstract: Fig. 1E

Description

Title of the invention: Method for manufacturing an electronic device Technical field

[0001] The present description relates generally to electronic devices, and in particular to the manufacture of electronic devices.

[0002] The present description relates in particular to the manufacture of an electronic device comprising an electronic component in a trench in a semiconductor substrate and another electronic component on the same semiconductor substrate. Prior art

[0003] When manufacturing an electronic device comprising different electronic components in and on the same semiconductor substrate, a manufacturer may seek to use the same manufacturing process for all or part of the electronic components, in particular for reasons of manufacturing cost. For example, the electronic components of the electronic device may be manufactured on the same manufacturing line. However, if the manufacturing process is implemented entirely on the entire semiconductor substrate, without separate processing such as providing protections, such as masks, any processing implemented applies to all of the electronic components.However, a treatment used to form one electronic component may not be suitable for another electronic component, and it is generally necessary to provide protections, such as masks, so that certain treatments are not applied to all electronic components.

[0004] Depending on the electronic device to be manufactured, and in particular depending on the different electronic components to be formed in and on the same semiconductor substrate, it may be complicated, or even impossible, to manufacture the different electronic components on the same manufacturing line. For example, it may be necessary to implement specific technological steps to form a trench electronic component, or vertical electronic component, in the semiconductor substrate and other specific technological steps to form another electronic component on the semiconductor substrate (so-called "planar" electronic component) which may be difficult to reconcile with the specific technological steps to form the trench electronic component.

[0005] It is specified that, when it is indicated that the electronic component is "on the semiconductor substrate", this does not necessarily mean that all the elements of this electronic component are on the semiconductor substrate, other elements can be formed in the semiconductor substrate but not in a trench formed in the semiconductor substrate.

[0006] The trench electronic component may be, for example, a capacitor, a selection transistor, a vertical transistor or a trench transistor. The electronic component on the semiconductor substrate may be, for example, a MOS transistor or a gate.

[0007] Furthermore, it is generally sought to use the smallest possible number of protective masks. Summary of the invention

[0008] There is a need for a manufacturing method for manufacturing an electronic device comprising different electronic components in and on the same semiconductor substrate, in particular an electronic component in a trench in the semiconductor substrate and another electronic component on the semiconductor substrate, and which does not require the use of specific technological steps to form all or part of the electronic components. It would be advantageous if this manufacturing method made it possible to use a reduced number of manufacturing steps, for example as many common manufacturing steps as possible, and / or the fewest protective masks.

[0009] One embodiment overcomes all or part of the drawbacks of known electronic device manufacturing methods.

[0010] One embodiment provides a method of manufacturing an electronic device comprising: - providing a semiconductor substrate covered with a dielectric layer; - forming a silicon nitride layer of a first thickness on the dielectric layer; - doping by ion implantation of a first portion of the silicon nitride layer located above a first semiconductor region of the semiconductor substrate, a second portion of said silicon nitride layer located above a second semiconductor region of the semiconductor substrate being protected from said ion implantation; - partial etching of the silicon nitride layer, the etching speed of the first portion being greater than the etching speed of the second portion so that the first portion is etched to a first depth less than or equal to the first thickness and the second portion is etched to a second depth less than the first depth, said partial etching forming a etched silicon nitride layer comprising a cavity in all or part of the first portion.

[0011] According to one embodiment, the etching speed of the first portion is greater than four times the etching speed of the second portion, for example greater than or equal to five times, or even ten times, the etching speed of the second portion.

[0012] According to one embodiment, the etching of the first portion stops before, or at, the dielectric layer, the dielectric layer forming for example a silicon nitride etching stop layer, the dielectric layer being for example made of silicon oxide.

[0013] According to one embodiment, the method comprises forming an insulating trench in the semiconductor substrate between the first semiconductor region and the second semiconductor region, the formation of said insulating trench being carried out before the formation of the silicon nitride layer.

[0014] According to one embodiment, the method comprises forming a trench in the second semiconductor region through the silicon nitride layer and the dielectric layer, preferably before partially etching the silicon nitride layer, the formation of said trench comprising for example dry etching.

[0015] According to one embodiment, the method comprises forming a polysilicon filling layer so as to at least fill the cavity and the trench, forming a first polysilicon region in said cavity and a second polysilicon region in said trench.

[0016] According to one embodiment, the method comprises the formation of a first layer of oxide, for example silicon oxide, on the sides and bottoms of the cavity and the trench, before the formation of the filling layer.

[0017] According to one embodiment, the method comprises removing the etched silicon nitride layer, after the formation of the filling layer, said removal comprising for example wet etching with a solution comprising phosphoric acid.

[0018] According to one embodiment, the method comprises the formation of a second oxide layer on the first and second polysilicon regions, and for example also on portions of the semiconductor substrate from which the dielectric layer has been removed, the formation of the second oxide layer being carried out after the removal of the etched silicon nitride layer.

[0019] According to one embodiment, the method comprises removing a second thickness of polysilicon in the second polysilicon region from a first face of the etched silicon nitride layer, the first polysilicon region being protected by a mask during this removal.

[0020] According to one embodiment, the first polysilicon region forms all or part of a first gate region of a first electronic component, said first gate region being on the first semiconductor region, and the second polysilicon region forms all or part of a second gate region of a second electronic component, said first gate region being in a trench in the second semiconductor region.

[0021] According to one embodiment, the first component is a MOS transistor, the method comprising: - the formation of a doped box in the first semiconductor region, before the formation of the silicon nitride layer; - the formation of insulating spacers on the sides of the first gate region; and - the formation of drain and source regions in the first semiconductor region.

[0022] According to one embodiment, the second component is a trench transistor, for example a trench selection transistor.

[0023] According to one embodiment, the partial etching of the silicon nitride layer is a wet etching, for example with a solution comprising phosphoric acid, or a solution based on hydrofluoric acid.

[0024] According to one embodiment: - the first depth is greater than or equal to 80% of the first thickness, for example substantially equal to the first thickness; and / or - the second depth is less than or equal to 50% of the first thickness, for example less than or equal to 20% of the first thickness, or even less than or equal to 10% of the first thickness.

[0025] According to one embodiment, the doping of the first portion of the silicon nitride layer is configured to dope a first sub-layer in contact with the dielectric layer less than a second sub-layer above the first sub-layer, such that, during the partial etching of the silicon nitride layer, the cavity formed in the silicon nitride layer comprises a first portion corresponding to the less doped first sub-layer and a second portion corresponding to the more doped second sub-layer, the second portion being wider than the first portion, for example the second portion having a wider doped shape than the first portion having a cylindrical shape.

[0026] Another embodiment provides an electronic device comprising: - a first electronic component including a first gate region on a first semiconductor region of a semiconductor substrate; and - a second electronic component including a second gate region in a trench in a second semiconductor region of the semiconductor substrate, the first gate region having a thickness greater than 50 nm, for example greater than or equal to 100 nm.

[0027] According to one embodiment, the first gate region comprises a first portion on the semiconductor substrate and a second portion on the first portion, the second portion being wider than the first portion, for example the first portion having a cylindrical shape and the second portion having a curved shape wider than the first portion.

[0028] One embodiment provides an electronic device obtainable during one of the manufacturing methods described above. Brief description of the drawings

[0029] These characteristics and advantages, as well as others, will be explained in detail in the following description of particular embodiments given without limitation in relation to the attached figures among which:

[0030] [Fig.lA], [Fig.lB], [Fig.lC], [Fig.lD], [Fig.lE], [Fig.lF], [Fig.lG], [Fig.lH], [Fig.ll], [Fig.U], [Fig.lK], [Fig.lL], [Fig.lM], [Fig.lN], [Fig.l0], [Fig.lP] and [Fig.lQ] are sectional views showing steps of a method of manufacturing an electronic device according to one embodiment;

[0031] [Fig.2] is a sectional view showing an electronic device according to one embodiment; and

[0032] [Fig.3A] and [Fig.3B] are sectional views showing a variation of the manufacturing method of Figures 1A to 1Q. Description of the embodiments

[0033] The same elements have been designated by the same references in the different figures. In particular, the structural and / or functional elements common to the different embodiments may have the same references and may have identical structural, dimensional and material properties.

[0034] For the sake of clarity, only the steps and elements useful for understanding the described embodiments have been shown and are detailed. In particular, not all the steps of the method of manufacturing the electronic components have been described, being achievable with the usual microelectronics methods. Similarly, not all the details of the electronic components have been described. Furthermore, not all the applications that the described electronic devices may have have been detailed.

[0035] Unless otherwise specified, when referring to two elements connected to each other, this means directly connected without intermediate elements other than conductors, and when referring to two elements connected (in English "coupled") between them, this means that these two elements can be connected or linked through one or more other elements.

[0036] In the following description, when reference is made to absolute position qualifiers, such as the terms "front", "back", "top", "bottom", "left", "right", etc., or relative position qualifiers, such as the terms "above", "below", "upper", "lower", etc., or to orientation qualifiers, such as the terms "horizontal", "vertical", etc., reference is made, unless otherwise specified, to the orientation of the figures or to an electronic device in a normal position of use.

[0037] Unless otherwise specified, the expressions "about", "approximately", "substantially", and "of the order of" mean to within 10%, preferably to within 5%.

[0038] When reference is made to a trench passing through the semiconductor substrate, this does not mean that the trench necessarily passes through the entire thickness of the semiconductor substrate. The trench may be formed from an upper face of the semiconductor substrate, which is the face covered by the dielectric layer and the silicon nitride layer described later.

[0039] When referring to a trench electronic component, reference is made to an electronic component primarily positioned in a trench passing through the semiconductor substrate, for example comprising a gate that is included in the trench. When referring to a planar electronic component, or to an electronic component on the semiconductor substrate, reference is made to an electronic component that is not positioned in a trench passing through the semiconductor substrate, and that comprises an element, for example a gate, positioned on the semiconductor substrate.

[0040] In the following description, the terms "insulator" and "conductor" mean respectively, unless otherwise specified, electrically insulating and electrically conductive.

[0041] [Fig.lA], [Fig.lB], [Fig.lC], [Fig.lD], [Fig.lE], [Fig.lF], [Fig.lG], [Fig.lH], [Fig.ll], [Fig.U], [Fig.lK], [Fig.lL], [Fig.lM], [Fig.lN], [Fig.l0], [Fig.lP] and [Fig.lQ], are sectional views showing a method of manufacturing an electronic device according to one embodiment.

[0042] [Fig. 1A] represents a starting structure comprising a semiconductor substrate 101 covered with a layer 102 of dielectric material, or dielectric layer.

[0043] The semiconductor substrate 101 may be a solid semiconductor substrate, for example made of silicon, without this being limiting. The semiconductor substrate 101 may be a semiconductor layer, for example a silicon layer, on a buried insulating layer of an SOI (Silicon On Insulator) structure. silicon on insulator). More generally, the semiconductor substrate 101 can be any semiconductor substrate in which a trench can be made.

[0044] The dielectric layer 102 is preferably an oxide layer, for example made of a silicon oxide, for example silicon dioxide (SiO2). According to variants, the dielectric layer 102 could be made of other insulating materials, such as in particular SiON, HfSiON, ZrO2, TiO2, TaO2 (non-limiting list).

[0045] Advantageously, the material of the dielectric layer 102 may be chosen to be less quickly etchable, or even not etchable, compared to silicon nitride (SiN). For example, the material of the dielectric layer 102 may be chosen to form an etch stop layer when the silicon nitride is etched. The dielectric layer 102 may form an interface layer between the semiconductor layer 101, for example made of silicon, and a silicon nitride layer 105 described later.

[0046] For example, the dielectric layer 102 has a thickness of between 1 and 50 nm.

[0047] A first semiconductor region 11 is defined in the semiconductor substrate 101 by first and second insulating trenches 103A, 103B. A second semiconductor region 12 is defined in the semiconductor substrate 101, isolated from the first semiconductor region 11 by the first insulating trench 103A. Although not shown, other semiconductor regions may be defined in the semiconductor substrate 101.

[0048] Doping by ion implantation, shown diagrammatically by the six vertical arrows, is carried out in the first semiconductor region 11, from the upper face of the semiconductor substrate 101 covered by the dielectric layer 102, so as to form a doped well 104. For example, if the first semiconductor region 11 is intended to form the drain, source and channel regions of an NMOS transistor, the well is P-doped. Alternatively, if the first semiconductor region 11 is intended to form the drain, source and channel regions of a PMOS transistor, the well is N-doped.

[0049] Although this is not shown, in order to properly define the ion implantation zone to form the doped well 104, it is possible to use a mask comprising in particular an opening located above the first semiconductor region 11, for example between the insulating trenches 103A, 103B, but covering other semiconductor regions, and in particular the second semiconductor region 12. This mask can be a mask already used to implant other semiconductor regions (not shown), i.e. open to these other semiconductor regions, and it is possible to provide for forming this opening in this existing mask. located above the first semiconductor region to implant this first semiconductor region.

[0050] [Fig.1B] represents a structure obtained after the deposition of a layer of silicon nitride 105 on the dielectric layer 102.

[0051] The thickness el (first thickness) of the silicon nitride layer 105 may be, for example, between 50 and 200 nm, for example equal to approximately 80 nm. These values ​​of the thickness el are not limiting, the thickness el being able, for example, to depend on the destructuring effect of the silicon nitride desired in the step described below.

[0052] [Fig. 1C] represents a structure obtained following the formation of a first mask 106 on the upper face of the silicon nitride layer 105, then doping by ion implantation, shown diagrammatically by the two vertical arrows, of the silicon nitride layer 105 through the first mask 106.

[0053] The first mask 106 comprises a first opening 106A leaving exposed a first portion 105A of the silicon nitride layer 105 positioned above the first semiconductor region 11, so that only this first portion 105A is doped by ion implantation.

[0054] Other portions 105B, 105C of the silicon nitride layer 105 are covered by this first mask 106. These other portions notably comprise a second portion 105B located above the second semiconductor region 12, and third portions 105C located on either side of the first portion 105A above the first semiconductor region 11.

[0055] The first mask 106 may be formed by depositing a photosensitive resin which is removed opposite the first portion 105A of the silicon nitride layer 105.

[0056] Other portions of the silicon nitride layer above other semiconductor regions defined in the semiconductor substrate could be covered by the first mask. Furthermore, the first mask could include several first openings leaving exposed several first portions of the silicon nitride layer, so that the silicon nitride layer could include several first doped portions, for example above other semiconductor regions defined in the semiconductor substrate.

[0057] The ion implantation parameters are preferably determined so that the etching rate of the first doped portion 105A is greater than the etching rate of the undoped portions 105B, 105C of the silicon nitride layer 105. The first portion 105A of the silicon nitride layer 105 can be said to be "destructured".

[0058] For example, the etching rate of doped silicon nitride can be up to 4 times, or 5 times, or even up to 10 times, higher than the etching rate of undoped silicon nitride.

[0059] The etching speed of the doped silicon nitride may vary depending on the type and / or number of implanted atoms. The person skilled in the art will know how to act on the type and / or number of implanted atoms to increase the etching speed of the doped silicon nitride. The etching speed of the doped silicon nitride may be a function of the modification of the crystal lattice of the silicon nitride induced by the ion implantation.

[0060] The implantation energy may be chosen to be able to reach the entire thickness of the nitride layer 105 in the first portion 105A, but this is not limiting and it may not reach the entire thickness of the nitride layer 105.

[0061] By way of example, for a thickness el of the silicon nitride layer 105 of between 60 and 200 nm, the implantation energy is between 10 and 150 keV.

[0062] The implanted atoms may be chosen from argon, nitrogen and phosphorus, but other atoms may be used. The person skilled in the art will know how to choose the appropriate atoms depending on the manufacturing process implemented.

[0063] [Fig. 1D] represents a structure obtained after removing the first mask 106, and forming a second mask 107 on the upper face of the silicon nitride layer 105, then etching a trench 109 passing through the silicon nitride layer 105, the dielectric layer 102 and the semiconductor substrate 101 over all or part of its thickness.

[0064] The second mask 107 comprises a second opening 107A leaving exposed a fourth portion 105D of the silicon nitride layer 105 positioned above the second semiconductor region 12, the second mask covering the remainder of the silicon nitride layer, so that the etching is localized in and under this fourth portion, and in the second semiconductor region 12.

[0065] The second mask 107 can be formed by depositing a photosensitive resin which is removed opposite the fourth portion 105D of the silicon nitride layer 105.

[0066] The second mask could comprise several second openings leaving exposed several fourth portions of the silicon nitride layer, so that several trenches could be formed, for example in other semiconductor regions defined in the semiconductor substrate.

[0067] The etching of the trench 109 is preferably a dry etching, of the plasma etching type.

[0068] In the example shown, the trench 109 does not pass through the semiconductor substrate 101 over its entire thickness.

[0069] [Fig. 1E] represents a structure obtained after removing the second mask 107, and etching the silicon nitride layer 105. This etching is a partial etching insofar as the silicon nitride layer is not entirely removed. This etching can be designated by the acronym NPB, from the English "Nitride Pull Back", or nitride removal.

[0070] During the NPB, the first doped portion 105A of the silicon nitride layer 105 is etched more quickly than the undoped portions 105B, 105C of the silicon nitride layer 105, typically at least 4 times or 5 times faster, up to 10 times. This can be referred to as the over-etching factor. Thus, the etched silicon nitride layer 105' has a cavity 111 located at the level of the first etched portion 105A, without it being necessary to provide a specific mask to produce this cavity, and without dry etching which could generate parasitic charges and / or defectivity problems.

[0071] Thus, the first doped portion 105A is etched over a first depth pl equal to the first thickness el, and the undoped portions 105B, 105C are etched over a second depth p2 less than the first depth pl, for example much less than the first depth pl. The first depth pl being equal to the first thickness el, the first portion 105A is etched over its entire thickness el, up to the dielectric layer 102.

[0072] the etching of the silicon nitride is preferably a wet etching, based on a solution. The solution is for example a solution comprising phosphoric acid (H3PO4), or a solution based on dilute hydrofluoric acid (HF). Such a solution has the advantage of making the etching of the silicon nitride very selective with respect to the silicon oxide which may constitute the dielectric layer 102. Thus, the silicon nitride can be etched while keeping the dielectric layer 102 practically intact. The solution can advantageously be hot, for example at a temperature greater than or equal to 160°C.

[0073] The parameters of the etching of the silicon nitride, in particular the composition and concentration of the solution, the duration and temperature of the etching, can be chosen so that the first depth p1 is equal to the first thickness el. The second thickness p2 can in particular depend on the over-etching factor and the first thickness el to be etched in the first portion 105A. For example, the second depth p2 can be between 10 and 50% of the first thickness el.

[0074] The second depth p2 is, for example, equal to approximately 10 to 20 nm for a thickness el of between 60 and 200 nm.

[0075] During this etching step, the semiconductor substrate 101 is not etched. The dielectric layer 102 is also preferably not etched, and may form an etching stop layer.

[0076] In the example shown, it can be seen that this etching etches the silicon nitride more than the material, for example SiO2, of the dielectric layer 102, so as to form a lateral withdrawal R of the silicon nitride above and on either side of the trench 109. This lateral withdrawal technique can be designated in English by the term "Nitride Pull Back", NPB, and makes it possible to produce a flared opening which can facilitate the subsequent filling of this trench. This lateral withdrawal R can for example be between 4 and 40 nm, for example between 10 and 20 nm.

[0077] [Fig. 1F] represents a structure obtained after the deposition of a first oxide layer 112, for example silicon oxide, on the structure of [Fig. 1E]. The first oxide layer 112 comes at the bottom and on the sides of the trench 109, at the bottom and on the sides of the cavity 111, and on the etched silicon nitride layer 105'.

[0078] This step of depositing the first oxide layer 112 may be preceded by a step of removing the exposed portions of the dielectric layer 102, for example at least the portion 102A of the dielectric layer located at the bottom of the cavity 111. This removal may be carried out by implementing wet etching, for example with a hydrofluoric acid (HF) solution.

[0079] This first oxide layer 112 can form a gate insulator layer for future gate regions, for example to form future transistors in the trench 109 and / or in the cavity 111. This oxide can be deposited or produced by growth, for example of the SiO2 or SiON type, with a thickness of, for example, 2 to 25 nm.

[0080] [Fig.1G] represents a structure obtained after the deposition of a first layer of polysilicon 113 (filling layer) on the first layer of oxide 112. The first layer of polysilicon 113 fills at least the trench 109 and the cavity 111, and may comprise a portion which extends above the first layer of oxide 112.

[0081] [Fig. 1H] represents a structure obtained after planarization of the first polysilicon layer 113, to remove the portion which extends above the first oxide layer 112, so that the polysilicon is flush with the upper face of the etched silicon nitride layer 105'. This planarization is for example carried out by the chemical mechanical polishing (CMP) technique. During this polishing, exposed portions of the first oxide layer 112 can also be removed, as shown.

[0082] A first polysilicon region 114 is thus formed on the first oxide layer 112 in the cavity 111 above the first semiconductor region. 11 of the semiconductor substrate 101 and a second polysilicon region 115 on the first oxide layer 112 in the trench 109 in the second semiconductor region 12 of the semiconductor substrate 101.

[0083] The first polysilicon region 114 may form a first gate region 130 in the cavity 111, for example the gate region of a first transistor (first electronic component), for example a MOS transistor 13, as described later in connection with [Fig. 1Q]. The thickness of the first polysilicon region 114, and thus of the first gate region 130 may be substantially equal to, or greater than or equal to, the depth pl of the cavity, i.e. the thickness el of the silicon nitride layer 105. The thickness of the first polysilicon region 114 may be greater than 50 nm, or even greater than 100 nm, for example between 50 and 200 nm.

[0084] The second polysilicon region 115 may form a second gate region 140 in the trench 109, for example the gate region of a second trench transistor (second electronic component), for example a selection transistor 14, as described further below in connection with [Fig.lQ].

[0085] More broadly, the embodiments allow forming a first polysilicon region on an oxide layer on a first semiconductor region of a semiconductor substrate, and a second polysilicon region on an oxide layer in a trench in a second semiconductor region of the same semiconductor substrate.

[0086] The following description shows that, according to the embodiments, a method for manufacturing a trench transistor in a semiconductor substrate can be carried out without impacting the manufacturing of a planar transistor on the semiconductor substrate, and vice versa. For example, the trench transistor and the planar transistor can be produced at the same time. The following description also shows that after the formation of the cavity in the silicon nitride layer and the filling of this cavity with polysilicon, common manufacturing steps can be implemented, for example along the same manufacturing line, to produce the two types of transistors, without having to multiply the masks. In addition, doping a portion of the silicon nitride layer to then etch the silicon nitride selectively in this doped portion makes it possible to avoid carrying out dry etching, other than dry etching to form the trench.This allows a polysilicon region to be formed without further dry etching (dry etching can be too impactful for nearby electronic components).

[0087] The following steps of the manufacturing method are specific to forming a trench transistor in the semiconductor substrate, such as a memory cell select transistor, adjacent to a MOS transistor on the semiconductor substrate. The manufacturing process may be adapted by the person skilled in the art to produce other electronic components including at least one electronic component in a trench in the semiconductor substrate and another electronic component on the semiconductor substrate.

[0088] [Fig. II] represents a structure obtained at the end of an optional step of removal by etching of a thickness of polysilicon in the trench 109, that is to say the removal of a thickness e2 (second thickness) of polysilicon in the second polysilicon region 115, from the upper face (first face) of the etched silicon nitride layer 105'. As a non-limiting example, the removal can be carried out so that the upper face of the second etched polysilicon region 115' arrives below the level of the dielectric layer 102. This etching of the polysilicon is, for example, a dry etching. During this etching removal of the polysilicon, the first polysilicon region 114 is preferably protected by a mask 116, which is then removed from the silicon nitride layer 105'.The portions 105C (third portions) of silicon nitride located above the first semiconductor region 11 may also be protected by the mask 116.

[0089] [Fig. 1 J] represents a structure obtained after removing the layer of etched silicon nitride 105'. Removal of silicon nitride can be achieved by wet etching using a phosphoric acid solution (H3PO4).

[0090] [Fig. 1K] represents a structure obtained after the deposition of a second oxide layer 117 on the structure of [Fig. U].

[0091] This step of depositing the second oxide layer 117 may be preceded by a step of removing the exposed portions of the dielectric layer 102. This removal may be carried out by implementing wet etching, for example with a hydrofluoric acid (HF) solution.

[0092] At the end of this step, all or part of a planar gate has been produced with the first polysilicon region 114 above the semiconductor substrate 101 co-integrated next to a vertical gate with the second polysilicon region 115 in the trench 109. Starting from this structure, different electronic components can be produced, including at least one planar electronic component and one trench electronic component. Figures 11 to 1Q described below show an example of electronic components that can be manufactured, i.e. an example of cointegration, starting from the structure of [Fig.U]. This example consists of forming stacks of gates on either side of the vertical gate to form memory cells, and a MOS transistor from the planar gate.This is a non-limiting example and other examples of co-integration of a planar electronic component with a vertical, or trench, electronic component may be envisaged by those skilled in the art.

[0093] [Fig. IL] represents a structure obtained after the deposition of a second layer of polysilicon 118 on the structure of [Fig. 1K].

[0094] [Fig. 1M] represents a structure obtained after removing a portion 118A of the second polysilicon layer 118 located above the first semiconductor region 11, for example by dry etching. Thus, the second polysilicon layer 118 is located above the second semiconductor region 12.

[0095] [Fig.lN] represents a structure obtained after the deposition of an oxide-nitride-oxide (ONO) layer 119 on the structure of [Fig.lM] then of a third layer of polysilicon 120 on the ONO layer 119.

[0096] [Fig. 10] represents a structure obtained after removing a portion 120A of the third polysilicon layer 120 located above the first semiconductor region 11, for example by dry etching. Thus, the third polysilicon layer 120 is located above the second semiconductor region 12.

[0097] The ONO layer 119 may be retained on the second oxide layer 117. The first polysilicon region 114 thus covered by the second oxide layer 117 and the ONO layer 119 may form a first gate region 130 above the first semiconductor region 11.

[0098] [Fig.lP] shows a structure obtained after the formation of lightly doped drain regions 131 (LDD) in the first semiconductor region 11 and insulating spacers 132 on the sides of the first gate region 130. The drain and source regions can then be formed in the first semiconductor region 11, with a channel forming region between these drain and source regions. Contact regions can be made, for example via silicided regions, on the drain, source and gate regions.

[0099] We thus obtain a MOS transistor 13 (first electronic component).

[0100] [Fig. 1Q] represents a structure obtained after etching the second polysilicon layer 118, the ONO layer 119 and the third polysilicon layer 120, so as to form state transistors 15 of memory cells separated by a selection transistor 14 (second electronic component) whose gate region 140 is in the trench 109.

[0101] Each state transistor 15 comprises a gate region 150 comprising for example a floating gate 151 formed by a portion of the second polysilicon layer 118 surmounted by a control gate 153 formed by a portion of the third polysilicon layer 120, the control gate being isolated from the floating gate by a portion 152 of the ONO layer 119. The gate region 150 of each state transistor 15 can be isolated by insulating spacers 154.

[0102] The electronic device 100 shown in [Fig.1Q] thus comprises a MOS transistor 13 whose gate region 130 is on the semiconductor substrate 101 (on the first semiconductor region 11) next to state transistors 15 of memory cells separated by a selection transistor 14 whose gate region 140 is in the trench 109 in the semiconductor substrate 101 (in the second semiconductor region 12). As indicated previously, this is a non-limiting example of co-integration of a planar electronic component with a vertical electronic component, but other examples of co-integration may be envisaged by the person skilled in the art. In particular, starting from a technology for manufacturing an electronic component in a trench, the embodiments make it possible to produce at least one planar electronic component.

[0103] [Fig.2] is a sectional view showing an electronic device according to one embodiment embodiment. [Fig.2] more generally illustrates an electronic device 200 which can be obtained by a manufacturing method according to one embodiment.

[0104] The electronic device 200 comprises: - a first electronic component 23 including a first gate region 230 on a first semiconductor region 11 of a semiconductor substrate 101; and - a second electronic component 24 including a second gate region 240 in a trench 109 in a second semiconductor region 12 of the semiconductor substrate.

[0105] A gate insulator layer 112 is preferably comprised between the first gate region 230 and the semiconductor substrate 101, and between the second gate region 240 and the semiconductor substrate 101.

[0106] The first and second electronic components may be separated by a first insulating trench 103A.

[0107] For example, the thickness of the first gate region 230 is greater than 50 nm, or even greater than or equal to 100 nm, for example between 50 and 200 nm.

[0108] [Fig.3A] and [Fig.3B] are sectional views showing a variant of the manufacturing method of Figures 1A to 1Q, in particular of the steps of Figures 1C to 1H. In Figures 3A and 3B, only the first semiconductor region 11 has been shown so as not to make the figure cumbersome, but the second semiconductor region 12 could be present, as well as other semiconductor regions in the same semiconductor substrate 101.

[0109] According to this variant, as shown in [Fig.3A], the doping by ion implantation of the silicon nitride layer 305 is carried out so as to dope more an upper portion 305S (second sub-layer) of the silicon nitride layer than a lower portion 3051 (first sub-layer) of this silicon nitride layer in contact with the dielectric layer 102. Thus, during the etching partial of the silicon nitride layer 305, the cavity 311 formed in the silicon nitride can take a particular shape. In the example shown, the cavity 311 comprises a lower portion 31 IA on the dielectric layer 102, the lower portion being substantially cylindrical, and an upper portion 31 1B on the lower portion 31 1A, the upper portion 31 1B having a wider domed shape than the lower portion.

[0110] As shown in [Fig.3B], when filling the cavity 311 with the first polysilicon layer, such as the first polysilicon layer 113 of [Fig.1G], a first polysilicon gate region 330 can be obtained, which comprises a first portion 330A in contact with the gate insulator layer 112 and a second portion 330B on the first portion 330A, the second portion 330B being wider than the first portion 330A, for example the first portion having a cylindrical shape and the second portion having a domed shape wider than the first portion. Other shapes of the first gate region can be envisaged.

[0111] This makes it possible, for example, to reduce the parasitic overlap capacitances between the gate region 330 formed in the cavity 311, the gate insulator 112 under the gate region 330 and the semiconductor substrate 101 under the gate insulator 112.

[0112] More broadly, the doping by ion implantation of the silicon nitride layer can be adapted to produce specific cavity shapes during the partial etching of the silicon nitride layer, so as to obtain a polysilicon region of specific shape.

[0113] The electronic devices obtained by the manufacturing methods described, more broadly by a manufacturing method according to one embodiment, can find applications in the fields of microcontrollers, the Internet of Things (IoT), analog circuits, memories, for example non-volatile memories (NVM), or memories of the EEPROM type (Electrically Erasable Programmable Read-Only Memory).

[0114] Various embodiments and variations have been described. Those skilled in the art will understand that certain features of these various embodiments and variations could be combined, and other variations will occur to those skilled in the art. In particular, a first planar electronic component is shown adjacent to a second trench electronic component, but other configurations are possible. For example, one or more other electronic components may be provided between the trench electronic component and the planar electronic component. The first planar electronic component may be an electronic component other than a MOS transistor, for example a capacitor, a resistor, etc. The second planar electronic component may be an electronic component other than a selection transistor, for example another transistor, a capacitor, etc. Furthermore, a polysilicon layer has been described for filling the trench and the cavity, but other conductive or semiconductive materials may be envisaged by the person skilled in the art, for example materials for forming a high-k metal gate, or HKMG, from the English High-K metal gate.

[0115] Finally, the practical implementation of the embodiments and variants described is within the reach of those skilled in the art from the functional indications given above.

Claims

Claims

1. A method of manufacturing an electronic device (100; 200) comprising: - providing a semiconductor substrate (101) covered with a dielectric layer (102); - forming a silicon nitride layer (105; 305) of a first thickness (el) on the dielectric layer; - doping by ion implantation a first portion (105A) of the silicon nitride layer located above a first semiconductor region (11) of the semiconductor substrate, a second portion (105B) of said silicon nitride layer located above a second semiconductor region (12) of the semiconductor substrate being protected from said ion implantation;- the partial etching of the silicon nitride layer, the etching speed of the first portion (105A) being greater than the etching speed of the second portion (105B) so that the first portion is etched to a first depth (pl) less than or equal to the first thickness (el) and the second portion is etched to a second depth (p2) less than the first depth, said partial etching forming an etched silicon nitride layer (105') comprising a cavity (111; 311) in all or part of the first portion.;

2. The method of claim 1, wherein the etching speed of the first portion (105A) is greater than four times the etching speed of the second portion (105B), for example greater than or equal to five times, or even ten times, the etching speed of the second portion.

3. Method according to claim 1 or 2, in which the etching of the first portion (105A) stops before, or at, the dielectric layer (102), the dielectric layer forming for example a silicon nitride etching stop layer, the dielectric layer being for example made of silicon oxide.

4. A method according to any one of claims 1 to 3, comprising forming an insulating trench (103A) in the semiconductor substrate (101) between the first semiconductor region (11) and the second semiconductor region (12), forming said insulating trench being made before the formation of the silicon nitride layer (105; 305).

5. A method according to any one of claims 1 to 4, comprising forming a trench (109) in the second semiconductor region (12) through the silicon nitride layer (105; 305) and the dielectric layer (102), preferably before partially etching the silicon nitride layer, the formation of said trench comprising for example dry etching.

6. A method according to claim 5, comprising forming a polysilicon filling layer (113) so as to at least fill the cavity (111; 311) and the trench (109), forming a first polysilicon region (114) in said cavity and a second polysilicon region (115) in said trench.

7. A method according to claim 6, comprising forming a first oxide layer (112), for example silicon oxide, on the sides and bottoms of the cavity (111) and the trench (109), before forming the filling layer (113).

8. A method according to claim 6 or 7, comprising removing the etched silicon nitride layer (105'), after the formation of the filler layer, said removal comprising for example wet etching with a solution comprising phosphoric acid.

9. A method according to claim 8, comprising forming a second oxide layer (117) on the first and second polysilicon regions (114, 115), and for example also on portions of the semiconductor substrate (101) from which the dielectric layer (102) has been removed, the formation of the second oxide layer being carried out after the removal of the etched silicon nitride layer (105').

10. A method according to any one of claims 5 to 9, comprising removing a second thickness (e2) of polysilicon in the second polysilicon region (115) from a first face of the etched silicon nitride layer (105'), the first polysilicon region (114) being protected by a mask (116) during this removal.

11. A method according to any one of claims 6 to 10, wherein the first polysilicon region (114) forms all or part of a first gate region (130; 230; 330) of a first electronic component (13; 23), said first gate region being on the first semiconductor region (11), and the second polysilicon region (115) forms all or part of a second gate region (140; 240) of a second electronic component (14; 24), said first gate region being in a trench (109) in the second semiconductor region (12).

12. The method of claim 11, wherein the first component (13) is a MOS transistor, the method comprising: - forming a doped well (104) in the first semiconductor region (11), before forming the silicon nitride layer (105; 305); - forming insulating spacers (132) on the flanks of the first gate region (130); and - forming drain and source regions in the first semiconductor region (11).

13. A method according to claim 11 or 12, wherein the second component is a trench transistor (14), for example a trench select transistor.

14. Method according to any one of claims 1 to 13, in which the partial etching of the silicon nitride layer (105; 305) is a wet etching, for example with a solution comprising phosphoric acid, or a solution based on hydrofluoric acid.

15. Method according to any one of claims 1 to 14, in which: - the first depth (pl) is greater than or equal to 80% of the first thickness (el), for example substantially equal to the first thickness; and / or - the second depth (p2) is less than or equal to 50% of the first thickness (el), for example less than or equal to 20% of the first thickness, or even less than or equal to 10% of the first thickness.

16. The method of any one of claims 1 to 15, wherein the doping of the first portion of the silicon nitride layer (305) is configured to less dope a first sub-layer (3051) in contact with the dielectric layer (102) relative to a second sub-layer (305S) above the first sub-layer, such that, upon partial etching of the silicon nitride layer (305), the dielectric layer (102) is less dope than the ... silicon nitride, the cavity (311) formed in the silicon nitride layer comprises a first portion (311 A) corresponding to the first less doped sub-layer and a second portion (31 IB) corresponding to the second more doped sub-layer, the second portion being wider than the first portion, for example the second portion having a wider domed shape than the first portion having a cylindrical shape.

17. Electronic device (100; 200) obtained by the manufacturing method according to any one of claims 1 to 16, the electronic device comprising: - a first electronic component (13; 23) including a first gate region (130; 230; 330) on a first semiconductor region (11) of a semiconductor substrate (101); and - a second electronic component (14; 24) including a second gate region (140; 240) in a trench (109) in a second semiconductor region (12) of the semiconductor substrate, the first gate region having a thickness greater than 50 nm, for example greater than or equal to 100 nm.

18. The electronic device (100; 200) of claim 17, wherein the first gate region (330) comprises a first portion (330A) on the semiconductor substrate and a second portion (330B) on the first portion, the second portion being wider than the first portion, for example the first portion having a cylindrical shape and the second portion having a domed shape wider than the first portion.

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