INTERCONNECTION STRUCTURE WITH VIAS CROSSING METALLIC LEVELS

Abstract

Implementation of a microelectronic device comprising: - a substrate coated with a stack comprising one or more conductive tracks (106a, 106b, 106c, 106) of a "lower (M1, Mk)" level, this lower level being coated with an "intermediate" insulating layer (113), the intermediate insulating layer being coated with one or more conductive tracks (116a, 116b, 116c, 216) of a "higher (M2, Mk +1)" level, - a conductive element (156b) passing through the intermediate insulating layer (113) and in contact with a first conductive track (106b, 206) of a given level among the higher (M2, Mk +1) and lower (M1, Mk) levels, while being isolated, via an insulating spacer (141e), from a second conductive track (116b, 216) of another level among the lower level and the upper level, the insulating spacer (141e) being disposed between the second conductive track (116b;216) and the conducting element (156b), the conducting element (156b) having a "lower" end (1562) making contact with a first region (102A, 102), conductive or semiconductive, of the substrate or stack, the conducting element (156a; 156b) passing through the first conductive track (106b, 206) and the second conductive track (116b, 216) and being surrounded by the insulating spacer (141e). Figure for the abstract: 21.;

Description

Title of the invention: INTERCONNECTION STRUCTURE A VIAS CROSSING METALLIC LEVELS

[0001] TECHNICAL FIELD AND PRIOR TECHNOLOGY

[0002] The present application relates to the field of microelectronics and

[0003] integrated circuits and relates more particularly to the implementation of an interconnection structure, with vertical connection elements commonly called "vias", having an improved arrangement.

[0004] Vias play a crucial role in the performance of electronic circuits, particularly with regard to interconnection density and electrical performance.

[0005] A via refers to an electrical connection element, disposed in an opening and passing through one or more layers or regions of a stack. This connection element is typically "vertical," that is, it extends orthogonally or substantially orthogonally to a principal plane of a substrate on which the layers or stack are formed. A via thus makes it possible to electrically connect regions belonging to different levels of a microelectronic device.

[0006] In some cases, it is desirable to be able to electrically connect regions belonging to non-adjacent levels arranged on a substrate, that is to say, separated by one or more intermediate levels of conductive elements or intermediate devices. For example, it may be desirable to connect a trace of a third metallic interconnection level, commonly called "metal 3", with a metallic trace of a first metallic interconnection level commonly called "metal 1", while avoiding contact on a trace of the intermediate metallic level, here a second metallic interconnection level called "metal 2".

[0007] To avoid unwanted connections or to avoid disrupting the operation of intermediate level devices traversed, the vertical connection elements can be formed at a certain distance from the access areas to these intermediate level devices, in other words by bypassing them.

[0008] Nevertheless, this results in a reduction of the integration density.

[0009] Document FR3030881 from the applicant presents a method for isolating certain lateral portions of a via in order to avoid unwanted electrical contact with one or more intermediate levels.

[0010] The problem therefore arises of making contacts that allow electrical connection of elements of non-adjacent levels without this being at the expense of the integration density. Description of the invention

[0011] It is therefore an object of the present invention to provide a microelectronic device comprising:

[0012] - a substrate coated with a stack comprising one or more tracks conductive layers of a so-called "lower" level, this lower level being covered with an insulating layer called an "intermediate" layer, the intermediate insulating layer being covered with one or more conductive tracks of a so-called "higher" level,

[0013] - a conductive element passing through the intermediate insulating layer and in contact with a first conductive track of a given level among the upper and lower levels, while being isolated, by means of an insulating spacer, from a second conductive track of another level among the lower and upper levels, the insulating spacer being disposed between the second conductive track and the conductive element, the conductive element having a so-called "lower" end making contact on a first region, conductive or semiconductive, of the substrate or stack,

[0014] the conductive element passing through the first conductive track and the second conductive track and being surrounded by the insulating spacer.

[0015] With such a device, and such an arrangement of interconnection structure, it is possible to make connections between different and non-adjacent floors while limiting the bulk, which promotes obtaining a better integration density.

[0016] Advantageously, the device may further comprise a second conductive element having a lower end making contact with a second region, conductive or semiconductive, of the substrate or stack, the second conductive element passing through a conductive track of the given level as well as the intermediate insulating layer and a conductive track of said other level, the second conductive element being isolated, by means of a second insulating spacer, from the conductive track of the given level which the second conductive element passes through, the second conductive element being in contact with the conductive track of the other level which it passes through.

[0017] With such an interconnection structure arrangement, independent connections can be made on two separate superimposed stages while improving the integration density.

[0018] According to one possible implementation of the device in which the conducting element and the second conducting element each pass through the first conductive track of the given level and respectively cross the second conductive track of the other level and a third conductive track of the other level distinct from the second conductive track, the second conductive track and the third conductive track extending parallel or substantially parallel to a first direction parallel to a principal plane of the substrate, the first conductive track extending in a second direction orthogonal to the first direction, or

[0019] - in which the conducting element and the second conducting element pass through each person takes the first conducting track of the given level and each person takes the second conducting track of the other level.

[0020] Such a structure is thus particularly suited to making contacts on conductive tracks of distinct levels and having a crossed arrangement or of the type commonly called "crossbar" or to making contacts on parallel and superimposed conductive tracks of distinct levels.

[0021] According to one possible implementation of the device, the stack includes a so-called "lower" insulating layer on which one or more conductive tracks of the given level are arranged, the first region being arranged between an area of ​​the substrate and the lower level, the conductive element also passing through the lower insulating layer.

[0022] Advantageously, the first region is a region of a semiconductor layer of the substrate or resting on the substrate.

[0023] Such a structure makes it possible to establish a selective contact between a semiconducting layer and one or more metallic interconnection levels while limiting the bulk.

[0024] According to a particular implementation possibility, the first region can form a quantum island. Such a structure is thus advantageously suited to addressing and / or biasing a matrix quantum circuit.

[0025] According to a particular embodiment, the first region can be a source or drain region of a transistor. Such a structure is thus advantageously suited to addressing and / or biasing transistors.

[0026] According to a particular embodiment, the insulating spacer can be based on a material capable of reversibly changing resistance and / or state between an amorphous phase and a crystalline phase, in particular under the effect of an electric current.

[0027] Such a structure is thus advantageously suited to the realization of ReRAM or PCMRAM memory circuits.

[0028] Advantageously, the first region can be a region of a semiconductor layer while the second region is another region of that semiconductor layer.

[0029] This application also relates to a method for making a microelectronic device as defined above.

[0030] According to another aspect, the present application also relates to a method for the production of a microelectronic device comprising the following steps:

[0031] a) provide a substrate coated with a stack comprising one or more conductive tracks of a so-called "lower" level, the lower level being coated with an insulating layer called "intermediate", the intermediate insulating layer being coated with one or more conductive tracks of a so-called "upper" level,

[0032] b) formation of a first opening and a second opening in the stack and each passing through a conductive track of the upper level, the intermediate insulating layer, and a conductive track of the lower level, the first opening exposing at least a first portion and the second opening exposing at least a second portion of one or more conductive tracks of the upper level, the first opening further exposing at least a third portion and the second opening further exposing at least a fourth portion, respectively of one or more conductive track(s) of the lower level,

[0033] c) formation in the first opening of a first insulating spacer against the first portion while leaving the third portion exposed and in the second opening of a second insulating spacer against the fourth portion while leaving the second portion exposed,

[0034] d) filling the first opening and the second opening with at least one conductive material, so as to form a first conductive element and a second conductive element, the first conductive element being in contact with the third portion and being isolated from the first portion by means of the first spacer, the second conductive element being in contact with the second portion while being isolated from the fourth portion by means of the second spacer.

[0035] Advantageously, step c) may include at least the following steps:

[0036] cl) deposition of a first thin insulating layer lining the walls of the first and second openings,

[0037] c2) partial etching of the first thin insulating layer at the level of the part upper part of the first opening, so as to expose the first portion, while preserving the first thin insulating layer at the lower part of the first opening as well as in the second opening,

[0038] c3) partial engraving of the first portion, so as to form a cavity,

[0039] c4) deposition of a second thin insulating layer lining the walls of the second opening and the first opening, and filling at least partially the cavity,

[0040] c5) engraving(s) of the second thin insulating layer, so as to preserve a region of the second thin insulating layer in the cavity.

[0041] According to one possible implementation after step cl) and prior to step c2), the process may comprise the following steps:

[0042] - depositing at least one sealing material for the first opening and the second opening,

[0043] - formation of a mask opposite the second opening and comprising a window opposite the first opening,

[0044] - engraving, through said window, of at least one material of the plug in a upper part of the first opening while retaining the plugging material in a lower part of the first opening, the process further comprising, after step c2) and prior to step c3):

[0045] - removal of the plugging material in the first opening and second opening.

[0046] According to one possible implementation of the process, the first thin insulating layer and the second thin insulating layer can be based respectively on at least one first material and at least one second material different from the first material, step c5) of etching the second thin insulating layer being carried out by a selective etching of the second material with respect to the first material, followed by an anisotropic etching of the first thin insulating layer.

[0047] According to one embodiment of the process, the substrate or stack may comprise a semiconducting layer coated with at least one insulating layer called "lower", the lower insulating layer being coated by the conductive track or tracks of the lower level and wherein in step b) of forming a first opening and a second opening, the first opening and the second opening are formed so as to pass through the lower insulating layer until reaching the semiconducting layer.

[0048] According to one possible embodiment of the process, the first opening and the second opening can be formed concurrently in step b) and the filling of the first opening and the second opening in step d) is advantageously carried out concurrently in the first opening and in the second opening. Brief description of the drawings

[0049] The present invention will be better understood upon reading the description of the exemplary embodiments given, by way of illustration only and in no way limiting, with reference to the accompanying drawings in which:

[0050] The present invention will be better understood upon reading the description of the given exemplary embodiments, provided for illustrative purposes only and in no way limiting the application, with reference to the accompanying drawings on which:

[0051] [Fig.1] [Fig.2] [Fig.3] [Fig.4A] [Fig.4B] [Fig.5] illustrate the realization of different levels of conductive tracks on a substrate.

[0052] [Fig.6] illustrates the creation of via openings through different levels of conductive tracks.

[0053] [Fig.7] [Fig.8A] [Fig.8B] [Fig.9] [Fig.10] [Fig.ll] [Fig.12] [Fig.13] [Fig.l4A] [Fig.l4B] illustrate an implementation of insulating spacers in the openings crossing the tracks, at least one spacer being formed against a track of a higher level, at least another spacer being formed against a track of a lower level.

[0054] [Fig.15A] [Fig.15B] [Fig.15C] illustrate the filling of the via openings and an interconnection structure thus obtained.

[0055] [Fig. 16] illustrates an example of an interconnection structure according to the invention formed on a semiconductor-on-insulator type substrate.

[0056] [Fig. 17] illustrates a contact of an interconnection structure on conductive or semiconductive regions which may be different.

[0057] [Fig. 18] illustrates an interconnection structure with vias passing through a keme and a (k+l)th metallic interconnection level.

[0058] [Fig. 19] illustrates a particular example of an interconnection structure formed of conductive vias each passing through the same conductive track of a higher level and the same conductive track of a lower level.

[0059] [Fig.20A] [Fig.20B] illustrate a particular example of an interconnection structure to control a matrix of quantum islands or qubits.

[0060] [Fig.21] illustrates a variant of the interconnection structure making contact on both sides of regions of a component.

[0061] [Fig.22A] [Fig.22B] illustrate an interconnection structure with a via forming a memory element and associated with a transistor.

[0062] [Fig.23] illustrates an interconnection structure equipped with a conductor and capable to form, with a conductive track that it crosses and an insulating spacer arranged between the track and the via, a ReRAM or PCRAM memory element.

[0063] Identical, similar or equivalent parts of the different figures bear the same numerical references so as to facilitate the transition from one figure to another.

[0064] The different parts represented in the figures are not necessarily shown on a uniform scale, in order to make the figures more legible.

[0065] In addition, in the description below, terms which depend on the orientation of the structure such as "above", "below", "lower", "upper", "juxtaposed", "superimposed", "vertical", "horizontal" apply considering that the structure is oriented in the manner illustrated in the figures.

[0066] DETAILED DESCRIPTION OF SPECIFIC EMBODIMENTS

[0067] Reference is made first to [Fig.1] (giving here a perspective view) which serves to illustrate a step in an example of a manufacturing process for an interconnecting structure.

[0068] The starting material of the process here comprises a layer 102 which can be conductive and in particular metallic, or semiconductive, and on which contact is to be made, this layer 102 belonging to a substrate or resting on a substrate (the substrate not being shown in this figure).

[0069] The layer 102 is first coated with an insulating layer 103 called "lower", for example based on SiO2 or formed of a stack for example of type PMD (for "Pre-Metal Dielectric", i.e. "pre-metal dielectric") comprising a layer of SiO2 deposited on a stop layer for example in SiN.

[0070] One or more conductive tracks are formed on the insulating layer 103 and belong here to a metallic interconnection level called "lower", for example corresponding to the lower metallic interconnection level M1 commonly called "metal 1". In the particular example illustrated, tracks 106a, 106b, 106c, here in the form of metallic lines, for example copper-based, are in particular made.

[0071] These tracks 106a, 106b, 106c extend here mainly in a direction parallel to a y direction and to a principal plane of the substrate. Here and throughout the description, the "principal plane" of the substrate is called a plane passing through the substrate and parallel to the plane [O;x;y] of an orthogonal coordinate system [O;x;y;z] given on [Fig.2] (this plane also being parallel to layer 102).

[0072] An example of a method for producing tracks 106a, 106b, 106c uses a Damascus-type technique where trenches, here oblong, are made in the insulating layer 103, and then the trenches are filled with a metallic material. This filling can be followed by a CMP (Chemical Mechanical Planarization) polishing step to remove excess metallic material extending beyond the trenches onto the insulating layer 103.

[0073] A similar sequence of steps can then be repeated to those described above in order to form this time one or more conductive tracks 116a, 116b, 116c of a higher metallic interconnection level, corresponding for example here to a second metallic interconnection level M2 commonly called "metal 2".

[0074] The tracks 106a, 106b, 106c of the lower level M1 are thus coated ([Fig.2] this time giving a cross-sectional view) with at least one other insulating layer 113 called "intermediate", which may have a composition similar to the layer lower insulating 103, for example based on SiO2, and / or can be formed from a stack of several insulating materials such as a stack of SiN and SiO2.

[0075] Trenches 115, here oblong, are then made in the intermediate insulating layer 113 ([Fig.3]).

[0076] Then, the trenches 115 are filled with metallic material. This filling can be followed by a CMP polishing step ("Chemical mechanical planarisation") in order to remove excess metallic material extending onto the insulating layer 113 outside the trenches.

[0077] The trenches 115, and the tracks 116a, 116b, 116c made by filling these trenches 115 are designed so as to extend parallel to a main plane of the substrate.

[0078] In this particular example illustrated in Figures 4A-4B (giving respectively a cross-sectional view and a top view), the tracks 116a, 116b, 116c, in the form of metallic lines, for example copper-based, belong to a higher metallic interconnection level, in particular to the second metallic interconnection level M2 commonly referred to as "metal 2". The tracks 116a, 116b extend mainly in a direction parallel to a second direction x, which is therefore orthogonal to that in which the tracks 106a, 106b, 106c of the lower level extend.

[0079] An insulating layer 123, referred to as the "top" layer, can then be deposited ([Fig.5]) on the level M2 of conductive tracks 116a, 116b, 116c. Here again, the "top" insulating layer 123 can, for example, be based on silicon oxide or a stack of dielectric materials with a stop layer, for example, of SiN surmounted by a layer of SiO2.

[0080] Openings 125a, 125b, 125c are then formed in the stack previously created. These openings 125a, 125b, 125c, which here preferably extend in a vertical direction, that is, orthogonally to the principal plane of the substrate, respectively expose, and advantageously respectively traverse, the conductive tracks 116a, 116b, 116c of the upper level M2. These openings 125a, 125b, 125c also each traverse the intermediate insulating layer 113 between levels M1 and M2, and each also expose, and advantageously each traverse, a conductive track 106a of the lower level M1. The etching of the openings 125a, 125b, 125c can be stopped on a layer located below the lower level M1.

[0081] In particular, an opening 125b exposes a portion 1161 of the conducting track 116b of the upper level M2 which it passes through and a portion 1061 of the track 106a of the lower level M1 which it passes through. An opening 125a exposes a portion 1162 of the conducting track 116a of the upper level M2 which it crosses and a portion 1062 of the track 106a of the lower level M1 which it crosses.

[0082] In the particular method described here, these openings 125a, 125b, 125c also pass through the lower insulating layer 103 located between the M1 level and the semiconducting or conductive layer 102, and expose the semiconducting or conductive layer 102. In particular, the bottom 127f of the openings 125a, 125b, 125c is expected to expose the semiconducting or conductive layer 102.

[0083] The fabrication of the apertures 125a, 125b, 125c typically includes a lithography step. The apertures 125a, 125b, 125c here have a diameter or width D (dimension measured parallel to the y-axis in [Fig. 6]), which is intended to be less than the width W of the conductive tracks 116a, 116b, 116c, 106a, 106b, 106c, with D, for example, on the order of 40 nm, the width W of the tracks being, for example, between 100 nm and 200 nm. WD is typically intended to be at least 60 nm.

[0084] Anisotropic dry etching can be performed to etch the stack and advantageously cross two metallic levels M1, M2. For example, plasma etching using at least one of the following compounds CC14, SiCl4, Cl2, HBr, CH3COOH can be used to cross two levels of copper tracks.

[0085] Next, a first thin insulating layer 131, with a thickness of for example between 5 nm and 10 nm, is deposited, lining the side walls 1271 and bottom walls 127f of the openings 125a, 125b, 125c. This thin insulating layer 131, also called a "liner", can be made by conformal deposition of a dielectric material, for example chosen from the following materials: SiN, SiBCN, SiOCN, SiCO, HfO2, TiO2, Al2O3 ([Fig.7]).

[0086] Next, targeted protection is carried out on the upper part of one or more given openings from among the set of openings 125a, 125b, 125c made.

[0087] To this end, one method includes a step of sealing all the openings 125a, 125b, 125c, by depositing at least one filling material 134 for the openings 125a, 125b, 125c. In the embodiment illustrated in [Fig. 8A], the filling material 134 is deposited so as to fill the openings 125a, 125b, 125c. The filling material 134 may, for example, be a spin-on-carbon (SOC) type layer, typically based on a polymer material, for example PGMEA (propylene glycol methyl ether acetate) with a carbon content typically greater than 80%, and fill the openings 125a, 125b, 125c preferably to their full depth.

[0088] A masking 138 is then formed, in this example on a layer of the filling material 134 that extends beyond the openings of the apertures 125a, 125b, 125c. This masking 138 is distributed in a targeted manner opposite one or more data points 125a, 125c among the apertures 125a, 125b, 125c, filled with the filling material 134, while retaining one or more windows 139, i.e. a or several holes arranged opposite one or more other openings among the openings 125a, 125b, 125c filled with material 134. Advantageously, the masking 138 formed for example of a photosensitive resin can be disposed on an intermediate anti-reflective layer (not shown) for example based on silicon (SiARC), itself disposed on the filling material 134.

[0089] Above a series of tracks along a direction orthogonal to these tracks, a masking block can be provided opposite one or more tracks 116a, 116c, while a window 139 is positioned opposite one or more other tracks 116b. According to a particular arrangement of the masking 138, this masking is provided opposite every other track. Thus, in the specific embodiment illustrated in Figures 8A and 8B (showing a cross-sectional view and a top view, respectively), the windows 139 are arranged in a staggered pattern.

[0090] A partial removal of the filling material 134 exposed by the window(s) 139 is then carried out. In particular, an upper portion of the filling material 134 located in the upper part of the relevant opening(s) 125b and positioned opposite a window 139 is removed. The filling material 134 is thus etched so as to leave it only in the lower part of the opening(s) 125b not covered by the masking 138 ([Fig. 9]). This partial etching of the filling material 134 can be carried out by plasma, for example, a fluorocarbon plasma.

[0091] This removal is followed by etching a portion of the first thin insulating layer 131 exposed by the window(s) 139 and not covered or protected by the filling material 134. The first thin insulating layer 131 is thus removed from the upper part of the opening(s) 125b located opposite a window 139 ([Fig. 10]). A selective isotropic wet etching can be used to perform this removal. In the specific case, for example, where the thin insulating layer 131 is made of SiN, this etching can be carried out using H3PO4. At the end of this step, one or more openings 125a, 125c are provided with a bottom wall and side walls entirely coated by the thin layer 131, while one or more openings 125b are coated with the thin layer 131 only at the level of their lower portion so as to cover the track 106a of lower level Ml.

[0092] A portion 1161 of conductive track 116b of the second level M2 is thus again exposed in each opening 125b where these withdrawals are made, while in the extension at the bottom of this or these same opening(s) 125b, a track 106a of lower level M1, here crossed by this opening 125b, remains protected by the filling material 134 and by the first thin insulating layer 131.

[0093] A partial engraving can then be carried out on the exposed portion 1161 of the track or tracks 116b not protected by the first thin insulating layer 131.

[0094] For this purpose, the filling material 134 and the masking 138 can be removed beforehand, as illustrated in [Fig. 1 1]. Such removal, particularly when the material 134 is a polymer and the masking 138 is a photosensitive resin, can be carried out by an elimination process commonly called "stripping" using, for example, an organic solvent, for example, based on acetone.

[0095] Partial etching of the exposed portion 1161 of the track(s) 116b in the upper part of the opening 125b is implemented so as to form a cavity 140 in the side wall 1271 of the opening 125b and exposing a remaining etched portion 1161' of the conductive track 116b. Selective wet etching, for example by means of a solution comprising a mixture of hydrogen peroxide (H2O2) and sulfuric acid (H2SO4) heated and commonly called "hotSPM" or TMAH (acronym for "TetraMethyl Ammonium Hydroxide") can in particular be used when the portion 1161 of the conductive track 116b to be etched is made of polysilicon or of a metal such as copper. Partial etching aims to remove a thickness of conductive material on the order of that of a liner, and in particular a second thin insulating layer intended to be deposited later.This second thin insulating layer can be designed with a thickness of the same order as that of the first thin insulating layer 131 and / or for example between 5 and 10 nm.

[0096] Next ([Fig. 12]), the second thin insulating layer 141 is deposited, lining the side walls and the bottom of the openings 125a, 125b, 125c. This second thin insulating layer 141, with a thickness of, for example, between 5 nm and 10 nm, can be produced by conformal deposition of a material which can be dielectric and chosen, for example, from the following materials: SiN, SiBCN, SiOCN, SiCO, HfO2, TiO2, Al2O3.

[0097] The thin insulating layer 141 may be of the same nature as the thin layer 131 or advantageously of a different material from that of the first thin insulating layer 131.

[0098] According to a particular embodiment, the thin insulating layer 141 may be a layer with variable resistivity intended to form a non-volatile memory element, in particular a layer such as is used in RRAM or ReRAM (Resistive Random Access Memory), where changing resistance allows information to be recorded. In this case, the thin insulating layer 141 may, in particular, be an oxide layer (for example, HfO2, TiO2, Al2O3) commonly used in OxRAM structures.

[0099] According to another particular embodiment, the thin insulating layer 141 can be based on a phase-change material, for example to form a memory of the PCM type ("Phase Change Memory"), capable of switching between an amorphous and a crystalline state. For example, a chalcogen material such as GST (for GeSbTe or chalcogenide glass) can be used.

[0100] The second thin insulating layer 141 is deposited so as to line the side and bottom walls of the openings 125a, 125b, 125c and to at least partially fill the cavity 140 made previously by engraving the conductive track 125b in the opening 116b.

[0101] A partial etching of the second insulating thin layer 141 is then performed. This etching is carried out in such a way as to remove this second insulating thin layer 141 entirely from the openings 116a, 116c and preferably from the opening 116b, while retaining it at least partially in the cavity 140 previously formed by etching the track 116b. Selective etching with respect to the material of the first insulating thin layer 131 can be performed when the second insulating thin layer 141 is based on a different material. Such an etching step can be carried out by wet etching, for example using HF, or by dry etching, for example using a CF₅Ar plasma, or even a combination of the two types of etching.

[0102] Thus, a portion of the second thin insulating layer 141 is retained at least against the second level conductive track 116b M2 exposed by the opening 125b. The retained portion of the second thin insulating layer 141 then forms an insulating plug, also called a "spacer" 141e, disposed against the exposed portion of the conductive track 116b ([Fig.13]).

[0103] Next, an etching step is carried out on the first thin insulating layer 131, so as to retain only regions of the first thin insulating layer 131 in the lower part of the openings 125a, 125c, in which the second thin layer 141 has been completely removed and which do not have a spacer 141e formed from such a layer 141. The regions of the first thin insulating layer 131 retained then form an insulating plug called a "spacer" 131e against portions of the conductive track 106a ([Fig. 14A] and 14B giving respectively a cross-sectional view and a top view).

[0104] In a case where the thin insulating layers 131, 141 are of different natures, the spacer(s) 131e are formed by performing an anisotropic etching step on the first thin insulating layer 131e. This etching is carried out below the second level M2 and preferably without reaching the lower level ML

[0105] Such an etching step can be carried out by dry etching, for example using a CF.4 / O2 type plasma.

[0106] Alternatively, in the case where the thin layers 131 and 141 are of the same nature and have identical compositions, the partial withdrawal of the second thin layer 141 and of the first thin layer 131 to form the spacers 131e, 141e can be carried out in a single anisotropic plasma etching of these thin layers 131, 141.

[0107] A conductive material 150 is then deposited to fill the openings 125a, 125b, 125c and form vertical conductive elements 156a, 156b, 156c commonly called "vias". A conformal metallic deposit of one or more of the following materials: Ti, TiN, W, Cu, Ta, Co, Ru, can be made, for example. Such a deposit is typically followed by a CMP planarization step of excess material(s) that may overflow beyond the openings of the ports 125a, 125b, 125c.

[0108] An interconnection structure is then obtained as illustrated in Figures 15A-15C (giving respectively a cross-sectional view, a top view and a perspective view).

[0109] The structure is provided with conductive elements 156a, 156b, 156c or "vias" each passing through the intermediate insulating layer 113 between levels M2 and M1, and the insulating layer 103 located below the lower level M1, to make contact through their respective lower ends 1561, 1562, 1563 on the conductive or semiconducting layer 102.

[0110] Among these conductive elements 156a, 156b, 156c, the given conductive elements 156a, 156c are in contact respectively with conductive tracks 116a, 116c of the upper level M2 which they respectively pass through while being insulated, via the insulating spacer 131e, from the same conductive track 106a of the first level M1 which they each also pass through.

[0111] At least one other conductive element 156b and is in contact with the conductive track 106a of the lower level M1 which it passes through while being insulated, via the insulating spacer 141e, from a conductive track of the second level M2 which it also passes through.

[0112] At the level of each lower level conductive track M1 or upper level M2, the conductive elements 156a, 156b, 156c are here surrounded and typically entirely surrounded by material of this conductive track.

[0113] The spacers 131e, 141e advantageously achieve an insulating closed contour forming a sleeve or ring around their respective element or via conductor traversing itself typically entirely surrounded by the conductive material of the track through which the element or via conductor passes.

[0114] Typically, the conductive elements 156a, 156b, 156c have respective upper ends 1567, 1568, 1569 that extend beyond the upper M2 level and each protrude from a conductive track of the upper M2 level, and respective lower ends 1561, 1562, 1563 that extend beyond the level lower Ml and each protrude from a lower level conductive track Ml to reach an area between the substrate and the lower level Ml.

[0115] Here we implement an interconnection structure which allows inter-level connections to be made while avoiding interconnecting tracks of levels M1, M2 that are directly adjacent or neighboring and having a compact arrangement favorable to a high integration density.

[0116] Such a through-via interconnection structure allows for a significant gain in integration density. Here, using spacers 131e, 141e, it is possible to avoid bypassing a metallic layer to which one does not wish to be electrically connected.

[0117] In the embodiment just described, the conducting elements 156a, 156b, 156c have respective lower ends 1561, 1562, 1563 making contact with the same conductive or semiconducting layer 102.

[0118] This layer 102 can advantageously be a semiconductor layer commonly called the "active layer" of a substrate or resting on a substrate and in which components or parts of components, for example such as transistors, are made or intended to be made.

[0119] Thus, a particular embodiment provides, as a starting structure for carrying out a process of the type described above, a semiconductor-on-insulator substrate 10 such as illustrated in [Fig. 16], for example of the SOI type (SOI for "Silicon On Insulator") having a semiconductor support layer 100, for example of silicon, coated with an insulating layer 101, for example of SiO2, and commonly called BOX ("buried-oxide"), the insulating layer 101 being itself coated with the semiconductor layer 102 forming here the surface layer of the substrate. Such a surface semiconductor layer can be, for example, of silicon, or of SiGe, or Ge.

[0120] A variant of the structure is shown in [Fig. 17], with a dashed block 200 schematically representing a substrate coated with one or more layers or a stack on which regions RA, RB, RC, to be contacted, are exposed. These regions RA, RB, RC are typically conductive or semiconductive but of different compositions. For example, one or more regions are made of a first metallic or semiconducting material, while at least one other region is made of a second material, for example, a semiconductor different from the first material. On these regions RA, RB, RC, the respective lower ends 1561, 1562, 1563 of the conducting elements 156a, 156b, 156c respectively make contact.

[0121] In the example described above, the vias formed cross conductive tracks of a lower level Ml, which may be the first metallic level of interconnection and a higher level M2 which can be the second metallic interconnection level. However, a similar process can be implemented on other metallic interconnection levels.

[0122] Thus, in the embodiment illustrated in [Fig. 18], the conductive elements 156a, 156b, 156c each pass through a conductive track of a (k+l)th level (with k an integer greater than 1) and a track of a kth level while being both in electrical contact with a conductive track of the kth level and isolated from a track of the (k+l)th level or being both in electrical contact with a track of the (k + l)th level and isolated from a track of the kth level.

[0123] In the method example described above in connection with Figures 1 to 15A-15C, the conductive elements 156a, 156b, 156c cross conductive tracks of a higher level which are orthogonal to one or more tracks of a given lower level. An alternative embodiment illustrated in [Fig. 19] provides that the conductive elements 156a, 156b, 156c each cross the same conductive track 216 of a higher level and each cross the same conductive track 106 of a given lower level, the conductive tracks 116 and 106 extending mainly in respective directions parallel to each other and in [Fig. 19] parallel to the y-axis of the orthogonal coordinate system [O; x; y; z].

[0124] An interconnection structure such as the one described above is particularly well-suited to addressing qubits, especially spin qubits located in semiconductor regions forming quantum dots. Parallel row and column addressing of a matrix of quantum dots (QDs) can be achieved using an interconnection structure such as the one described above while limiting the number of control signals required.

[0125] Thus, in a particular embodiment illustrated in Figures 20A and 20B, the conducting elements 156a, 156b, 156c have their lower ends making contact respectively with regions 102A, 102B, 102C, typically semiconducting and for example of the same semiconducting layer and each forming a quantum dot associated with a Qubit QD21, QD22, QD23.

[0126] A conductive element 156a allows an electrical connection between a conductive track 116a of a higher level M2 and a region 102A forming a qubit QD21, while being isolated from a conductive track 106 of the lower level M1 by means of an insulating spacer 131e. Another conductive element 156b allows an electrical connection between a conductive track 106a of the lower level M1 and a region 102B forming another qubit QD22, while being isolated from a conductive track 116b of the higher level M2 by means of an insulating spacer 141e.

[0127] A particular staggered arrangement of the conducting elements or through vias can be provided for the two-dimensional network of Qubits.

[0128] Such an example of a staggered arrangement is illustrated in [Fig. 20B], where the conducting elements have a matrix arrangement in different rows 250i, 2052, 2503, ..., 250m, each row being formed of an alternation of conducting elements 156b, 156d connected to the lower metal level M1 and insulated from the upper metal level M2 and of conducting elements 156a, 156c connected to the upper metal level M2 and insulated from the lower metal level M1, this alternation being offset from one row to the next. Thus, a first row 250i has at its end a conducting element 156b connected to the lower metal level M1 and insulated from the upper metal level M2.A neighboring row 2502, typically with the same number of qubits as the first row 250i, has at its end a conductive element 156a, this time connected to the upper metal level M2 and isolated from the lower metal level M1. A neighboring row 2503, also typically with the same number of qubits as the rows 250i and 2502, has at its end a conductive element 156b, isolated from the upper metal level M2 but connected to the lower metal level M1. A single row 2502 can thus comprise an alternation of qubits QD21 and QD23 controlled by a track of the upper metal level and a track of qubits QD22 controlled by a track of the upper metal level.

[0129] Such an arrangement is conducive to the implementation of an error correction for example of the "Surface Code" type as proposed by Fowler et al. in the document "Surface codes: Towards practical large-scale quantum computation", Phys review A, 2012.

[0130] In the embodiment illustrated in [Fig. 21], an interconnection structure of the type described above can be adapted for addressing and / or biasing one or more circuits or components Ci, C2, for example, of transistors, capacitors, resistors, or components with transistors formed at least partially in layer 102 on which the conductive elements 156a, 156b, 156c are located. Here again, one or more conductive elements 156a, 156c are isolated from a lower level M1 while being coupled to a higher level M2, while one or more other conductive element(s) 156b are coupled to the lower level M1 while being isolated from the higher level M2. A particular embodiment, shown here in [Fig.21], further provides that at least one conductive element 156b, here coupled to the lower level M1, forms with a conductive track 156b of the second level M2 which it passes through, a non-volatile memory element meml.

[0131] In this case, the insulating spacer 141e which is arranged between this conductive track 116b and the through-conductive element 156b is provided with a specific material, in particular a material whose resistance is capable of being reversibly modified under the effect of an electric current or a material whose state is capable of being reversibly modified to pass from an amorphous state to a crystalline state and from a crystalline state to an amorphous state.

[0132] The conductive element 156b and the conductive track 116b thus form, respectively, a first and a second electrode between which the phase-change material and / or variable resistance is arranged. The non-volatile memory element meml can thus be, for example, a ReRAM (Resistive Random-Access Memory) element, in particular an OxRAM element. In this case, the insulating spacer 141e can, for example, be made of at least one of the following materials: HfO2, TiO2, Al2O3, TaOxZrOx.

[0133] Alternatively, the non-volatile memory element meml may be of the PCRAM type (for “Phase-Change Random Access Memory”). In this case, the insulating spacer 141e may, for example, be made of a chalcogenide material such as GST (GeSbTe).

[0134] The implementation of such ReRAM or PCRAM memory elements can make it possible to form, for example, 1T1R type structures where a transistor is associated with such a memory element formed at the level of a via.

[0135] A particular embodiment of such a structure illustrated in Figures 22A-22B provides that vertical through-conducting elements 156a, 156b are arranged on either side of a gate 104 of a transistor Ti and make contact respectively on a region 102A among a source region and a drain region of the transistor Ti and on a second region 102B among a drain region and a source region distinct from the first region.

[0136] In [Fig. 22A], a particular operating mode is illustrated. The conductive element 156a, connected to level M2 but isolated from level M1 by means of its spacer 131e, allows a bias potential Vsource to be applied to region 102A of transistor T1, which in this particular example forms a source region. This bias potential is carried here by the conductive track 116a with which the conductive element 156a is in contact and through which it passes. The other conductive element 156b, connected to level M1 but isolated from the upper level M2 by means of its spacer 141e, allows a bias potential Vdrain to be applied to region 102B of transistor T1, which, in this particular example, forms a drain region. This bias potential is carried here via the conductive trace 106a through which both elements 156a and 156b pass, but to which only the other element 156b is electrically connected. This interconnection structure is thus used to bias a transistor Ti (the biasing of gate 104 is not shown here) while minimizing its size. The conductive element 156b can form, with a conductive trace 116b at level M2, a volatile memory element which, in this operating mode, is not used.

[0137] Fig. 22B illustrates another mode of operation where the conductive track 116a forms a bit line BL for addressing a memory structure, connected here to the region 102A of the transistor Th, while a word line WL for addressing the memory structure is connected here to the gate 104 of the transistor Ti, the region 102B of the transistor being connected in series with a non-volatile memory meml element, formed by the conductive element 156b, its insulating spacer 141e, and the conductive track 116b through which this conductive element 156b passes and against which the insulating spacer 141e is arranged. A 1T1R type memory cell is thus formed by the transistor Tl in series with the memory element meml, a bit being able to be stored via the spacer 141e depending on its state, and the transistor Tl serving here as a selection transistor also called a "selector".

[0138] Another example of a structure given in [Fig.23] provides for vertical conductive elements 256b, 256d passing respectively through a first conductive track 216b and a second conductive track 216d at the same level as the first, while being insulated respectively by means of insulating spacers 241e from these tracks 216b, 216d.

[0139] The vertical conductive elements 256b, 256d also each pass through the same third conductive track 206 of a different level and are electrically connected to this same third conductive track 206.

[0140] Here again, non-volatile memory elements mem' 1, mem'2 can each be formed by a horizontal conductive track 216b (resp. 216d) forming a first electrode, a spacer 241e forming a memory layer, and a vertical conductive element 256b (resp. 216d) forming a first electrode.

[0141] Tracks 216b and 216d can serve here for example as BL bit lines, while the conductive track 206 of different level forms for example a WL word line.

[0142] An interconnection structure such as described above finds applications in particular in the polarization of 3D circuits with superimposed levels of semiconductor layers, in the realization of memory circuits, in the addressing of matrix circuits, in particular of memory matrices or matrices of quantum dots or qubits.

Claims

Demands

1. A microelectronic device comprising: - a substrate coated with a stack comprising one or more conductive tracks (106a, 106b, 106c, 106) of a so-called "lower (Mb Mk)" level, this lower level being coated with an insulating layer (113) called "intermediate", the intermediate insulating layer being coated with one or more conductive tracks (116a, 116b, 116c, 216) of a so-called "upper (M2, Mk +1)" level, - a conductive element (156b) passing through the intermediate insulating layer (113) and in contact with a first conductive track (106b, 206) of a given level among said upper (M2, Mk +1) level and said lower (Mb Mk) level, while being isolated, by means of an insulating spacer (141e), from a second conductive track (116b, 216) of another level among said lower level and said upper level, said insulating spacer (141e) being disposed between the second conductive track (116b;216) and said conducting element (156b), said conducting element (156b) having a so-called "lower" end (1562) making contact on a first region (102A, 102), conductive or semiconductive of the substrate or stack, said conducting element (156a; 156b) passing through the first conductive track (106b, 206) and the second conductive track (116b, 216) and being surrounded by said insulating spacer (141e).

2. Microelectronic device according to claim 1, further comprising a second conductive element (156a) having a lower end (1562) making contact with a second region (102A, 102), conductive or semiconductive, of the substrate or stack, the second conductive element (156a) passing through a conductive track of said given level as well as the intermediate insulating layer (113) and a conductive track of said other level, said second conductive element (156a) being insulated, by means of a second insulating spacer (131e), from said conductive track of said given level which the second conductive element passes through, the second conductive element being in contact with said conductive track of said other level which it passes through.

3. Electronic device according to claim 2, - wherein the conducting element (156b) and the second conducting element (156a) each pass through the first conducting track (106b, 206) of said given level and respectively pass through the second conducting track (116b) of said other level and a third conducting track (116a) of said other level distinct from the second conducting track, the second conducting track (116b) and the third conducting track (116a) extending parallel or substantially parallel to a first direction parallel to a principal plane of the substrate, the first conducting track extending in a second direction orthogonal to the first direction, or - wherein the conducting element (156b) and the second conducting element (156a) each pass through the first conducting track of said given level and each pass through the second conducting track of said other level.

4. Electronic device according to any one of the preceding claims, wherein the stack comprises an insulating layer (103) referred to as "lower" on which said one or more conductive tracks (106a) of said given level (Mb Mk) are disposed, the first region (102A, 102) being disposed between an area of ​​the substrate and said lower level, the conductive element (156b) further passing through the lower insulating layer (103).

5. Electronic device according to any one of the preceding claims, the first region (102A) being a region of a semiconductor layer (102) of the substrate or resting on the substrate.

6. Electronic device according to any one of the preceding claims, the first region forming a quantum island (QD1; QD2).

7. An electronic device according to any one of the preceding claims, wherein the first region is a source or drain region of a transistor Tp

8. Electronic device according to any one of the preceding claims, said insulating spacer (141e) being based on a material capable of reversibly changing resistance and / or state between an amorphous phase and a crystalline phase, in particular under the effect of an electric current.

9. Electronic device according to any one of claims 2 or 3, the first region (102A) being a region of a semiconductor layer (102), the second region (102A) being another region of said semiconductor layer (102).

10. A method for making a microelectronic device comprising the following steps: a) providing a substrate coated with a stack having one or more conductive tracks (106b) of a so-called "lower level (Mi, Mk)", the lower level being coated with an insulating layer (113) called "intermediate", the intermediate insulating layer being coated with one or more conductive tracks of a so-called "upper level (M2-Mk+1)", b) forming a first opening (125b) and a second opening (125a) in the stack and each passing through a conductive track (116a, 116b, 116c) of the upper level (M2, Mk+1), the intermediate insulating layer (113), and a conductive track (106a, 106) of the lower level (Mb Mk), the first opening (125b) exposing at least a first portion (1161) and the second opening (125a) exposing at least a second portion (1162) respectively of one or more conductive tracks of said upper level,the first opening (125b) further exposing at least a third portion (1061) and the second opening (125a) further exposing at least a fourth portion (1062) respectively of one or more conductive track(s) (106a) of said lower level, c) formation in the first opening (125b) of a first insulating spacer (141e) against the first portion (1161) of conductive track while leaving the third portion (1061) of conductive track exposed and formation in the second opening (125a) of a second insulating spacer (131e) against the fourth portion (1062) of conductive track while leaving the second portion (1162) of conductive track exposed, d) filling the first opening (125b) and the second opening (125a) with at least one conductive material (150), so as to form a first conductive element (156b) and a second conductive element (156a),the first conducting element (156b) being in contact with the third portion (1061) while being isolated from the first portion (1161) by means of the first spacer (141e), the second conducting element (156b) being in contact with the second portion (1162) while being isolated from the fourth portion (1062) by means of the second spacer.

11. A method according to the preceding claim, wherein step c) comprises at least the following steps: c1) deposition of a first thin insulating layer (131) lining the walls of the first opening (125b) and the second opening (125a), c2) partial etching of the first thin insulating layer (131) at the level of said upper part of the first opening (125b), so as to expose the first portion (1161), while preserving the first thin insulating layer at said lower part of the first opening as well as in the second opening (125a), c3) partial etching of the first portion (1161), so as to form a cavity (140), c4) deposition of a second thin insulating layer (141) lining the walls of the second opening (125a) and the first opening (125b), and at least partially filling the cavity (140), c5) etching of the second thin insulating layer (141),so as to preserve a region (141e) of the second thin insulating layer (141) in the cavity (140).

12. A method according to claim 11, wherein after step c1) and prior to step c2), the method comprises the following steps: - depositing at least one plugging material (134) in the first opening (125a) and the second opening (125b), - forming a mask (138) opposite the second opening (125a) and having a window (139) opposite the first opening (125b), - engraving, through said window (139), said at least one plugging material (134) in an upper part of the first opening (125b) while retaining the plugging material (134) in a lower part of the first opening (125b), the method further comprising, after step c2) and prior to step c3): - removing the plugging material (134) from the first opening (125b) and second opening (125a).

13. A method according to any one of the preceding claims, the first thin insulating layer (131) and the second thin insulating layer (141) being based respectively on at least one first material and at least one second material different from the first material, step c5) of etching of the second thin insulating layer (141) being carried out by a selective etching of the second material with respect to the first material, followed by an anisotropic etching of the first thin insulating layer.

14. A method according to any one of the preceding claims, wherein the substrate or stack comprises a semiconducting layer (102) coated with at least one insulating layer (103) referred to as "lower", the lower insulating layer (103) being coated by the conductive track(s) of the lower level (Mb Mk) and wherein in step b) of forming a first opening (125b) and a second opening (125a), the first opening (125b) and the second opening (125a) are formed so as to pass through the lower insulating layer (103) until reaching said semiconducting layer (102).

15. A method according to any one of the preceding claims, wherein the first opening (125b) and the second opening (125a) are formed concurrently in step b) and wherein the filling of the first and second openings in step d) is advantageously carried out concurrently in the first and second openings.

Images