Electronic chips

Abstract

Electronic Chips This description relates to an electronic chip (100) comprising: - a semiconductor substrate (102) in and on which an integrated circuit (104) is formed; - at least one connection metallization (106) of the integrated circuit formed on the side of a front face of the semiconductor substrate; - a first passivation layer (108) covering the front face of the semiconductor substrate, the first passivation layer having openings aligned with the connection metallization of the integrated circuit; and a second passivation layer (110) covering lateral sides of the semiconductor substrate, the second passivation layer being made of parylene and the first and second passivation layers being in contact on the side of the front face of the semiconductor substrate. Figure for the abbreviation: Fig. 1

Description

Title of the invention: Electronic chips technical field

[0001] This description relates generally to the manufacture of electronic chips. It relates more particularly to the manufacture of so-called surface-mount chips, that is to say, having, on the side of a connection face, one or more connection metallizations intended to be soldered to corresponding connection areas located on a connection face of an external device, for example a printed circuit board or another chip. Previous technique

[0002] Conventionally, the contact metallizations of a surface-mount chip are located on the side of the chip facing the contact face of the external device. To ensure the electrical reliability of the electronic chip and prevent short circuits, particularly after soldering the chip to the external device, the contact face of the electronic chip can be electrically insulated by a passivation layer formed around the contact metallizations. For certain applications, it is desirable to electrically insulate not only the contact face but also the lateral sides of the electronic chip.

[0003] There is a need for improvement of electronic chips. Summary of the invention

[0004] For this purpose, an embodiment provides an electronic chip comprising: - a semiconductor substrate in and on which an integrated circuit is formed; - at least one connection metallization of the integrated circuit formed on the side of a front face of the semiconductor substrate; - a first passivation layer covering the front face of the semiconductor substrate, the first passivation layer having openings in line with the metallization of the integrated circuit connection; and a second passivation layer covering the lateral sides of the semiconductor substrate, the second passivation layer being made of parylene and the first and second passivation layers being in contact on the side of the front face of the semiconductor substrate.

[0005] According to one embodiment, the electronic chip according to claim 1, wherein the second passivation layer is made of parylene-N.

[0006] According to one embodiment, the second passivation layer is made of parylene-C.

[0007] According to one embodiment, the second passivation layer is made of parylene- AF4.

[0008] According to one embodiment, a rear face of the semiconductor substrate, opposite to the front face of the semiconductor substrate, is covered by the second passivation layer.

[0009] Another embodiment provides a method for manufacturing a plurality of electronic chips from a structure comprising: - a plurality of integrated circuits formed in and on a semiconductor substrate; - at least one metallization of the connection per integrated circuit formed on the front side of the semiconductor substrate; and - a first passivation layer covering the front face of the semiconductor substrate, the first passivation layer having openings in line with the metallizations of the connection of the integrated circuits, the process comprising a step of depositing a second passivation layer on the lateral sides of the semiconductor substrate, the second passivation layer being in a parylene and the first passivation layer and the second passivation layer being in contact on the side of the front face of the semiconductor substrate.

[0010] According to one embodiment, the step of depositing the second passivation layer comprises: - a vaporization step in which solid parylene dimers are heated and vaporized into a dimer gas; - a pyrolysis step in which the dimer gas is treated by pyrolysis to transform the dimers into their monomer forms; and - a deposition step during which the monomer gas is deposited on all exposed surfaces.

[0011] According to one embodiment, during the step of depositing the second passivation layer, the second passivation layer is deposited on the back face of the semiconductor substrate.

[0012] According to one embodiment, the step of depositing the second passivation layer is preceded by a step of forming first trenches in the semiconductor substrate.

[0013] According to one embodiment, the first trenches are non-through and are formed by the front face of the semiconductor substrate and the step of forming the first trenches is followed by a step of forming openings, in the semiconductor substrate, from the rear face of the semiconductor substrate, opposite the first trenches.

[0014] According to one embodiment, the step of depositing the second passivation layer is followed by a step of forming second trenches opposite the first trenches so as to form individual electronic chips.

[0015] Another embodiment provides a method for using the aforementioned chip, comprising a step of transferring the electronic chip, from the metallization side of its connection, onto a metallization of an external device, the transfer step consisting of depositing a solder material onto the metallization of the external device and then compressing the electronic chip onto the external device. Brief description of the drawings

[0016] These features and advantages, as well as others, will be described in detail in the following description of particular embodiments, given by way of non-limiting example, in relation to the accompanying figures, among which:

[0017] [Fig.1] is a partial and schematic cross-sectional view of an example of a surface-mount electronic chip according to one embodiment;

[0018] [Fig.2], [Fig.3A], [Fig.3B], [Fig.4A], [Fig.4B], [Fig.5A], [Fig.5B], [Fig.6] and [Fig.7] are each a cross-sectional or perspective view of a structure obtained at the end of a step in a manufacturing process of the electronic chip illustrated in [Fig.1], according to a first embodiment;

[0019] Fig. 8A, Fig. 8B, Fig. 9A and Fig. 9B are each a cross-sectional or perspective view of a structure obtained at the end of a step in a manufacturing process of the electronic chip illustrated in Fig. 1, according to a second embodiment; and

[0020] Fig.10, Fig.11, Fig.12, Fig.13, Fig.14 and Fig.15 are each a cross-sectional or perspective view of a structure obtained at the end of a step in a manufacturing process of the electronic chip illustrated in Fig.1, according to a third embodiment. Description of the implementation methods

[0021] The same elements have been designated by the same reference numerals in the different figures. In particular, the structural and / or functional elements common to the different embodiments may have the same reference numerals and may have identical structural, dimensional and material properties.

[0022] For the sake of clarity, only the steps and elements useful for understanding the described embodiments have been shown and are detailed. In particular, the implementation of the integrated circuits present in the described electronic chips has not been detailed.

[0023] Unless otherwise specified, when referring to two elements connected together, this means directly connected without intermediate elements other than conductors, and when referring to two elements connected (in English "coupled") together, this means that these two elements can be connected or linked through one or more other elements.

[0024] In the following description, when referring to absolute positional qualifiers, such as the terms "front", "back", "top", "bottom", "left", "right", etc., or relative, such as the terms "above", "below", "superior", "inferior", etc., or to orienting qualifiers, such as the terms "horizontal", "vertical", etc., it refers, unless otherwise specified, to the orientation of the figures.

[0025] Unless otherwise specified, the expressions "approximately", "about", "Sensibly" and "on the order of" mean to within 10% or 10°, preferably to within 5% or 5°.

[0026] Fig. 1 is a partial, schematic cross-sectional view of an example of a surface-mount electronic chip 100 according to one embodiment.

[0027] The electronic chip 100 comprises a semiconductor substrate 102 in and on which one or more integrated circuits 104 are formed. The substrate 102 is made of a semiconductor material, for example silicon. The substrate 102 has, for example, a thickness in the range of 50 pm to 1400 pm, for example a thickness of approximately 400 pm.

[0028] The substrate 102 has, for example, a parallelepiped shape.

[0029] Each integrated circuit 104 includes, for example, one or more electronic components (transistors, diodes, thyristors, triacs, etc.).

[0030] The substrate 102 and the integrated circuit 104 are for example surmounted by a stack of insulating and conductive layers called an interconnect stack, in which interconnecting elements of the components of the circuit 104 can be formed. The interconnect stack includes in particular, for each integrated circuit 104, one or more connection metallizations 106 of the integrated circuit formed, in the orientation of [Fig.1], on the side of the lower face of the semiconductor substrate 102 and intended to be connected to an external device 112.

[0031] For example, the connection metallizations 106 are made of copper.

[0032] In the example of [Fig. 1], two connection metallizations 106 are shown. However, the number of connection metallizations 106 per chip 100 may be different from two, for example greater than two.

[0033] The electronic chip 100 further comprises a first passivation layer 108 covering the underside of the semiconductor substrate 102. More specifically, the passivation layer 108 covers all portions of the underside of the substrate 102 not covered by the connection metallizations 106. The first passivation layer 108 has openings aligned with the connection metallizations 106 of the integrated circuit 104. By way of example, the first passivation layer 108 covers the lateral sides of the connection metallizations 106. By way of example, the first passivation layer 108 also covers the periphery of the underside of the connection metallizations 106.

[0034] The passivation layer 108 is, for example, made of an electrically insulating material, for example, a dielectric material. By way of example, the passivation layer 108 is made of a nitride or a polyimide, for example, silicon nitride.

[0035] The passivation layer 108 has, for example, a thickness in the range from 10 nm to 15 pm, for example a thickness of the order of 5 pm.

[0036] The electronic chip 100 further comprises a second passivation layer 110 covering lateral sides of the semiconductor substrate 102.

[0037] The second passivation layer 110 is made of parylene. For example, the passivation layer 110 is made of N-parylene or C-parylene ( ( (J!Cl- . Alternatively, the passivation layer 110 is parylene-AF4 ((-CF2-C6H4-CF2-)J, marketed under the name parylene-HT®.

[0038] The passivation layer 110 is deposited with a thickness for example in the range of 50 nm to 60 pm, for example a thickness of the order of 2 pm.

[0039] On the side of the lower face of the semiconductor substrate 102, the first passivation layer 108 is in contact, by its lateral side, with the second passivation layer 110.

[0040] In [Fig. 1], the electronic chip 100 is mounted on the external device 112. The external device 112 is, for example, an integrated circuit board or PCB (from the English "Printed Circuit Board") or another electronic component.

[0041] The electrical and mechanical connection between the chip 100 and the external device 112 is established by a solder material 114. The chip 100 is in fact electrically and mechanically connected, by its lower face in the orientation of [Fig.1], with the external device 112. The solder material 114 is for example a tin-based material, for example tin- and silver-based.

[0042] In the example of [Fig.1], the solder material is formed at the interface between each connection metallization 106 of the electronic chip 100 and a metallization, not shown, of the external device 112.

[0043] In the remainder of this description, the front face of the substrate 102 is considered to be the face bearing the connecting metallizations 106, for example the lower face of the substrate 102 in [Fig. 1], and the rear face of the substrate 102 is considered to be the face opposite the front face, for example the upper face of the substrate in [Fig. 1]. In the remainder of this description, the front face of the structure under consideration is further considered to be the face located on the side of the front face of the substrate 102, and the rear face of the structure under consideration is considered to be the face located on the side of the rear face of the substrate 102.

[0044] An advantage of the present embodiment is that it helps to limit the risks of mechanical contact between the brazing material 114 and the substrate 102, particularly on the lateral sides of the substrate 102.

[0045] Another advantage of the present embodiment is that it helps to limit the risks of short-circuiting the chip 100.

[0046] Fig.2, Fig.3A, Fig.3B, Fig.4A, Fig.4B, Fig.5A, Fig.5B, Fig.6 and Fig.7 are each a cross-sectional or perspective view of a structure obtained at the end of a step in a manufacturing process of the electronic chip illustrated in Fig.1, according to a first embodiment.

[0047] In particular, [Fig.2] illustrates a starting structure in which several integrated circuits 104 have been formed in and on the substrate 102. The structure of [Fig.2] includes the connection metallizations 106 of the integrated circuits 104 and the passivation layer 108 extending over the front face of the substrate 102.

[0048] In the starting structure, the substrate 102 can correspond to a plate of a semiconductor material, for example a round plate with a diameter of 300 mm or 200 mm.

[0049] In [Fig.2], the integrated circuits 104 are schematically represented separated from each other by dotted lines.

[0050] In [Fig.2], two integrated circuits 104 have been shown, it being understood that, in practice, the number of integrated circuits 104 formed in and on the substrate 102 of the starting structure may be different from two, for example greater than two.

[0051] Figures 3A and 3B illustrate a structure obtained at the end of a step of trench formation 116 in the structure illustrated in [Fig.2], [Fig.3B] being a perspective view and [Fig.3A] being a cross-sectional view along section plane A of [Fig.3B].

[0052] In this step, the trenches 116 are formed from the front face of the structure illustrated in [Fig.2] and extend through the thickness of the substrate 102, passing through the passivation layer 108. For example, the trenches 116 extend to a depth greater than the depth of the integrated circuits 104. The trenches 116 are, for example, not through and do not open onto the rear face of the substrate 102.

[0053] By way of example, the trenches 116 form, in top view, a grid, for example orthogonal, delimiting the integrated circuits 104 formed in and on the substrate 102. At the end of this step, each integrated circuit 104 is, for example, separated from neighboring integrated circuits 104 by a trench 116.

[0054] As an example, trenches 116 are made by sawing.

[0055] By way of example, each trench 116 has a width within the range going from 1 pm to 100 pm, for example, a width of approximately 50 pm. As an example, Each trench has a depth within the range of 100 pm to 400 pm, for example a depth of around 200 pm.

[0056] Figures 4A and 4B illustrate a structure obtained after a step of reversing the structure illustrated in Figures 3A and 3B and transferring it onto a support film 118, [Fig.4B] being a perspective view and [Fig.4A] being a cross-sectional view along the cutting plane A of [Fig.4B].

[0057] More specifically, during this step, the structure illustrated in figures 3A and 3B is reversed and transferred onto the support film 118 so that, at the end of this step, the connecting metallizations 106 are in contact with the support film 118. The connecting metallizations 106 are then not exposed and protected for the following steps.

[0058] The support film 118 is for example made of a polymer.

[0059] Figures 5A and 5B illustrate a structure obtained after a step of deposition of the layer 110 in parylene, for example in parylene-N, on all the surfaces of the structure illustrated in Figures 4A and 4B, [Fig.5B] being a perspective view and [Fig.5A] being a cross-sectional view along the cross-sectional plane A of [Fig.5B].

[0060] By way of example, the deposition of layer 110 includes a first vaporization step in which solid parylene dimers, for example (2,2)paracyclophane dimers, are heated and vaporized into a dimer gas. By way of example, this step is carried out at a temperature of approximately 175 °C.

[0061] By way of example, the deposition of layer 110 includes a second step in which the dimer gas is treated by pyrolysis to transform the dimers into their monomeric forms. Pyrolysis is carried out, for example, at approximately 690 °C. By way of example, during this step, the carbon-carbon single bonds linking the two monomers of the parylene dimers are broken. Carbon-carbon double bonds are then formed on either side of the aromatic ring, so as to obtain, for example, p-xylylene.

[0062] By way of example, the deposition of layer 110 includes a third step in which, in a deposition chamber, the monomer gas is deposited on all exposed surfaces of the structure illustrated in Figures 4A and 4B. By way of example, this step is carried out at ambient temperature, for example at a temperature within the range of 10 °C to 30 °C. By way of example, during this step, in order to reach the interior of all the trenches 116 and in particular the parts of the trenches 116 located in the center of the substrate 102, the monomer gas enters the grid formed by the trenches 116 from the trenches 116 opening onto the periphery of the substrate 102.

[0063] By way of example, a cold trap, for example having a temperature of -90°C, is connected to the deposition chamber so as to protect the pump which makes it possible to carry out the vacuum by entrusting the volatile residues to it.

[0064] By way of example, all of these steps are carried out under a primary vacuum.

[0065] By way of example, during the deposition step, layer 110 is deposited progressively, a thin layer of parylene is applied so that initially all exposed surfaces of the structure shown in Figures 4A and 4B are covered. Once the entire structure is covered by this thin layer and the deposition process continues, the parylene layer thickens until trenches 116 are filled. Layer 110 then covers the rear face and lateral sides of the structure shown in Figures 4A and 4B.

[0066] Figure 6 illustrates, by way of a cross-sectional view, a structure obtained at the end of a thinning step of the structure illustrated in Figures 5A and 5B, from its rear face.

[0067] More specifically, the structure illustrated in Figures 5A and 5B is, for example, thinned from its rear face, i.e., the upper face in the orientation of [Fig. 5A]. During this step, a portion of the rear face of the substrate 102 and the part of the layer 110 that had formed on the rear face of the substrate 102 are removed. This step is stopped, for example, when the part of the layer 110 formed in the bottom of the trenches 116 is exposed. By way of example, the thinning step is stopped when the integrated circuits are no longer mechanically held together by a semiconductor material. By way of example, the thinning step is stopped before reaching the rear face of the integrated circuits. By way of example, the thinning is carried out by chemical mechanical polishing (CMP).

[0068] Fig. 7 illustrates, by way of a cross-sectional view, a structure obtained at the end of an individualization step of the integrated circuits 104.

[0069] More particularly, this step corresponds to the formation of trenches 120 in the structure illustrated in [Fig.6] so as to form individual chips 100, each chip 100 comprising, for example, a single integrated circuit 104. The trenches 120 are formed opposite the trenches 116 filled by the layer 110 and are, for example, aligned with them. The trenches 120 are through trenches, that is to say they pass through the entire thickness of the substrate 102 so as to open onto the upper face of the support film 118. The trenches 120 have a width strictly less than the width of the trenches 116 so that the layer 110 remains on the lateral sides of the substrate 102 on either side of the trenches 120. As an example, the trenches 120 have a width in the range from 1 pm to 60 pm, for example a width of the order of 17 pm.

[0070] By way of example, trenches 120 are formed by sawing.

[0071] By way of example, the chips 100 can, at the end of this step, be picked up from the support film 118 and transferred and soldered onto the external device 112 as illustrated in [Fig. 1]. By way of example, the chips 100 can be transferred by a placement method called "pick and place".

[0072] Fig. 8A, Fig. 8B, Fig. 9A and Fig. 9B are each a cross-sectional or perspective view of a structure obtained at the end of a step in a manufacturing process of the electronic chip 100 illustrated in Fig. 1, according to a second embodiment.

[0073] The second embodiment of the chip manufacturing process 100 differs from the first embodiment in that it includes, before the deposition of the parylene layer 110, the formation of openings through the substrate 102 and leading into the trenches 116. Such openings ensure good penetration of the parylene into the trenches 116 and thus ensure their proper filling.

[0074] The second embodiment of the manufacturing process for chip 100 includes the same first steps as those described in the first embodiment in relation to Figures 2 to 4B.

[0075] Figures 8A and 8B illustrate a structure obtained at the end of a step of forming the openings 122 in the structure illustrated in Figures 3A and 3B, [Fig.8B] being a perspective view and [Fig.8A] being a section view along the section plane A of [Fig.8B].

[0076] More specifically, during this step, openings 122 are created opposite certain portions of trenches 116. The openings 122 are formed so as to open onto the trenches 116 formed during the step illustrated in Figures 4A and 4B. By way of example, the openings 122 are formed, in top view, in a central part of the substrate 102.

[0077] In the present embodiment, the openings 122 are formed by the rear face of the substrate 102. Alternatively, the openings 122 may be formed by the front face of the substrate 102 before the structure is transferred onto the support film 118.

[0078] The openings 122 have, for example, a circular shape in top view. By way of example, the openings 122 have a diameter less than or equal to the width of the trenches 116.

[0079] The openings 122 are for example formed by laser ablation.

[0080] Figures 9A and 9B illustrate a structure obtained after a step of deposition of the parylene layer 110 on the rear face of the structure illustrated in Figures 8A and 8B, [Fig.9B] being a perspective view and [Fig.9A] being a cross-sectional view along the cross-sectional plane A of [Fig.9B].

[0081] This step is for example identical to what has been described in relation to figures 5A and 5B except that the filling of the trenches 118 by the layer 110 is optimized by the openings 122.

[0082] At the end of this step, the process is, in its second embodiment, identical to what was described in the first embodiment, in relation to figures 6 and 7.

[0083] Fig. 10, Fig. 11, Fig. 12, Fig. 13, Fig. 14 and Fig. 15 are each a cross-sectional or perspective view of a structure obtained at the end of a step in a manufacturing process of the electronic chip illustrated in Fig. 1, according to a third embodiment.

[0084] The third embodiment of the manufacturing process for the chip 100 differs from the first embodiment in that the trenching step 116 is replaced by a trenching step 124 traversing the entire substrate 102.

[0085] Fig. 10 is a cross-sectional view of a starting structure similar to that illustrated in Fig. 2, except that it is mounted, by its front face, on a support film 126. The support film 126 is, for example, a polymer film.

[0086] Fig. 11 is a cross-sectional view of a structure obtained at the end of a trench formation step 124 in the structure illustrated in Fig. 10.

[0087] More particularly, during this step, the trenches 124 are formed so as to cross the entire thickness of the substrate 102 and open onto the passivation layer 108. Alternatively, the trenches 124 cross the passivation layer 108 and open onto the support film 126.

[0088] By way of example, the trenches 124 form, in top view, a grid similar to the grid formed by the trenches 116 described in relation to figures 3A and 3B.

[0089] As an example, trenches 124 are made by sawing.

[0090] By way of example, each trench 124 has a width within the range of 10 pm to 80 pm, for example a width of approximately 28 pm.

[0091] By way of example, before or after the formation of the trenches 124, the structure can be thinned from its rear face so that the thickness of the substrate 102 corresponds to the final thickness of the substrate 102 in the chip 100.

[0092] Fig. 12 is a cross-sectional view of a structure obtained after a step of deposition of the parylene layer 110 on the upper face of the structure illustrated in Fig. 11.

[0093] This step is similar to what has been described in relation to Figures 5A and 5B except that, in the present embodiment, the trenches 124 are all filled from their rear face.

[0094] Fig. 13 and Fig. 14 are cross-sectional views of a structure obtained after steps leading to the individualization of electronic chips 100.

[0095] In particular, [Fig. 13] illustrates a structure obtained after a thinning step similar to that described in relation to [Fig. 6], with the difference that it is stopped when the desired thickness for the chip 100 is reached.

[0096] Fig. 14 illustrates a structure obtained at the end of an individualization step of the integrated circuits 104 by the formation of trenches 120 in the same way as described in relation to Fig. 7.

[0097] The [Fig. 15] is a cross-sectional view of a structure obtained at the end of an individualization step of the electronic chips 100 in variant of the steps of figures 13 and 14.

[0098] More specifically, during this step, the thinning step is omitted and the trenches 120 are made while the parylene layer 110 remains on the back face of the substrate 102.

[0099] By way of example, during this step, a thinning of the structure may also be provided, so as to reduce the thickness of the layer 110 on the back face of the substrate 102 however without revealing the back face of the substrate 102.

[0100] Many applications are likely to benefit from the advantages provided by the electronic chip 100, this chip 100 being able to be integrated into various types of components.

[0101] By way of example, the chip 100 can be integrated into a component intended for the automotive industry. The electrification of motor vehicles is causing a sharp increase in the number of electronic components present in vehicles. The component includes, for example, thyristors, rectifiers, transient voltage suppression diodes, modules, etc., intended to be incorporated into said vehicles. Furthermore, driver assistance and driving automation are leading to an increase in the number of electronic components in vehicles. The component includes, for example, transient voltage suppression diodes, electrostatic discharge protection, and common-mode filters to protect the component against electrical hazards.

[0102] By way of example, the chip 100 can be integrated into a component intended for industrial use. In particular, the component is used, for example, for the development of green energy or for the electrification of infrastructure, for example, for charging stations or for solar energy collection. The component can also be used in the field of the Internet of Things or in the field of smart homes. The component is intended, for example, to be implemented in electrical power supply circuits for equipment, including, for example, 800 V or 1200 V thyristors, ultrafast 1200 V diodes, and carbide diodes. Silicon, transient voltage suppression diodes, and electrostatic discharge protection. The component can also be used for implementing cloud computing systems, 5G radio frequency communication networks, data centers, and servers. The component includes, for example, wide bandgap materials.

[0103] By way of example, the chip 100 can be integrated into a component intended for use in personal electronics, for example, to increase the volume of information exchanged via radio frequency communication, in 5G communication systems, or more generally in any connected component. The component is, for example, a mobile phone, or smartphone, or is part of an Internet of Things network. The component is, for example, connected via 5G, Wi-Fi, or broadband communication. The component includes, for example, high-speed interfaces, for example, with advanced filtering and protection against electrostatic discharge.

[0104] By way of example, the chip 100 can be integrated into a component intended for use in communication equipment, or in computers and peripherals. The component is used, for example, in 5G infrastructures and dedicated data centers. The component includes, for example, silicon carbide diodes, Schottky power transistors, electrostatic discharge protection, and transient voltage suppression diodes. The component can also be used in satellites, including, for example, integrated passive components for radio frequency applications.

[0105] Furthermore, the chip 100 described herein can be integrated into other components and thus have other applications than those mentioned above.

[0106] Various embodiments and variations have been described. A person skilled in the art will understand that certain features of these various embodiments and variations could be combined, and other variations will become apparent to a person skilled in the art.

[0107] Finally, the practical implementation of the embodiments and variants described is within the reach of a person skilled in the art, based on the functional indications given above.

Claims

Demands

1. Electronic chip (100) comprising: - a semiconductor substrate (102) in and on which an integrated circuit (104) is formed; - at least one connection metallization (106) of the integrated circuit (104) formed on the side of a front face of the semiconductor substrate (102); - a first passivation layer (108) covering the front face of the semiconductor substrate (102), the first passivation layer (108) having openings aligned with the connection metallization (106) of the integrated circuit (104); and a second passivation layer (110) covering lateral sides of the semiconductor substrate (102), the second passivation layer (110) being in parylene and the first passivation layer (108) and the second passivation layer (110) being in contact with the front side of the semiconductor substrate (102).

2. Electronic chip (100) according to claim 1, wherein the second passivation layer (110) is made of parylene-N.

3. Electronic chip (100) according to claim 1, wherein the second passivation layer (110) is parylene-C.

4. Electronic chip (100) according to claim 1, wherein the second passivation layer (110) is parylene-AF4.

5. Chip according to any one of claims 1 to 4, wherein a rear face of the semiconductor substrate (102), opposite to the front face of the semiconductor substrate (102), is covered by the second passivation layer (110).

6. A method for manufacturing a plurality of electronic chips from a structure comprising: - a plurality of integrated circuits (104) formed in and on a semiconductor substrate (102); - at least one connection metallization (106) per integrated circuit (104) formed on the side of a front face of the semiconductor substrate (102); and - a first passivation layer (108) covering the front face of the semiconductor substrate (102), the first passivation layer (108) having openings aligned with the connection metallizations (106) of the integrated circuits (104), the process comprising a step of depositing a second passivation layer (110) on the lateral sides of the semiconductor substrate (102), the second passivation layer (110) being in a parylene and the first passivation layer (108) and the second passivation layer (110) being in contact with the side of the front face of the semiconductor substrate (102).

7. A method according to claim 6, wherein the step of depositing the second passivation layer (110) comprises: - a vaporization step in which solid parylene dimers are heated and vaporized into a dimer gas; - a pyrolysis step in which the dimer gas is pyrolyzed to transform the dimers into their monomer forms; and - a deposition step in which the monomer gas is deposited on all exposed surfaces.

8. Method according to claim 6 or 7, wherein during the step of depositing the second passivation layer (110), the second passivation layer (110) is deposited on the back face of the semiconductor substrate (102).

9. A method according to any one of claims 6 to 8, wherein the step of depositing the second passivation layer (110) is preceded by a step of forming first trenches (116; 124) in the semiconductor substrate (102).

10. A method according to claim 9, wherein the first trenches (116; 124) are non-through and are formed by the front face of the semiconductor substrate (102) and the step of forming the first trenches (166; 124) is followed by a step of forming openings (122), in the semiconductor substrate (102), from the back face of the semiconductor substrate (102), opposite the first trenches (116; 124).

11. A method according to claim 9 or 10, wherein the step of depositing the second passivation layer (110) is followed by a step of forming second trenches (120) opposite the first trenches (116; 124) so ​​as to form individual electronic chips (100).

12. A method of using an electronic chip (100) according to any one of claims 1 to 5, comprising a step of transferring the electronic chip to the side of its connection metallization (106) on a metallization of an external device (112), the transfer step consisting of the deposition of a brazing material (114) on the metallization of the external device (112) and then the compression of the electronic chip (100) on the external device (112).

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