Silicon carbide epitaxy

Abstract

A method of growing epitaxial 4H-SiC on 4H-SiC comprising: Heating a 4H-SiC substrate 2 to a temperature equal to or greater than 1200℃ and less than or equal to 1600℃ to anneal the substrate; and, depositing an epitaxial layer 12 of 4H-SiC on the substrate at a second temperature equal to or greater than 1400℃ and equal to or less than 1600℃. The substrate may be subdivided into a plurality of mesa regions 6 by at least one cavity 9 and the epitaxial deposition occurs in the cavity. The deposition may be in the presence of a chlorine-containing gas such as hydrogen chloride. The substrate and epitaxial layer may have opposite conductivity types. The method may produce a homostructure or a superfunction structure, and may be used in a power semiconductor device.

Description

Field of the Invention The present invention relates silicon carbide epitaxy. In particular, the present invention relates to growing epitaxial 4H-SiC on 4H-SiC. The present invention also relates to superjunctions. Background Silicon carbide is an attractive material for power electronics applications because it can sustain much higher voltages and currents than silicon, can operate at much higher temperature than silicon, and has a thermal conductivity similar to copper. Silicon carbide exists in several different crystal forms (or "polytypes") depending on the sequence in which bilayers of silicon and carbon stack. One of the most commonly used polytypes of silicon carbide is four-step hexagonal sequence silicon carbide (4H-SiC). The material can be used to fabricate power semiconductor devices such as metal-oxide-semiconductor field-effect transistors (MOSFETs). It can be desirable to reduce the specific on resistance of unipolar silicon carbide power semiconductor devices, particularly in devices for high voltage (for example, above 1.7 kV) applications. One way to achieve this is to make use of a superjunction structure in which p and n type layers are arranged in a repeating structure that extends laterally through a device, typically a MOSFET, forming the drift region. The superjunction effectively extends the drift region and can reduce the specific on resistance of the device. Silicon-based superjunctions can be made by multiepitaxial growth. It is, however, costly to produce silicon carbide-based superjunctions with a high column depth and, so far, alternatives such as sidewall implantation methods are limited to relatively low aspect ratio columns (for example, columns having a depth to width ratio equal to or less than 2) and low surface areas. Trench filling epitaxy, in which etched cavities between mesa regions are refilled through a partially selective epitaxial process, provides a feasible way to fabricate silicon carbide based superjunctions at the high aspect ratios (for example, columns having a depth to width ratio equal to or greater than 2.5) required to support high voltage. Growth of high-quality 4H-SiC layers by trench filling epitaxy can, however, be difficult to achieve. In particular, voids can be formed by premature trench closing 134086GB1 and ultimately degrade device performance, end surfaces which are not flat can result from overgrowth on mesa regions and mean that planarization is required before further device fabrication steps can be carried out, and trench filling epitaxy methodologies can have narrow process windows. 5 R. Kosugi et al.: "Strong impact of slight trench direction misalignment from

[1120] on deep trench filling epitaxy for SiC super-junction devices", Japanese Journal of Applied Physics, volume 56, page 04CR05 (2017) describes that trenches need to be aligned within 0.5° of the

[1120] crystal direction to permit high-quality 4H-SIC growth. This 10 angle is equivalent to the standard variation in wafer alignment during mass fabrication. Z. Zhao et al.: "4H-SIC trench filling by chemical vapor deposition using trichlorosilane as Si-species precursor", Journal of Crystal Growth, volume 607, page 127104 (2023) 15 describes 4H-SiC trench filling by chemical vapor deposition with a gas mixture comprising trichlorosilane, ethylene, hydrogen, and hydrogen chloride at a growth temperature of 1650 °C and a growth pressure of 60 kPa. Summary According to a first aspect of the present invention there is provided a method comprising heating a 4H-SiC substrate in the presence of hydrogen to a first temperature equal to or greater than 1,200 °C and equal to or less than 1,600 °C so as to anneal the substrate, and depositing an epitaxial layer of 4H-SiC on the substrate at a second temperature equal to or greater than 1,400 °C and equal to or less than 1,600 °C. The combination of hydrogen annealing at a temperature equal to or greater than 1,200 °C and equal to or less than 1,600 °C, and epitaxial deposition at a temperature equal to or greater than 1,400 °C and equal to or less than 1,600 °C, can help form a high-quality 4H-SiC layer on 4H-SiC. The high-quality 4H-SiC layer may be monocrystalline and substantially void-free. The high-quality 4H-SiC layer may have a planar end surface having an RMS surface roughness equal to or less than 10 nm or equal to or less than 7 nm, as measured using an atomic force microscope. The first temperature may be between 1,200 °C and 1,600 °C. The second temperature may be between 1,400 °C and 1,600 °C. The first temperature may be equal to or greater than 1,400 °C and / or equal to or less than 1,550 °C. The second temperature may be equal to or greater than 1,450 °C and / or equal to or less than 1,550 °C. The first temperature may be between 1,400 °C and 1,550 °C. The second temperature may be between 1,450 °C and 1,550 °C. Heating the 4H-SiC substrate in the presence of hydrogen may be carried out on an unpatterned substrate or a patterned substrate. Depositing the epitaxial layer of 4H-SiC may be carried out on an unpatterned substrate which has been heated in the presence of hydrogen to the first temperature so as to be annealed or a patterned substrate which has been heated in the presence of hydrogen to the first temperature so as to be annealed. The method may further comprise forming a structure in the substrate such that the structure extends from a main surface of the substrate into a first semiconductor layer of the substrate and such that the structure subdivides the first semiconductor layer into a plurality of mesa regions, the structure comprising at least one cavity. Depositing the epitaxial layer on the substrate may comprise depositing the epitaxial layer in the at least one cavity. Forming the structure in the substrate may be carried out on an unpatterned substrate or a patterned substrate. Each cavity may be a gap or a depression between mesa regions. Each mesa region may have a respective mesa top surface and at least one respective sidewall surface. Each cavity may have a respective cavity bottom surface. Each mesa top surfaces may be flat. Each cavity bottom surface may be flat. Mesa regions and cavities may be arranged in a repeating structure. The repeating structure may have translational symmetry. A pitch of the repeating structure (that is, a distance between repeated elements in the repeating structure) may be equal to or greater than 1.6 pm and equal to or less than 100 pm, optionally equal to or greater than 2 pm and / or equal to or less than 50 pm. A pitch of the repeating structure may be between 1.6 pm and 100 pm, optionally between 2 pm and 50 pm. The mesa regions may each have a width of around half the pitch. Each cavity may have a depth to width ratio equal to or greater than 2.5, equal to or greater than 5, equal to or greater than 10, or equal to or greater than 30. The substrate may be {0001} oriented and, optionally, have a non-zero miscut angle. The miscut angle may be equal to or less than 8°, optionally equal to or less than 4°. The miscut angle may deviate from the <0001> direction of the substrate along a <1120 >direction of the substrate or a <1100> direction of the substrate. The substrate may have a miscut angle of around 0°. Each mesa may have a sidewall surface which extends along a <U20> direction of the substrate. Each mesa region may have a sidewall surface that is inclined at an angle equal to or less than 30° relative to an <0001 >direction of the substrate. Each mesa region may have a sidewall surface that is inclined at an angle equal to or less than 20° relative to an <0001> direction of the substrate. Each mesa region may have a sidewall surface that is inclined at an angle equal to around 8° relative to an <0001> direction of the substrate. The mesa regions may be pillars, for example hexagonal pillars. The mesa regions may be elongate. Two or more elongate mesa regions may be discrete, for example if they extend along the same direction and are laterally offset. Three or more mesa regions may intersect to form a grid. The grid may be according to any one of the five 2D Bravais lattices, with a motif Including one or more mesa regions. The grid may be a quadrilateral grid or a hexagonal grid. Forming the structure may comprise providing an unpatterned 4H-SiC substrate having an initial surface and forming the structure on or from the initial surface. Forming the structure(s) may comprise applying an etch mask to the initial surface. The etch mask may be a patterned hardmask layer, a patterned resist layer, or a shadow mask (or "stencil") to the initial surface. The hardmask layer or the resist layer may be patterned using photolithography, electron beam lithography, proton beam writing (or "p-beam writing"), ion beam lithography, direct-write lithography, or soft lithography. Forming the structures may comprise applying a protective layer to the initial surface, such as a SiO2 protective layer, prior to applying the etch mask. The main surface may comprise portions of the initial surface. The method may comprise forming the structure on the substrate such that the structure extends from the main surface away from the first semiconductor layer such that the structure defines a plurality of mesa regions which are extensions of the first semiconductor layer. Forming the structure may comprise etching. Etching may comprise reactive ion etching or ion beam milling. Gases used during reactive ion etching may include hexafluorobutadiene (C4F6), sulphur hexafluoride (SFe), argon (Ar), oxygen (O2), tetrafluoromethane (CF4), and / or other suitable gas(es). Ion beam milling may comprise broad argon beam ion milling. Ion beam milling may comprise focused ion beam milling. The substrate may comprise, substantially consist of, or consist of a single-crystal 4H-SiC substrate. The substrate may comprise, substantially consist of, or consist of a monocrystalline 4H-SiC layer disposed on a polycrystalline layer. The substrate may be an engineered substrate, such as an Auto SmartSiC (RTM) substrate. The substrate may include a 4H-SiC epilayer deposited prior to the method being carried out. The substrate may include a 4H-SiC epilayer disposed on the single-crystal 4H-SiC substrate, the monocrystalline 4H-SiC layer, or the engineered substrate. Expressed differently, the substrate may be a buffered substrate including a 4H-SiC epilayer as a buffer layer. The main surface of the substrate may be a surface of the epilayer. The epilayer may be of the same conductivity type (for example, p type or n type) as the single-crystal 4H-SiC substrate or the monocrystalline 4H-SiC layer. The epilayer may have a different conductivity to the single-crystal 4H-SIC substrate or the monocrystalline 4H-SiC layer. The substrate may have a diameter which is equal to or greater than 100 mm, equal to or greater than 150 mm, or equal to or greater than 200 mm. The substrate need not be {0001} oriented. In the case that the substrate comprises the monocrystalline 4H-SIC layer disposed on the polycrystalline layer, the structure may not extend from the main surface into the polycrystalline layer. In the case that the substrate comprises the epilayer, the structure may not extend from the main surface into a layer upon which the epilayer is disposed. The substrate may be a lithographically-patterned substrate. Heating the substrate may be carried out in the presence of a chlorine-containing gas. The chlorine-containing gas may not comprise silicon or carbon. The chlorinecontaining gas may be hydrogen chloride. The chlorine-containing gas may be chlorine (CI2), boron trichloride (BCH), chlorine trifluoride (CIF3), or another chlorine-containing gas for use as an etchant gas in chloride-based chemical vapour deposition. Heating the substrate may be carried out in a pure hydrogen atmosphere. Heating the substrate may be carried out at a pressure equal to or greater than 10 mbar and equal to or less than 300 mbar, optionally equal to or greater than 80 mbar and / or equal to or less than 120 mbar. Heating the substrate may be carried out at a pressure between 10 mbar and 300 mbar, optionally between 80 mbar and 120 mbar. Heating the substrate may be carried out at a hydrogen flow rate equal to or greater than 10 slm and equal to or less than 200 slm, optionally equal to or greater than 80 slm and / or equal to or less than 120 slm, optionally equal to or greater than 90 slm and / or equal to or less than 110 slm. Heating the substrate may be carried out at a hydrogen flow rate between 10 slm and 200 slm, optionally between 80 slm and 120 slm, optionally between 90 slm and 110 slm. Heating the substrate may comprise heating the substrate at a rate equal to or greater than 10 °C / min and equal to or less than 100 °C / min, optionally equal to or greater than 25 °C / min and / or equal to or less than 75 °C / min. Heating the substrate may comprise heating the substrate at a rate between 10 °C / min and 100 °C / min, optionally between 25 °C / min and 75 °C / min. Heating the substrate may comprise maintaining a temperature of the substrate at the first temperature for a time interval equal to or greater than 1 minute and equal to or less than 120 minutes prior to depositing the epitaxial layer of 4H-SiC on the substrate. Heating the substrate may comprise maintaining a temperature of the substrate at the first temperature for a time interval between 1 minute and 120 minutes prior to depositing the epitaxial layer of 4H-SiC on the substrate. A temperature of the substrate may be maintained at the first temperature for a time interval equal to or greater than 5 minutes and / or equal to or less than 60 minutes. A temperature of the substrate may be maintained at the first temperature for a time interval between 5 minutes and 60 minutes. Depositing the epitaxial layer of 4H-SIC on the substrate may be carried out at the end of the time interval or after the end of the time Interval. In the case that heating the substrate is carried out in the presence of a chlorinecontaining gas, such as hydrogen chloride (HCI), while the temperature of the substrate Is maintained at the first temperature for the time interval, a flow rate of the chlorine-containing gas may be equal to or greater than 0.1 seem and equal to or less than 1500 seem, optionally equal to or greater than 100 seem and / or equal to or less than 900 seem. In the case that heating the substrate Is carried out in the presence of a chlorine-containing gas such as hydrogen chloride (HCI), while the temperature of the substrate is maintained at the first temperature for the time interval, a flow rate of the chlorine-containing gas may be between 0.1 seem and 1500 seem, optionally between 100 seem and 900 seem. Depositing the epitaxial layer of 4H-SiC may be carried out at the end of the time interval. The first temperature may be equal to the second temperature. The first temperature may be different to the second temperature. The first temperature may be greater than the second temperature or less than the second temperature. Heating the substrate may comprise changing a temperature of the substrate from the first temperature to the second temperature over a time interval sufficient to allow facet surfaces to form. Depositing the epitaxial layer of 4H-SIC may be carried out at the end of the time interval. The first temperature may be within 300 °C of the second temperature. The first temperature may be within 100 °C of the second temperature. The first temperature may be within 50 °C of the second temperature. A rate at which the temperature of the substrate is changed from the first temperature to the second temperature may be equal to or greater than 10 °C / min and equal to or less than 100 °C / min, optionally equal to or greater than 25 °C / min and / or equal to or less than 75 °C / min. A rate at which the temperature of the substrate is changed from the first temperature to the second temperature may be between 10 °C / min and 100 °C / min, optionally between 25 °C / min and 75 °C / min. Depositing the epitaxial layer of 4H-SIC may be carried out by chemical vapour deposition in a gas mixture comprising a silicon source precursor, a carbon source precursor, and a carrier gas. Depositing the epitaxial layer of 4H-SIC may be carried out by remote plasma chemical vapour deposition (RPCVD), high-temperature chemical vapor deposition (HTCVD), metal-organic chemical vapour deposition (MOCVD), or plasma-enhanced chemical vapor deposition. Depositing the epitaxial layer of 4H-SiC may be carried out at a pressure equal to or greater than 10 mbar and equal to or less than 300 mbar, optionally equal to or greater than 80 mbar and / or equal to or less than 120 mbar, such as 100 mbar. Depositing the epitaxial layer of 4H-SIC may be carried out at a pressure between 10 mbar and 300 mbar, optionally between 80 mbar and 120 mbar, such as 100 mbar. The silicon source precursor may be different to the carbon source precursor. The silicon source precursor may be the same as the carbon source precursor. The silicon source precursor may be a chlorine-containing silane. The silicon source precursor may be silane (SiH4) or another suitable silicon source precursor which does not contain chlorine. The chlorine-containing silane may be trichlorosilane. Depositing the epitaxial layer of 4H-SiC may be carried out at a trichlorosilane flow rate equal to or greater than 10 seem and equal to or less than 470 seem, optionally equal to or greater than 20 seem and / or equal to or less than 150 seem. Depositing the epitaxial layer of 4H-SIC may be carried out at a trichlorosilane flow rate between 10 seem and 470 seem, optionally between 20 seem and 150 seem. The chlorine-containing silane may be dichlorosilane (H2SiCl2), methyltrichlorosilane (CHsSiCh), or another suitable chlorine-containing silane. The carbon source precursor may be ethylene. Depositing the epitaxial layer of 4H-SIC may be carried out at an ethylene flow rate equal to or greater than 8 seem and equal to or less than 220 seem, optionally equal to or greater than 10 seem and / or equal to or less than 100 seem. Depositing the epitaxial layer of 4H-SIC may be carried out at an ethylene flow rate between 8 seem and 220 seem, between 10 seem and equal to or less than 100 seem. The carbon source precursor may be propane (CsHs) or another suitable carbon source precursor. The carrier gas may be hydrogen. Depositing the epitaxial layer of 4H-SiC may be carried out at a hydrogen flow rate equal to or greater than 10 slm and equal to or less than 200 slm, optionally equal to or greater than 80 slm and / or equal to or less than 120 slm, optionally equal to or greater than 90 slm and / or equal to or less than 110 slm. Depositing the epitaxial layer of 4H-SiC may be carried out at a hydrogen flow rate between 10 slm and 200 slm, optionally between 80 slm and 120 slm, optionally between 90 slm and 110 slm. The carrier gas may be argon (Ar) or another suitable carrier gas. The gas mixture may further comprise a chlorine-containing gas which is not the silicon source precursor or the carbon source precursor. The chlorine-containing gas which is not the silicon source precursor or the carbon source precursor may be hydrogen chloride. Depositing the epitaxial layer of 4H-SIC may be carried out at a hydrogen chloride flow rate equal to or greater than 0.1 seem and equal to or less than 1500 seem, optionally equal to or greater than 100 seem and / or equal to or less than 1000 seem. Depositing the epitaxial layer of 4H-SIC may be carried out at a hydrogen chloride flow rate between 0.1 seem and 1500 seem, optionally between 100 seem and 1000 seem. The chlorine-containing gas which is not the silicon source precursor or the carbon source precursor may be chlorine (Ch), boron trichloride (BCh), chlorine trifluoride (CIF3), or another chlorine-containing gas for use as a suitable etchant gas in chloride-based chemical vapour deposition. The gas mixture may have a C / Si ratio equal to or greater than 0.4 and equal to or less than 1.5, optionally equal to or greater than 0.6 and / or equal to or less than 1.2, for example 0.75. The gas mixture may have a C / Si ratio between 0.4 and 1.5, optionally between 0.6 and 1.2, for example 0.75. The gas mixture may have a Cl / Si ratio equal to or greater than 2 and equal to or less than 60, optionally equal to or greater than 3 and / or equal to or less than 30. The gas mixture may have a Cl / Si ratio between 2 and 60, optionally between 3 and 30. The gas mixture may have a Si / H ratio equal to or greater than 0.008% and equal to or less than 0.6%, optionally equal to or greater than 0.01 and / or equal to or less than 0.2%. The gas mixture may have a Si / H ratio between 0.008% and 0.6%, optionally between 0.01% and 0.2%. Depositing the epitaxial layer of 4H-SIC may be carried out while rotating the substrate in the gas mixture at a rate equal to or greater than 5 rpm and equal to or less than 120 rpm, optionally equal to or greater than 20 rpm and / or equal to or less than 80 rpm. Depositing the epitaxial layer of 4H-SiC may be carried out while rotating the substrate in the gas mixture at a rate between 5 rpm and 120 rpm, optionally between 20 rpm and 80 rpm. Depositing the epitaxial layer of 4H-SiC may be carried out until at least a time at which the epitaxial layer has a thickness equal to or greater than 0.1 pm and equal to or less than 100 pm, optionally equal to or greater than 0.5 pm and / or equal to or less than 30 pm, optionally equal to or greater than 2 pm and / or equal to or less than 30 pm, optionally equal to or greater than 3 pm and / or equal to or less than 30 pm. Depositing the epitaxial layer of 4H-SIC may be carried out until at least a time at which the epitaxial layer has a thickness between 0.1 pm and 100 pm, optionally between 0.5 pm and 30 pm, optionally between 2 pm and less than 30 pm, optionally between 3 pm and 30 pm. Depositing the epitaxial layer of 4H-SiC may be carried out until at least a time at which the epitaxial layer has a thickness equal to or greater than double a width of a cavity between two mesa regions. The gas mixture may further comprise a p doped source precursor and / or an n doped source precursor. The p doped source precursor may be trimethylaluminium (Al2(CH3)6), diborane (B2H6), or another suitable p doped source precursor. The n doped source precursor may be nitrogen (N2), ammonia (NH3), phosphine (PH3), or another suitable n doped source precursor. A bake-out process may be carried out on a chemical vapour deposition reactor in which the method is performed prior to loading the substrate. The bake-out process may comprise maintaining a temperature of walls of the reactor at around 1100 °C for several hours under vacuum conditions. Forming the structure may further comprise forming a plurality of trenches that each extend from the main surface of the substrate into the first semiconductor layer. Forming the structure may further comprises forming a cavity in each of the trenches. The trenches may be parallel trenches. The parallel trenches may be arranged In a repeating structure. A pitch of the repeating structure may be equal to or greater than 1.6 pm and equal to or less than 100 pm. A pitch of the repeating structure may be equal to or greater than 2 pm and / or equal to or less than 50 pm. A pitch of the repeating structure may be between 1.6 pm and 100 pm. A pitch of the repeating structure may be between 2 pm and 50 pm. The mesa regions may each have a respective width of around half the pitch. The trenches may be not parallel. The trenches may intersect. The trenches may have a depth equal to or greater than 0.1 pm and equal to or less than 30 pm, optionally equal to or greater than 0.5 pm and / or equal to or less than 20 pm. The trenches may have a depth between 0.1 pm and 30 pm, optionally between 0.5 pm and 20 pm. Each trench may have a depth to width ratio equal to or greater than 2.5, equal to or greater than 5, equal to or greater than 10, or equal to or greater than 30. The substrate may be {0001} oriented and, optionally, have a non-zero miscut angle. The miscut angle may be equal to or less than 8°, optionally equal to or less than 4°. The miscut angle may deviate from the <0001> direction of the substrate along a <1120 >direction of the substrate or a <1100> direction of the substrate. The substrate may have a miscut angle of around 0°. Each mesa region may have a sidewall surface which extends along a direction within 1.5° of a <1120> direction of the substrate or within 1.5° of a <1100> direction of the substrate. Each mesa region may have a sidewall surface which extends along a direction within 1.5° of a <U20> direction of the (patterned) substrate or within 1.5° of a <1100> direction of the (patterned) substrate. Each sidewall surface may be inclined at an angle equal to or less than 30° relative to an <oooi> direction of the substrate. Each mesa region may have a sidewall surface that is Inclined at an angle equal to or less than 20° relative to an <0001> direction of the substrate, for example, 2°, 5° or 8°. Mesa sidewalls may have an undercut or an overcut. In other words, the angle can be positive or negative. The sidewalls may be perpendicular to a principal plane of the substrate. The substrate may be on-axis or off-axis. The substrate may be a vicinal substrate. A surface normal to the main surface may deviate from a <0001> direction of the substrate by a miscut angle equal to or less than 8°, optionally equal to or less than 4°. The mlscut angle may deviate from the <0001> direction of the substrate along a <1120 >direction of the substrate or a <1100> direction of the substrate. The substrate may have a miscut angle of around 0°. Depositing the epitaxial layer of 4H-SiC may be carried out until at least a time at which a deposited epitaxial layer of 4H-SiC having a planar end surface is provided, the planar end surface having an RMS surface roughness equal to or less than 10 nm or equal to or less than 7 nm. RMS surface roughness can be measured using an atomic force microscope. Heating the substrate may be carried out until at least a time at which top corner facet surfaces and / or bottom corner facet surfaces form on each of the mesa regions, the top corner facet surfaces and / or bottom corner facet surfaces having a length equal to or greater than 0.05 pm. At the time, the top corner facet surfaces and / or the bottom corner facet surfaces may have a length equal to or greater than 0.1 pm. At the time, the top corner facet surfaces and / or the bottom corner facet surfaces may have a length equal to or greater than 1 pm. At the time, the top corner facet surfaces and / or bottom corner facet surfaces may have a length equal to or greater than 5 pm. At the time, the top corner facet surfaces and / or bottom corner facet surfaces may have a length equal to or greater than 10 pm. At the time, the top corner facet surfaces and / or bottom corner facet surfaces may have a length equal to or less than 1.5 pm. At the time, the top corner facet surfaces and / or bottom corner facet surfaces may have a length equal to or less than 0.8 pm. Depositing the epitaxial layer on the annealed substrate may further comprise depositing the epitaxial layer on the top corner facet surfaces and / or the bottom corner facet surfaces. Prior to deposition, the annealed substrate may have a profile which includes flat mesa top surfaces, flat sidewall surfaces, flat cavity bottom surfaces, flat top corner facet surfaces between mesa top surfaces and sidewall surfaces, and flat bottom corner facet surfaces between sidewall surfaces and cavity bottom surfaces. Each facet surface may be inclined at a facet angle relative to a <0001> direction of the substrate, the facet angle equal to or greater than 35° and equal to or less than 70°, optionally equal to or greater than 40°and / or equal to or less than 65°, optionally equal to or greater than 40°and / or equal to or less than 50°. Each facet surface may be inclined at a facet angle relative to a <0001> direction of the substrate, the facet angle between 35° and 70°, optionally between 40°and 65°, optionally between 40°and 50°. Each facet surface may be faceted to one or more crystal planes. Each facet surface may be faceted to a lithographically-defined surface, such a surface of a mesa region. The lithographically-defined surface need not be parallel to a crystal plane. The substrate may have a first conductivity type and the epitaxial layer may have a second conductivity type opposite to the first conductivity type. According to a second aspect of the present invention there is provided a homostructure obtained by the method of the first aspect. Chemical-mechanical polishing (CMP) and / or dry etching may be used to remove an end surface of the epitaxial layer of the homostructure so as to expose an upper surface of a repeating pattern of alternating columns of the annealed substrate and of the epitaxial layer. According to a third aspect of the present invention there is provided a superjunction structure obtained by the method of the first aspect. According to a fourth aspect of the present invention there is provided a superjunction structure having a faceted interface between a p-column structure and an n-column structure. The faceted interface may include a bottom corner facet surface and / or a top corner facet surface. According to a fifth aspect of the present invention there is provided a power semiconductor device comprising a drift region, the drift region comprising the superjunction structure of the third aspect or the fourth aspect. The drift region may substantially consist of or consist of the superjunction structure. The power semiconductor device may be a unipolar device such as a power metal-oxide-semlconductor field-effect transistor (MOSFET) or a Schottky barrier diode (SBD). 5 The power semiconductor device may be a PiN diode (PIN), an insulated-gate bipolar transistor (IBGT), a gate turn-off thyristor (GTO), or another power semiconductor device having a drift region suitable for incorporating a superjunction structure. According to a sixth aspect of the present invention there is provided a power 10 conversion assembly comprising the power semiconductor device of the fifth aspect. The power conversion assembly may be a DC-AC converter (inverter) such as a photovoltaic inverter. The power conversion assembly may be another power conversion assembly in which the power semiconductor device may be implemented. 15 According to a seventh aspect of the present invention there is provided a vehicle comprising the power conversion assembly of the sixth aspect. The vehicle may be a hybrid vehicle or a fully electric vehicle. Brief Description of the Drawings Certain embodiments of the present invention will now be described, by way of example, with reference to the accompanying drawings in which: Figure 1 schematically illustrates growing epitaxial 4H-SiC on 4H-SiC; Figure 2 is a process flow diagram of a method of growing epitaxial 4H-SiC on 4H-SIC; Figure 3 illustrates a temperature profile of a 4H-SiC epitaxial growth process; Figure 4 is a process flow diagram of a 4H-SiC epitaxial growth process; Figure 5 schematically illustrates forming a structure in a 4H-SiC substrate; Figure 6 schematically illustrates a patterned 4H-SiC substrate with parallel trenches; Figure 7 schematically illustrates a patterned 4H-SiC substrate comprising mesa regions having sloped sidewalls; Figure 8 schematically illustrates an annealed 4H-SiC substrate comprising mesa regions having sloped sidewalls and facet surfaces; Figure 9 schematically illustrates an annealed 4H-SiC substrate and an epitaxial layer of 4H-SiC deposited thereon forming a superjunction structure; Figure 10 is a schematic block diagram of a power semiconductor device comprising the superjunction structure shown in Figure 9; Figure 11 is a set of cross-sectional SEM micrographs showing (top) 4 pm pitch, 2 pm sloped trenches refilled with 1000 seem of HCI and (bottom) 8 pm pitch, 8 pm sloped trenches refilled with 500 seem of HCI; Figure 12 schematically illustrates growing epitaxial 4H-SIC on the annealed 4H-SiC substrate shown in Figure 8; Figure 13 shows plots of void area and percentage trench fill against mesa sidewall angle for different pitch sizes, at a constant HCI flow rate; Figure 14A is a set of cross-sectional SEM micrographs showing filled trenches of 4 pm, 8 pm, and 20 pm pitch size at sidewall angles of 2°, 5°, and 8°; Figure 14B shows plots of initial epilayer growth rate on mesa top surfaces, mesa sidewalls, and trench bottom surfaces against sidewall angle for trenches of 4 pm and 8 pm pitch and schematically illustrates exaggerated relative growth rates highlighted on each plot by dashed borders for correspondingly labelled SEM micrographs shown in Figure 14A; Figure 15A is a set of cross-sectional SEM micrographs showing filled trenches of 4 pm at a sidewall angle of 2° under different flow rates of HCI, with overlaid lines following void top and bottom position across the set of micrographs; Figure 15B is a set of cross-sectional SEM micrographs showing filled trenches of 8 pm at a sidewall angle of 2° under different flow rates of HCI, with overlaid lines following void top and bottom position across the set of micrographs; Figure 16A shows a plot of percentage trench fill against HCI flow rate for 8 pm pitch trenches at sidewall angles of 2°, 5°, and 8°; Figure 16B shows a plot of epilayer thickness on mesa top surfaces, faceted top corner surfaces, and trench bottom surfaces, against HCI flow rate at sidewall angles of 2°, 5°, and 8° for 8 pm trenches; Figure 16C schematically illustrates how facet-mesa top boundary angle Ofi determines end surface topography at 6 pm growth thickness; Figure 16D shows a plot of top corner facet layer thickness against the facet boundary angles, 0fi and ¢=2, at different HCI flow rates; Figure 16E is a set of cross-sectional SEM micrographs showing 8 pm pitch trenches at a sidewall angle of 2° at different HCI flow rates, with highlighted facet layers reflecting those depicted in Figure 16C; Figure 17A is a 10 pm x 10 pm AFM micrograph of the surface morphology of a 2 pm trench refill without HCI; Figure 17B is a 30 pm x 30 pm AFM micrograph of the surface morphology of a 2 pm trench refill without HCI; Figure 17C is a 10 pm x 10 pm AFM micrograph of the surface morphology of a 2 pm trench refill at 500 seem HCI flow rate; Figure 17D is a 30 pm x 30 pm AFM micrograph of the surface morphology of a 2 pm trench refill at 500 seem HCI flow rate; Figure 17E is a 10 pm x 10 pm AFM micrograph of the surface morphology of a 2 pm trench refill at 1000 seem HCI flow rate; Figure 17F is a 30 pm x 30 pm AFM micrograph of the surface morphology of a 2 pm trench refill at 1000 seem HCI flow rate; Figure 18A is a set of SEM micrographs showing the influence of trench angle from the <1120> direction on the growth direction; Figure 18B shows a plot of growth angle calculated from SEM imaging away from the

[0001] direction against trench angle from the <1120> direction; Figure 19 is a set of SEM micrographs showing 4H-SiC trenches annealed in hydrogen for 1 min, 10 min, and 2 hr; and Figure 20 Is a set of SEM micrographs showing two different trench / mesa profiles refilled under different flow rates of hydrogen chloride. Detailed Description of Certain Embodiments Introduction Herein, deposition of epitaxial 4H-SiC on a hydrogen-annealed 4H-SiC substrate is described. The combination of hydrogen annealing at a temperature equal to or greater than 1,200 °C and equal to or less than 1,600 °C, and deposition at a temperature equal to or greater than 1,400 °C and equal to or less than 1,600 °C can help form a high-quality 4H-SiC layer on 4H-SiC. A 4H-S1C layer can be considered to be a high-quality 4H-SiC layer if it is monocrystalline, substantially void-free, and has a planar end surface having an RMS surface roughness equal to or less than 10 nm or equal to or less than 7 nm as measured using an atomic force microscope. In particular, the method can be used to fabricate superjunction structures, alternating p / n columns, and / or selectively doped regions in a way which is suitable for application in front-end-of-line (FEOL) processing in semiconductor foundries. 4H-SiC / 4H-SiC structure 1 Referring to Figures 1 and 2, growth of epitaxial 4H-SiC on 4H-SIC to provide a 4H-SiC / 4H-SiC structure 1 is shown. A 4H-SiC substrate 2 having a main surface 3 is prepared for deposition of 4H-SIC by forming a structure 4 in the main surface 3 (steps Sl.l and SI.2; steps S2.1 and S2.2). By forming the structure 4 in the main surface 3, the substrate 2 is modified, that is, patterned. Figure 1 shows this being achieved by etching selected areas of the main surface 3 to subdivide a first semiconductor layer 5 of the substrate 2 (that is, a surface region of the substrate 2) into a plurality of mesa regions 6 each having a mesa top surface 7 and mesa sidewall surfaces 8, so as to provide a patterned substrate 2'. The mesa regions 6 are separated by cavities 9, each of which have a cavity bottom surface 10. The formation of the structure 4 is described in more detail hereinafter with reference to Figure 5. The patterned substrate 2' is then heated in a hydrogen atmosphere to modify the structure 4 (step SI.3; step S2.3), so as to provide an annealed substrate 2". Figure 1 shows the structure 4 as being modified by forming facet surfaces 11 at top and bottom corners of the mesa regions 6, and the facet surfaces 11 can help to promote void-free layer growth. The modification of the structure 4 is carried out at a first temperature equal to or greater than 1,200 °C and equal to or less than 1,600 °C. The first temperature may be equal to or greater than 1,400 °C and equal to or less than 1,550 °C. Next, an epitaxial layer 12 of 4H-SIC is deposited on the annealed substrate 2" (step SI.4; step S2.4) using a partially-selective epitaxial process in which cavities 9 are preferentially filled. The deposition is carried out at a second temperature equal to or greater than 1,400 °C and equal to or less than 1,600 °C. The second temperature may be equal to or greater than 1,450 °C and equal to or less than 1,550 °C. After the cavities 9 are filled, the epitaxial layer 12 can proceed to form a planar end surface 13. The planar end surface 13 can have an RMS surface roughness equal to or less than 10 nm or equal to or less than 7 nm, as measured using atomic force microscopy. The formation of a planar end surface 13 follows from growth above the level of the cavities 9 being even, and can permit chemical mechanical polishing and dry etching to be used to efficiently smooth and etch back overgrowth prior to subsequent device fabrication steps being carried out without there being any need to use purely mechanical polishing techniques such as grinding to flatten the already relatively flat planar end surfaces 13. The second temperature (that is, the deposition temperature) being relatively low (for example, equal to or less than 1600 °C) can help the epitaxial layer 12 to form a planar end surface 13. The patterned substrate 2' may be heated in the presence of a chlorine-containing gas in addition to hydrogen (H2). The chlorine-containing gas may be hydrogen chloride (HCI), chlorine (Ch), boron trichloride (BCh), or chlorine trifluoride (CIF3). Annealing in the presence of both hydrogen and a chlorine-containing gas such as hydrogen chloride (HCI) can help facet surfaces 11 which promote void-free layer growth to form, while also helping to flatten mesa top surfaces 7 and cavity bottom surfaces 10. In particular, annealing in the presence of hydrogen chloride (HCI) can help to flatten features such as microtrenches resulting from etching. Alternatively, the patterned substrate 2' may be heated in a pure hydrogen atmosphere. The patterned substrate 2' is heated at a pressure equal to or greater than 10 mbar and equal to or less than 300 mbar. The pressure may be equal to or greater than 80 mbar and equal to or less than 120 mbar. Deposition of the epitaxial layer 12 is carried out by chemical vapour deposition, for example by remote plasma chemical vapour deposition (RPCVD), high-temperature chemical vapor deposition (HTCVD), metal-organic chemical vapour deposition (MOCVD), or plasma-enhanced chemical vapor deposition. A wide variety of gas mixtures can be used in the deposition of 4H-SiC by chemical vapour deposition. Typically, the gas mixture includes a silicon source precursor, a carbon source precursor, and a carrier gas. The silicon source precursor may be trichlorosilane (HChSi), the carbon source precursor may be ethylene (C2H4), the carrier gas may be hydrogen (H2), and the gas mixture may further include hydrogen chloride (HCI) as an etchant gas. Other gases, however, may be included in the gas mixture in place of or in addition to the gases described hereinbefore. In particular, another chlorine-containing silane such as dichlorosilane (H2SICI2) or methyltrichlorosilane (CHsSiCh) may be used as the silicon source precursor, propane (CsHs) may be used as the carbon source precursor, argon (Ar) may be used as the carrier gas, and chlorine (CI2), boron trichloride (BCI3), or chlorine trifluoride (CIF3) may be used as in addition to or as an alternative to hydrogen chloride (HCI). A chlorine-containing silicon source precursor such as trichlorosilane (HChSi) can promote the formation of a planar end surface 13 by contributing to a supersaturation of chlorine during the deposition process. The gas mixture including a further chlorinecontaining gas such as hydrogen chloride (HCI) can also help to provide a supersaturation of chlorine during the deposition process. A supersaturation of chlorine during the deposition process can limit overgrowth at mesa top surfaces 7 and thereby help to prevent void-formation resulting from premature closing of the cavities 9. Using trichlorosilane (HSiCh) or another chlorine-containing gas as the Si source precursor can reduce the amount of HCI (or other etchant gases) that would otherwise need to be included in the gas mixture to provide a supersaturation of chlorine during the deposition process. A supersaturation of chlorine during the deposition process can also help to enhance the process window. The gas mixture having a C / Si ratio equal to or greater than 0.4 and equal to or greater than 1.5, for example greater than 0.6 and equal to or less than 1.2, can help form a high-quality 4H-SiC layer on 4H-SiC. The CI / SI ratio of the gas mixture determines the relative rates of etching and deposition for a given set of conditions. Generally, too much Cl (or too little Si) can result in over-etching at mesa top surfaces 7 and too little Cl (or too much Si) can not sufficiently reduce overgrowth at mesa top surfaces 7 which results in voids. The gas mixture having a Cl / Si ratio equal to or greater than 2 and equal to or less than 60, for example equal to or greater than 3 and equal to or less than 30, can help form a high-quality 4H-SiC layer on 4H-SiC. The gas mixture having a Si / H ratio equal to or greater than 0.008% and equal to or less than 0.6%, for example equal to or greater than 0.01% and / or equal to or less than 0.2%, can help form a high-quality 4H-SiC layer on 4H-SiC. The epitaxial layer 12 is deposited on the annealed substrate 2" at a pressure equal to or greater than 10 mbar and equal to or less than 300 mbar. Heating of the patterned substrate 2' is carried out at around the same pressure. The epitaxial layer 12 may deposited at a pressure equal to or greater than 80 mbar and equal to or less than 120 mbar, for example 100 mbar. The substrate 2 may be a single-crystal 4H-SiC substrate or a so-called engineered substrate which includes a monocrystalline 4H-SiC layer disposed on a polycrystalline layer. The substrate 2 may include an epilayer deposited on the single-crystal 4H-SIC substrate or the monocrystalline 4H-SiC layer. The epilayer may be of the same conductivity type as the single-crystal 4H-SiC substrate (or the monocrystalline 4H-SiC layer) and have a different conductivity to the single-crystal 4H-SiC substrate (or the monocrystalline 4H-SiC layer). The gas mixture may include a p doped source precursor and / or an n doped source precursor to result in the deposited epitaxial layer 12 being doped. The p doped source precursor may be trimethylaluminium (Al2(CH3)6), diborane (B2H6), or another suitable p doped source precursor. The n doped source precursor may be nitrogen (N2), ammonia (NH3), phosphine (PH3), or another suitable n doped source precursor. Referring to Figure 3, a temperature profile of a 4H-SiC epitaxial growth process is shown. Referring also to Figure 4, the epitaxial growth process is shown. At a time to and at a load / unload temperature To, the patterned substrate 2' is loaded into a chemical vapour deposition reactor (not shown) (step S3.1). The load / unload temperature To, can take a value between room temperature and 1,200 °C. At a time ti, which is the same or later than to (step S3.2), hydrogen is introduced into the reactor, along with any other gas in which annealing is to be carried out in the presence of, and heaters (not shown) are switched on and controlled so that the temperature of the patterned substrate 2' reaches the first temperature Ti at a later time t2 (step S3.3). The first temperature is equal to or greater than 1,200 °C and equal to or less than 1,600 °C. The first temperature may be equal to or greater than 1,400 °C and equal to or less than 1,550 °C. During heating, a hydrogen flow rate is equal to or greater than 10 slm and equal to or less than 200 slm, for example equal to or greater than 80 slm and equal to or less than 120 slm, and in the case that heating is carried out in the presence of hydrogen chloride, a hydrogen chloride flow rate is equal to or greater than 0.1 seem and equal to or less than 1500 seem, for example equal to or greater than 100 seem and equal to or less than 900 seem. Between tz and a later time t3, the temperature of the patterned substrate 2' may be maintained at the first temperature Ti (step S3.4). The time interval between tz and t3 may be equal to or greater than 1 minute and equal to or less than 120 minutes, for example equal to or greater than 5 minutes and equal to or less than 60 minutes. Maintaining the temperature of the patterned substrate 2' between tz and the time ts can allow sufficient time for facet surfaces 11 to form while preventing overannealing. Overannealing can result in an extent of rounding which decreases the quality of stepflow epitaxy on the annealed substrate 2" by causing surface steps to be lost and other SiC polytypes to form in the cavities 9. Overannealing can also result in an extent of rounding which negatively affects the charge balance in subsequently formed superjunction structures. The time ts need not, however, be later than tz (that is, tz and ts may be the same time) if facet surfaces 11 are allowed other opportunity to sufficiently form. Deposition of the epitaxial layer 12 may be started at ts by introducing source precursors into the reactor, and starting deposition at t3 can help to prevent overannealing. Alternatively, between ts and a later time t4 the temperature of the patterned substrate 2' may be changed (by heating and / or cooling) from the first temperature to the second temperature over a time interval sufficient to allow facet surfaces 11 to form (step S3.5). The temperature of the patterned substrate 2' may be changed at a rate equal to or greater than 10 °C / min and equal to or less than 100 °C / min, for example equal to or greater than 25 °C / min and equal to or less than 75 °C / min. Deposition of the epitaxial layer 12 may be started at U by introducing source precursors into the reactor, and starting deposition at U can help to prevent overannealing. Alternatively, the temperature of the patterned substrate 2' may be maintained at the second temperature Tz until a later time ts at which deposition is started (step S3.6), allowing a temperature of the annealed substrate 2" to stabilise prior to deposition while not resulting in overannealing. At a time ts, which is the same as one of t3 or t4 or later than t4, the source precursors are introduced into the reactor to start deposition of the epitaxial layer 12 (step S3.7). In the case that the gas mixture comprises trichlorisilane (HSiCh), ethylene (C2H4), hydrogen (Hz), and hydrogen chloride (HO), during deposition a trichlorosilane flow rate may be equal to or greater than 20 seem and equal to or less than 470 seem, for example equal to or greater than 10 seem and equal to or less than 150 seem, an ethylene flow rate may be equal to or greater than 8 seem and equal to or less than 220 seem, for example equal to or greater than 10 seem and equal to or less than 100 seem, a hydrogen flow rate may be equal to or greater than 10 slm and equal to or less than 200 slm, for example equal to or greater than 80 slm and equal to or less than 120 slm, and a hydrogen chloride flow rate may be equal to or greater than 0.1 seem and equal to or less than 1500 seem, for example equal to or greater than 100 seem and equal to or less than 1000 seem. During deposition, the annealed substrate 2" is rotated in the gas mixture. The rotation rate is equal to or greater than 5 rpm and equal to or less than 120 rpm, for example equal to or greater than 20 rpm and equal to or less than 80 rpm. The time ts may be a time at which top corner facet surfaces and bottom corner facet surfaces having a length equal to or greater than at least one of 0.05 pm, 0.1 pm, 1 pm, 5 pm, and 10 pm have formed on the mesa regions 6. The time ts may be a time at which top corner facet surfaces and bottom corner facet surfaces having a length equal to or less than at least one of 1.5 pm and 0.8 pm have formed on the mesa regions 6. At a time te, which is later than ts, deposition is ended by removing the source precursors from the reactor, leaving only the carrier gas. Deposition may be carried out until at least a time at which the epitaxial layer 12 has a thickness equal to or greater than 2 pm and equal to or less than 30 pm, for example equal to or greater than 3 pm and equal to or less than 30 pm. Deposition may be carried out until at least a time at which the epitaxial layer has a thickness equal to or greater than double a width of a cavity 9 between two mesa regions 6. Between te and a later time t?, the temperature of the annealed substrate 2" may be maintained (step S3.8). At a time t?, which is the same as or later than te, the annealed substrate 2" is cooled (step S3.9), reaching the load / unload temperature To at a time ts. At a time to, which is the same as or later than (step S3.10) ts, the annealed substrate 2" is unloaded from the reactor (step S3.11). The annealed substrate 2" need not be unloaded from the reactor at the same temperature at which it is loaded into the reactor. Referring to Figure 5, forming a structure 4 in the substrate 2 is shown. An etch mask 14 is applied to the main surface 3 of the substrate 2 (steps S4.1 and S4.2). The etch mask 14 may be a patterned hard mask layer formed using photolithography and sputtering, and / or other suitable techniques. The etch mask 14 may be a shadow mask or a patterned resist layer. Exposed regions of the main surface 3 are etched, forming the cavities 9 (step S4.3) and thus providing the patterned substrate 2'. Etching can be carried out using reactive ion etching, ion beam milling, and / or other suitable techniques. Gases used during reactive ion etching may include hexafluorobutadiene (C4F6), sulphur hexafluoride (SFs), argon (Ar), oxygen (O2), and / or tetrafluoromethane (CF4). Ion beam milling may comprise broad argon beam ion milling or focused ion beam milling. The etch mask 14 is removed from the main surface 3 of the patterned substrate 2' (step S4.4). In this way, the substrate 2 can be lithographically-patterned prior to being annealed (that is, prior to step SI.3 being carried out). In cases in which etching is carried out using a local etching technique such as focused ion beam milling, the step of applying an etch mask 14 can be omitted. Typically, the mesa regions 6 and cavities 9 are arranged in a repeating structure having a pitch equal to or greater than 1.6 pm and equal to or less than 100 pm, for example equal to or greater than 2 pm and equal to or less than 50 pm. The mesa regions 6 may each have a respective width of around half the pitch. In the case that the patterned substrate 2' is {0001} oriented, each mesa region may have a sidewall surface 6 which extends along a direction within 1.5° of a <1120> direction of the patterned substrate 2' or within 1.5° of a <1100> direction of the patterned substrate 2'. Sidewall surfaces 6 extending along these directions can help the growth of the epitaxial layer 12 on the annealed substrate 2". The mesa regions 6 and structure 4 can have a wide range of geometries. The mesa regions 6 may be pillars such as hexagonal pillars and the mesa regions 6 may be arranged to define a grid according to any one of the five 2D Bravais lattices with a motif including one or more mesa regions 6. Alternatively, the mesa regions 6 may be elongate and formed such that the structure 4 comprises trenches 15. Referring to Figure 6, a patterned substrate 2' with trenches 15 is shown. Figure 6 shows the trenches 15 as being parallel, but this need not be the case, for example, the trenches 15 can extend along different directions, and even intersect. The trenches 15 have a depth equal to or greater than 0.1 pm and equal to or less than 30 pm, for example equal to or greater than 0.5 pm and equal to or less than 20 pm. Referring to Figure 7, a patterned substrate 2' comprising mesa regions 16 having sloped sidewalls surfaces 17 is shown. The mesa regions 16 are examples of the mesa regions 6 and the sloped sidewall surfaces 17 are examples of the sidewall surfaces 8. The sidewall surfaces 17 are inclined relative to a surface normal of a principal plane of the patterned substrate 2' by an angle 0s equal to or less than 30°, for example equal to or less than 20°. The sidewalls 17 being sloped can help to promote void-free growth of the epitaxial layer 12 in the cavities 9 of the annealed substrate 2". The patterned substrate 2' may be {0001} oriented and the sidewall surfaces 17 may be inclined at an angle equal to or less than 30°, for example equal to or less than 20°, relative to an <0001> direction of the patterned substrate 2'. The sidewall surfaces 17 being inclined at an angle relative to an <0001> direction of the annealed substrate 2" can help to promote void-free growth of the epitaxial layer 12 in the cavities 9 of the annealed substrate 2". Alternatively, the sidewall surfaces 8 may be perpendicular to a principal plane of the patterned substrate 2'. The substrate 2 may be on-axis or off-axis. A surface normal to the main surface 3 may deviate from a <0001> direction of the substrate 2 by a miscut angle equal to or less than 8°, for example equal to or less than 4°. The mlscut angle may deviate from a <0001 >direction of the substrate 2 towards a <1120 >direction of the substrate 2 or a <1100> direction of the substrate 2. The substrate 2 having a non-zero miscut angle can help the epitaxial layer 12 to grow in a step-flow growth mode on the annealed substrate 2", particularly when the miscut angle deviates from a <0001> direction of the substrate 2 towards a <1120 >direction of the substrate 2 or a <1100> direction of the substrate 2. Referring to Figure 8, an annealed substrate 2" comprising mesa regions 6 having sloped sidewalls 17, top corner facet surfaces 18:, and bottom corner facet surfaces 182 formed on the mesa regions 6 is shown. The top corner facet surfaces 18i and bottom corner facet surfaces I82 are examples of the facet surfaces 11. The annealed substrate 2" shown in Figure 8 is an example of the patterned substrate 2' shown in Figure 7 which has been annealed in the way described hereinbefore. Each top corner facet surface I81 and bottom corner facet surface I82 has a respective length Ltcf, Lbcf. Ltcf and Lbcf may each be equal to or greater than at least one of 0.05 pm, 0.1 pm, 1 pm, 5 pm, and 10 pm. Ltcf and Lbcf may each be equal to or less than at least one of 1.5 pm and 0.8 pm. Each facet surface 18i, I82 is inclined at a facet angle <Df relative to a <0001> direction of the annealed substrate 2". The facet angle is equal to or greater than 35° and equal to or less than 70°, for example equal to or greater than 40°and equal to or less than 65°. Figure 8 shows that, prior to deposition, the annealed substrate 2" can has a profile which includes flat mesa top surfaces 7, flat sidewall surfaces 8, flat cavity bottom surfaces 10, flat top corner facet surfaces I81 between mesa top surfaces 7 and sidewall surfaces 8, and flat bottom corner facet surfaces I82 between sidewall surfaces 8 and cavity bottom surfaces 10. The structure 4 shown in Figure 8 Includes trenches 15 having trench width L, separated by mesa regions 6 having mesa width S. The trenches 15 are parallel and have a pitch L+S. The mesa regions 6 each have a height D. The pitch is equal to or greater than 1.6 pm and equal to or less than 100 pm, for example equal to or greater than 2 pm and equal to or less than 50 pm. The mesa regions 6 may each have a respective width of around half the pitch. An aspect ratio of a mesa region is D / S and an aspect ratio of a trench 15 is D / L. Referring to Figure 9, a 4H-SiC / 4H-SIC structure 1 including an annealed substrate 2" and an epitaxial layer 12 deposited on the annealed substrate 2" is shown. The annealed substrate 2" may be of a first conductivity type, the epitaxial layer 12 may be of a second, different conductivity type, and the repeating structure of alternating p and n type layers (herein also respectively referred to as p-column structures and n-column structures) may form a superjunction structure 19. The parts of the annealed substrate 2" which are included in the superjunction structure 19 (that is, the mesa regions 6) may be wholly contained in a 4H-SiC epilayer 20 included in the annealed substrate 2. The epilayer 20 may have a different conductivity to a portion 21 of the annealed substrate 2" on which the epilayer 20 is disposed. Faceted interfaces, namely the top corner facet surfaces 18i and / or the bottom corner facet surfaces I82, may separate the p-column structures and n-column structures. Chemical-mechanical polishing (CMP) or dry etching may be used to remove the planar end surface 13 of the epitaxial layer 12 so as to expose an upper surface of the superjunction structure 19 prior to subsequent device fabrication steps being carried out. In the course of the etching, the top corner facet surfaces I81 may be removed and the mesa height D may be reduced. The planar end surface 13 of the epitaxial layer 12 may be bonded to a handle wafer (not shown) and the portion 21 and part of the epilayer 20 removed so as to expose a lower surface of the superjunction structure 19 prior to subsequent devices fabrication steps being carried out. In the course of removing the portion 21 and part of the epilayer 20, the bottom corner facet surfaces I82 may be removed and the mesa height D may be reduced. Referring to Figure 10, a power semiconductor device 22 having a drift region 23 including the superjunction structure 19 is shown. The power semiconductor device 22 may be a unipolar device such as a power metal-oxide-semiconductor field-effect transistor (MOSFET), a Schottky barrier diode (SBD), or another power semiconductor device having a drift region suitable for incorporating the superjunction structure 19. Specific studies are now presented. Effect of Mesa Profile on 4H-SIC CVD Trench Filling using HSICh and HCI Introduction In ideal trench filling epitaxy, deposition would occur selectively inside trenches with zero growth on mesa top surfaces to produce defect-free columns 25 at a fast filling rate. Using a conventional silane-alkane SiC CVD gas system, SiH4 + CzHa + Hz, narrow and deep stripe trenches tend to form voids, caused by premature trench closing. This occurs when the epitaxial layer grows faster at the mesa top surface than inside the trench, causing the epitaxial layer to fuse before the trench is filled. Mesa overgrowth can be mitigated by tuning the chamber conditions, such as temperature, pressure, flow rates and gas chemistry to improve both anisotropy and fill rate. In particular, the utilisation of "chlorine chemistry", typically in the form of HCI, is advantageous to trench filling epitaxy in two ways. Firstly, HCI can selectively etch SiC growing at mesa top surfaces to limit overgrowth and, secondly, it can react with SiH4 in the gas phase to produce more active chlorosilanes that enhance the filling rate. The ratio of Cl / Si can be an important parameter to tune, since it determines the relative rates of etching and deposition for a given set of conditions. Generally, too much Cl (or too little Si) can result in over-etching at mesa top surfaces which reduces the trench depth, and too little Cl (or too much Si) does not sufficiently reduce overgrowth which results in voids. Using trichlorosilane (HSiCIs) as a Si source precursor can supply both deposition and suppressant reactants, reducing the need for large amounts of HCI. Tuning the source gas and etchant flow rates can improve both selectivity and trench filling rate for a given condition set and mesa profile (that is, sidewall angle 0s, aspect ratio, and shape features such facet surfaces). In particular, high pressure can improve selectivity by increasing the pressure gradient between the mesa top surfaces and cavity bottom surfaces, promoting diffusion of mainly the more diffusive precursor gases, and not etchant species. However, this can lower the overall growth and etching rates due to more difficult penetration of reactants through a thicker boundary layer. This can be offset by increasing the flow rates of source gases and decreasing the H2 flow rate, since the carrier gas acts as a dilutant and may passivate the growing surface. HCI may strip H adatoms from the growing surface, increasing the surface potential and affecting the diffusion of reactants and products by the Gibbs-Thomson effect. Since high temperature chemical vapour deposition (CVD) is masstransport limited and gases follow a continuum diffusion model, reaction rates and growth selectivity are governed by flux and surface diffusivity, while reaction thermodynamics can be considered negligibly fast. Here, 4H-SiC trenches filled by CVD using HSiCh + C2H4 + HCI + H2 to benefit from both a high trench filling rate by a chlorosilane precursor and to maintain tunability of the precursor-etchant ratio with additional HCI are described. Here, how the mesa sidewall angle 0s, and other profile features such as microtrenches and faceted surfaces 11, can influence process optimisation is described. Experimental details 4H-SiC stripe trenches 15 were etched along the

[1120] direction by reactive ion etching of commercial n-i- substrates (4° off-axis, Si-face) to produce 3 different sidewall profiles (2° slope + microtrenches, 5° slope without microtrenches and 8° slope without microtrenches), all at around 5 pm trench depth. The stripe patterns on the lithography mask were of equal line (L) and spacing (S) at 2 pm (4 pm pitch), 4 pm (8 pm pitch) and 10 pm (20 pm pitch). The temperature was ramped to the growth temperature T2 over 10 min with the sample under H2 flow, causing corner facets I81, I82. Trench filling was performed by hot-wall reduced pressure chemical vapour deposition (RP-CVD) with a 60rpm rotating susceptor at 1550 °C and 100 mbar chamber pressure. A fixed ratio of source gases HSiCH (70 seem) + C2H4 (26 seem) and H2 flow (100 slm) were used to grow a 6 pm epitaxial layer 12 (31 min), with HCI flow rates varied from (0 seem to 1000 seem). The Si / C ratio was held constant at around 0.75 to offset Si-selective etching. Every 4 minutes 45 seconds, n+ (around lx 1019 cm'3) marker layers were added via 30 second additions of N2. Cross-sectional SEM images were recorded on the

[1100] cleave plane, orthogonal to the trench direction. Referring to Figure 11, a set of cross-sectional SEM micrographs showing (top) 4 pm pitch, 2 pm sloped trenches 15 refilled with 1000 seem of HCI and (bottom) 8 pm pitch, 8 pm sloped trenches 15 refilled with 500 seem of HCI is shown. Referring also to Figure 12, growing epitaxial 4H-SiC 12 on the annealed 4H-SIC substrate 2" shown in Figure 8 is shown. Figure 11 shows data from experiments performed to assess how the trench pitch, and mesa sidewall angle influence filling behaviour under varied HCI flow rates (none, 250, 500, 750 and 1000 seem, corresponding to respective Cl / Si ratios of 3, 7, 10, 14 and 17 or HCI / HSiCh ratios of 0, 4, 7, 11 and 14). Flow rates will be referred to hereinafter, since the Cl is derived from non-equivalent states. Cl / Si ratios are calculated using Equation 1: Cl _ 3 x FHSlcl3 + FHa Ci FHSicl (Equation 1) Fhsici3 is the flow rate of HSiCH and Fhci is the flow rate of HCI. Figure 11 shows the extent of feature variation in the epitaxial layer 12 caused by differences in the profile of the mesa regions 6 and the HCI flow rate. Figure 12 defines measures and terminology used herein. Trench pitch is defined as L+S, where L is the line width and S is the space width of the stripe patterns used on the photolithography mask. For simplicity, all trenches 15 were etched to the same depth, D, of around 5 pm. The mesa sidewall angle, 0s is measured at 1 / 2D from the normal of the annealed substrate 2" to the mesa top surface 7, and all top corner facet surfaces I81 were angled at 50±5° and were 0.5±0.3 pm in length. Labels T, F, S and B refer to the region of the epitaxial layer 12 growing normal to the mesa top surface 7, mesa top corner facet surface I81, sidewall surface 8 and trench bottom surface 10, respectively. Growth rates of these regions are calculated using the n+ doping markers, appearing as dark lines in SEM images. Angles q>ri and q>F2 denote the boundary angles of the F-T and F-S regions, tpri is also referred to as the facet-top angle and the q>F2as the facet-sidewall angle. Where not stated, the standard error for all following measurements are: pitch (±0.3 pm), depth (±0.2 pm), angles (±1°), growth rates (±1.3 pm / hr). Effect of Mesa Sidewall Angle on Trench Filling Referring to Figure 13, plots of void area and percentage trench fill against mesa sidewall angle 9s for different pitch sizes, at a constant HCI flow rate, are shown. To assess how 9s affects trench-filling behaviour, trenches 15 with vertical (2°), intermediate (5°) and sloped (8°) sidewalls 17 were filled under a constant HCI flow of 500 seem. At around 8 pm pitch, the percentage trench fill increases with 9s from 90% with vertical sidewalls to 100% with sloped sidewalls. While 100% fill is measured, some filled trenches contained small "pinhole" voids where adjacent surfaces fused due to shortcomings of the lithography used in this study; higher throughput optimised lithographic processes would allow for higher consistency. Referring to Figure 14A, a set of cross-sectional SEM micrographs showing filled trenches 15 of 4 pm, 8 pm, and 20 pm pitch size at sidewall angles of 2°, 5°, and 8° is shown. Referring also to Figure 14B, plots of initial epitaxial layer 2 growth rate on mesa top surfaces 7, mesa sidewalls 8, and trench bottom surfaces 10 against sidewall angle for trenches of 4 pm and 8 pm pitch are shown. Figure 14B includes illustrations of exaggerated relative growth rates highlighted on each plot by dashed borders for the correspondingly labelled SEM micrographs shown in Figure 14A. An increase in trench filling was also seen at around 4 pm pitch for more sloped sidewalls 17, but the percentage fill was consistently lower than for the wider trenches 15, increasing from 69% to 87% when changing from vertical and sloped mesa regions 6. At narrow pitch, the fill percentage was found to directly correlate with an increase in void area (Av), where voids are contained entirely inside the trench area and decrease from 1.6 pm2 at 9s=2° to 9.5 pm2 at 9s=8°. While a similar decrease in void area was found at 8 pm pitch (1.4 to 9.9 pm2 at 9s=2 to 8°, respectively) it is not an exact correlation to fill percentage as the voids shifted up in position so that they were not fully contained inside the trench area but extended into the excess epilayer. This was caused by the relatively thick trench bottom layers seen at all angles for the wider pitch trenches compared with the narrower ones, as all voids were of a similar length and rather tend to vary in width. Plots in Figure 14B show how the initial growth rates on the trench bottom surface (Rb), sidewall surface (Rs) and mesa top surface (Rt) vary with sidewall angle at a constant HCI flow. At 4 pm pitch, Rs is the slowest at all angles, although increases from 2.5 to 5.0 pm / hr from vertical to intermediate sidewall angle and shows no further change when the sidewalls are sloped. Similarly, Rt increases from 6.0 to 7.0 pm / hr, plateauing at 0s=5°. The trend is slightly different for Rb, which peaks at 9.0 pm / hr for the intermediate sidewall angle and is faster than both Rt and Rs. The intermediate sidewall angle was found to be the most favourable growth regime, whereby Rb>Rt, the sloped sidewalls 17 show a slightly improved fill percentage despite slower Rb. At 8 pm pitch, increasing 0s was found to linearly increase the initial growth rate on all facet surfaces 11, with Rb showing the highest sensitivity to angle change. In this case, Rb>Rt at 0s=8° and the trenches 15 filled to 100%. For both pitches, Rt is very similar and Rb shows the greatest sensitivity to sidewall angle, but Rs is consistently around 2 pm / hr faster at wider pitch. This difference in sidewall growth rate may account for voids forming at 4 pm pitch (0s=5°) but not at 8 pm pitch (0s=8°), despite Rb>Rt in both cases, as shown in Figure 14B, as growth regimes A and B. In regime A, slow sidewall growth means that a void forms since the trench bottom growth is not sufficiently fast to reach the trench top before the mesa top layer fuses. In regime B, fast sidewall growth means the epitaxial layer 12 inside the trench 15 can "zip-up", completely filling the trench 15 before it is sealed. Effect of HCI on Trench Filling For each mesa profile, the filling behaviour with different HCI flow rates was examined. For all sidewall angles at 4 pm pitch, increasing the HCI flow rate in increments from 0 to 1000 seem causes a decrease in fill percentage. At 0s=2 and 5°, a gradual drop in fill percentage by around 20% was seen between 0 and 1000 seem, starting at 78% for vertical sidewalls 8 and 93% for intermediate sidewalls 8, 17. Sloped sidewalls 8, 17 at 0s=8° were found to show better filling and lower sensitivity to HCI flow at <500 seem, changing only from 93% to 90% at 0 seem and 500 seem, respectively. However, the fill percentage drops to 60% at 1000 seem. Referring to Figure 15A, a set of cross-sectional SEM micrographs showing filled trenches 15 of 4 pm at a sidewall angle of 2° under different flow rates of HCI Is shown, with overlaid lines following void top and bottom position across the set of micrographs. Figure 15A shows the fill percentage plotted against HCI flow rate for trenches 15 of 8 pm pitch, indicating a similar trend to the narrower pitch at vertical and intermediate sidewall angles but at a much lower HCI sensitivity. Here, only a 3% drop was observed from 0 to 750 seem for both 0s=2 and 5°, starting at respective fill percentages of 97% and 93%. While overall demonstrating higher filling, sloped sidewalls 17 indicate a more complex relationship with HCI flow rate, showing a local minimum of 96% at 250 seem followed by a maximum of 100% at 500 seem. Flow rates of 250-750 seem for 8 pm pitch trenches with sloped sidewalls showed a propensity for multiple, small circular voids in the trench centres, rather than uniform singular voids as seen for the other profiles. Referring also to Figure 15B, a set of cross-sectional SEM micrographs of filled trenches 15 of 8 pm at a sidewall angle of 2° under different flow rates of HCI is shown, with overlaid lines following void top and bottom position across the set of micrographs. Figure 15B shows the thickness of each epitaxial layer 12 region measured at a normal angle to the growth direction for different HCI flow rates at 8 pm pitch. For all sidewall angles, the mesa top (T) is the thickest region, while the trench bottom (B) Is the thinnest by an average difference of around 3 pm. The trench bottom thickness is measured either up to the void bottom or where the sidewall layers fuse, depending on which comes first. Both the thickness and normal angle of the top corner facet (F) change significantly with HCI, with the thickness increasing from 3.5 pm to 5.9 pm at 0 and 1000 seem, respectively for both vertical and intermediate sidewall angles. This becomes significantly thinner for trenches 15 with sloped sidewalls 17, measuring at 2.1 and 3.8 pm under the same change in conditions. This diminished facet growth with HCI was found to be a factor aiding the fast sidewall growth observed for sloped trenches, resulting in near-voidless filling. Referring to Figure 16A, a plot of percentage trench fill against HCI flow rate for 8 pm pitch trenches 15 at sidewall angles of 2°, 5°, and 8° is shown. Referring also to Figure 16B, a plot of epitaxial layer 12 thickness on mesa top surfaces 7, top corner facet surfaces 18, and trench bottom surfaces 10, against HCI flow rate at sidewall angles of 2°, 5°, and 8° for 8 pm trenches is shown. Referring also to Figure 16C, an illustration of how facet-mesa top boundary angle Ofi determines end surface topography at 6 pm growth thickness is shown. Referring also to Figure 16D, a plot of top corner facet layer thickness against the facet boundary angles, Ofi and Ofz, at different HCI flow rates is shown. Referring also to Figure 16E, a set of cross-sectional SEM micrographs showing 8 pm pitch trenches 15 at a sidewall angle of 2° at different HCI flow rates is shown, with highlighted facet layers reflecting those shown in Figure 16C. Examination of void geometry Indicates that HCI causes a non-uniform growth rate on the sidewalls, which is dependent on depth. Figure 16E shows how the void shape and position change with HCI flow rate. Here, trenches 15 with vertical sidewalls are shown for clarity, since they have the largest void area. At 4 pm pitch, oval voids are formed that widen with increasing HCI flow, suggesting that HCI slows the sidewall growth rate. While void widening is also observed at 8 pm pitch, the degree to which the sidewall growth rate is changed by HCI depends on its depth, leading to anisotropic sidewall growth that forms droplet-shaped voids. This Indicates that HCI, while slowing sidewall growth at the bottom, is increasing sidewall growth at the top. At 1000 seem, the void position moves up for both pitches because the trench remains open for a longer time, as indicated by the third doping marker. This may be caused by the change in the normal angle for the top corner facet growth resulting in the growing facet regions require a longer time to fuse. To encompass both the top corner facet growth direction and its width, the boundary angles where it meets the mesa top region (cppi) and the sidewall region (<p=z) are plotted in Figure 16D. Increasing the HCI flow rate widens this facet region by changing the inclination of q>Fi from the trench centre (positive angle) to the mesa centre (negative angle). In addition to prolonging the trench-closing time, this causes a distinct change in the top surface topography, illustrated in Figure 16C. When the facet region is narrow, such that <ppi>0, adjacent facets fuse early above the trench centre, allowing subsequent growth on top to level into a flat end surface 13. Conversely, when <pfi<0, the facet regions are very wide and can fuse over the mesa centre, resulting in a corrugated end surface at the thickness grown. At q>Fi<0, an intermediate top surface topography is observed, where the facet region terminates before fusing, leading to a flat end surface above mesas but 'scored' above trenches. In the latter two cases, it is possible that a flat surface 13 could be formed for a thicker epilayer. For superjunction fabrication, such a flat end surface 13 is desirable as it permits etching back the excess layer by dry etching, without requiring chemical mechanical polishing to remove uneven overgrowth. Conclusions Here, 8 pm pitch / 5 pm / 8° sidewall trenches filled at 19±0.4 pm / hr using TCS + ethylene + HO + H2 and having flat end surfaces were produced. It was found that: larger sidewall angle can improve trench filling (in particular, by improving trench bottom growth); wider pitch can improve filling (in particular, by improving sidewall growth); HO can improve filling at an optimal flow rate, that optimum depending on the profile of the mesa regions 6 (in particular, by delaying trench sealing), and that HCI can also affect sidewall anisotropy and end surface topography. Analysis of Epitaxial 4H-SIC Trench Refill by Chlorinated Chemistry Introduction Some trench filling epitaxy methodologies can have one or more drawbacks, such as rounding caused by hydrogen etching at relatively high temperatures, and poor crystal quality of the 4H-SiC resulting from growth on different crystal planes. Experimental details 4H-SiC substrates 2 of 100mm diameter were first coated in 500 nm SiO; within a TEOS CVD to protect the 4H-SIC substrates 2 from any contamination introduced during a trench fabrication process. A hard mask 14 was then patterned using photolithography, Ni sputtering and lift-off techniques to define trenches 15 of widths 2 pm and 4 pm. Trenches 15 were etched to a depth of 5 pm using SFe and O2 in a reactive ion etch (RIE) process with an induced coupled plasma (ICP) at a rate of 20 pm / hr. The trenches were aligned to the

[1120] direction on the Si-faces of the patterned 4H-SiC substrates 2'. The patterned substrates 2' were then cleaned ready for trench refill. The Ni mask was removed by aqua regia, the SiCh removed by an HF etch and the substrates were finally cleaned within an RCA process. Epitaxial growth on the patterned substrates 2' was carried out within an LPE ACiS M8 RP-CVD reactor. The Si and C precursors were trichlorosilane (TCS) and ethylene (C2H4) respectively and a H2 carrier gas was used for growth at a reduced pressure of 100 mbar. The growth temperature of 4H-SiC was reduced to 1550 °C to reduce the H? etching effect on the trenches 15 prior to epitaxy. Due to necessary stabilization times within the growth system, the trenches 15 were annealed in H2 for 10 mins before growth initiated. Additional HCI was introduced Into the process to influence the growth of the 4H-SIC within the trenches 15 at flow rates of 0, 500 and 1000 seem. A total epitaxial layer thickness of 5 pm of 4H-SiC was grown on the annealed substrates 2" and 100 nm thick N2 doped "markers" were deposited at around each 1 micron of growth, this enabled the evolution of the 4H-SIC epilayer to be observed within a scanning electron microscope (SEM). The growth rate of 4H-SiC was kept constant at 8.5 pm / hr and was found to be almost independent of the HCI flow rate. The refilling of the 4H-SiC trenches 15 was analyzed using SEM operating in an in-lens configuration. The crystal structure of the 4H-SiC epitaxial layer 12 was imaged using cross-sectional transmission electron microscope (X-TEM) with an electron transparent cross section being extracted by focused ion beam (FIB-SEM). The surface morphology of the refilled trenches was measured by atomic force microscope (AFM). Results and Discussion Referring to Figures 17A to 17F, AFM micrographs of the surface morphology of 2 pm trench refills without HCI, at 500 seem HCI flow rate, and at 1000 seem HCI flow rate are shown. The AFM micrographs have scan ranges of 10x10 pm and 30x30 pm. The RMS surface roughness of the 0 seem HCI sample can be seen to be around 40 nm, however, the trench pattern is still clearly defined on the surface. The addition of 500 seem HCI can be seen to improve the refilling process and to reduce the surface roughness to less than 7 nm. The roughness of the 1000 seem HCI sample was high, due to the trenches 15 being unable to refill within the 5 pm of epitaxial growth. Referring to Figure 18A, a set of SEM micrographs showing the influence of trench angle from the <1120> direction on the growth direction is shown. Referring also to Figure 18B, a plot of growth angle calculated from SEM imaging away from the

[0001] direction against trench angle from the <1120> direction is shown. To assess the impact of trench orientation, trenches 15 were fabricated at angles of -5° to +5° with respect to the <1120 >crystal direction. Trench refill was observed in all cases, however, the doping markers indicated that the angle by which the growth propagated varied with the trench angle. This angle was found to stay close to 0° over a range of -1.5° to +1.5°, offering a wide process window and tolerance on the fabrication of such trench structures 15, well within the tolerance of lithography tools. Beyond ±1.5° the growth angle was found to vary linearly with trench angle. Conclusions Trenches of depth 5pm and width 2 / 4pm were refilled using chlorinated chemistry at 1550°C. Reducing the growth temperature to this level can help to suppress an undesirable rounding of the trench structures. The addition of HCI was found to affect the growth rates of the 4H-SiC epitaxial layer 12 on the trench base surfaces 10, sidewall surfaces 8 and facet surfaces 11 as well as the mesa top surfaces 7, but also to improve the fusing of adjacent growth fronts resulting in a smoother surface morphology. The trenches 15 were primarily aligned to the

[1120] direction. It was found that applying an offset angle to this can have a profound effect on the growth process. An angle to the epilayer growth relative to the

[0001] direction was observed for offset angles greater than ±1.5°, offering a wide process window well within the tolerance of lithography tools to maintain optimal epitaxial growth. Reshaping Mesas by Gas Annealing The 'shape' of a trench and its corresponding mesa regions can be important for both device performance and the fabrication process. Since a superjunction relies on charge-balance to mitigate electric fields at reverse bias, sharp corners where there may be a disparity in charge can lead to premature breakdown. This corner shape can also influence the trench-filling process by determining the growth direction of the epitaxial layer. Here, 4H-SiC trenches were annealed in hydrogen and hydrogen chloride to determine structure-process relationships. Referring to Figure 19, a set of cross-sectional SEM micrographs of trenches 15 annealed at 1550 °C in hydrogen for 1 min, 10 min and 2 hr Is shown, and a clear evolution in profile can be tracked. Tunable corner faceting by hydrogen annealing was achieved and the length of facets was found to be dependent on the annealing duration. Thus, greater control over trench-filling CVD, and more precise control of microstructuring processes in 4H-SIC in general, can be provided. Further, the formation of facet surfaces was found to substantially remove microtrenches, which can otherwise cause problems for both processing and device operation. Filling Trenches by Chemical Vapour Deposition Unlike epitaxial growth on planar substrates, trench filling by CVD can produce epitaxial layers 12 containing voids, which may cause superjunction charge imbalance if not properly compensated by the doping distribution. To prevent void formation inside filled trenches 15, a chlorinated etchant can be added to the gas stream to selectively etch the growing epitaxial layer 12 at mesa top surfaces 7, allowing trenches 15 to fill before being sealed. In a typical SiC CVD system, the gas stream is composed of silane (Si source), propane (C source), hydrogen chloride (etchant) and hydrogen as a carrier gas. The addition of a chloride compound can increase deposition anisotropy as well increase the trench-filling rate. Here, a gas system comprised of trichlorosilane (Si source and etchant source), ethene (C source), hydrogen chloride (etchant) and hydrogen (carrier), was used to study the benefits of fast trench filling while tuning the etchant flow rate. Referring to Figure 20, a set of cross-sectional SEM micrographs for two different trench / mesa structures with different widths and sidewall angles is shown. The two trench / mesa structures were filled under different flow rates of hydrogen chloride. Changes in either trench / mesa structure or silicon-chloride stoichiometry were found to alter the refill behavior, producing voids of different size, shape and position and changing the topography of the epilayer surface. The optimal hydrogen chloride flow rate for trench refilling epitaxy was found to be dependent on the trench / mesa width and sidewall angle. Modifications It will be appreciated that various modifications may be made to the embodiments hereinbefore described. Such modifications may involve equivalent and other features which are already known in the growth of silicon carbide, and which may be used instead of or in addition to features already described herein. Features of one embodiment may be replaced or supplemented by features of another embodiment. The structure 4 need not be formed by a subtractive technique such as etching. Instead, the structure 4 may be additively formed, for example, by selective epitaxial growth. In selective epitaxial growth, growth only occurs on exposed areas of a surface and regions on which growth is not desired are masked with a hard template. Although claims have been formulated in this application to particular combinations of features, it should be understood that the scope of the disclosure of the present invention also includes any novel features or any novel combination of features disclosed herein either explicitly or implicitly or any generalization thereof, whether or not it relates to the same invention as presently claimed In any claim and whether or not it mitigates any or all of the same technical problems as does the present invention. The applicants hereby give notice that new claims may be formulated to 5 such features and / or combinations of such features during the prosecution of the present application or of any further application derived therefrom.

Claims

1. A method comprising:heating a 4H-SiC substrate in the presence of hydrogen to a first temperature equal to or greater than 1,200 °C and equal to or less than 1,600 °C so as to anneal the substrate; anddepositing an epitaxial layer of 4H-SiC on the substrate at a second temperature equal to or greater than 1,400 °C and equal to or less than 1,600 °C.

2. The method of claim 1, further comprising:forming a structure in the substrate such that the structure extends from a main surface of the substrate into a first semiconductor layer of the substrate and such that the structure subdivides the first semiconductor layer into a plurality of mesa regions, the structure comprising at least one cavity,wherein depositing the epitaxial layer on the substrate comprises depositing the epitaxial layer in the at least one cavity.

3. The method of claim 1 or 2, wherein heating the substrate is carried out in the presence of a chlorine-containing gas.

4. The method of claim 3, wherein the chlorine-containing gas is hydrogen chloride.

5. The method of any one of claims 1 to 4, wherein heating the substrate comprises maintaining a temperature of the substrate at the first temperature for a time interval equal to or greater than 1 minute and equal to or less than 120 minutes prior to depositing the epitaxial layer of 4H-SiC on the substrate.

6. The method of claim 5, wherein depositing the epitaxial layer of 4H-SiC is carried out at the end of the time interval.

7. The method of any one of claims 1 to 6, wherein depositing the epitaxial layer of 4H-SiC is carried out by chemical vapour deposition in a gas mixture comprising a silicon source precursor, a carbon source precursor, and a carrier gas.

8. The method of claim 7, wherein the silicon source precursor is a chlorinecontaining silane.

9. The method of claim 8, wherein the chlorine-containing silane is trichlorosilane.

10. The method of any one of claims 7 to 9, wherein the carrier gas is hydrogen.

11. The method of any one of claims 7 to 10, wherein the gas mixture furthercomprises a chlorine-containing gas which is not the silicon source precursor or the carbon source precursor.

12. The method of claim 11, wherein the chlorine-containing gas which is not the silicon source precursor or the carbon source precursor is hydrogen chloride.

13. The method of any one of claims 7 to 12, wherein the gas mixture has a C / Siratio equal to or greater than 0.4 and equal to or less than 1.5.

14. The method of any one of claims 7 to 13, wherein the gas mixture has a Cl / Siratio equal to or greater than 2 and equal to or less than 60.

15. The method of any one of claims 7 to 14, wherein the gas mixture furthercomprises a p doped source precursor and / or an n doped source precursor.

16. The method of any one of claims claim 2 to 15, wherein forming the structure comprises:forming a plurality of trenches that each extend from the main surface of the substrate into the first semiconductor layer, andforming a cavity in each of the trenches.

17. The method of claim any one of claims 2 to 16, wherein the substrate is {0001} oriented and each mesa region has a sidewall surface which extends along a direction within 1.5° of a <1120> direction of the substrate or within 1.5° of a <1100> direction of the substrate.

18. The method of claim 17, wherein each sidewall surface is inclined at an angle equal to or less than 30° relative to an <0001> direction of the substrate.

19. The method of any one of claims 1 to 18, wherein depositing the epitaxial layer of 4H-S1C is carried out until at least a time at which a deposited epitaxial layer of 4H-SiC having a planar end surface is provided, the planar end surface having an RMS surface roughness equal to or less than 10 nm.

20. The method of any one of claims 2 to 19, wherein heating the substrate is carried out until at least a time at which top corner facet surfaces and / or bottom corner facet surfaces form on each of the mesa regions, the top corner facet surfaces and / or bottom corner facet surfaces having a length equal to or greater than 0.05 pm.

21. The method of any one of claims 1 to 20, wherein the substrate has a first conductivity type and the epitaxial layer has a second conductivity type opposite to the first conductivity type.

22. A homostructure obtained by the method of any one of claims 1 to 21.

23. A superjunction structure obtained by the method of any one of claims 1 to 21.

24. A superjunction structure having a faceted interface between a p-column structure and an n-column structure.

25. A power semiconductor device comprising a drift region, the drift region comprising the superjunction structure of claim 23 or 24.41

Images