Vertical resonator surface emitting laser element

Abstract

To provide a vertical resonator surface emitting laser element that can reduce the variation in threshold current.SOLUTION: A vertical resonator surface emitting laser element includes a substrate containing GaN, an AlGaN underlayer provided on the upper surface of the substrate, a multilayer reflective layer including an AlInN layer and provided on the upper surface of the underlayer, an n-side semiconductor layer, an active layer, and a p-side semiconductor layer. The n-side semiconductor layer, active layer, and p-side semiconductor layer are provided above the multilayer reflective layer.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a vertical cavity surface emitting laser device. [Background technology]

[0002] 2. Description of the Related Art As a vertical cavity surface emitting laser element, which is an example of a semiconductor element, one that includes, for example, a GaN-based semiconductor layer and a multilayer reflective layer has been proposed (for example, Patent Document 1). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2003-101141 A Summary of the Invention [Problem to be solved by the invention]

[0004] When a GaN layer is provided between the substrate and the multilayer reflective layer, the surface morphology may become rough, which may result in a decrease in the flatness of the multilayer reflective layer. [Means for solving the problem]

[0005] The present invention according to one aspect of the present application comprises: a substrate including GaN; an AlGaN underlayer provided on an upper surface of the substrate; a multilayer reflective layer including an AlInN layer provided on an upper surface of the underlayer; The vertical cavity surface emitting laser element includes an n-side semiconductor layer, an active layer, and a p-side semiconductor layer provided above the multilayer reflective layer. Effect of the Invention

[0006] According to the above-described invention of the present application, it is possible to provide a vertical cavity surface emitting laser element capable of reducing the variation in threshold current. [Brief description of the drawings]

[0007] [Figure 1] 1 is a schematic cross-sectional view showing a vertical cavity surface emitting laser element according to an embodiment. [Diagram 2] 1 is a schematic cross-sectional view showing a structure of a vertical cavity surface emitting laser element in an embodiment. [Diagram 3] FIG. 11 is a schematic cross-sectional view showing the structure of a vertical cavity surface emitting laser element in a comparative example. [Figure 4] FIG. 13 is a diagram showing cumulative distribution of threshold currents in a plurality of vertical cavity surface emitting laser elements in an example and a comparative example. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0008] The embodiments described below are intended to embody the technical ideas of the present disclosure, and unless otherwise specified, the present disclosure is not limited to the following. The contents described in one embodiment or example are applicable to other embodiments and examples. The size, thickness, positional relationship, etc. of the members shown in each drawing may be exaggerated to clarify the explanation. The same names and symbols generally indicate the same or similar members, and duplicate explanations are omitted as appropriate. In the surface-emitting laser element, the light extraction surface side of the surface-emitting laser element may be referred to as the first surface or bottom surface, and the side opposite the light extraction surface may be referred to as the second surface or top surface.

[0009] Embodiment 1: Vertical-cavity surface-emitting laser element As shown in FIG. 1 , the vertical cavity surface emitting laser device 10 according to the first embodiment of the present disclosure includes a substrate 1 containing GaN, an AlGaN underlayer 12 (hereinafter referred to as underlayer 12) provided on an upper surface of the substrate 1, a multilayer reflective layer 11 including an AlInN layer provided on the upper surface of the underlayer 12, and a semiconductor laminate 5 including an n-side semiconductor layer 2, an active layer 3, and a p-side semiconductor layer 4 provided above the multilayer reflective layer 11. The underlayer 12 functions as the first layer when a crystal grows on the substrate 1 . Unlike the first embodiment of the present disclosure, when the underlayer 12 of the GaN layer is formed on the substrate 1, the reflectance may be insufficient. It is expected that the cause of this is that the surface morphology of the underlayer 12 is insufficient, and when the underlayer 12 is formed of an AlGaN layer as in the first embodiment of the present disclosure, the surface morphology of the underlayer 12 is improved. This is thought to be because the diffusion length of Al adatoms during crystal growth is larger than that of Ga. The adatom refers to the atom located on the most surface side of the layer. By improving the surface morphology of the underlayer 12, the flatness of the multilayer reflective layer 11 provided thereon is improved, and the substantial reflectance of the multilayer reflective layer 11 is improved. As a result, the variation in the threshold current in the vertical cavity surface emitting laser element 10 can be reduced. In addition, the average value of the threshold current in the multiple vertical cavity surface emitting laser elements 10 can be reduced. The threshold current means the minimum current required for laser oscillation of the vertical cavity surface emitting laser element 10. The vertical cavity surface emitting laser element 10 preferably includes an electrode layer 6 on the p-side semiconductor layer 4, and a reflecting layer 8 on the electrode layer 6. With this configuration, the reflecting layer 8 can improve the light reflection characteristics. The vertical cavity surface emitting laser element 10 preferably includes an electrode layer 9n on the n-side semiconductor layer 2. With this structure, it is not necessary for the current to pass through the multilayer film reflecting layer 11 as a current path, so there is no need to dope the multilayer film reflecting layer 11 with n-type impurities, and the reflectance of the multilayer film reflecting layer 11 can be further improved. The vertical cavity surface emitting laser element 10 according to the first embodiment of the present disclosure emits laser light from the substrate 1 side.

[0010] (Substrate 1) The substrate 1 functions as a base for growing a semiconductor laminate 5 including an n-side semiconductor layer 2, an active layer 3, and a p-side semiconductor layer 4. The substrate 1 can be appropriately selected depending on the material of the semiconductor laminate 5, but preferably contains GaN, and in particular, it is preferable to use a substrate of a single layer of GaN as the substrate 1. By using a substrate of a single layer of GaN as the substrate 1, the crystallinity of the underlayer 12 provided on the upper surface of the substrate 1 can be made good. The substrate 1 may have an off-angle with respect to its main surface. If a substrate having a predetermined off-angle and an appropriate atomic step spacing is used as the substrate 1, the underlayer 12 can be grown with good crystallinity. The direction perpendicular to the main surface of the substrate 1 is, for example, <0001> The direction perpendicular to the main surface of the substrate 1 is <0001> It may be parallel to the direction, <0001> The off-angle may have a predetermined off-angle inclination with respect to the direction. The off-angle directional component along the <11-20> axis is, for example, 0.4° or more and 10° or less. The off-angle directional component along the <1-100> axis is, for example, 0° or more and 0.4° or less. The composite off-angle obtained by combining the off-angle directional component along the <11-20> axis and the off-angle directional component along the <1-100> axis is, for example, 0.4° or more and 10° or less, and preferably 0.4° or more and 0.6° or less. By setting the composite off-angle to 0.6° or less, the occurrence of step bunching can be suppressed, and the deterioration of the surface morphology of the underlayer 12 can be suppressed. By setting the composite off-angle to 0.4° or more, the occurrence of hillocks originating from screw dislocations can be suppressed, and the deterioration of the surface morphology can be suppressed. The upper and lower surfaces of the substrate 1 are preferably parallel to each other, and the upper and lower surfaces are preferably flat. With such a configuration, the quality of the laser light emitted from the vertical cavity surface emitting laser device 10 can be improved. The surface of the substrate 1 may have some irregularities, and the irregularities may have a surface roughness Ra of, for example, 0 nm or more and 1 nm or less. Alternatively, the irregularities may have an arithmetic mean roughness Sa of, for example, 0 nm or more and 1 nm or less. The substrate 1 may have a thickness of, for example, 100 μm or more and 1000 μm or less.

[0011] (base layer 12) The underlayer 12 is provided on the upper surface of the underlayer 12. That is, the underlayer 12 is provided in contact with the upper surface of the underlayer 12. The underlayer 12 is a layer provided as the first layer when crystals are grown on the upper surface of the substrate 1, and is a layer that can improve the crystallinity of the layer formed thereon. For example, if the substrate 1 is scratched, without the underlayer 12, the layer formed thereon would reflect the scratch on the substrate 1, resulting in a deteriorated surface morphology. Even if the surface of the substrate 1 is rough, the underlayer 12 can mitigate the effect, and the condition of the layer formed on the underlayer 12 can be improved. The underlayer 12 is preferably a single layer of an AlGaN layer. x Ga 1-xN, and x is 0.004 or more and less than 0.08, preferably 0.01 or more and less than 0.08, and more preferably 0.01 or more and 0.05 or less. This can reduce the surface morphology of the underlayer 12. Also, x can be 0.015 or more and 0.035 or less. This can reduce the probability of cracks occurring in the underlayer 12 while reducing the effect of reducing the surface morphology. When a GaN layer not containing Al is provided as the underlayer 12, the diffusion length of Ga adatoms is small during crystal growth, which tends to cause undulations on the surface, and the flatness of the surface morphology tends to decrease. If the flatness of the surface morphology is insufficient, the parallelism of a pair of mirrors constituting the vertical cavity surface emitting laser element 10 decreases, and the feedback rate of light traveling back and forth through the cavity decreases. This can reduce the substantial reflectance of the multilayer film reflective layer 11 provided on the upper surface, which can deteriorate the threshold current. Therefore, by improving the surface morphology of the underlayer 12, the reflectance of the multilayer reflective layer 11 can be improved, and as a result, deterioration of the threshold current of the vertical cavity surface emitting laser device 10 can be suppressed, and the variation in the threshold current can be reduced. It is considered that the effect of improving the surface morphology can be enhanced by increasing the Al composition ratio in the underlayer 12, but on the other hand, the probability of cracks occurring in the underlayer 12 can be suppressed by decreasing the Al composition ratio. Therefore, by setting the Al composition ratio in the above-mentioned range, it is possible to achieve a balance between the improvement of the surface morphology and the suppression of cracks, and it is possible to improve the surface morphology and suppress cracks at the same time. The underlayer 12 may be an amorphous layer, a single crystal layer, or a mixture of these. Among them, a layer that is not amorphous is preferable, a single crystal layer is more preferable, and a single layer of a single crystal AlGaN layer is even more preferable. By making the underlayer 12 a single crystal layer, the possibility of dislocations occurring in a layer formed on the underlayer 12 can be reduced. The underlayer 12 may have a thickness of 3.5 μm or less, preferably 3.0 μm or less, more preferably 2.5 μm or less, and even more preferably 1.5 μm or less. This thickness reduces the possibility of cracks occurring in the underlayer 12. The underlayer 12 may have a thickness of 0.1 μm or more, preferably 0.2 μm or more. This thickness more effectively reduces the effect of the substrate 1 having a rough surface morphology. The upper and lower surfaces of the underlayer 12 may be flat or slightly uneven. The upper surface of the underlayer 12 may have an arithmetic mean height Sa of, for example, 3.0 nm or less. Alternatively, the upper surface of the underlayer 12 may have a surface roughness Ra of, for example, 3.0 nm or less. The underlayer 12 can be formed by epitaxial growth using a method known in the art, for example, metal organic chemical vapor deposition (MOCVD).

[0012] (Multilayer reflective layer 11) The multilayer reflective layer 11 is provided on the upper surface of the underlayer 12. In order to obtain a desired reflectance, the material constituting each layer, the film thickness, the number of layers, and the like of the multilayer reflective layer 11 can be appropriately selected. Specific examples include AlN, InN, GaN, AlGaN, InGaN, and AlInGaN. Also, examples of combinations of materials include AlInN / GaN, AlInN / AlGaN, and AlInN / AlN. Among them, the multilayer reflective layer 11 preferably includes an AlInN layer, and more preferably uses AlInN / GaN as the material. Here, the AlInN layer preferably has an In composition ratio of 1% to 30%. By setting the ratio within this range, the lattice constant of the AlInN layer and the lattice constant of the GaN layer can be made close to each other, thereby reducing the possibility of warping or cracking of the wafer when the multilayer reflective layer 11 is grown. The thickness of each layer constituting the multilayer film reflective layer 11 is, for example, λ / (4n) (where λ is the oscillation wavelength of the laser, and n is the refractive index of the medium constituting each layer), and can be appropriately set according to the oscillation wavelength λ and the refractive index n of the material used. Specifically, it is preferable to set it to an odd multiple of λ / (4n). For example, in a light emitting device with an oscillation wavelength λ of 450 nm, when the multilayer film reflective layer 11 is made of AlInN / GaN, the thickness of each layer can be 40 nm or more and 70 nm or less. The number of layers of the multilayer film can be appropriately set according to the intended characteristics. The number of layers of the multilayer film can be 2 or more, for example, 5 layers or more and 100 layers or less. The total thickness of the multilayer film reflective layer 11 can be, for example, 0.05 μm or more and 10 μm or less, preferably 0.1 μm or more and 10 μm or less, more preferably 0.1 μm or more and 8 μm or less, and even more preferably 0.1 μm or more and 7 μm or less. This range makes it possible to increase the light output while maintaining a good reflectance of the multilayer reflective layer 11. The size and shape of the multilayer reflective layer 11 in a top view can be appropriately designed as long as it covers the resonance region. The multilayer reflective layer 11 can be formed on the upper surface of the underlayer 12 by epitaxial growth using a method known in the art, such as MOCVD.

[0013] (Semiconductor laminate 5) The semiconductor laminate 5 is provided above the multilayer reflective layer 11. That is, the semiconductor laminate 5 may be formed in contact with the surface of the multilayer reflective layer 11, or may be formed on the multilayer reflective layer 11 via a semiconductor layer such as an intermediate layer or a buffer layer. In particular, the semiconductor laminate 5 is preferably formed in contact with the surface of the multilayer reflective layer 11. The semiconductor laminate 5 preferably includes an n-side semiconductor layer 2, an active layer 3, and a p-side semiconductor layer 4 in this order. The n-side semiconductor layer 2 may have a layer that does not contain n-type impurities as long as a part of the layers constituting the n-side semiconductor layer 2 contains n-type impurities, and the p-side semiconductor layer 4 may have a layer that does not contain p-type impurities as long as a part of the layers constituting the n-side semiconductor layer 2 contains p-type impurities. The semiconductor laminate 5 may be, for example, a III-V group compound semiconductor.X Al Y Ga 1-X-Y Examples of the nitride-based semiconductor materials include InN (0≦X, 0≦Y, X+Y≦1), and examples of the nitride-based semiconductor materials that can be used include InN, AlN, GaN, InGaN, AlGaN, InGaAlN, and the like. The thickness and layer structure of each layer can be those known in the art. Specifically, In X Al Y Ga 1-X-Y The n-side semiconductor layer 2 is made of an InN compound semiconductor. X Al Y Ga 1-X-Y The active layer 3 is made of an InN compound semiconductor. X Al Y Ga 1-X-Y The p-side semiconductor layer 4 made of an N compound semiconductor is laminated in this order. The n-side semiconductor layer 2 is a single layer or a multilayer, and has one or more semiconductor layers doped with n-type impurities, such as Si or Ge. The active layer 3 has a multiple quantum well structure or a single quantum well structure. For example, a layered structure in which quantum well layers made of InGaN and barrier layers made of GaN are alternately stacked can be mentioned. The number of layers can be appropriately set according to the desired characteristics. In addition to GaN, InGaN or the like having a lower In composition than the InGaN of the quantum well layer can be used as the barrier layer. The p-side semiconductor layer 4 is a single layer or a multilayer, and can have a p-side cladding layer and a p-side contact layer disposed thereon. The p-side contact layer is a layer doped with p-type impurities, such as Mg. The p-side cladding layer can be a layer doped with p-type impurities at a lower concentration than the p-side contact layer, or an undoped layer. In this case, the p-side contact layer is the top layer of the p-side semiconductor layer 4. The p-side contact layer is, for example, a GaN layer containing p-type impurities. The thicknesses of the n-side semiconductor layer 2, the active layer 3, and the p-side semiconductor layer 4 can be appropriately set. The total film thickness from the upper surface of the multilayer reflective layer 11 (to be described later) to the lower surface of the reflective layer 8 (to be described later) is λ / (2n eq )(n eqis an integer multiple of the equivalent refractive index of the waveguide) so that a standing wave occurs between them. It is preferable to arrange the active layer 3 so that the antinode of the standing wave is located at the active layer 3 and the node of the standing wave is located at the transparent electrode layer 6, which will be described later. By setting it in this way, the threshold current can be reduced. The shape and size of the semiconductor laminate 5 can be appropriately set depending on the size of the intended surface light emitting device, etc. Examples of shapes include a circle, an ellipse, a square, a rectangle, a polygon such as a hexagon, etc., as viewed from above, and examples of sizes include a rectangle with one side of 0.1 mm×0.1 mm or more and 1.0 mm×1.0 mm or less, a circle or a hexagon with one side or diameter of 0.1 mm or more and 1 mm or less, etc. The semiconductor laminate 5 can be formed, for example, by epitaxial growth on the multilayer reflective layer 11 provided on the upper surface of the underlayer 12 using a method known in the art, such as MOCVD.

[0014] As shown in FIG. 1, when the semiconductor laminate 5 has a convex portion including a resonance region, the p-side semiconductor layer 4, the active layer 3, and the n-side semiconductor layer 2 are partially removed in the thickness direction around the convex portion to expose the n-side semiconductor layer 2. This allows the p-side electrode layer 6 and the n-side electrode layer 9n that supply current to the vertical cavity surface emitting laser element 10 to be disposed on the same surface side of the semiconductor laminate 5. The convex portion can be formed by using a known method such as photolithography and etching after the semiconductor laminate 5 is formed. This exposes a part of the n-side semiconductor layer 2 around the convex portion. The side surface of the convex portion, that is, the exposed surface in the thickness direction of the n-side semiconductor layer 2, the active layer 3, and the p-side semiconductor layer 4 may be perpendicular to or inclined from the surface of the p-side semiconductor layer 4 opposite to the active layer 3. The surface (upper surface) of the p-side semiconductor layer 4 may be a flat plane or may have irregularities. When the upper surface of the p-side semiconductor layer 4 is a flat plane, the electrode layer 6 formed thereon can be disposed flat, and current concentration due to bending of the electrode layer 6 or the like can be avoided. Here, flatness refers to, for example, the maximum height roughness Rz of the surface of the p-side semiconductor layer 4 being 0.1 nm or more and 2 nm or less. By making the upper surface of the p-side semiconductor layer 4 flat, the reflective layer 8 described below can be formed flat. The convex portions are preferably located at positions where uniform light emission can be obtained in the plane of the surface light emitting element, and can be appropriately set depending on the planar shape of the semiconductor laminate 5, and can be located at any position in the semiconductor laminate 5 as viewed from above. For example, the convex portions can be located inside the semiconductor laminate 5, that is, at positions where the entire periphery thereof is surrounded by the n-side semiconductor layer 2.

[0015] In order to effectively resonate, it is preferable to arrange the current confinement region 4b so as to surround the current injection region 4a on the surface of the p-side semiconductor layer 4. In this case, the shapes, thicknesses, etc. of the current injection region 4a and the current confinement region 4b can be appropriately set depending on the characteristics of the vertical cavity surface emitting laser device 10 to be obtained.

[0016] (electrode layer 6) An electrode layer 6 is preferably disposed on the p-side semiconductor layer 4. The electrode layer 6 can be formed of a light-transmitting material having a transmittance of 80% or more, preferably 99% or more, for light of the peak wavelength of the laser light oscillated by the vertical cavity surface-emitting laser device 10. Examples of the light-transmitting material include transparent conductive materials having an oxide as a base material, such as indium tin oxide (ITO) and indium zinc oxide (IZO). The thickness of the electrode layer 6 is, for example, 5 nm or more and 100 nm or less. More preferably, it is 20 nm or more and 30 nm or less. By setting the thickness of the electrode layer 6 within this range, it is possible to reduce light absorption by the electrode layer 6 and reduce the threshold current. The electrode layer 6 can be formed after exposing the n-side semiconductor layer 2, which will be described later.

[0017] (Reflection layer 8) The reflective layer 8 is preferably disposed as a second reflective layer on the surface of the p-side semiconductor layer 4 including the electrode layer 6. The reflective layer 8 may be disposed, for example, only on the electrode layer 6, or may be disposed from above the electrode layer 6 to the surface of the p-side semiconductor layer 4 on which the electrode layer 6 is not provided. When the reflective layer 8 is formed only on the electrode layer 6, it is possible to form the reflective layer 8 more flatly. This makes it easier to control the shape of the oscillated laser light. The reflective layer 8 is formed on the surface of the electrode layer 6, directly above the current injection region 4a and over the current confinement region 4b around it. This facilitates pattern alignment during the formation of the reflective layer 8, improving productivity. The reflective layer 8 may be formed only directly above the current injection region 4a. In addition, since the reflective layer 8 is located above the current injection region 4a and formed on the flat electrode layer 6, it is possible to suppress the influence of unevenness. This allows the reflectance to be made somewhat uniform over a relatively wide area. As a result, the shape of the oscillating laser light is more stabilized, making it easier to control.

[0018] The reflective layer 8 has a diameter (or a side) larger than the diameter (or a side) of the current injection region 4a in a top view. The diameter (or a side) of the reflective layer 8 can be, for example, 1.1 to 1.5 times the diameter (or a side) of the current injection region 4a. The reflective layer 8 can be configured to include a dielectric multilayer film. The reflective layer 8 can be configured, for example, in the same manner as the semiconductor multilayer film or the dielectric multilayer film exemplified in the multilayer film reflective layer 11 described above. When the reflective layer 8 is configured by a dielectric multilayer film such as SiO2 / Nb2O5, each layer can have a thickness of 40 nm or more and 100 nm or less. The number of layers of the multilayer film can be 2 or more, for example, 5 layers or more and 20 layers or less. The total thickness of the reflective layer 8 can be, for example, 0.08 μm or more and 2.5 μm or less, and can be 0.6 μm or more and 1.7 μm or less. The reflective layer 8 is preferably formed apart from the insulating film 7 described later. In other words, the reflective layer 8 is preferably disposed so as not to overlap the insulating film 7 described later in a top view. This allows the reflective layer 8 to have fewer steps.

[0019] (insulating film 7, p-pad electrode 9p, electrode layer 9n) It is preferable to remove a portion of the p-side semiconductor layer 4, the active layer 3, and the n-side semiconductor layer 2 in the thickness direction, and to dispose an insulating film 7 on the partially exposed portion of the n-side semiconductor layer 2 and on the side surfaces of the p-side semiconductor layer 4, the active layer 3, and the n-side semiconductor layer 2. This insulating film 7 may cover the upper surface of the p-side semiconductor layer 4, but it is preferable to dispose it at least away from the current injection region 4a of the p-side semiconductor layer 4 where the above-mentioned reflective layer 8 is provided. The insulating film 7 is made of a SiO 2 -containing SiO 2 x SiN based materials, such as SiN y based materials, SiO x N y The insulating film 7 can be formed of inorganic materials such as Ta2O5, ZrO2, AlN, Al2O3, Ga2O3, etc. The thickness of the insulating film 7 can be set appropriately.

[0020] A p-pad electrode 9p is preferably disposed on the electrode layer 6. The p-pad electrode 9p is preferably formed in a shape surrounding the outer periphery of the current injection region 4a and in contact with the electrode layer 6. This allows a current to be more uniformly injected from the p-pad electrode 9p through the electrode layer 6 into the p-side semiconductor layer 4. The p-pad electrode 9p is also disposed so as to overlap with the above-mentioned reflective layer 8 in a top view. In other words, since the reflective layer 8 is formed after the p-pad electrode 9p is disposed, the p-pad electrode 9p is disposed so as to overlap with the outer periphery of the reflective layer 8 in a top view.

[0021] Moreover, an electrode layer 9n is preferably disposed on the exposed n-side semiconductor layer 2. This allows the electrode layer 6 and the electrode layer 9n that supply current to the vertical cavity surface emitting laser element 10 to be disposed on the same side of the semiconductor laminate 5. The p-pad electrode 9p and the electrode layer 9n may be formed of the same material in a single layer or laminated structure. When the electrode layer 9n and the p-pad electrode 9p are formed of the same material in the same laminated structure, the electrode layer 9n and the p-pad electrode 9p can be formed in the same process. The p-pad electrode 9p and the electrode layer 9n can be formed of a conductive material used as an electrode in the relevant field. For example, Ti / Pt / Au, Ti / Rh / Au, etc. can be mentioned.

[0022] The vertical cavity surface emitting laser element 10 configured in this manner can improve the surface morphology as described above. This prevents a decrease in the effective reflectance of the multilayer reflective layer 11 and improves the reflectance. The effective reflectance here means a reflectance that does not include the radiation mode and is coupled only to the cavity mode. As a result of the improvement in the reflectance of the multilayer reflective layer 11, the characteristics of the vertical cavity surface emitting laser element 10 can be stabilized, and for example, the variation in the threshold current can be reduced.

[0023] Working Example As shown in Fig. 2, a GaN substrate having a (0001) plane was used as the substrate 1, and an AlGaN layer (Al mixed crystal ratio 1.6%) was grown to a thickness of 1 µm on the substrate 1 as the underlayer 12 by metal organic chemical vapor deposition (MOCVD). 0.8 In 0.2 The multilayer reflective layer 11 was formed by stacking 50 pairs of N (50 nm thick) / GaN (45 nm thick). On the multilayer reflective layer 11, an n-GaN layer of 1.5 μm was laminated as the n-side semiconductor layer 2, five pairs of a quantum well layer InGaN (3 nm thick) / barrier layer GaN (2 nm thick) were laminated as the active layer 3, and an undoped GaN (25 nm thick) and an electron blocking layer AlGaN (10 nm thick) were formed as the final barrier layer. On top of that, a p-GaN layer (70 nm thick) was formed as the p-side semiconductor layer 4, thereby forming a semiconductor laminate 5. On the obtained semiconductor laminate 5, a transparent electrode ITO (30 nm thick) was formed by sputtering as the electrode layer 6, a spacer layer Nb2O5 (35 nm thick) was formed, and a dielectric multilayer film SiO2 (75 nm thick) / Nb2O5 (45 nm thick) was formed thereon as the reflective layer 8. In this way, a vertical cavity surface emitting laser element structure 20 was formed.

[0024] Comparative Example As shown in FIG. 3, a structure 20a similar to that of the example was formed on the substrate 1, except that a GaN layer was grown to a thickness of 1 μm as the underlayer 12a instead of the AlGaN layer (Al mixed crystal ratio: 1.6%).

[0025] For each of the vertical cavity surface emitting laser element structures 20 obtained in the examples and the comparative examples, the surface condition immediately after the completion of the formation of the underlayer 12 or the underlayer 12a was observed with a white light interference microscope, and the arithmetic mean height Sa was evaluated. As a result, it was confirmed that the structure of the example showed a good Sa value compared to the comparative example, and step mendering was suppressed. Further, based on the above-mentioned structure, a plurality of blue-emitting vertical-cavity surface-emitting laser elements 10 were fabricated, and the threshold current was measured. As a result, as shown in FIG. 4, it was confirmed that the element according to the embodiment has a smaller difference between the threshold current in the high percentile region (region of 50 percentile or higher) and the threshold current in the low percentile region than the element according to the comparative example, and the variation in threshold current for each element can be reduced. It was also confirmed that the threshold current in the high percentile region is lower than that of the comparative example. The horizontal axis in FIG. 4 represents percentile. Note that percentile refers to a quantity that represents what percentage of the total a certain numerical value is located in, starting from the smallest data, when multiple data are arranged in ascending order.

[0026] Test Example A GaN substrate having a (0001) plane was used as the substrate 1, and an AlGaN layer was grown to a thickness of 1 μm by metalorganic chemical vapor deposition (MOCVD) on the substrate 1 as the underlayer 12. At that time, the Al mole fraction of the AlGaN layer was changed between 0 and 8.0% to form samples with different Al mole fractions. The surface condition and occurrence of cracks were checked for each of the obtained samples. As a result, it was confirmed that good results were obtained for the flatness and cracks of the surface of the underlayer 12 in each sample obtained when the Al mixed crystal ratio of the underlayer 12 was in the range of more than 0.4% and less than 8.0%. In particular, the surface condition of the underlayer 12 was the best when the Al mixed crystal ratio of the underlayer 12 was 1.5%.

[0027] This application includes the following inventions. (1) a substrate including GaN; an AlGaN underlayer provided on an upper surface of the substrate; a multilayer reflective layer including an AlInN layer provided on an upper surface of the underlayer; A vertical cavity surface emitting laser element comprising an n-side semiconductor layer, an active layer and a p-side semiconductor layer provided above the multilayer reflective layer. (2) The underlayer is Al x Ga 1-x N, and x is 0.01 or more and less than 0.08. (3) The vertical cavity surface emitting laser element according to (1) or (2), wherein the underlayer has a thickness of 3.5 μm or less. (4) The vertical cavity surface emitting laser element according to any one of (1) to (3), wherein the AlInN layer has an In composition ratio of 1% to 30%. (5) The vertical cavity surface emitting laser element according to any one of (1) to (4), wherein the substrate has an off angle of 0.4° or more and 10° or less. (6) The vertical cavity surface emitting laser element according to any one of (1) to (5), further comprising an electrode layer and a reflective layer on the p-side semiconductor layer. [Explanation of symbols]

[0028] 1 Board 2 n-side semiconductor layer 3 Active layer 4 p-side semiconductor layer 4a Current injection area 4b Current confinement region 5. Semiconductor laminate 6 Electrode layer 7. Insulating Film 8 reflective layer 9n electrode layer 9p p-pad electrode 10 Vertical-cavity surface-emitting laser element 11 Multilayer reflective layer 12, 12a Base layer 20 Vertical-cavity surface-emitting laser device structure

Claims

1. a substrate comprising GaN; an AlGaN underlayer provided on an upper surface of the substrate; a multilayer reflective layer including an AlInN layer provided on an upper surface of the underlayer; A vertical cavity surface emitting laser element comprising an n-side semiconductor layer, an active layer and a p-side semiconductor layer provided above the multilayer reflective layer.

2. The underlayer is Al ｘ G １－ｘ 2. The vertical cavity surface emitting laser device of claim 1, wherein N is 0.01 or more and less than 0.

08.

3. 2. The vertical cavity surface emitting laser device according to claim 1, wherein the underlayer has a thickness of 3.5 μm or less.

4. 2. The vertical cavity surface emitting laser device according to claim 1, wherein the AlInN layer has an In composition ratio of 1% to 30%.

5. 2. The vertical cavity surface emitting laser device according to claim 1, wherein the substrate has an off angle of 0.4° to 10°.

6. The vertical cavity surface emitting laser device according to claim 1 , further comprising an electrode layer and a reflective layer on the p-side semiconductor layer.

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