Semiconductor device based on selective area epitaxy growth using mask to increase or decrease growth at edges

Abstract

To provide structures and manufacturing processes that enable reliable, manufacturable modulators monolithically integrated with lasers and optical amplifiers having well confined current injection.SOLUTION: A method of forming a photonic integrated circuit including a photonic device and a gain element structure is provided. The gain element is formed by a process including: depositing by epitaxy a first doped layer on a wafer; depositing by epitaxy an active layer capable of optical gain on the first doped layer; depositing by epitaxy a second doped layer on the active layer; pattern-etching at least the second doped layer and the active layer to form a first ridge; and depositing by epitaxy a current blocking layer that is laterally adjacent to the first ridge and at least partially fills the volume of the active layer removed by the pattern etching; where the current blocking layer forms a portion of the photonic device.SELECTED DRAWING: Figure 4

Description

[Technical field]

[0001] The present disclosure relates generally to semiconductor, i.e. photonic components for use in optical devices and optical networks. More particularly, the present disclosure relates to systems and methods for monolithically integrated gain elements, and to semiconductor devices with selective area epitaxy (SAE) growth utilizing a mask to suppress or promote edge growth, and modulators with monolithically integrated optical amplifiers. [Background technology]

[0002] The various possible configurations of planar optical waveguides used in photonic integrated circuits (PICs) are often broadly divided into two categories, strong and weak lateral guiding, depending on the strength of lateral guiding. The strength of lateral guiding determines how well an optical mode is confined to the center of the waveguide and determines the minimum radius that a curved optical waveguide can achieve before the mode does not couple and radiates out of the waveguide. As shown in FIG. 1A, a waveguide 3 may consist of a core guiding region 5 with an optical index of refraction Ng and a laterally adjacent cladding region 7 with an optical index of refraction Nc. Strong guiding refers to a large difference between Ng and Nc. For example, in an Indium Phosphide (InP) based PIC with a strong guiding waveguide, the waveguide core 5 may have an optical index of refraction of Ng=3.54, while the cladding 7 may be made of a dielectric material such as silicon dioxide (SiO2) and have an index of Nc=1.5. Conversely, weak guiding refers to the core index Ng being designed to be slightly higher than the cladding index Nc. For example, if the InP based PIC lateral cladding 7 were fabricated from a semiconductor instead of silicon dioxide, the waveguide 5 would still have Ng=3.54, but the lateral cladding 7 would have Nc=3.46, which may result in weak guiding. Another weak guiding structure is shown in Figure 1B. Here, there is no actual index change in the material 7 adjacent to the waveguide core 5, but a waveguide ridge 9 centrally located above the core 5 creates an effective index difference in the region laterally adjacent to the waveguide core 5. Such a weak waveguide 3 may be called a shallow ridge waveguide and may have an index contrast of Ng-Nc<0.05.

[0003] In the photonic component industry, InP-based Mach-Zehnder modulators (MZMs) are widely known for their low cost, small size, and high performance. In general, it is desirable to use a strongly guiding waveguide with a dielectric cladding 7 as shown in Figure 1A in such modulators. Strongly guiding waveguides not only allow for compact routing of the waveguide to reduce size, but also confine the mode to the central portion 5 of the waveguide 3, which provides the optical modulation function, thereby achieving high efficiency.

[0004] Modulators of the type described herein typically mix a continuous wave (CW) optical carrier input, which has no data content, with a wideband electrical signal carrying the data. The frequency of the CW carrier is, for example, about 193 THz, and is typically desired to be as narrow as possible, for example with a linewidth of 100 kHz. The bandwidth of the electrical data signal may range, for example, from 500 MHz to 10 GHz, or in modern high capacity communication systems, from 500 MHz to 70 GHz. Depending on the modulation scheme used, data rates of 10 Gbit / s to 400 Gbit / s or more can be obtained. The data is transmitted as an optical carrier at the frequency of the original CW optical carrier input, with an envelope modulation determined by the electrical data signal. The modulator thus performs the function of upconversion of the original RF (Radio Frequency) data from baseband to optical frequencies, enabling transmission over optical fiber. Modulators also combine multiple RF data tributaries, which are often amplitude modulated, into more complex phase- and amplitude-modulated formats, which improves the signal-to-noise ratio (SNR) of the data at the receiving end of a fiber, for example.

[0005] Critical to the functioning of such a modulator is the input of a CW optical carrier. In some applications, the CW optical carrier is provided by an external laser and coupled to the input of the modulator through a short length of optical fiber if they are packaged separately, or via a microlens or optical waveguiding system if they are co-packaged. In these applications, the light lost during the coupling and modulation process is a key performance parameter. If too much light is lost from the CW optical carrier, the upconverted data signal output from the modulator will have low power and a low SNR at the receiver. One obvious solution is to use a high-power laser to compensate for the loss. However, there are technical limitations to increasing the laser power, and there are engineering implications such as power loss, nonideal performance, and cost. Monolithic integration of a semiconductor optical amplifier (SOA) with the modulator can solve these problems.

[0006] In other applications, it is preferable to monolithically integrate the laser itself with the modulator, thus avoiding optical coupling losses, packaging complexity and costs associated with external solutions. Of course, laser integration can also be combined with integrated SOAs to further increase the optical output. Lasers and SOAs are generally called active or gain elements. Whether lasers or SOAs, the technical situation of lateral optical guiding means is fundamentally similar. With such integration, the need often arises to integrate photonic components other than the modulator, laser or SOA, i.e. detectors, optical monitors, phase adjustment elements, variable optical attenuators, etc. Thus, the extension of the invention to the integration of gain elements (lasers and SOAs) with photonic components other than modulators is of fundamental importance.

[0007] Known shallow ridge, or stripe, lasers and SOAs have configurations similar to Figure 1B. In addition to being weakly guided, they lack lateral current confinement, causing the current to spread non-uniformly and inefficiently over a large area, reducing gain.

[0008] Known planar deep ridge lasers and SOAs similar to FIG. 1A have dielectric lateral cladding 7 and, like most modulators, are largely unused because the etched sidewalls of the waveguide core 5 leave dangling chemical bonds that act as mid-level traps. These mid-level traps add a large non-radiative component to the associated carrier recombination, making the current-gain curve very unfavorable. Appropriate chemical treatment of the sidewalls and semiconductor overgrowth can remove the dangling chemical bonds.

[0009] Known Buried Heterostructure (BH) laser and SOA structures, with numerous variations and the current industry standard, achieve favorable current confinement to the multi-quantum well (MQW) core by placing current blocking layers at higher levels. One drawback is that the regrowth method is complex and difficult to integrate monolithically with the modulator in a manufacturable manner. Furthermore, BH lasers and SOAs with Al-containing cores are notorious for reliability issues. As shown in FIG. 2A, the BH structure 15 is fabricated by blanketing an N-InP wafer 10 with an initial growth of MQW material 12. This is followed by selective etching to form the MQW ridge. Subsequently, a multilayer stack 16 is selectively grown around the MQW ridge on the N-InP wafer 10 to the sensitive critical dimension. Finally, an overgrowth of P-type semiconductor 18 is blanketed on top of the MQW ridge and the multilayer stack 16. In this way, the current is highly confined, but the waveguide is still weakly guided.

[0010] Recently, attempts have been made to simplify the complex arrangement of current blocking layers in BH lasers using a self-aligned single-growth technique. This structure exhibits beneficial current confinement. As shown in FIG. 2B, the simplified BH structure 15b is fabricated by blanketing an N-InP wafer 10 with an initial growth of MQW 12 and P-type semiconductor 18 materials. Selective etching is performed to form the MQW ridge. A single blanket layer of undoped InP 17 is then grown on top of the structure 15. This undoped InP 17 is removed from the top of the ridge using a self-aligned etching technique. Like the more complex BH structure 15a (FIG. 2A), this simplified BH structure 15b (FIG. 2B) achieves good current confinement but is still weakly waveguiding.

[0011] Neither the shallow ridge structure (Fig. 1B) nor the BH structure (Fig. 2B) can be optically coupled directly to a modulator due to the incompatibility of the waveguides, requiring some interconnect means to bridge the strongly and weakly guiding waveguides, as described, for example, in US Pat. No. 5,399,663.

[0012] Thus, there remains a need in the art for structures and processes that enable reliable, manufacturable modulators monolithically integrated with lasers and optical amplifiers with well-confined current injection.

[0013] Moreover, selective area epitaxy (SAE) involves the localized growth of an epitaxial layer through an amorphous dielectric mask, typically silicon dioxide (SiO2) or silicon nitride (Si3N4), patterned on a semiconductor wafer. The semiconductor growth conditions are selected to ensure epitaxial growth on the exposed wafer and not on the dielectric mask. SAE is formed by covering a portion of the semiconductor surface with a mask material where no growth occurs. Traditionally, SAE has been used to intentionally enhance the growth of an epitaxial layer. The larger the area of ​​the masked region, the greater the proportion of crystalline growth adjacent to the mask. The degree of growth enhancement depends on many factors, including growth temperature, growth pressure, mask composition, mask area, and mask orientation.

[0014] Unintentional growth promotion at the mask edges is a continuing problem with SAE. Solutions to date have focused on modifying the growth conditions for epitaxial growth. Of note, SAE is a technique used in the fabrication of InP photonics. One example of such an optical modulator is described in U.S. Patent No. 5,399,363, entitled “Monolithic Optoelectronic TWE-component Structure for High Frequencies and Low Optical Insertion Loss,” the contents of which are incorporated herein by reference in their entirety.

[0015] Varying growth conditions to suppress unintentional enhancement has the drawback of suppressing intentional growth enhancement, which is often the purpose of pursuing SAE growth in the first place. The use of traditional straight-sided SAE masks results in linear structures of enhanced growth material along the mask edges that are fragile and prone to breaking off and forming contamination on the device surface, adversely affecting manufacturability and reliability. [Prior art documents] [Patent documents]

[0016] [Patent Document 1] U.S. Patent No. 7,184,207 [Patent Document 2] U.S. Patent No. 9,182,546 Summary of the Invention

[0017] The present disclosure relates to a system and method for semiconductor devices having selective area epitaxy (SAE) growth utilizing a mask to inhibit or promote edge growth. To reiterate, SAE is a technique for growing crystals on a semiconductor wafer. Areas of the wafer are covered or masked with a thin film of dielectric material (e.g., SiO2, Si3N4, etc.). In a crystal growth reactor, such as a Metal-Organic, Chemical-Vapor Deposition (MOCVD) chamber, crystal growth proceeds selectively only in areas not covered by the mask. The present disclosure provides a process for fabricating semiconductor devices that include areas that are selectively grown in any direction, without unwanted enhanced growth and corresponding defects at the edges outside the masked areas. Specifically, the process includes a variable profile of the mask edge that is used to inhibit or promote edge growth.

[0018] The present disclosure also provides a design for efficient monolithic integration of optical amplifiers into deep etched ridge waveguide modulators formed on InP wafers, such as those described in US Pat. No. 5,399,363, and in particular multi-growth modulators. This design allows the existing undoped overgrowth of the TWE modulator to be reused for current blocking purposes. Subsequent deep etching of the current blocking buried ridge provides independent control of the confinement factor, allowing efficient coupling to the deep etched modulator. In this way, the present disclosure provides a means to reuse the overgrowth already present in the standard modulator process sequence, thereby reducing many epitaxial growth-related problems such as cost, complexity, and reliability issues. The present disclosure provides better current confinement, and therefore better electrical efficiency, than alternative shallow ridge solutions. The present disclosure decouples the current confinement (provided by the i-InP blocks detailed below) from the optical confinement (provided by the etched regions detailed below). Thus, the present disclosure provides an efficient alternative for coupling light from a modulator to a gain section without introducing additional or new optical elements into the design, such as those provided in US Pat. No. 6,399,323.

[0019] The present disclosure provides a modulator having an optical amplifier including an N-type layer, a multiple quantum well material disposed on the N-type layer, and a P-type layer disposed on the multiple quantum well material opposite the N-type layer. A portion of the N-type layer, the multiple quantum well material, and a portion of the P-type layer collectively form a ridge structure, and using selective area epitaxy, an intentionally undoped material (commonly referred to as intrinsic, or i-type) is disposed on the N-type layer and around the sides of the ridge structure. Although i-type is the common designation for an intentionally undoped semiconductor, the i-type material contains low levels of unintentional trace dopant contamination, in some cases up to 1e16 atoms / cm. 3The above may be present, but those skilled in the art will appreciate that a lower concentration is typically desired. Optionally, the i-type material is etched deeper to form a strong waveguiding structure. The N-type layer includes N-InP. The P-type layer includes either P-InGaAs or P-InP. The i-type material includes i-InP, but may alternatively be any type of suitable current blocking material that blocks current flow, such as semi-insulating iron-doped InP. Optionally, the width of the strong waveguiding structure is selected to efficiently couple to the strongly guided modulator waveguide over all or part of its length. [Brief description of the drawings]

[0020] [Figure 1] 1A and 1B are a series of schematic diagrams illustrating a conventional strongly guiding waveguide and a weakly guiding waveguide (shallow ridge), respectively. [Figure 2A] 2A and 2B are a series of schematic diagrams illustrating a conventional method for fabricating a BH laser or SOA structure. [Figure 2B] 2A and 2B are a series of schematic diagrams illustrating a conventional method for fabricating a BH laser or SOA structure. [Diagram 3] FIG. 3 is a series of schematic diagrams illustrating a conventional method for manufacturing a gain element. [Figure 4] FIG. 4 is a series of schematic diagrams illustrating a method for fabricating one exemplary embodiment of a gain element of the present disclosure. [Diagram 5] FIG. 5 is a series of schematic diagrams illustrating the fabrication of another exemplary embodiment of a gain element of the present disclosure and the coupling of an associated SOA and modulator. [Figure 6] FIG. 6 is a schematic diagram illustrating the flaring of the width of a waveguide SOA or modulator to match the optical mode of an associated modulator SOA according to the methods of the present disclosure. [Figure 7] FIG. 7 is another schematic diagram illustrating flaring the width of a waveguide modulator to match an SOA optical mode according to the method of the present disclosure. [Figure 8]FIG. 8 is a schematic diagram showing a new geometry for the edge of a mask used to overgrow an epitaxial layer and suppress unwanted growth enhancement according to the method of the present disclosure. [Figure 9A] 9A-9D are block diagrams illustrating steps in an SAE growth process on a wafer, showing excess growth at the edges of the mask. [Figure 9B] 9A-9D are block diagrams illustrating steps in an SAE growth process on a wafer, showing excess growth at the edges of the mask. [Figure 9C] 9A-9D are block diagrams illustrating steps in an SAE growth process on a wafer, showing excess growth at the edges of the mask. [Figure 9D] 9A-9D are block diagrams illustrating steps in an SAE growth process on a wafer, showing excess growth at the edges of the mask. [Figure 10] FIG. 10 is a photograph of the actual wafer after the step of FIG. 9D. [Figure 11] Figure 11A is a top view of the wafer showing an area, and Figure 11B is a photograph of the wafer showing the area and overgrowth over the mask. [Figure 12] 12A and 12B are photographs showing a cross section of the P island of FIGS. 9A-9D in the direction of the waveguide (FIG. 12A) and perpendicular to the waveguide (FIG. 12B). [Figure 13] FIG. 13 shows a diagram of a wafer, an InP wafer oriented in the (100) plane having a major flat and a minor flat perpendicular to the major flat, and a graph showing the preferred orientation of the wafer. [Figure 14] FIG. 14 is an illustration of an angled rectangular mask from series 2 and a zigzag shaped mask with variable angles from both series 1 and 2. [Figure 15] FIG. 15 is a diagram of an example InP wafer with a mask placed on the wafer. [Figure 16] FIG. 16 is a diagram of an example InP wafer with mask 12B placed on the wafer. [Figure 17] FIG. 17 is a flow chart of a process for growing epitaxial layers on a semiconductor wafer for a semiconductor device. [Figure 18] FIG. 18 is a photograph of a circular mask in a high resolution Field of View (FOV) showing how the preferred angle was determined. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0021] The present disclosure is illustrated and described herein with reference to various drawing figures, in which like reference numbers are used, where appropriate, to designate like system components / method steps.

[0022] To reiterate, the present disclosure provides a design for efficient monolithic integration of optical amplifiers into deep etched ridge waveguide modulators formed on InP wafers, such as those described in US Pat. No. 5,399,363, and in particular multi-growth modulators. This design allows the existing undoped overgrowth of the TWE modulator to be reused for current blocking purposes. Subsequent deep etching of the current blocking buried ridge provides independent control of the confinement factor, allowing efficient coupling to the deep etched modulator. In this way, the present disclosure provides a means to reuse the overgrowth already present in the standard modulator process sequence, thereby reducing many epitaxial growth-related problems such as cost, complexity, and reliability issues. The present disclosure provides better current confinement, and therefore better electrical efficiency, than alternative shallow ridge solutions. The present disclosure decouples the current confinement (provided by the i-InP blocks detailed below) from the optical confinement (provided by the etched regions detailed below). Thus, the present disclosure provides an efficient alternative for coupling light from a modulator to a gain section without introducing additional or new optical elements into the design, such as those provided in US Pat. No. 6,399,323.

[0023] The present disclosure provides a modulator having an optical amplifier including an N-type layer, a multiple quantum well material disposed on the N-type layer, and a P-type layer disposed on the multiple quantum well material opposite the N-type layer. A portion of the N-type layer, the multiple quantum well material, and a portion of the P-type layer collectively form a ridge structure, and using selective area epitaxy, a material that is not intentionally doped (undoped, or i-type) is disposed on the N-type layer and around the sides of the ridge structure. Optionally, the i-type material is etched deeper to form a strong waveguiding structure. The N-type layer includes N-InP. The P-type layer includes either P-InGaAs and P-InP. The i-type material includes i-InP, but may alternatively be any type of suitable current blocking material that blocks current flow, such as semi-insulating iron-doped InP. Optionally, the width of the strong waveguiding structure is selected to efficiently couple to a strongly guided modulator waveguide over all or a portion of its length.

[0024] Monolithic Integrated Gain Element FIG. 3 illustrates the fabrication of a conventional modulator structure 25, such as by the process provided in U.S. Pat. No. 6,399,363. The modulator structure 25 is fabricated by blanketing an N-type wafer 10 with an initial growth of MQW material 12 and P-type layer 18. In an i-type ridge embodiment, the P-type layer 18 is then selectively etched and a u-InP layer 20 is selectively grown in the etched area. The P-type layer 18 and MQW material 12 are then selectively etched, leaving an i-InP capped ridge in an i-type ridge SOA embodiment and a P-type capped ridge in a P-type ridge modulator embodiment. Thus, a selective i-type growth step is commonly utilized. It remains desirable to monolithically integrate an SOA with a modulator and provide similar performance to the BH structure 15 (FIGS. 2A and 2B) without introducing critical alignment growth steps. It also remains desirable to create a BH-like structure with a lateral optical mode compatible with optical coupling to a deeply etched modulator ridge for a monolithically integrated SOA.

[0025] 4, in one embodiment, the gain element structure 35 of the present disclosure is fabricated by blanketing an N-type layer 1 with first growth of optical gain material 12 and a P-type layer 18. The P-type layer 18, optical gain material 12, and N-type layer 10 are then selectively etched away to leave a P-capped ridge covered by a mask 19. An i-type growth step is then utilized to fill the lateral regions of the ridge with i-InP material 20, where the lateral i-InP material 20 provides excellent current blocking without the need for additional growth steps or critical placement associated with BH fabrication.

[0026] FIG. 5 is a series of schematic diagrams illustrating the fabrication of another exemplary embodiment of the gain element structure 35 of the present disclosure, as well as associated SOA 37 and modulator 39 coupling means. The i-InP material 20 and N-type material 10 are etched to form walls of i-InP material on either side of the ridge, thereby providing strong waveguiding on either side of the ridge. In addition, the deeply etched modulator waveguide can be widened to provide lateral optical matching. In FIG. 5, it will be understood that the bottom schematic represents the modulator waveguide width-matched to the SOA input / output waveguides shown in the central schematic. In the SOA 37, W1 (current confinement) and W2 (optical mode overlap) can be independently varied, e.g., to vary the gain along the length of the SOA 37, to mitigate spatial hole burning effects.

[0027] FIG. 6 is a schematic diagram showing the flaring of the width of a waveguide SOA or modulator to match the optical mode of an associated modulator SOA according to the method of the present disclosure. Any combination of central and outer widths with a taper in between is possible. For example, it is possible to only tape the center and omit the constant sections at the beginning and end. This provides practical advantages for spatial hole burning by having high optical confinement at the beginning, increasing the injection dose, but less optical overlap at the end.

[0028] 7 is another schematic diagram illustrating flaring the width of a waveguide modulator to an SOA optical mode according to the methods of the present disclosure, where an SOA waveguide 37 is coupled to a modulator waveguide 39 via a tapered passive waveguide 38 or a tapered section of the SOA waveguide 37 or modulator waveguide 39.

[0029] In the conventional modulator structure 25 of FIG. 3, there is already a selective growth of the i-InP layer 20, the thickness of which may be determined by the optimization of the modulator design. This same growth is used here to provide better current blocking for the SOA. As shown in FIG. 4, the i-InP layer 20 from the conventional modulator may be deposited on either side of the SOA ridge 19. However, the design requirements of the modulator 25 may not provide a thickness of the i-InP layer 20 sufficient to match the height of the SOA ridge 19. Enhanced growth may be used to create a more planar top surface to improve the manufacturability of subsequent processing steps. It should be noted that for areas that do not require the increased lateral confinement of the current blocking mesa, the width may be increased to improve the thermal impedance of the SOA. Also, if one wishes to enhance the lateral optical confinement (to match the mode of the modulator and / or improve the efficiency of the SOA), a deep etch ridge may be used.

[0030] Semiconductor devices with inhibited or enhanced selective area epitaxy (SAE) growth The present disclosure also relates to systems and methods for semiconductor devices having selective area epitaxy (SAE) growth utilizing a mask to inhibit or promote edge growth. To reiterate, SAE is a technique for growing crystals on a semiconductor surface. Wafer areas are covered or masked with a thin film of dielectric material (e.g., SiO2, Si3N4, etc.). In a crystal growth reactor, such as a metal-organic vapor phase deposition (MOCVD) chamber, crystal growth proceeds selectively only in areas not covered by the mask. The present disclosure provides a process for fabricating semiconductor devices that include areas that selectively grow in any direction and that are free of defects corresponding to unwanted enhanced growth on the edges outside the masked areas. Specifically, the process includes a variable profile of the mask edge that is used to inhibit or promote edge growth.

[0031] As an enabling technique, FIG. 8 shows a novel shape 50 for the edge of the mask used to overgrow the epitaxial layer. For example, there is often an undesirable degree of enhanced crystal growth that occurs at the mask edge where the pattern is in the

[0011] or [0-11] direction. Using a nonlinear shape 50 for the mask edge can suppress this undesirable enhanced growth. Using a zigzag pattern for the mask edge, rather than a straight edge, is a novel solution. Unintended enhanced growth at the mask edge is a continuing problem in selective area growth. Previous solutions have focused on changing the growth conditions for the epitaxial growth. Selective area epitaxy is a technique used to fabricate many InP optical modulators. This technique and the use of mask patterns to suppress unintended enhancement are associated with multi-growth modulators on InP wafers, as described in US Pat. No. 5,399,363. Varying the growth conditions to suppress unintended enhancement has the drawback of suppressing intentional enhanced growth, which is often the purpose of pursuing selective area growth in the first place. The use of conventional straight-sided SAE masks results in linear structures of growth-enhancing material along the mask edges, which are prone to breaking off and forming contamination on the device surface, negatively impacting manufacturability and reliability. By using the shape solution 50, the intentional growth-enhancing at the edges of the mask can be suppressed without compromising the intentional growth-enhancing. The effect of unintentional promotion at the mask edges is anisotropic at the wafer surface; the effect is stronger along one directional axis, but weaker along the perpendicular axis. By placing the zigzag pattern 50 along the edges susceptible to promotion, there are few boundaries parallel to the line where unintentional promotion occurs.

[0032] 9A-9D are block diagrams illustrating steps of an SAE growth process 95 on a wafer 100 showing excess growth at the edges of the mask 102. The wafer 100 is a wafer including a wafer 104, P islands 106 of indium phosphide (InP), and a contact layer 108 including, for example, indium gallium arsenide (InGaAs). The mask 102 may include SiO2 and is deposited on the contact layer 108 in FIG. 9A. In FIG. 9B, areas are etched through the mask 102, the P islands 106, and the contact layer 108. In FIG. 9C, SAE growth is performed in the etched areas. Note that there is no SAE growth on top of the mask 100. In FIG. 9D, the mask 100 has been removed. FIGS. 9C and 9D include excess growth 110 at the edges of the mask 100.

[0033] Figure 10 is a photograph of Figure 9D on an actual wafer 100. Specifically, it shows that the conventional use of a straight-sided SAE mask 102 results in linear structures of growth-promoting 110 material along the mask edges that are prone to break and form contaminants on the device surface, adversely affecting manufacturability and reliability. Figure 10 shows how, upon cleanup of the residual oxide, the excess growth 110 breaks along the edges of the P islands 106 parallel to the major flats, even though the edges parallel to the minor flats (perpendicular to the length of the waveguide) are clean.

[0034] Figure 11A is a top view of wafer 100 showing region 140, and Figure 11B is a photograph of wafer 100 showing region 140 and overgrowth 110 extending above mask 102. The bare wafer is masked with oxide, and there is a thick overgrowth of InP in region 140. This creates a "cap" of overgrowth that hangs over the oxide. A subsequent etch is sufficient to remove the oxide under the cap, but tends to destroy other materials.

[0035] Figures 12A and 12B are photographs showing cross sections of the P island 106 in the waveguide direction (Figure 12A) and perpendicular to the waveguide (Figure 12B). Note that in Figure 12A the interface is well behaved in the waveguide direction, while Figure 12B shows after wet cleanup that the overgrowth has been destroyed. In front of this is a large "mushroom cap" shape of InP. This feature leaves a residual column of material when later etched away.

[0036] Variously, the present disclosure notes that a particular preferred angle of the mask 102, adaptation of the shape and / or orientation of the mask 102, and / or a zigzag edge of the mask 102 can result in suppression (or promotion) of growth at the edges of the mask 102. That is, the mask 102 includes a particular shape that suppresses or promotes intentional growth promotion at the edges of the mask 102 without compromising the intentional growth promotion that is the objective of the SAE. The effect of unintended promotion at the mask edges is anisotropic at the wafer surface, i.e., it is different when measured in different directions. The effect is stronger along one axis and weaker along the perpendicular axis. This is illustrated in Figures 12A and 12B.

[0037] In one embodiment, a zigzag pattern or other angular pattern is placed along edges susceptible to promotion so that most of the boundaries are not parallel to the line where unintended promotion occurs.

[0038] Through growth experiments with III-V semiconductor materials (specifically, InP wafers oriented in the (100) plane), it has been found that edges of the mask 102 aligned along certain crystal axes are particularly sensitive to the orientation of the 0011 or

number

[0039] It has also been determined that the converse is true: unwanted enhanced crystal growth along certain crystallographic directions is suppressed, and in fact, the crystal growth is inhibited along the 0011 axis or

number

number

[0040] For an InP wafer 150 oriented in the (100) plane (wafer 100), for example, growth promotion passes through a null when the edge of the SAE mask 102 is aligned at one of the following angles ("preferred angles") relative to the 0011 direction 164, collected in two series: [Table 1]

[0041] Each series includes four angular orientations, each orientation being 90 degrees apart from the other three orientations in the series. For a (100) oriented InP wafer 150, there are a total of eight orientations available to the edge of the SAE mask 102 that are free of promotion and defects. Specifically, graph 160 shows in graphical form series 1 and 2 relative to the

[0011] direction 164. Although the angles for series 1 and 2 are specified relative to the

[0011] direction 164, one of ordinary skill in the art will recognize that these angles relative to the edge of the mask 102 are:

number

[0042] FIG. 14 is a perspective view of a rectangular mask 102A angled according to series 2 and a zigzag shaped mask 102B with variable angles from both series 1 and 2. FIG. 15 is a perspective view of an InP wafer 150 with an exemplary mask 102A disposed thereon. FIG. 16 is a perspective view of an InP wafer 150 with an exemplary mask 102B disposed thereon. Those skilled in the art will recognize that FIGS. 13-16 are not to scale. Typically, the InP wafer 150 may be on the order of centimeters in size (diameter) from the major flat 152 to the opposite side (top). The mask 102 is on the order of hundreds of microns in length and tens of microns in width, with the teeth of the zigzag being on the order of microns.

[0043] The use of mask 102 with InP wafer 150 is utilized to form a semiconductor device having an SAE that is fabricated via a process of growing an epitaxial layer on semiconductor wafer 150. In one embodiment, the semiconductor device includes 1) a first region covered by mask 102 that inhibits crystal growth on the surface of semiconductor wafer 150, 2) a second region that is complementary (proximate) to the first region and not covered by mask 102 that allows crystal growth on semiconductor wafer 150, and 3) a perimeter of mask 102 that surrounds the first region and serves as a boundary between the first and second regions, where a majority of the length of the perimeter is substantially aligned along a preferred crystal direction that provides reduced growth enhancement on semiconductor wafer 150.

[0044] Also, semiconductor wafer 150 may have areas where enhanced growth is desired and areas where enhanced growth is not desired, and the present disclosure provides the flexibility to meet both needs, e.g., enhanced growth is desired for spot size converters and minimal growth is desired for traveling wave electrodes.

[0045] In one embodiment, the mask 102A is a quadrilateral in shape, i.e. a polygon with four sides (or sides) and four vertices or corners, i.e. the perimeter may be a quadrilateral. What is important is that one of the four sides coincides with the preferred angle.

[0046] In another embodiment, mask 102B is in the shape of a series of zigzag patterns, ie, the perimeter includes a series of small corners along with a preferred corner.

[0047] The semiconductor wafer surface 150 is composed of a compound of group III and group V elements. In one embodiment, the semiconductor wafer surface 150 is InP cut near the (100) direction. The preferred crystal orientations are approximately one or more of the following angles with respect to the 0011 direction: 34, 124, 214, 304, 56, 146, 236, 326 degrees. It should be noted that each of the last four numbers is (360 - one of the first four numbers) and vice versa. That is, 326 = 360 - 34, 236 = 360 - 124, etc.

[0048] 17 is a flow chart of a process 180 for growing an epitaxial layer on a semiconductor wafer for a semiconductor device. The process 180 includes using a semiconductor wafer having an in-plane orientation to deposit one or more masks on the semiconductor wafer, each mask configured to cover a portion of the semiconductor wafer, each mask including a periphery having a plurality of sides substantially aligned along a preferred crystal direction with respect to the orientation providing enhanced or reduced growth promotion at the edges of the substantially aligned sides (step 184). It also includes performing selective area epitaxy (SAE) growth on the surface of the semiconductor wafer (step 186).

[0049] The periphery has a quadrilateral shape or a series of zigzag patterns. The semiconductor wafer can include a compound of group III and group V elements. The semiconductor wafer can be indium phosphide (InP) and the plane can be close to a (100) direction. The preferred crystal orientation can be one or more of the following with respect to the 0011 direction of the semiconductor wafer: an angle close to 34, 124, 214, 304, 56, 146, 236, 326 degrees.

[0050] In one embodiment, the mask is for a spot size converter and the preferred crystal orientation is selected to provide maximum growth enhancement, in another embodiment, the mask is for a traveling wave electrode and the preferred crystal orientation is selected to provide reduced growth enhancement.

[0051] Additionally, the process 180 may form a semiconductor device.

[0052] In another embodiment, a semiconductor device is fabricated via a process of growing an epitaxial layer on a semiconductor wafer via selective area epitaxy (SAE) and includes a first region covered by a mask that inhibits crystal growth on a surface of the first region, a second region adjacent the first region and not covered by the mask that allows crystal growth on a surface of the second region, and a perimeter of the mask that serves as a boundary between the first and second regions, wherein a plurality of sides of the perimeter are substantially aligned along a preferred crystal direction relative to an orientation of the semiconductor wafer to minimize or maximize growth promotion at edges of the substantially aligned sides.

[0053] FIG. 18 is a photograph of the circular mask in a high resolution field of view (FOV) showing how the preferred angles were determined. Of note is that the circular mask represents all possible angle values ​​(0-360 degrees) relative to the 0011 direction 164. In this manner, small islands could be isolated and data extracted. It was determined that it was possible to correlate island height and volume with the angle. In this manner, the preferred crystal orientations were determined to be one or more of the following angles relative to the 0011 direction of the InP wafer 150: approximately 34, 124, 214, 304, 56, 146, 236, 326 degrees. One skilled in the art will recognize that this same approach, i.e., using a circular mask to experimentally determine growth characteristics at different angles, can be used with other types of wafers 100 having other crystal axes, etc., to determine the preferred mask 102 angle.

[0054] While the present disclosure has been illustrated and described herein with reference to preferred embodiments and specific examples thereof, it will be readily apparent to those skilled in the art that other embodiments and examples may perform similar functions and / or achieve similar results. All such equivalent embodiments and examples are within the spirit and scope of the present disclosure, are contemplated thereby, and are intended to be covered by the following claims.

Claims

1. A method of forming a photonic integrated circuit including a photonic device and a gain element structure (35), the method comprising: epitaxially depositing a first doped layer (10) on the wafer; epitaxially depositing on said first doped layer (10) an active layer (12) capable of optical gain; epitaxially depositing a second doped layer (18) on said active layer (12); pattern-etching at least the second doped layer (18) and the active layer (12) to form a first ridge; epitaxially depositing a current blocking layer (20) laterally adjacent to said first ridge and at least partially filling a volume of the active layer (12) removed by said pattern etching; The method, wherein the current blocking layer (20) forms part of the photonic device.

2. a first waveguide formed by the combination of the first ridge and an adjacent current blocking layer, the first waveguide being constant or tapered and having a first overall length and a first overall width; 10. The method of claim 1, further comprising: a second waveguide formed by selectively etching the current blocking layer, the second waveguide being contiguous with the first waveguide, the second waveguide being constant or tapered, and having a second overall length and a second overall width.

3. The method of claim 2 , wherein the first overall width is greater than the second overall width, the first waveguide being weakly guided and the second waveguide being strongly guided.

4. The method of claim 1 , wherein the second overall width tapers along the second overall length to provide a transition from weak to strong waveguiding in the second waveguide.

5. The method according to any of the preceding claims, wherein the gain element structure (35) is optically coupled to the photonic device.

6. 6. The method of claim 2, further comprising a strongly guided third waveguide contiguous with the second waveguide and having a third width, the third width and the second width being selected to provide optimal coupling of light between the second and third waveguides.

7. The method according to any of the preceding claims, wherein the photonic device is an optical modulator (39).

8. The method of any of claims 1 to 7, wherein the current blocking layer (20) comprises an undoped semiconductor.

9. The method of any of claims 1 to 8, wherein the wafer comprises indium phosphide.

10. 10. The method of any of claims 1 to 9, wherein any of the first doped layer (10), the second doped layer (18), and the current blocking layer (20) are made substantially conductive or non-conductive using ion implantation means.

11. 10. The method of any of claims 1 to 9, wherein any of the first doped layer (10), the second doped layer (18), and the current blocking layer (20) are made substantially conductive or non-conductive using dopant diffusion means.

12. The method of any of claims 1 to 11, wherein the current blocking layer (20) comprises multiple sublayers, each sublayer having a different dopant.

13. The method of any of claims 1 to 12, wherein the current blocking layer (20) is an overcladding layer in the photonic device.

14. The method of claim 1 , wherein the current blocking layer comprises iron-doped indium phosphide.

15. A photonic integrated circuit formed by the method of any of claims 1 to 14.

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