Method for producing multilayer film SOI wafer and multilayer film SOI wafer

Abstract

To provide a multilayer film SOI wafer, in which, by creating a terrace-free structure with no steps on a peripheral part, a large effective area of an active layer is secured and variations in in-plane thickness can be minimized.SOLUTION: A method for producing a multilayer film SOI wafer includes the steps of: subjecting each of a plurality of silicon wafers to double side polish, thereby forming a plurality of active layer substrates 4, 6; forming an oxide film layer on a surface of at least one of active layer substrates that are bonded to each other, among the plurality of active layer substrates; stacking the plurality of active layer substrates through the oxide film layer, thereby forming an element side substrate 10; subjecting the element side substrate to double side polish; polishing a silicon wafer to form a support substrate 2 and forming an oxide film layer on a surface of the support substrate; and bonding one side of the element side substrate to the support substrate through the oxide film layer formed on the support substrate.SELECTED DRAWING: Figure 3

Description

[Technical field]

[0001] The present invention relates to a method for manufacturing a multi-layer SOI wafer and a multi-layer SOI wafer, and more particularly to a method for manufacturing a terrace-free multi-layer SOI wafer that does not have a step on the outer periphery, and a multi-layer SOI wafer. [Background technology]

[0002] SOI (Silicon on Insulator) wafers achieve high integration, low power consumption, high speed, and high reliability of semiconductor devices by forming a highly electrically insulating oxide film layer inside the wafer. SOI wafers have a structure in which an oxide film and an active layer (SOI layer) are layered on a supporting substrate.

[0003] As disclosed in Patent Document 1, in a conventional SOI wafer manufacturing method, first, as shown in Fig. 6(a), a support substrate 51 and a first active layer substrate 52 are prepared. The peripheral edges of the support substrate 51 and the first active layer substrate 52 are chamfered. Next, as shown in Fig. 6(b), an oxide film 61 is formed on the surface of the support substrate 51 by heat treatment, and as shown in Fig. 6(c), the first active layer substrate 52 is placed on the support substrate 51 via the oxide film 61 and bonded by heat treatment. At this time, an oxide film is also formed on the surface of the first active layer substrate 52 as shown in Fig. 6(d).

[0004] Here, an unbonded area Ar1 is formed on the periphery of the bonding surface between the support substrate 51 and the first active layer substrate 52 due to the chamfering of the substrates. If such an unbonded area Ar1 exists, there is a risk that the wafer may chip or crack in the subsequent grinding / polishing process. Therefore, the periphery of the first active layer substrate 52 is chamfered as shown in FIG. 6(e), and the remaining residue 53 is removed by etching as shown in FIG. 6(f). As a result, a step (terrace 54) is formed on the periphery of the support substrate 51. Finally, as shown in FIG. 6( g ), the upper surface of the first active layer substrate 52 is ground and polished to adjust the thickness, thereby producing an SOI wafer 50 .

[0005] Furthermore, as a material suitable for more highly integrated devices, there is a multilayer SOI wafer having a structure in which at least a first oxide film, a first active layer, a second oxide film, and a second active layer are laminated in this order on a supporting substrate.

[0006] In the method for producing this multi-layer SOI wafer, as shown in FIG. 7(a), the SOI wafer 50 formed in FIG. 6(g) and a second active layer substrate 70 are prepared. Next, as shown in Fig. 7(b), an oxide film 62 is formed on the surface of the SOI wafer 50 by heat treatment, and as shown in Fig. 7(c), a second active layer substrate 70 is placed on the first active layer substrate 52 via the oxide film 62 and bonded by heat treatment. At this time, an oxide film is also formed on the surface of the second active layer substrate 70 as shown in Fig. 7(d).

[0007] Here, an unsupported area Ar2 is formed on the peripheral portion of the bonding surface between the first active layer substrate 52 and the second active layer substrate 70 due to the difference in substrate diameter. If such an unsupported area Ar2 exists, there is a risk that the wafer will chip or crack in a later process. Therefore, as shown in FIG. 7(e), the peripheral portion of the second active layer substrate 70 is chamfered, and further, as shown in FIG. 7(f), the remaining residue portion 71 is removed by etching. As a result, a step (terrace 55) is also formed on the peripheral portion of the first active layer substrate 52. Finally, as shown in FIG. 7( g ), the upper surface of the second active layer substrate 70 is ground and polished to adjust the thickness, thereby producing a multilayer SOI wafer 80 . [Prior art documents] [Patent documents]

[0008] [Patent Document 1] JP 2018-182146 A Summary of the Invention [Problem to be solved by the invention]

[0009] Incidentally, the multilayer SOI wafer 80 shown in FIG. 7(g) is manufactured by chamfering the peripheral portion each time to form a terrace portion (step) in order to remove unbonded areas Ar1 and unsupported areas Ar2 that occur on the peripheral portion when substrates are bonded together. In this case, however, the peripheral portion of the multilayer SOI wafer becomes stepped, which poses the problem that the effective area of ​​the active layer in the upper layer (top side) becomes smaller.

[0010] In addition, in a conventional multilayer SOI structure in which active layer substrates are stacked in order on a support substrate 51, each time an active layer substrate is stacked (bonded), the stacked active layer is polished on one side using a single-sided batch method to adjust the thickness. However, if the peripheral portion has terraces 54 and 55, the polishing pad sinks in the peripheral portion during polishing of the peripheral portion of the active layer, and a large load is concentrated on the peripheral portion. In this case, polishing is accelerated more in the peripheral portion than in the center of the substrate, resulting in a problem that the thickness of the substrate varies greatly between the center and the peripheral portion.

[0011] Furthermore, if there is variation in the thickness accuracy of the first (lower) active layer (first active layer substrate 52) that has been polished on one side, the oxide film layer above it will not be horizontal, but will have irregularities. In that case, when the surface of the second active layer (second active layer substrate 70) bonded on top of it is polished on one side, the load of the polishing pad will change due to the irregularities in the lower oxide film layer, which will affect the variation in thickness accuracy of the second active layer. In this way, the variation in thickness of the lower layer significantly affects the thickness accuracy of the upper layer, making it difficult to meet the required thickness accuracy.

[0012] Furthermore, if the terraces 54 and 55 are present, there is a risk that dust or particles may be generated therefrom, and in that case, there is a problem that the generated dust or particles may adhere to the wafer surface.

[0013] The present invention has been made under the above circumstances, and has an object to provide a method for manufacturing a multilayer SOI wafer, and a multilayer SOI wafer, which can ensure a wide effective area of ​​an active layer and minimize variations in in-plane thickness by providing a terrace-free structure with no steps at the periphery of the multilayer SOI wafer. [Means for solving the problem]

[0014] The method for manufacturing a multilayer SOI wafer according to the present invention, which has been made to solve the above-mentioned problems, is a method for manufacturing a multilayer SOI wafer in which an element-side substrate is stacked on a support substrate via an oxide layer, and the element-side substrate is a plurality of active layer substrates stacked on each other via an oxide layer, and is characterized in that it includes the steps of: polishing both sides of a plurality of silicon wafers to form the plurality of active layer substrates; forming an oxide layer on a surface of at least one of the plurality of active layer substrates that are to be bonded to each other among the plurality of active layer substrates; stacking the plurality of active layer substrates via the oxide layer to form the element-side substrate; polishing both sides of the element-side substrate; polishing a silicon wafer to form the support substrate and forming an oxide layer on the surface of the support substrate; and bonding one surface of the element-side substrate to the support substrate via the oxide layer formed on the support substrate.

[0015] In addition, after the step of bonding one surface of the element side substrate to a support substrate via an oxide film layer formed on the support substrate, it is desirable to include a step of polishing the top side active layer substrate of the element side substrate by single-sided polishing and adjusting the thickness of the top side active layer substrate. In addition, it is preferable to perform a step of polishing the top-side active layer substrate in the element-side substrate and, prior to the step of adjusting the thickness of the top-side active layer substrate, to perform peripheral grinding until no unbonded area is left in the peripheral portion of the wafer, and then to chamfer the peripheral portion of the wafer. It is also preferable that no oxide film is formed on the active layer substrate on the bottom side of the element substrate, and that a multi-layer SOI wafer in which two active layers are stacked is manufactured.

[0016] By configuring it in this manner, the active layer substrate that will be the intermediate layer, excluding the active layer substrate that is the top layer, is subjected to final thickness adjustment by double-sided polishing (DSP) before bonding, making it possible to significantly reduce thickness variation in the wafer after bonding compared to conventional methods. Furthermore, in the past, for example, when a support substrate and an active layer substrate serving as an intermediate layer were bonded, an unbonded region was generated on the periphery of the bonding surface, and there was a risk of the unbonded region cracking when the active layer substrate was subsequently ground / polished to adjust the thickness. For this reason, in the past, the unbonded region was chamfered to form a terrace portion (step portion), and then the active layer substrate was ground / polished. In this case, the effective area of ​​the upper active layer substrate is reduced, but in this embodiment, the thickness of the intermediate active layer substrate is adjusted by double-sided polishing before bonding the substrates, so that chamfering of the unbonded area is not required each time. As a result, the effective area of ​​all active layers can be secured to be large, and a terrace-free multilayer SOI wafer can be formed without forming steps on the periphery.

[0017] Further, the multilayer SOI wafer according to the present invention, which has been made to solve the above-mentioned problems, is a multilayer SOI wafer in which an element side substrate is laminated on a support substrate via an oxide layer, and the element side substrate has a plurality of active layer substrates formed of a plurality of silicon wafers each polished on both sides, and a plurality of oxide layer layers respectively formed between the plurality of active layer substrates, and the double-sided polished element side substrate is laminated on the support substrate via the oxide layer, and the peripheral portion has a terrace-free shape without any steps.

[0018] In the multilayer SOI wafer thus constructed, the double-sided polishing of the element substrate makes it possible to suppress variations in the thickness of the wafer after bonding more remarkably than ever before, and the terrace-free shape with no steps at the periphery ensures a wide effective area for the active layer. Effect of the Invention

[0019] According to the present invention, it is possible to provide a method for manufacturing a terrace-free multilayer SOI wafer having no steps on the periphery and a multilayer SOI wafer in which the effective area of ​​the active layer is wider than that of a conventional multilayer SOI wafer and thickness variations are reduced. [Brief description of the drawings]

[0020] [Figure 1] FIG. 1 is a cross-sectional view showing a schematic view of a part of a multilayer SOI (Silicon on Insulator) wafer produced by a production method according to the present invention. [Diagram 2] FIG. 2 is a flow chart showing a method for manufacturing a multilayer SOI wafer according to the present invention. [Diagram 3] FIG. 3 is a transition diagram (cross-sectional view) corresponding to the flow of FIG. [Figure 4] FIG. 4 is a transition diagram (cross-sectional view) for manufacturing an SOI wafer having three active layers. [Diagram 5] FIG. 5 is a graph showing the results of the examples. [Figure 6] FIG. 6 is a state transition diagram showing a conventional method for manufacturing an SOI wafer. [Figure 7] FIG. 7 is a state transition diagram showing a conventional method for manufacturing a multilayer SOI wafer. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0021] Hereinafter, preferred embodiments of the present invention will be described with reference to the drawings. A multilayer SOI wafer manufactured by the manufacturing method according to the present invention has a plurality of active layers stacked with oxide films interposed therebetween, but in this embodiment, a multilayer SOI wafer having two active layers stacked thereon will be described as an example. FIG. 1 is a cross-sectional view showing a schematic view of a part of a multilayer SOI (Silicon on Insulator) wafer produced by a production method according to the present invention.

[0022] 1, the multilayer SOI wafer 1 has a support substrate 2, a first oxide film layer 3 formed on the support substrate 2, a first active layer 4 formed on the first oxide film layer 3, a second oxide film layer 5 formed on the first active layer 4, and a second active layer 6 formed on the second oxide film layer 5. In this embodiment, as shown in FIG. 1, the second active layer 6 is the uppermost top layer, and the first active layer 4 is the second layer (intermediate layer) underneath. The support substrate 2, the first active layer 4, and the second active layer 6 can be formed of a silicon wafer. Furthermore, any impurity may be added to this silicon wafer to make it n-type or p-type.

[0023] In addition, the edges of the multilayer SOI wafer 1 are chamfered to form a beveled surface 1a, giving it a terrace-free shape with no unbonded areas or steps between the substrates. This terrace-free structure not only ensures a wide effective area for the active layer, but also suppresses the generation and adhesion of dust and particles from the edges.

[0024] Here, the thickness of the support substrate 2 is, for example, 250 μm or more and 600 μm or less, the thickness of the first oxide film layer 3 is 0.2 μm or more and 2.0 μm or less, the thickness of the first active layer 4 is 3.0 μm or more and 300 μm or less, the thickness of the second oxide film layer 5 is 0.2 μm or more and 2.0 μm or less, and the thickness of the second active layer 6 is 3.0 μm or more and 300 μm or less.

[0025] Next, a process for manufacturing such a multilayer SOI wafer 1 will be described with reference to Fig. 2 and Fig. 3. Fig. 2 is a flow chart showing a process for manufacturing the multilayer SOI wafer 1, and Fig. 3 is a transition diagram (cross-sectional view) corresponding to the flow chart of Fig. 2.

[0026] (Formation of the second active layer substrate (top layer)) 2 and 3, a silicon wafer 60 is prepared, and then, as shown in step S2, a grinder (GD) is used to grind the wafer in the thickness direction, and then both sides of the wafer are double-side polished (DSP: Double Side Polish) to form a second active layer substrate 61 (which will eventually become the second active layer 6) having a desired thickness (e.g., 550 μm). By performing double-side polishing in this manner, a second active layer substrate 61 with small thickness variation can be obtained. Also, as shown in step S3, a second oxide film layer 5 having a thickness of 0.2 μm or more and 2.0 μm or less is formed on the upper and lower surfaces of the second active layer substrate 61 by heat treatment.

[0027] (Formation of the first active layer substrate (second layer)) Meanwhile, as shown in step S4, a silicon wafer 40 is prepared, and as shown in step S5, the upper or lower surface is ground in the thickness direction using a grinder (GD), and then both sides of the wafer are double-sided polished (DSP) to form a first active layer substrate 41 (which will eventually become the first active layer 4) of a desired thickness (e.g., 400 μm). By performing double-sided polishing in this manner, a first active layer substrate 41 with small thickness variation is obtained. Here, in order to suppress the thickness variation of the first active layer 4 shown in FIG. 1 with high accuracy, it is preferable not to perform an oxide film peeling process, and therefore an oxide film is not formed on the upper and lower surfaces of the first active layer substrate 41. The order in which steps S1 to S3 and steps S4 and S5 are carried out may be in any order.

[0028] (Formation of element side substrate) 2 and 3, the first active layer substrate 41 formed in step S5 is bonded onto the second active layer substrate 61 formed in step S3 via the second oxide film 5. This bonding is performed via a silicon oxide film of several tens of nm formed by annealing treatment.

[0029] As shown in step S7, this is ground in the thickness direction using a grinder (GD), and then both sides of the wafer are polished (DSP) while adjusting the thickness. As a result, the second oxide film layer 5 on the lower surface side of the second active layer substrate 61 is removed as shown in step S7 of Fig. 3, and an element-side substrate 10 with reduced thickness variation is obtained. This element-side substrate 10 is formed by bonding the second active layer substrate 61 and the first active layer substrate 41 together via the second oxide film 5. 1, the second active layer 6 is the uppermost top layer and the first active layer 4 is the second layer below it, so that the thickness of the first active layer 4 (first active layer substrate 41), which is the intermediate layer, is controlled by double-sided polishing in step S7. As described above, in this embodiment, the element-side substrate 10 has two active layer substrates (first active layer substrate 41, second active layer substrate 61) without an oxide film being formed on the bottom active layer substrate (first active layer substrate 41).

[0030] (Formation of Support Substrate) 2 and 3, a silicon wafer 20 is prepared, and after grinding in the thickness direction using a grinder (GD) as shown in step S9, the wafer surface is mirror polished (ML) with extremely fine abrasive grains to form a support substrate 21 (which will eventually become the support substrate 2) of a desired thickness as shown in step S9. In addition, a first oxide film layer 3 having a thickness of 0.2 μm or more and 2.0 μm or less is formed on the upper and lower surfaces of the support substrate 21 as shown in step S10. It should be noted that the order in which steps S6, S7 and steps S8 to S10 are carried out may be in any order.

[0031] (Formation of multi-layer SOI wafers) 2 and 3, the element-side substrate 10 is bonded onto the support substrate 21 formed in step S10. Here, the first active layer substrate 41 (first active layer 4) is bonded onto the support substrate 21 via the first oxide film layer 3. This bonding is performed via a silicon oxide film of several tens of nm formed by annealing treatment.

[0032] As shown in step S12, the outer periphery of the multilayer SOI wafer 1 in which the support substrate 21 and the element substrate 10 are bonded is ground using a grinder (GD) (hereinafter, also referred to as "outer periphery grinding"). This outer periphery grinding is performed until at least the unbonded regions occurring in the peripheral parts of the bonding surfaces between the support substrate 21 and the element substrate 10, and between the first active layer substrate 10 and the second active layer substrate 61, disappear. As a result, a multilayer SOI wafer 1 without unbonded regions is formed. Next, the first oxide film layer 3 on the lower surface side is removed by hydrofluoric acid treatment, and if required, sandblasting is performed by spraying fine granular abrasive material onto the back surface of the wafer to form a support substrate 2 with a matte lower surface.

[0033] Finally, as shown in step 13, the peripheral edge of the wafer is chamfered to form a bevel surface 1a on the multilayer SOI wafer 1 from which the non-bonded region has been removed by peripheral grinding. Next, the surface of the second active layer substrate 61 is mirror-polished (ML) with extremely fine abrasive grains to form the second active layer 6, which is the top layer, to obtain the multilayer SOI wafer 1 with a terrace-free structure.

[0034] As described above, according to the embodiment of the present invention, the active layer substrate serving as the intermediate layer (the first active layer substrate 41 in this embodiment), excluding the active layer substrate serving as the top layer (the second active layer substrate 61 in this embodiment), is subjected to final thickness adjustment by double-sided polishing (DSP) before bonding, so that the thickness variation of the wafer after bonding can be suppressed significantly more than in the past. Furthermore, in the past, for example, when a support substrate and an active layer substrate serving as an intermediate layer were bonded, an unbonded region was generated on the periphery of the bonding surface, and there was a risk of the unbonded region cracking when the active layer substrate was subsequently ground / polished to adjust the thickness. For this reason, in the past, the unbonded region was chamfered to form a terrace portion (step portion), and then the active layer substrate was ground / polished. In this case, the effective area of ​​the upper active layer substrate is reduced, but in this embodiment, the thickness of the intermediate active layer substrate is adjusted by double-sided polishing before bonding the substrates, so that chamfering of the unbonded area is not required each time. As a result, the effective area of ​​all active layers can be secured to be large, and a terrace-free multilayer SOI wafer can be formed without forming steps on the periphery.

[0035] In the above embodiment, a multi-layer SOI wafer having two active layers has been described as an example, but the present invention is not limited thereto and can be applied to a multi-layer SOI wafer having three or more active layers. For example, when three active layers are stacked, a multi-layer SOI wafer can be manufactured according to the state transition diagram shown in FIG.

[0036] In this case, the process up to step S7 in FIG. 3 (creation of the first and second active layer substrates) is the same as the process for manufacturing a multilayer SOI wafer having two active layers, so a description of the process up to step S7 will be omitted. 3 and 4, a substrate is manufactured in which the second active layer substrate 61 and the first active layer substrate 41 are bonded to each other via the second oxide film 5, and then a silicon wafer 90 is prepared as in step St1 of Fig. 4. Then, as shown in step St2, the wafer is ground in the thickness direction using a grinder (GD), and then both sides of the wafer are double-side polished (DSP: Double Side Polish) to form a third active layer substrate 91 (which will eventually become the third active layer 9) of a desired thickness (e.g., 550 µm). By performing double-side polishing in this manner, a third active layer substrate 91 with small thickness variation is obtained. Also, as shown in step St3, a third oxide film layer 7 having a thickness of 0.2 μm or more and 2.0 μm or less is formed on the upper and lower surfaces of the third active layer substrate 91 by heat treatment.

[0037] (Formation of element side substrate) 4, the third active layer substrate 91 formed in step St3 is bonded onto the first active layer substrate 41 of the substrate formed in step S7 (in FIGS. 3 and 4) via the third oxide film 7. This bonding is performed via a silicon oxide film of several tens of nanometers formed by annealing treatment.

[0038] This is ground in the thickness direction using a grinder (GD), and then both sides of the wafer are polished (DSP) while adjusting the thickness. As a result, the third oxide film layer 7 on the upper surface side of the second active layer substrate 61 is removed as shown in step St5 of Fig. 4, and an element-side substrate 11 with reduced thickness variation is obtained. This element-side substrate 11 is formed by bonding the second active layer substrate 61 and the first active layer substrate 41 to each other via the second oxide film 5, and bonding the second active layer substrate 61 and the third active layer substrate 91 to each other via the third oxide film 7.

[0039] (Formation of Support Substrate) 4, a silicon wafer 20 is prepared, and then ground in the thickness direction using a grinder (GD) as shown in step St7, and the wafer surface is mirror-polished (ML) with very fine abrasive grains to form a support substrate 21 (which will eventually become the support substrate 2) of a desired thickness as shown in step St7. In addition, a first oxide film layer 3 having a thickness of 0.2 μm or more and 2.0 μm or less is formed on the upper and lower surfaces of the support substrate 21 as shown in step St8.

[0040] (Formation of multi-layer SOI wafers) 4, the element-side substrate 11 is bonded onto the support substrate 21 formed in step St8. Here, the first active layer substrate 41 (first active layer 4) is bonded onto the support substrate 21 via the first oxide film layer 3. This bonding is performed via a silicon oxide film of several tens of nanometers formed by annealing treatment.

[0041] As shown in step St10, the outer periphery of the multilayer SOI wafer 1 in which the support substrate 21 and the element substrate 11 are bonded is ground using a grinder (GD). This outer periphery grinding is performed until at least the unbonded regions occurring in the peripheral portions of the bonding surfaces of the support substrate 21 and the element substrate 11, and the first, second, and third active layer substrates, disappear. As a result, a multilayer SOI wafer 1 without unbonded regions is formed. Next, the first oxide film layer 3 on the lower surface side is removed by hydrofluoric acid treatment, and if required, sandblasting is performed by spraying fine granular abrasive material onto the back surface of the wafer to form a support substrate 2 with a matte lower surface.

[0042] Finally, as shown in step St11, the peripheral edge of the wafer is chamfered to form a bevel surface 1a, and then the surface of the second active layer substrate 61 is mirror-polished (ML) with very fine abrasive grains to form a third active layer 9, which is a top layer. This results in a multilayer SOI wafer 1 with a terrace-free structure having three active layers. EXAMPLES

[0043] The method for manufacturing a multilayer SOI wafer according to the present invention will be further described with reference to an example. In this example, the following experiment was carried out based on the above-described embodiment.

[0044] Example 1 In Example 1, after both sides of the first active layer substrate (second active layer) and the second active layer substrate (top active layer substrate) were polished, an oxide film having a thickness of 1.0 μm was formed on the surface of the second active layer substrate, and the first active layer substrate and the second active layer substrate were bonded through the oxide film to prepare an element-side substrate. The element-side substrate was then polished on both sides until the first active layer substrate had a desired thickness (for example, 75 μm), and the thickness of the first active layer substrate was measured. Then, the element-side substrate was bonded to a support substrate on which an oxide film was formed, and the above-mentioned peripheral grinding, grinding, and chamfering were performed to produce a multilayer SOI wafer with a terrace-free structure. Thereafter, one side of the surface of the second active layer substrate was polished, and the thickness of the second active layer substrate was adjusted until the desired thickness (for example, 50 μm) was obtained. The thickness variation of the first active layer substrate, which is the second active layer of this multi-layer SOI wafer, was measured using a Fourier transform infrared spectrophotometer (FTIR). The graph in Figure 5 shows, in box plot form, the results of the thickness variation in Example 1. In Figure 5, the vertical axis represents the thickness variation (µm).

[0045] Comparative Example 1 In Comparative Example 1, a first active layer substrate (second active layer) was bonded onto a supporting substrate via an oxide film, and the peripheral portion was chamfered to form a terrace portion, after which the thickness was adjusted by polishing one side. Furthermore, a second active layer substrate (top active layer) was bonded via an oxide film, and after chamfering to form a terrace portion, the thickness was adjusted by one-sided polishing to produce a multilayer SOI wafer. The thickness variation of the first active layer substrate, which is the second active layer of this multi-layer SOI wafer, was measured using a Fourier transform infrared spectrophotometer (FTIR). The graph in Fig. 5 shows the results of thickness variation in Comparative Example 1 together with Example 1. In Fig. 5, the vertical axis represents thickness variation (µm).

[0046] 5, the thickness variation of the first active layer (second active layer) could be suppressed to a small value in Example 1, but the thickness variation of the first active layer (second active layer) became larger in Comparative Example 1. From this result, the effect of the present invention could be confirmed. [Explanation of symbols]

[0047] 1. Multi-layer SOI wafer 2 Support substrate 3 First oxide layer 4. First active layer (first active layer substrate) 5 Second oxide layer 6 Second active layer (second active layer substrate) 10. Element side substrate

Claims

1. A method for manufacturing a multilayer SOI wafer, comprising: a device-side substrate laminated on a support substrate via an oxide film layer; and the device-side substrate is a plurality of active layer substrates laminated on each other via an oxide film layer, the method comprising: polishing a plurality of silicon wafers on both sides to form the plurality of active layer substrates; forming an oxide film layer on a surface of at least one of the active layer substrates that are bonded to each other among the plurality of active layer substrates; forming the element-side substrate by stacking the plurality of active layer substrates with the oxide film layer interposed therebetween; polishing the element substrate on both sides; polishing a silicon wafer to form the support substrate, and forming an oxide layer on a surface of the support substrate; bonding one surface of the element substrate to a supporting substrate via an oxide film layer formed on the supporting substrate; A method for producing a multilayer SOI wafer, comprising:

2. After bonding one surface of the element substrate to a support substrate via an oxide film layer formed on the support substrate, 2. The method for manufacturing a multilayer SOI wafer according to claim 1, further comprising a step of polishing a top-side active layer substrate in the element-side substrate by single-sided polishing to adjust a thickness of the top-side active layer substrate.

3. Prior to a step of polishing a top-side active layer substrate in the element-side substrate and adjusting a thickness of the top-side active layer substrate, 3. A method for producing a multilayer SOI wafer according to claim 2, further comprising the steps of: grinding the peripheral edge of the wafer until all unbonded areas at the peripheral edge of the wafer are removed; and then chamfering the peripheral edge of the wafer.

4. 2. The method for manufacturing a multilayer SOI wafer according to claim 1, wherein no oxide film is formed on the active layer substrate on the bottom side of the element side substrate, and a multilayer SOI wafer in which two active layers are stacked is manufactured.

5. A multilayer SOI wafer in which an element-side substrate is laminated on a support substrate via an oxide film layer, The element side substrate is A plurality of active layer substrates each formed of a plurality of silicon wafers each polished on both sides, and a plurality of oxide film layers respectively formed between the plurality of active layer substrates, A multilayer SOI wafer, characterized in that the element side substrate, which has been polished on both sides, is laminated on the support substrate via an oxide film layer, and the peripheral portion has a terrace-free shape with no steps.

Images