Wiring board

Abstract

To reduce the stray capacitance that occurs between the side of a land and the side of a solid pattern.SOLUTION: A wiring board according to the present disclosure is a wiring board having a first conductive layer, an insulating layer covering the first conductive layer, a second conductive layer formed on the insulating layer, and a via conductor that penetrates the insulating layer and connects the first conductive layer and the second conductive layer, and the first conductive layer is provided with a pad connected to the via conductor and a solid pattern having an opening that contains the pad, and a gap is provided between the side of the pad and the insulating layer, or between the inner side of the opening of the solid pattern and the insulating layer.SELECTED DRAWING: Figure 3

Description

[Technical field]

[0001] The present disclosure relates to a wiring board in which conductive layers are connected to each other by via conductors. [Background technology]

[0002] Conventionally, as this type of wiring board, there is known one in which the lands of via conductors connecting conductive layers are surrounded by a solid pattern (see, for example, Patent Document 1). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2017-11093 A (Fig. 1, etc.) Summary of the Invention [Problem to be solved by the invention]

[0004] In the above-mentioned conventional wiring board, it is required to reduce the stray capacitance generated between the side surface of the land and the side surface of the solid pattern. [Means for solving the problem]

[0005] The wiring board of the present disclosure is a wiring board having a first conductive layer, an insulating layer covering the first conductive layer, a second conductive layer formed on the insulating layer, and a via conductor penetrating the insulating layer and connecting the first conductive layer and the second conductive layer, wherein the first conductive layer is provided with a pad connected to the via conductor and a solid pattern having an opening that contains the pad, and a gap is provided between a side of the pad and the insulating layer, or between an inner side of the opening of the solid pattern and the insulating layer. [Brief description of the drawings]

[0006] [Figure 1] FIG. 1 is a cross-sectional side view of a wiring board according to an embodiment of the present disclosure. [Diagram 2]Cross-sectional view of the via land area [Diagram 3] Side cross section of the via land [Figure 4] 1 is a side cross-sectional view showing a method for manufacturing a wiring board. [Diagram 5] 1 is a side cross-sectional view showing a method for manufacturing a wiring board. [Figure 6] 1 is a side cross-sectional view showing a method for manufacturing a wiring board. [Figure 7] 1 is a side cross-sectional view showing a method for manufacturing a wiring board. [Figure 8] 1 is a side cross-sectional view showing a method for manufacturing a wiring board. [Figure 9] FIG. 13 is a cross-sectional side view of a wiring board according to a modified example. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0007] Hereinafter, one embodiment of the present disclosure will be described with reference to Figures 1 to 8. As shown in Figure 1, a wiring board 10 of this embodiment has a core substrate 11 and first and second buildup layers 12A, 12B laminated on both the front and back surfaces (first surface 11F and second surface 11S) of the core substrate 11.

[0008] The core substrate 11 includes, for example, an insulating layer 11K and conductive layers 13 laminated on both sides of the insulating layer 11K. The insulating layer 11K has a structure in which, for example, a plurality of prepregs (B-stage resin sheets made by impregnating a core material made of fibers such as glass cloth with resin) are laminated. In addition, the insulating layer 11K has a through-hole conductor 14 formed therein.

[0009] The first and second buildup layers 12A and 12B are formed by alternately laminating insulating layers 15 and conductive layers 16. In detail, a first insulating layer 15A, a first conductive layer 16A, a second insulating layer 15B, a second conductive layer 16B, a third insulating layer 15C, and a third conductive layer 16C are laminated in this order from the core substrate 11 side. Each insulating layer 15 is, for example, an insulating film for a buildup substrate (a film having no core material and made of, for example, a thermosetting resin containing an inorganic filler), and the conductive layer 16 is mainly electrolytic plating. In addition, the first to third insulating layers 15A to 15C are formed with via conductors 19 that respectively connect the conductive layer 13 of the core substrate 11 and the first conductive layer 16A, the first conductive layer 16A and the second conductive layer 16B, and the second conductive layer 16B and the third conductive layer 16C. In this embodiment, the first and second buildup layers 12A and 12B have the same number of layers, but may have different numbers of layers.

[0010] A solder resist layer 17 having a plurality of openings 17A corresponding to the plurality of pads 18 included in the third conductive layer 16C is laminated on the first and second buildup layers 12A, 12B.

[0011] In the wiring board 10 of this embodiment, each conductive layer 16 has a via land 20 (also called a "pad 20") connected through a via conductor 19 and a through-hole conductor 14, and a solid pattern 21 surrounding the via land 20. The via land 20, the via conductor 19, and the through-hole conductor 14 of each conductive layer 16 are aligned in the vertical direction, and the pad 18 on the first buildup layer 12A side is electrically connected to the pad 18 on the second buildup layer 12B side. As shown in FIG. 2, the via land 20 has a circular shape in a plan view, and the solid pattern 21 has a circular opening 21A corresponding to the via land 20. The diameter of the opening 21A of the solid pattern 21 is 2 to 3 times the diameter of the via land 20, and the distance between the side surface of the via land 20 and the opening edge of the opening 21A of the solid pattern 21 is about 300 to 700 μm.

[0012] 3, the side surface of the via land 20 has a smaller roughness than the top surface of the via land 20. The insulating layer 15 is in close contact with the top surface of the via land 20, but is partially peeled off from the side surface of the via land 20, leaving a via land-side gap 25 between the side surface of the via land 20 and the insulating layer 15.

[0013] Similarly, the inner side surface of the opening 21A of the solid pattern 21 has a smaller roughness than the upper surface of the solid pattern 21. The insulating layer 15 is in close contact with the upper surface of the solid pattern 21, but is peeled off from the inner side surface of the opening 21A of the solid pattern 21, and a solid pattern-side gap 26 (see FIG. 2) is provided between the insulating layer 15 and the inner side surface of the opening 21A of the solid pattern 21.

[0014] The lateral length of the via land side void 25 and the solid pattern side void 26 is about 0.01 to 0.1 μm. Although the via land 20 and the solid pattern 21 in the first conductive layer 16A on the first buildup layer 12A side are illustrated in Fig. 2 and Fig. 3, the via land side void 25 is also arranged on the side surface of the via land 20 in the second conductive layer 16B on the first buildup layer 12A side. The via land side void 25 may be arranged on the side surface of all the via lands 20, or may be arranged on the side surface of only some of the via lands 20. A gap may be arranged between the via land 20 of the third conductive layer 16C and the solder resist layer 17.

[0015] 2, the via land side voids 25 and the solid pattern side voids 26 may be scattered, or may be disposed between the insulating layer 15 and the entire side surface of the via land 20 and the inner surface of the opening 21A of the solid pattern 21. The via land side voids 25 and the solid pattern side voids 26 may be scattered in the vertical direction.

[0016] Next, a method for manufacturing the wiring board 10 will be described.

[0017] (1) First, a copper-clad laminate 11Z is prepared in which copper foil 11C is laminated on both sides of an insulating layer 11K. As shown in FIG. 4(A), a laser is irradiated onto both sides of the copper-clad laminate 11Z to form through-holes 14H.

[0018] (2) By a subtractive process, conductive layers 13 including copper foil 11C are formed on both sides of insulating layer 11K, and through-hole conductors 14 are formed on the inner surfaces of through-holes 14H (see FIG. 4(B)). In this way, core substrate 11 is formed.

[0019] (3) Next, an insulating film for a build-up substrate is laminated as an insulating layer 15 on the conductive layers 13 on both the front and back sides of the core substrate 11, and then hot-pressed. At this time, the non-patterned portions of the conductive layers 13 are filled with the insulating film. As a result, insulating layers 15 (first insulating layers 15A) are formed on both the front and back sides of the core substrate 11.

[0020] 4(C), a laser is irradiated to form a tapered via hole 19H penetrating the insulating layer 15, and the inside of the via hole 19H is cleaned (dry desmear treatment). Next, an electroless plating treatment is performed to form an electroless plating film (not shown) on the insulating layer 15 and the inner surface of the via hole 19H.

[0021] (5) As shown in FIG. 5(A), a plating resist 33 having a predetermined pattern is formed on the electroless plating film.

[0022] (6) As shown in FIG. 5(B), an electrolytic plating process is performed, filling the via hole 19H with electrolytic plating to form the via conductor 19, and forming an electrolytic plating film 16M on the portion of the electroless plating film (not shown) on the first surface 11F side and the second surface 11S side that is exposed from the plating resist 33.

[0023] (7) As shown in Fig. 6(A), plating resist 33 is peeled off. Next, the electroless plating film below plating resist 33 is removed, and the remaining electroless plating film and electrolytic plating film 16M form conductive layer 16 (first conductive layer 16A). First conductive layer 16A is provided with via land 20 connected to via conductor 19 penetrating first insulating layer 15A, and solid pattern 21 surrounding via land 20.

[0024] 6(B), a protective film 35 is disposed between the via land 20 and the solid pattern 21, and then the surface of the first conductive layer 16A is roughened. As a result, the side surface of the via land 20 and the inner surface of the opening 21A of the solid pattern 21 are not roughened, but the upper surface of the via land 20 and the upper surface of the solid pattern 21 are roughened, so that the roughness of the side surface of the via land 20 and the inner surface of the opening 21A of the solid pattern 21 is smaller than the roughness of the upper surface of the via land 20 and the upper surface of the solid pattern 21.

[0025] (9) As shown in FIG. 7(A), the protective film 35 is removed.

[0026] (10) As shown in Fig. 7(B), an insulating film for a build-up board is laminated as an insulating layer 15 and is hot-pressed. At that time, the non-patterned portions of the conductive layer 16, including between the via lands 20 and the solid pattern 21, are filled with the insulating film. As a result, an insulating layer 15 (second insulating layer 15B) is formed on the first conductive layer 16A.

[0027] At this time, due to thermal shrinkage of the insulating film for the build-up board, the portion of the insulating layer 15 between the via land 20 and the solid pattern 21 is partially peeled off from the side surface of the via land 20, which has a relatively small degree of roughness, and from the inner surface of the opening 21A of the solid pattern 21. As a result, a via land side gap 25 and a solid pattern side gap 26 are formed between the side surface of the via land 20 and the insulating layer 15, and between the inner surface of the opening 21A of the solid pattern 21 and the insulating layer 15, respectively.

[0028] (11) The same steps as those (4) to (10) described above are repeated to form a second conductive layer 16B, a third insulating layer 15C, and a third conductive layer 16C, as shown in FIG.

[0029] (12) A solder resist layer 17 is laminated on the third conductive layer 16C. Next, openings 17A are formed in predetermined locations of the solder resist layer 17 by, for example, laser processing or photolithography processing. Then, pads 18 are formed in portions of the third conductive layer 16C that are exposed from the solder resist layer 17 by the openings 17A.

[0030] (13) A metal film is formed by laminating a nickel layer, a palladium layer, and a gold layer in this order on the pads 18. With the above steps, the wiring board 10 shown in FIG.

[0031] Next, the effects of the wiring board 10 and the manufacturing method thereof will be described. In the wiring board 10 of this embodiment, the via land 20 connected in the vertical direction through the via conductor 19 is surrounded by the solid pattern 21. Here, if stray capacitance occurs between the side surfaces of the via land 20 and the solid pattern 21, it is considered that high frequency signals will be affected.

[0032] In contrast, in the wiring board 10 of this embodiment, a via land side gap 25 is provided between the side surface of the via land 20 and the insulating layer 15, and the presence of air with a low dielectric constant reduces the generated stray capacitance. This also reduces the effect on high frequency signals.

[0033] Moreover, since solid pattern side gap 26 is provided between the inner side surface of opening 21A of solid pattern 21 and insulating layer 15, the generated stray capacitance can be further reduced.

[0034] Furthermore, by protecting the side surface of the via land 20 and the inner surface of the opening 21A of the solid pattern 21 during the roughening stage of the conductive layer 16, a via land side gap 25 and a solid pattern side gap 26 can be selectively generated between the side surfaces when the insulating film serving as the insulating layer 15 is hot-pressed, thereby suppressing the generation of unnecessary gaps (for example, the generation of a gap between the upper surface of the via land 20 and the insulating layer 15).

[0035] [Other embodiments] (1) In the above embodiment, the via land side voids 25 are formed by reducing the roughness of the side surface of the via land 20, but they may be formed, for example, by allowing the desmear liquid of the desmear treatment inside the via hole 19H to enter the via land side voids 25. In this case, it is considered that the via land side voids 25 are scattered on the upper surface and the side surface of the via land 20.

[0036] (2) The upper surface of the electrolytic plating film 16M may be roughened in the state shown in Fig. 5(B) where the plating resist 33 is arranged. In this case, too, a difference in roughness can be created between the side and upper surfaces of the via land 20. In this case, the process of forming the protective film 35 is not necessary, and the manufacturing process can be simplified. However, since a process of removing the electroless plating film (e.g., quick etching) is performed after roughening, it is necessary to set the roughness so that the roughness of the upper surface of the via land 20 will be small when roughening.

[0037] 9, multiple via lands 20 may be arranged within opening 21A of solid pattern 21, and multiple wirings may be arranged in conductive layer 16. In this case, if the distance between the via lands 20 or between the wirings is narrower than the distance between the side of the via land 20 and the inner side of opening 21A of solid pattern 21, the volume of the resin of insulating layer 15 arranged between the via lands 20 and between the wirings is small, and peeling due to thermal shrinkage is unlikely to occur.

[0038] (4) The wiring board 10 may have a coreless structure.

[0039] (5) Only one of the via land side gap 25 and the solid pattern side gap 26 may be provided.

[0040] In addition, although this specification and drawings disclose specific examples of the technology included in the scope of the claims, the technology described in the claims is not limited to these specific examples, but includes various modifications and variations of the specific examples, as well as parts of the specific examples taken alone. [Explanation of symbols]

[0041] 10 Wiring board 15 Insulating layer 15A First Insulation Layer 15B Second insulating layer 16 Conductive layer 16A First Conductive Layer 16B Second conductive layer 19 Via conductor 20. Beerland 21 Solid Pattern 21A opening 25 Via land side gap 26 Solid pattern side gap 35 Protective film

Claims

1. A first conductive layer; an insulating layer covering the first conductive layer; a second conductive layer formed on the insulating layer; a via conductor penetrating the insulating layer and connecting the first conductive layer and the second conductive layer, the first conductive layer is provided with a pad connected to the via conductor and a solid pattern having an opening containing the pad; A gap is provided between a side surface of the pad and the insulating layer, or between an inner side surface of the opening of the solid pattern and the insulating layer.

2. 2. The wiring board according to claim 1, A gap is provided between a side surface of the pad and the insulating layer, and between an inner side surface of the opening of the solid pattern and the insulating layer.

3. 2. The wiring board according to claim 1, The roughness of the side surface of the pad is less than the roughness of the top surface of the pad.

4. 2. The wiring board according to claim 1, The voids are scattered at a plurality of locations.

5. 2. The wiring board according to claim 1, The maximum width of the gap is 0.01 to 0.1 μm.

6. 2. The wiring board according to claim 1, The distance between the side surface of the pad and the inner side surface of the opening of the solid pattern is 300 to 700 μm.

7. 2. The wiring board according to claim 1, The diameter of the opening in the solid pattern is two to three times the diameter of the pad.

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