Electronic apparatus

Abstract

To provide an electronic apparatus for use in an artificial neuron network by miniaturizing or reducing the power consumption of the electronic apparatus.SOLUTION: In an electronic apparatus, an artificial neural array 111 comprises a first circuit 10, a second circuit 11, and a plurality of wires. The first circuit includes a first transistor M1, a second transistor M2, and a capacitance element C1. The second circuit includes a third transistor M3. The gate of the first transistor is electrically connected to a first wire WW, a first terminal is electrically connected to a second wire WB, and the second terminal is electrically connected to the gate of the second transistor; the capacitance element capacitively couples a third wire DL and the gate of the second transistor. The first terminal of the second transistor is electrically connected to a fourth wire RB and the second terminal is electrically connected to a sixth wire VNN, and the gate of the third transistor is electrically connected to the third wire, the first terminal is electrically connected to a fifth wire RD, and the second terminal is electrically connected to the sixth wire. The first circuit stores the weight as an analog value. The first transistor is typically an oxide semiconductor transistor.SELECTED DRAWING: Figure 3

Description

[Technical field]

[0001] This application discloses, for example, an electronic device capable of storing an analog electrical potential. [Background technology]

[0002] As one type of machine learning, neural networks (also called artificial neural networks) When constructing a neural network, for example, analog circuits are used. Circuit configurations that incorporate this have been proposed (for example, Patent Documents 1 and 2). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 5-12466 [Patent Document 2] Japanese Patent Application Publication No. 6-187472 Summary of the Invention [Problem to be solved by the invention]

[0004] The problem is, for example, to provide a novel electronic device and method of operating the same. [Means for solving the problem]

[0005] One embodiment of the present invention includes a first circuit, a second circuit, and first to sixth wirings. The first circuit is The second circuit includes a first transistor, a second transistor, and a capacitance element. a gate of the first transistor electrically connected to a first wiring; The first terminal of the first transistor is electrically connected to the second wiring, and the second terminal of the first transistor is electrically connected to the second wiring. the first terminal of the capacitance element is electrically connected to the third wiring; The second terminal of the capacitance element is electrically connected to the gate of the second transistor. The first terminal of the third transistor is electrically connected to the fourth wiring, and the gate of the third transistor is electrically connected to the third wiring. a first terminal of the third transistor electrically connected to the fifth wiring, and a second terminal of the second transistor electrically connected to the fifth wiring. The second terminal of the third transistor is electrically connected to the sixth wiring, and the second terminal of the third transistor is electrically connected to the sixth wiring. It is an electronic device that is electrically connected to six wires.

[0006] The electronic device of the above embodiment is configured such that at least a current flowing through the fourth wiring and a current flowing through the fifth wiring are The second transistor may have a function of calculating a correction amount of the potential of the gate of the second transistor by using the second transistor. In the above embodiment, the channel formation region of the first transistor is preferably made of an oxide semiconductor. It may be formed of a body.

[0007] In this specification, when it is described that X and Y are connected, it is assumed that X and Y are connected by an electric field. There are three cases: when X and Y are electrically connected, when X and Y are functionally connected, and when X and Y are directly connected. The case where the signal is connected to the input terminals is also considered to be disclosed in the present specification. The connection relationships are not limited to those shown in the drawings or text, and may be changed without departing from the spirit or scope of the present invention. Anything other than the above connection relationship is also considered to be described in the drawing or text. X and Y are the object ( For example, a device, element, circuit, wiring, electrode, terminal, conductive film, layer, etc.

[0008] A transistor has three terminals called the gate, the source, and the drain. is a node that functions as a control node that controls the conductive state of the transistor. The two input / output nodes that function as drains or drains are determined by the type of transistor and the Depending on the level of the applied potential, one becomes the source and the other becomes the drain. In the specification, the terms source and drain may be used interchangeably. In addition, in this specification and the like, the two terminals other than the gate may be referred to as the first terminal and the second terminal. be.

[0009] Depending on the circuit configuration and device structure, a node may be a terminal, a wiring, an electrode, a conductive layer, a conductor, or an insulator. In addition, terminals, wiring, etc. can be called nodes. It is possible.

[0010] A voltage is the potential between a certain potential and a reference potential (e.g., ground potential (GND) or source potential). In many cases, it refers to the difference between the voltage and the potential. The potential is relative. Therefore, even if it is written as GND, it does not necessarily mean 0V. In some cases this is not the case.

[0011] In this specification, ordinal numbers such as "first," "second," and "third" are used to indicate order. In some cases, the term "common" is used to avoid confusion between components. In this case, the use of ordinal numbers does not limit the number of components, nor does it limit the order. In addition, for example, "first" can be replaced with "second" or "third" to describe one aspect of the invention. It can be clarified.

[0012] Other matters related to the description of this specification etc. are noted in the fifth embodiment. Effect of the Invention

[0013] According to one aspect of the present invention, a novel electronic device or a method of operating a novel electronic device is provided. According to one aspect of the present invention, it is possible to provide a miniaturized electronic device. For example, one embodiment of the present invention is a computer for machine learning. The present invention can be applied to a weighting system. It is an electronic device that takes analog values ​​as input and stores those analog values.

[0014] The description of a plurality of effects does not preclude the existence of other effects. It is not necessary to have all of the effects exemplified above. Other problems, advantages, and novel structures will become apparent from the description and drawings of this specification. This will become clear. [Brief description of the drawings]

[0015] [Figure 1] FIG. 1 is a block diagram showing an example of the configuration of an electronic device. [Diagram 2] FIG. 1 is a block diagram showing an example of the configuration of an electronic device. [Diagram 3] A: Circuit diagram showing an example of the configuration of an artificial neural array (ANA). B: Circuit diagram showing an example of the configuration of the circuits contained in an ANA. [Figure 4] FIG. 2 is a circuit diagram showing a configuration example of a memory cell. [Diagram 5] 1A is a block diagram showing an example of the configuration of an electronic device, and B is a circuit diagram showing an example of the configuration of a wiring switch. [Figure 6] 1A is a flowchart showing an example of a method for manufacturing an electronic component, and B is a schematic perspective view showing an example of the configuration of an electronic component. [Figure 7] AH: A diagram showing an example of the configuration of an electronic device. [Figure 8] 8A, B, C, and D show a cross-sectional view of a transistor shown in FIG. 8A along line A1-A2 and line A3-A4, respectively. [Figure 9] A: Enlarged view of a portion of Fig. 8B. B: Energy band diagram of the transistor. [Figure 10]10A, B, C, and D show a cross-sectional view of a transistor taken along line A1-A2 and line A3-A4 in FIG. 10A. [Figure 11] 11A, B, C, and D show a cross-sectional view of a transistor shown in FIG. 11A along line A1-A2 and A3-A4, respectively. [Figure 12] A: A top view showing an example of the configuration of a transistor, B: A cross-sectional view taken along line A1-A2 in Fig. 12A, C: A cross-sectional view taken along line A3-A4 in Fig. 12A, and D: A partially enlarged view of Fig. 12B. [Figure 13] A: A top view showing an example of the configuration of a transistor, B: A cross-sectional view taken along line y1-y2 in Fig. 13A, C: A cross-sectional view taken along line x1-x2 in Fig. 13A, and D: A cross-sectional view taken along line x3-x4 in Fig. 13A. [Figure 14] 1A and 1B are cross-sectional views showing an example of the configuration of an electronic device. [Figure 15] 1A to 1C are cross-sectional views showing examples of the structure of a transistor. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0016] Hereinafter, an embodiment of the present invention will be described. However, one embodiment of the present invention is not limited to the following description. The present invention is not limited to the above embodiment, and the mode and details of the present invention may be modified in various ways without departing from the spirit and scope of the present invention. It will be readily understood by those skilled in the art that the above-mentioned features are not necessarily essential to the present invention. The present invention should not be construed as being limited to the description of the embodiments.

[0017] The following embodiments can be combined as appropriate. In the case where a plurality of configuration examples (including manufacturing method examples, operation method examples, etc.) are shown in the form, The configuration examples may be appropriately combined, and one or more configuration examples described in other embodiments may be combined. Appropriate combinations are also possible.

[0018] In the drawings, elements that are the same or have similar functions, elements that are made of the same material, or elements that are the same In some cases, the same reference numerals may be used to denote elements formed at the same time, and repeated explanations thereof will be omitted. There are cases.

[0019] Also, when there are multiple elements with the same code and it is necessary to distinguish between them, The code is written with identification codes such as "[1]", "_1", "_2", "[i, j]" etc. For example, to distinguish between multiple wirings WL, the address number (row number) The wiring WL in the second row may be written as wiring WL[2] by using the wiring number WL[1]. When the rows and columns are not the subject of the calculation, only the wiring WL is written.

[0020] In this specification, for example, the high power supply potential VDD is abbreviated to potential VDD, VDD, etc. This may be due to the presence of other components (e.g., signals, voltages, circuits, elements, electrodes, wiring, etc.). The same applies to (etc.).

[0021] [First embodiment] A neural network is an information processing system modeled on a neural network. One model of neural network is a hierarchical network in which artificial neurons are layered. The network structure is as follows: an artificial neuron receives multiple inputs and generates one or more The artificial neuron generates an output corresponding to the signal transmission efficiency of the synapse for each input node. The weights that correspond to the signal and the threshold value that corresponds to the membrane potential of the nerve cell are set. By doing this, we obtain an output value of 1 from multiple input signals. Typically, in an artificial neuron, The sum of the products of all input values ​​and the weights (weighted sum, or sum of products) is calculated, and the threshold is calculated from the weighted sum. The value obtained by subtracting 1 from 1 is calculated, and the transfer function (e.g., step function or sigmoido) that uses this value as input is The output value is determined by the input function of the next layer of artificial neurons. In supervised learning, the output value is compared with the teacher signal, and the weight correction amount is calculated based on the error. The calculation is performed by modifying the weights, or in some cases modifying both the weights and the thresholds.

[0022] The input signal value of an artificial neuron is not a discrete value (digital value) of "0" or "1", It is desirable to have a continuous value (analog value). Therefore, the input signal of the artificial neuron is converted into an analog value. In the artificial neuron, the input signal is processed as an analog signal. It is efficient. For example, when an artificial neuron is a digital processing circuit, it is possible to reduce certain weights. (This is equivalent to weakening the synaptic connections of other nerve cells.) When a local solution is reached, in order to escape from the local solution and converge to the correct solution, This requires complex circuits, which increases the size of electronic devices and increases power consumption. It also leads to.

[0023] In addition, the storage means for storing analog values ​​(weights, threshold values) is SRAM (static RAM). Dynamic Random Access Memory (DRAM) It is possible to use memory such as a DDR3 memory or a flash memory, but the following problems arise: When using SRAM, an analog-to-digital converter is used to convert analog values ​​to digital values. A digital converter is required. It is difficult to control the writing of analog values ​​in flash memory. There is also a limit to the number of times it can be rewritten. DRAM has no limit to the number of times it can be rewritten, Maintaining analog values ​​requires frequent refreshing, which increases power consumption. In addition, if the storage capacitance is increased to reduce the effect of charge leakage from the storage capacitance, the write This increases the power consumption of the embedded circuit.

[0024] In this embodiment, an electronic device that can be applied to a computing system for machine learning Typically, weights and thresholds are stored as analog values ​​in a digital memory. 1 is a block diagram showing an example of the configuration of an electronic device.

[0025] <<Electronic equipment>> The electronic device 100 shown in FIG. 1 includes an artificial neural array (ANA) 111, a row decoder 11 2, column decoder 113, input circuit 114, output circuit 115, analog signal processing circuit 116 , and a memory 130. The electronic device 100 may be referred to as an artificial neural network device, It may also be called a neural network.

[0026] ANA111 includes a plurality of circuits 10 and 11, a plurality of wirings WW, WB, DL, RB, and one The circuit 10 is arranged in an array of n rows and m columns. The array is arranged in rows and columns, where n is an integer greater than 1 and m is an integer less than 0. In accordance with the arrangement of the circuit 10, n wires WW, DL and m wires Wires WB and RB are provided. Circuit 10[i,j] (i is greater than 1 and less than or equal to n) j is an integer greater than 0 and less than or equal to m.) is the wiring WW[i], WB[ The circuit 11[j] is electrically connected to the wiring DL[j], DL[i], and RB[j]. , RD. Circuit 10 is a basic unit of an artificial neural network. This is an artificial neuron.

[0027] The row decoder 112 is electrically connected to n wires WW, and the column decoder 113 is electrically connected to m wires WW. The row decoder 112 and the column decoder 113 are electrically connected to the wiring WB. is a peripheral circuit for writing weights or thresholds to

[0028] The data DIN is the input data to be processed by the ANA 111. Here, the data DIN is It is an analog voltage signal, and the voltage value of data DIN corresponds to the input value to ANA111. The data DIN is written to the ANA 111 by the input circuit 114. To 14, n wirings DL are electrically connected.

[0029] In addition, in the electronic device 100, for example, the wirings DL[1] to DL[n-1] are each Input data and input analog data according to the threshold value to wiring DL[n]. Alternatively, the threshold value may be subtracted from the weighted sum. In order to do this, the circuits 10[n,1] to 10[n,m] that hold the threshold values ​​are The circuit configuration may be different from that of the circuits in the rows to n-1. Data is input to each of the wirings DL[n] to DL[n], and a threshold value is stored in the output circuit 115. Then, the output circuit 115 may be configured to subtract the threshold value from the weighted sum. .

[0030] The output circuit 115 is a circuit for reading data from the ANA 111. 5 processes analog signals input via m wires RB and RD to generate data. The data DOUT is an analog output signal of the electronic device 100. That is, the output circuit 115 is an analog signal processing circuit.

[0031] The analog signal processing circuit 116 is a circuit for generating a learning signal from a teacher signal. The signal TC is a teacher signal. A learning signal is a signal obtained by combining the output signal of the electronic device 100 and a teacher signal. The analog signal processing circuit 1 The learning signal generated by the input 16 is a signal having a value calculated using the data DOUT and the signal TC. The analog signal processing circuit 116 also calculates the amount of weighting correction based on the learning signal. The calculated correction amount is stored in the memory 130 as an analog value. The correction amount stored as 0 is used to calculate the correction amount the next time learning is performed.

[0032] That is, for each learning, the analog signal processing circuit 116 performs a learning signal and a signal obtained in the previous learning. The correction amount is calculated by analog operation with the correction amount obtained. The weights stored in the row decoder 112 and the column decoder 113 are updated. The weights stored in the circuit 10 (weights W pv ) via wire RB to output circuit 11 5. The output circuit 115 writes the read weights W pv New weighting with the correction amount added to (Weight W nw ) is calculated. nw is sent to the column decoder 113. 12, the column decoder 113 assigns weights W nw is written.

[0033] The amount of correction obtained from the previous learning is the weight W nw Although it is not essential for the calculation of, its use may slow down the convergence. It gets faster. Weight W nw If you do not want to use the correction value obtained in the previous learning to calculate An artificial neural network device can be constructed using electronic device 101 (FIG. 2) that does not include 30. good.

[0034] In the electronic devices 100 and 101, the wiring DL can be controlled by the row decoder 112. In this case, the wiring DL may be electrically connected to the row decoder 112.

[0035] The memory 130 includes a memory cell array 131, a row decoder 132, and a column decoder 133. The memory cell array 131 includes a plurality of memory cells 30 and a plurality of wirings WL and BL. do.

[0036] The memory cells 30 are arranged in an array of p rows and q columns, where p and q are integers equal to or greater than 1. In accordance with the arrangement of the memory cells 30, p wirings WL and q wirings BL are provided. The memory cell 30 is electrically connected to the wirings WL and BL. The line BL is a bit line and is electrically connected to the row decoder 132. The row decoder 132 and the column decoder 133 are electrically connected to the row decoder 132 and the column decoder 133. Data is written to and read from the memory cell array 131 .

[0037] <ana> 3A shows an example of the circuit configuration of the ANA 111. The circuit 10 includes a node SN1, a transistor The circuit 11 includes transistors M1, M2, and a capacitor C1. The circuit 11 includes a transistor M3.

[0038] (Circuit 10) The node SN1 is a holding node. The potential of the node SN1 is a weight stored in the circuit 10. The capacitance element C1 is a storage capacitance for storing the potential of the node SN1. A first terminal of the element C1 is electrically connected to the wiring DL, and a second terminal of the element C1 is electrically connected to the node SN1. The gate of the transistor M1 is connected to the wiring WW, the first terminal is connected to the wiring WB, and the second terminal is connected to the node SN 1. The on / off state of the transistor M1 is controlled by the wiring WW. The transistor M1 controls electrical connection or disconnection between the node SN1 and the wiring WW. The gate of the transistor M2 is connected to the node SN1, the first terminal is connected to the wiring RB, and the second terminal is connected to the potential V It is electrically connected to the power supply line (VNN line) that supplies NN.

[0039] When writing a weight to the circuit 10, the column decoder 113 first reads a value corresponding to the weight. Then, analog data (weight data) having a voltage value corresponding to the row decoded data is written to the wiring WB. The weight data written in the wiring WB is turned on by the transistor M1 by the transistor 112. The data is written to node SN1.

[0040] When the weight is read from the circuit 10, the potential of the wiring DL is increased by the input circuit 114. As the potential of the wiring DL rises, the potential of the node SN1 also rises. An on-current (source-drain current) flows, and the potential of the wiring RB changes. In this case, the weight value can be obtained by detecting the potential of the wiring RB.

[0041] (Circuit 11) The circuit 11 has a circuit configuration similar to that of the circuit 10 except that the transistor M1 and the capacitor C1 are omitted. The transistor M3 is a transistor having a device structure similar to that of the transistor M2. The gate of the transistor M3 is connected to the wiring DL, the first terminal is connected to the wiring RD, and the second terminal is connected to the wiring RD. is electrically connected to the VNN line.

[0042] <<Examples of electronic device operation>> An example of a method of operation of electronic device 100 will be described with reference to FIGS. 1 and 3A.

[0043] Before learning (inputting data DIN), the current I flowing from ANA111 through wire RB RB0 =βW 2 is read out and stored in the output circuit 115. β is a coefficient, and W is the node S Potential V of N1 w The initial value of the weight of each circuit 10 is an analog voltage that depends on the run. A dam is fine, so the current I RB0 The initial weights should not be written before reading them. Or, the current I RB0 Before reading out the weights, the initial values ​​are written to each circuit 10. That's fine.

[0044] Next, the data DIN for learning is input to the input circuit 114. The input circuit 114 is Analog potential V corresponding to the input value is applied to the row wiring DL. x The current I RB 1=β(X+W) 2 flows, and the current I RD1 =βX 2 where X is , analog potential V x is an analog voltage that depends on

[0045] In the output circuit 115, the difference in the current flowing through the wiring RB[i] is ΔI RB1 [i]=I RB1 [i]―I RD1 -I RB0 Calculate [i] and ΔI of m wirings RB RB1 Take the sum of This provides a value equivalent to the current of 2βΣWX. The circuit for calculating the current difference can be a common one such as an operational amplifier. Circuits that correspond to transfer functions such as step functions and sigmoid functions include, for example, inverter circuits. When using an inverter circuit, the differential of the transfer function The minutes can be calculated using the current flowing through the inverter circuit.

[0046] Next, as described above, the amount of weight correction is calculated, and the corrected weight is written to the circuit 10.

[0047] In the circuit 10, a leakage current from the node SN1 (typically, a capacitance element C1, a transistor If the leakage current from the transistors M1 and M2 can be sufficiently reduced, the circuit 10 can operate normally during non-learning (learning After the end of the period, the fluctuation of the potential of the node SN1 can be suppressed. The row decoder 112, the column decoder 113, the input circuit 114, and the output circuit 115 are stopped. This allows the power consumption of the electronic device 100 to be reduced.

[0048] One of the causes of the potential fluctuation leakage current of the node SN1 is the source current of the transistor M1 in the off state. The leakage current (off-state current) between the drain and the transistor using metal oxide as the semiconductor. The off-state current of an oxide semiconductor transistor (OS transistor) is extremely low. Therefore, it is suitable for the transistor M1.

[0049] Since the band gap of oxide semiconductors is 3.0 eV or more, OS transistors can be thermally excited. The leakage current due to the gate insulating layer is small, and as shown above, the off-current is extremely small. The channel forming region of the transistor contains at least one of indium (In) and zinc (Zn). An oxide semiconductor is preferable. Such an oxide semiconductor is In-M-Zn The oxide (element M is, for example, Al, Ga, Y or Sn) is a typical example. By reducing impurities such as moisture and hydrogen that cause defects and also reducing oxygen vacancies, the oxide semiconductor The conductor can be made i-type (intrinsic semiconductor) or can be made as close to i-type as possible. In this case, such an oxide semiconductor can be called a highly purified oxide semiconductor. By using a optimized oxide semiconductor, an OS transistor with a standardized channel width can be realized. The off-state current of the OS transistor can be reduced to a level of several yA / μm or more and several zA / μm or less. The transistor and the oxide semiconductor will be described in Embodiments 3 and 5.

[0050] While the electronic device 100 is learning, the analog voltage held at node SN1 is updated frequently. A transistor using silicon as a semiconductor (Si transistor) is used for transistor M1. If the learning circuit 10 is not refreshed, the learning circuit 10 needs to be refreshed even during the learning process. When an OS transistor is used for the transistor M1, the potential fluctuation of the node SN1 is suppressed. , there is no need to refresh the circuit 10.

[0051] Compared to Si transistors, OS transistors have a higher voltage that can be applied between the source and drain, The upper limit of the voltage that can be applied between the source and gate is high (it has excellent voltage resistance). By using OS transistors for transistors M1 and M2, a higher voltage is maintained at node SN1. Therefore, the voltage applied to the wirings WW, DL, etc. can be increased.

[0052] A variation of circuit 10 is shown in FIG. 3B. Circuit 13 of FIG. 3B has a buffer instead of transistor M1. A transistor M4 having a gate is provided. The transistor M4 is also a transistor Like M1, it is preferably an OS transistor. By controlling the potential of the transistor M4, the threshold voltage of the transistor M4 can be changed. Therefore, for example, the leakage current of transistor M4 can be changed. The potential of the back gate of transistor M4 may be controlled for each circuit 13 or by ANA111. may be divided into a plurality of blocks and the process may be performed for each block.

[0053] When the leakage current of the transistor M4 increases during non-learning, the potential of the node SN1 decreases. This corresponds to a weakening of synaptic connections.

[0054] During training, if the leakage current of transistor M4 increases, the correct weights are written to circuit 13. In particular, supervised learning of neural networks (called backpropagation) In this case, the calculation result tends to be a local solution, so the leakage current of transistor M4 is adjusted accordingly. Increasing the current can sometimes help escape a local minimum and converge to the correct solution. In other words, the electronic device 100 has a large-scale algorithm for escaping a local solution and converging to the correct solution. Since there is no need to provide a circuit, the electronic device 100 can be made smaller. This allows for lower power consumption.

[0055] The method of changing the leakage current of transistor M4 is not limited to controlling the backgate potential. For example, exposure to ultraviolet light can increase the leakage current of transistor M4. The same is true for transistor M1.

[0056] FIG. 4 shows an example of a circuit configuration of a memory cell suitable for the memory cell 30. The memory cell 31 includes transistors M31 and M35, a capacitance element C2, and a node SN2. The cell 31 is a gain type cell having two transistors. In principle, the memory cell 31 This is a memory circuit that is capable of storing analog potentials and has no restrictions on the number of times it can be rewritten. .

[0057] The node SN2 is a node that holds a potential corresponding to data, and the capacitance element C2 is a node S The transistor M31 is a write transistor. By turning on the transistor M31, data is written to the node SN2. Transistor M35 is a read transistor whose gate is electrically connected to node SN2. is connected to

[0058] The memory cell 32 shown in FIG. 4B is a modification of the memory cell 31. Instead, a transistor M32 having a back gate is provided. Cell 33 is a modification of memory cell 31, in which a back gate is used instead of transistor M31. The back gate of the transistor M33 is The back gate is electrically connected to the source or drain. Good too.

[0059] The transistors M31 to M33 are OS transistors with extremely low off-state current. As a result, the retention times of the memory cells 31 to 33 are In the memory cells 31 to 33, the transistor M3 5 is a p-channel transistor, but it may be an n-channel transistor. In the case of a channel transistor, the transistor M35 may be an OS transistor. , Si transistors may also be used.

[0060] The memory cell 34 shown in FIG. 4D is a gain type cell having three transistors. The recell 34, like the memory cell 31, is also in principle not limited in the number of times it can be rewritten, and is analog The memory circuit is capable of holding a gate potential.

[0061] The memory cell 34 includes transistors M31, M36, and M37, a capacitance element C2, and a node SN2. Instead of the transistor M31, the transistor M32 or the transistor M33 is The transistors M36 and M37 may be OS transistors. Alternatively, the transistors M36 and M37 may be p-channel transistors. It could also be a gyroscope.

[0062] The memory cell 35 shown in FIG. 4E has a circuit configuration similar to that of a DRAM memory cell. Like the memory cell 31, the cell 35 is also essentially unlimited in the number of times it can be rewritten, and is analog The memory cell 35 is a memory circuit capable of holding a potential. , a capacitance element C2, and a node SN2. 32 or transistor M33 may be provided.

[0063] An artificial neural network device with complex functions that connects multiple ANA111s In addition, multiple ANA111s can be used to create FPGA-like structures. In this case, we can build an artificial neural network device using ANA111. Considering it as a logic element, ANA111 and ANA111 are programmable switches. An example of an electronic device having such a configuration is shown in FIG. 5A.

[0064] The electronic device 102 shown in FIG. 5A includes a plurality of ANAs 111 and a wiring switch array 140. The wiring switch array 140 has a plurality of wiring switches. 1 shows an example of a switch configuration.

[0065] The wiring switch 141 shown in FIG. 5B is a programmable wiring switch. The output node of ANA111 is electrically connected to node OUT, and another ANA11 The wiring switch 141 electrically connects the input nodes of the transistors M41 to M1. A transistor M43, a capacitor C4, a node SN4, and wirings 144 to 146 are included. The potential of node SN4 determines the conduction state between nodes IN and OUT. The capacitance element C4 is a storage capacitance of the node SN4. The transistor M41 is a As with the transistor M31 of the third embodiment, the transistor M31 is preferably an OS transistor. This allows the state of the wiring switch 141 to be maintained for a long period of time. , a transistor having a back gate such as the transistor M32 or the transistor M33 The criterion may be applied.

[0066] The electronic device of this embodiment allows the construction of an artificial neural network. The electronic device of this embodiment can perform, for example, voice recognition and image recognition. For example, by making the electronic device of the present embodiment perform voice recognition, electronic devices can be For example, the electronic device of the present embodiment can perform image recognition. By incorporating electronic devices, it is possible to match faces and fingerprints, input handwritten characters, etc. This makes it possible to perform optical character recognition.

[0067] [Embodiment 2] In this embodiment, a manufacturing method and a configuration example of an electronic device will be described. This section explains electronic devices and other devices that can be used with this equipment.

[0068] <<Examples of how to manufacture electronic components>> 6A is a flow chart showing an example of a method for manufacturing an electronic component. After going through the manufacturing process (pre-process) and assembly process (post-process) of these devices, The assembly is completed by assembling multiple detachable parts. Figure 6A shows an example of the post-process. The electronic components that are completed through the post-processing are called semiconductor packages, IC packages, or package Electronic components are classified into several standards according to the terminal extraction direction, terminal shape, etc. There are cases and names. Here, we will explain an example.

[0069] First, a pre-process is performed to complete the element substrate (step S1). Next, the substrate is bonded to a plurality of chips. A dicing process is performed to separate the substrate into multiple pieces (step S2). By making the film thinner, warping of the board during the pre-processing can be reduced, and the parts can be made smaller. Then, the die is bonded to the lead frame (step S 3) In the die bonding process, the chip and the lead frame are bonded using resin or tape. The bonding method can be selected according to the product. In the wire bonding process, the chip may be mounted on the interposer and bonded. The leads of the lead frame and the electrodes on the chip are electrically connected with thin metal wires. (Step S4). For the thin metal wire, a silver wire or a gold wire can be used. The bonding may be either ball bonding or wedge bonding.

[0070] The wire-bonded chip is then sealed with epoxy resin or other materials in a molding process. (Step S5). The leads of the lead frame are plated. Then the leads are cut off. The leads are cut and shaped (step S6). The leads are then plated to prevent rust. This allows for more reliable soldering when mounting the package on a printed circuit board. The printing process (marking) is performed (step S7). After the inspection process (step S8), The child part is completed (step S9).

[0071] <<Example of electronic component configuration>> FIG. 6B is a perspective schematic diagram of an electronic component. As an example, FIG. 6B shows a QFP (Quad FP) The electronic component 7000 shown in FIG. 6B has a lead 7001. The circuit section 7003 includes, for example, the electronic device of the first embodiment. The electronic component 7000 is, for example, a printed circuit board 7002. A number of such electronic components 7000 are assembled and each is printed. The electrical connections are made on the substrate 7002. The completed circuit board 7004 is then mounted on an electronic device. can be.

[0072] The electronic component 7000 can be used in a variety of processors. For example, the electronic component 700 0 is for digital signal processing, software radio, avionics (communications equipment, navigation systems, Electronic equipment related to aviation, such as autopilots and flight management systems, ASIC prototyping processing, medical image processing, speech recognition, cryptography, bioinformatics, Emulators of mechanical devices, radio telescopes in radio astronomy, and electronic devices in automobiles, etc. It can be applied to electronic components (IC chips) in a wide range of electronic devices.

[0073] Other electronic devices that can use the electronic component 7000 include smartphones, mobile phones, etc. Telephones, game consoles including portable ones, e-book terminals, cameras (video cameras, digital still cameras) Wearable information terminals (head-mounted, goggles, glasses, armbands, etc.) bracelet type, wristwatch type, necklace type, etc.), navigation systems, audio playback devices ( Car audio, digital audio players, etc.), television broadcast receiving tuners , copiers, facsimiles, printers, printer-combinations, automated teller machines (ATMs) ), vending machines, etc.

[0074] By mounting the electronic component 7000, the electronic device has the function of the electronic device of the first embodiment. For example, by providing electronic devices with a voice recognition function, it becomes possible to control electronic devices by voice. It is possible to operate a device or input information into an electronic device. By equipping the device with image recognition capabilities, it is possible to match fingerprints, veins, faces, etc., and also input handwritten characters. A specific example of such an electronic device is shown in Figure 7.

[0075] The portable game machine 2900 shown in FIG. 7A includes a housing 2901, a housing 2902, a display unit 2903, and a controller 2904. , a display unit 2904, a microphone 2905, a speaker 2906, operation keys 2907, etc. The display unit 2903 is provided with a touch screen as an input device, and It can be operated using Rath2908 and other similar devices.

[0076] The information terminal 2910 shown in FIG. 7B includes a housing 2911, a display unit 2912, a microphone 2917, A speaker unit 2914, a camera 2913, an external connection unit 2916, and operation buttons 29 The display unit 2912 includes a display panel and a touch screen using a flexible substrate. The information terminal 2910 is, for example, a smartphone, a mobile phone, a tablet, The device can be used as a portable information terminal, a tablet PC, an e-book terminal, etc.

[0077] The notebook PC 2920 shown in FIG. 7C includes a housing 2921, a display unit 2922, a keyboard 29 23, and a pointing device 2924.

[0078] The video camera 2940 shown in FIG. 7D includes a housing 2941, a housing 2942, a display unit 2943, The operation key 2944 includes an operation key, a lens 2945, and a connection part 2946. The lens 2945 is provided in the housing 2941, and the display unit 2943 is provided in the housing 2942. The housing 2941 and the housing 2942 are connected by a connection portion 2946. The angle between the housing 2941 and the housing 2942 can be changed by a connecting portion 2946. Depending on the angle of the housing 2942 with respect to the housing 2941, You can change the orientation of the image displayed on the 2943 and switch the image display / non-display. can.

[0079] An example of a bangle-type information terminal is shown in FIG. The display unit 2952 is supported by a curved housing 2951. The display unit 2952 is equipped with a display panel using a flexible substrate, It is possible to provide an information terminal 2950 that is flexible, lightweight, and easy to use.

[0080] FIG. 7F shows an example of a wristwatch-type information terminal. The information terminal 2960 includes a housing 2961, a display unit 2962, band 2963, buckle 2964, operation button 2965, input / output terminal 296 The information terminal 2960 is equipped with a mobile phone, an e-mail, a text browsing and writing, a music player, etc. It can run various applications such as playback, internet communication, and computer games. It is possible.

[0081] The display surface of the display unit 2962 is curved, and display can be performed along the curved display surface. The display unit 2962 is also equipped with a touch sensor, and can be operated by touching the screen with a finger or a stylus. For example, the icon 2967 displayed on the display unit 2962 can be operated by touching the The operation button 2965 is used for setting the time, In addition to the settings, it can also turn the power on and off, turn wireless communication on and off, activate silent mode, and It can have various functions such as turning off the power saving mode, turning on and off the power saving mode, etc. The operating system incorporated in the information terminal 2960 controls the operation of the operation button 2965. You can also set the functions.

[0082] In addition, the information terminal 2960 is capable of performing short-distance wireless communication that complies with a communication standard. For example, by communicating with a wireless headset, The information terminal 2960 is also provided with an input / output terminal 2966, and can receive other information. Data can be exchanged directly between the terminal and the connector. Charging can also be performed via the input / output terminal 2966. This may be achieved by wireless power supply.

[0083] FIG. 7G shows an electric refrigerator-freezer as an example of a household electrical appliance. The electric refrigerator-freezer 2970 is The refrigerator has a housing 2971, a refrigerator door 2972, and a freezer door 2973.

[0084] FIG. 7H is an external view showing an example of the configuration of an automobile. The automobile 2980 includes a body 2981, The vehicle 298 includes wheels 2982, a dashboard 2983, and lights 2984. The electronic components of this embodiment can also be incorporated into ships, aircraft, and two-wheeled automobiles. can.

[0085] Third Embodiment In this embodiment, a device structure and the like of an OS transistor will be described.

[0086] <<Transistor configuration example 1>> 8A is a top view of transistor 400a. FIG. 8B is a top view of the transistor 400a of FIG. 8A taken along line A1-A2. 8C is a cross-sectional view of FIG. 8A taken along line A3-A4. The direction of the line is called the channel length direction of the transistor 400a, and the direction of the A3-A4 line is called the channel length direction of the transistor 400a. In FIG. 8A, for the sake of clarity, 9A and other top views are similar to FIG. 8A.

[0087] The transistor 400a is formed on a substrate 450. The transistor 400a is an insulating The insulating films 401 to 408, the conductive films 411 to 414, and the conductive films 421 to 424 are 24, metal oxide 431 to metal oxide 433. The metal oxides 433 may be collectively referred to as metal oxides 430.

[0088] The metal oxide 432 is a semiconductor and has a channel formation region. The metal oxide layer 432 is formed by the metal oxide layer 432. The layer 432 is formed by the metal oxide layer 432. The region 441 is formed in a region where the conductive film 421 and the stack are in contact with each other, and the region 442 is formed in a region where the conductive film 421 and the stack are in contact with each other. , are formed in the region where the conductive film 423 and the stack are in contact with each other. The region 42 is a low resistance region having a lower resistivity than the other regions. In this way, the contact resistance between the conductive film 421 and the stacked layers can be reduced. By providing the region 442, the contact resistance with the conductive film 423 can be reduced. It becomes Noh.

[0089] The stack of the conductive films 421 and 422 and the stack of the conductive films 423 and 424 are source electrodes. The conductive film 422 is less permeable to oxygen than the conductive film 421. This makes it possible to prevent a decrease in the conductivity of the conductive film 421 due to oxidation. Similarly, the conductive film 424 is less permeable to oxygen than the conductive film 423. Therefore, it is possible to prevent a decrease in the conductivity of the conductive film 423 due to oxidation.

[0090] The conductive films 411 to 413 are the gate electrode (front gate The conductive films 411 to 413 are formed in regions that form gate electrodes. The insulating film 405 is formed in a self-aligned manner so as to fill an opening 415 formed therein. It is preferable that the conductive films 411 and 413 are less permeable to oxygen than the conductive film 412. This makes it possible to prevent a decrease in the conductivity of the conductive film 412 due to oxidation. This constitutes a back gate electrode. The conductive film 414 may be omitted in some cases.

[0091] The insulating films 405 to 408 serve as protective insulating films or interlayer insulating films for the transistor 400a. In particular, the insulating film 406 constitutes a gate insulating film. In particular, the insulating films 402 to 404 function as base insulating films for the transistor 400a. The film 404 also functions as a gate insulating film on the back gate side.

[0092] As shown in FIG. 8C, the side surface of the metal oxide 432 is surrounded by the conductive film 411. By adopting such a device structure, the electric field of the gate electrodes (conductive films 411 to 413) Therefore, the metal oxide 432 can be electrically surrounded. The structure of a transistor that electrically surrounds a semiconductor is called a surrounded channel. This is called the el (s-channel) structure. Therefore, the entire (bulk) of the metal oxide 432 The s-channel structure is a transistor with a source-drain A large current can flow between the gates, and the on-state current of the transistor can be increased. The channel structure provides a high on-current, making it suitable for use in microfabrication of processors, memory devices, etc. This structure is suitable for semiconductor devices that require finely-tuned transistors. Since the transistors can be thinned, semiconductor devices having the transistors can be highly integrated and highly dense. This makes it possible to form a semiconductor device.

[0093] As shown in FIG. 8B, the stack of the conductive films 411 to 413 and the conductive film 422 are insulating films. The conductive films 405 and 406 overlap each other. The laminate of the conductive film 413 and the conductive film 424 overlap each other with the insulating films 405 and 406 interposed therebetween. These regions are between the gate electrode and the source or drain electrode. This acts as a parasitic capacitance and causes the operating speed of the transistor 400a to decrease. The transistor 400a has a relatively thick insulating film 405, which reduces the parasitic capacitance described above. The insulating film 405 is preferably made of a material having a low relative dielectric constant. preferable.

[0094] 9A is an enlarged view of a channel formation region of the transistor 400a. The bottom surface of the conductive film 411 is in contact with the metal oxide 432 via the insulating film 406 and the metal oxide 433. The length of the area parallel to the top surface of G Width L G is the transistor 400a 9A. In FIG. 9A, the line width of the gate electrode is shown. Length Width L SD Width L SD The source electrode and the drain electrode of the transistor 400a It represents the length between.

[0095] Width L SD is often determined by the minimum processing dimension. As shown in Figure 9A, G is the width L SD This is because the line width of the gate electrode of the transistor 400a is smaller than the minimum processing dimension. For example, the width L G 5nm or more 60 It is possible to make the thickness smaller than 5 nm, preferably smaller than 30 nm.

[0096] In FIG. 9A, the total thickness of the conductive film 421 and the conductive film 422, or the total thickness of the conductive film 423 and The total thickness of the conductive film 424 is the height H SD The thickness of the insulating film 406 is expressed as a height H SD Same as or smaller, the electric field of the gate electrode is applied to the entire channel formation region. For example, the thickness of the insulating film 406 is 30 nm or less, preferably 1 0 nm or less.

[0097] In addition, the parasitic capacitance formed between the conductive film 422 and the conductive film 411 and the conductive film 424 are The magnitude of the parasitic capacitance formed between the conductive film 411 is inversely proportional to the thickness of the insulating film 405. For example, the thickness of the insulating film 405 is set to be three times or more, preferably five times or more, the thickness of the insulating film 406. By doing so, these parasitic capacitances become negligibly small, and the This is preferable because it improves the high frequency characteristics. The explanation will be given below.

[0098] <Metal oxide> The metal oxide 432 is, for example, an oxide semiconductor containing indium (In). If the material 432 contains indium, for example, the carrier mobility (electron mobility) increases. Moreover, the metal oxide 432 preferably contains an element M. The element M is preferably aluminum. Al (Al), Gallium (Ga), Yttrium (Y) or Tin (Sn), etc. Other elements that can be used for M include boron (B), silicon (Si), titanium ( Ti), iron (Fe), nickel (Ni), germanium (Ge), zirconium (Zr) , Molybdenum (Mo), Lanthanum (La), Cerium (Ce), Neodymium (Nd), Haf Hf, tantalum (Ta), tungsten (W), magnesium (Mg), etc. However, the element M may be a combination of two or more of the above elements. The element M may be, for example, For example, indium has a high bond energy with oxygen. Or, the element M is, for example, an element having an energy gap of a metal oxide. The metal oxide 432 contains zinc (Zn). It is preferable that the metal oxide contains zinc, and may be easily crystallized.

[0099] However, the metal oxide 432 is not limited to an oxide semiconductor containing indium. The material 432 is a non-indium-containing material, such as zinc tin oxide or gallium tin oxide. , oxide semiconductors containing zinc, oxide semiconductors containing gallium, oxide semiconductors containing tin, etc. may be also possible.

[0100] The metal oxide 432 is, for example, an oxide semiconductor having a wide energy gap. The energy gap of the oxide 432 is preferably, for example, 2.5 eV or more and 4.2 eV or less. Preferably, the value is 2.8 eV or more and 3.8 eV or less, and more preferably, 3 eV or more and 3.5 eV or less. The metal oxide 432 is preferably made of CAAC-OS, which will be described later.

[0101] For example, the metal oxides 431 and 433 contain at least the metal element constituting the metal oxide 432. It is preferable that the metal oxide 431 and the metal oxide 432 are also included. At the interface between the metal oxide 432 and the metal oxide 433, an interface state is formed. Pile.

[0102] When the metal oxide 431 is an In-M-Zn oxide, the sum of In and M is 100 atom. When expressed as mic%, it is preferable that In is less than 50 atomic % and M is 50 atomic %. %, and more preferably In is less than 25 atomic % and M is 75 atomic %. When the metal oxide 431 is formed by a sputtering method, the above composition is satisfied. It is preferable to use a sputtering target having a composition in which In:M:Zn=1: Preferred are In:M:Zn=3:2, In:M:Zn=1:3:4, etc.

[0103] When the metal oxide 432 is an In-M-Zn oxide, the sum of In and M is 100 atom. When the atomic percentage is 100 atomic %, it is preferable that In is higher than 25 atomic % and M is 75 atomic %. % or less, more preferably In is higher than 34 atomic % and M is 66 atomic % or less. When the metal oxide 432 is formed by sputtering, the above composition is For example, it is preferable to use a sputtering target that satisfies the following formula: In:M:Zn= 1:1:1, In:M:Zn=1:1:1.2, In:M:Zn=2:1:3, In:M In:M:Zn=3:1:2, and In:M:Zn=4:2:4.1 are particularly preferred. When the atomic ratio of In:Ga:Zn=4:2:4.1 is used as the target, the film is formed. The atomic ratio of the metal oxide 432 to be formed is approximately In:Ga:Zn=4:2:3. be.

[0104] In addition, when the metal oxide 433 is an In-M-Zn oxide, the sum of In and M is 100 atom. When expressed as mic%, it is preferable that In is less than 50 atomic % and M is 50 atomic %. %, and more preferably In is less than 25 atomic % and M is 75 atomic %. %. For example, In:M:Zn=1:3:2, In:M:Zn=1:3:4 The metal oxide 433 is preferably the same as the metal oxide 431. It's fine.

[0105] In addition, the metal oxide 431 or the metal oxide 433 may not necessarily contain indium. For example, metal oxide 431 or metal oxide 433 may be gallium oxide.

[0106] <Energy band structure> Using the energy band structure diagram shown in FIG. 9B, the metal oxides 431 to 433 The function and effect of the metal oxide 430 formed by stacking the above will be described. shows the energy band structure of the portion indicated by the Y1-Y2 line in FIG. 9A. 4, Ec431, Ec432, Ec433, and Ec406 are insulating film 404 and gold, respectively. Metal oxide 431, metal oxide 432, metal oxide 433, and insulating film 406 This indicates energy.

[0107] Here, the difference between the vacuum level and the conduction band minimum energy (also called "electron affinity") is The energy difference between the vacant level and the top of the valence band (also called the ionization potential) The energy gap is calculated by subtracting the energy gap from the spectroscopic ellipsometer. The energy difference between the vacuum level and the top of the valence band can be measured using ultraviolet photoelectron spectroscopy. Analysis(UPS:Ultraviolet Photoelectron Spectro This can be measured using a scopy device.

[0108] Since the insulating films 404 and 406 are insulators, Ec406 and Ec404 are It is closer to the vacuum level (has smaller electron affinity) than Ec432 and Ec433.

[0109] The metal oxide 432 has a higher electron affinity than the metal oxide 431 and the metal oxide 433. It is preferable to use a metal oxide. For example, the metal oxide 432 is 1 and the metal oxide 433, the electron affinity of which is 0.07 eV or more and 1.3 eV or less, preferably is 0.1 eV or more and 0.7 eV or less, more preferably 0.15 eV or more and 0.4 eV or less The electron affinity is calculated by the relationship between the vacuum level and the conduction band minimum energy. This is the difference.

[0110] Indium gallium oxide has a small electron affinity and a high oxygen blocking property. Therefore, the metal oxide 433 preferably contains indium gallium oxide. The atomic ratio [Ga / (In+Ga)] is, for example, 70% or more, preferably 80% or more, and more preferably 100% or more. More preferably, it is 90% or more.

[0111] When a gate voltage is applied to the transistor 400a, the electron affinity of the metal oxide 430 is increased. A channel is formed in the metal oxide 432, which has a large force. At this time, the electrons flow through the metal oxide 432. 31, 433, but mainly in the metal oxide 432. The interface between the oxide 431 and the insulating film 404, or the interface between the metal oxide 433 and the insulating film 406 Even if there are many interface states at the interface that hinder the flow of electrons, the transistor 400a The metal oxides 431 and 433 have no effect on the on-current of the gate insulating film. It works.

[0112] Between the metal oxide 431 and the metal oxide 432, In addition, there may be a mixed region between the metal oxide 432 and the metal oxide 433. In some cases, a mixed region of the metal oxide 432 and the metal oxide 433 may exist. Therefore, the stacking of metal oxides 431-433 is A band structure in which the energy changes continuously near the interface (also called a continuous junction). It becomes.

[0113] The interface between the metal oxide 431 and the metal oxide 432, or the interface between the metal oxide 432 and the metal oxide As described above, the interface between the metal oxide 432 and the substrate 433 has a low interface state density. Since the movement of electrons is not hindered much, the on-current of the transistor 400a is increased. This makes it possible.

[0114] For example, the movement of electrons in the transistor 400a is affected by the physical unevenness of the channel formation region. In order to increase the on-current of the transistor 400a, for example, The upper or lower surface of the metal oxide 432 (the surface on which the metal oxide 432 is to be formed, here, the upper surface of the metal oxide 431) The root mean square (RMS) roughness in the range of μm×1 μm is less than 1 nm, preferably 0 Less than 0.6 nm, more preferably less than 0.5 nm, and even more preferably less than 0.4 nm. In addition, the average surface roughness (also called Ra) in an area of ​​1 μm × 1 μm is less than 1 nm. less than 0.6 nm, more preferably less than 0.5 nm, and even more preferably less than 0. The maximum height difference (PV) in the area of ​​1 μm x 1 μm should be less than 4 nm. ) is less than 10 nm, preferably less than 9 nm, more preferably less than 8 nm, and even more preferably It is preferable that the thickness is less than 7 nm.

[0115] The movement of electrons is also hindered when the density of defect states is high in the region where the channel is formed. For example, metal oxide 432 has oxygen vacancies (V O If the structure has oxygen vacancies, Hydrogen can enter the oxygen vacancy site, forming a donor level. The state in which hydrogen has entered is V O It may be written as H. V O H scatters electrons, This causes a decrease in the on-state current of the transistor. Therefore, in order to reduce the oxygen vacancies in the metal oxide 432, By doing so, the on-state current of the transistor can be increased in some cases.

[0116] For example, at a certain depth in the metal oxide 432 or in a certain region of the metal oxide 432 The hydrogen concentration measured by secondary ion mass spectrometry (SIMS) is 1×10 16 ato ms / cm 3 That's it, 2 x 10 20 atoms / cm 3 Less than or equal to 1×10 16 at oms / cm 3 That's it, 5 x 10 19 atoms / cm 3 Less than or equal to 1×10 1 6 atoms / cm 3 That's it, 1×10 19 atoms / cm 3 More preferably, 1 ×10 16 atoms / cm 3 That's it, 5 x 10 18 atoms / cm 3 The following is the result.

[0117] In order to reduce the oxygen vacancies in the metal oxide 432, for example, the excess oxygen in the insulating film 404 is removed. The element is transferred to the metal oxide 432 via the metal oxide 431. In this case, the metal oxide 431 is an oxygen-permeable layer (a layer that allows oxygen to pass through or permeate). It is preferable that

[0118] The thickness of the metal oxide 432 can be 1 nm or more and 20 nm or less. The thickness of 2 depends on the channel length. The shorter the channel length, the thinner it can be. For example, it can be 1 nm or more and 15 nm or less. The thickness can be 1 nm or less, or between 1 nm and 10 nm or less.

[0119] The thickness of the metal oxide 431 can be 5 nm to 200 nm, or less than 10 nm. 120nm or more, or 20nm or more and 120nm or more, or 40nm or more and 80nm or more Metal oxide 431 is preferably thicker than metal oxide 432. By making the metal oxide 431 thicker, the interface between the adjacent insulator and the metal oxide 431 is The distance to the channel formation region can be increased.

[0120] The thickness of the metal oxide 433 can be 1 nm to 100 nm, or less than 1 nm. The thickness of the transistor may be set to 50 nm or less, or 1 nm or more and 10 nm or less. To increase the on-current of 400a, the metal oxide 433 should be thinner than the metal oxide 431. It is preferable to do so.

[0121] For example, between the metal oxide 432 and the metal oxide 431, for example, silicon The concentration of 16 atoms / cm 3 That's it, 1×10 19 atoms / cm 3 less than , preferably 1 x 10 16 atoms / cm 3 That's it, 5 x 10 18 atoms / cm 3 Not yet More preferably, 1×10 16 atoms / cm 3 More than 2×10 18 atoms / c m 3 In addition, between the metal oxide 432 and the metal oxide 433, there is a region in which S Silicon concentration by IMS is 1×10 16 atoms / cm 3 More than 1×10 19 ato ms / cm 3 Less than 1 x 10 16 atoms / cm 3 5×10 or more 18 ato ms / cm 3 less than 1×10 16 atoms / cm 3 More than 2×10 18 atoms / cm 3 has an area that is less than

[0122] In order to reduce the hydrogen concentration in the metal oxide 432, the metal oxide 431 and the metal oxide It is preferable to reduce the hydrogen concentration of the metal oxide 433. In IMS, 1×10 16 atoms / cm 3 That's it, 2 x 10 20 atoms / cm 3 Less than or equal to 1×10 16 atoms / cm 3 That's it, 5 x 10 19 atoms / c m 3 Less than or equal to 1×10 16 atoms / cm 3 That's it, 1×10 19 atom s / cm 3 Less than 1×10, more preferably 16 atoms / cm 3 That's it, 5 x 10 18 atoms / cm 3 The hydrogen concentration in the metal oxide 432 is as follows: In order to reduce the concentration, the nitrogen concentration of the metal oxide 431 and the metal oxide 433 is reduced. The metal oxide 431 and the metal oxide 433 have a SIMS resolution of 1×10 16 atoms / cm 3 5×10 or more 19 atoms / cm 3 Less than 1 x 10 16 atoms / cm 3 5×10 or more 18 atoms / cm 3 Less than or equal to 1×10 16 atoms / cm 3 That's it, 1×10 18 atoms / cm 3 More preferably, 1×10 16 atoms / cm 3 5×10 or more 17 atoms / cm 3 With the following nitrogen concentration It has a region as follows.

[0123] The metal oxides 431 to 433 can be formed by a sputtering method, a CVD (Chemical Vapor Deposition) method, or the like. ical vapor deposition) method, MBE (Molecular Be am Epitaxy) method or PLD (Pulsed Laser Depositio) n) method, ALD (Atomic Layer Deposition) method, etc. Just say it.

[0124] After the metal oxides 431 and 432 are formed, a first heat treatment is preferably performed. The heat treatment is carried out at a temperature of 250° C. to 650° C., preferably 450° C. to 600° C., more preferably The first heat treatment is preferably performed at a temperature of 520° C. to 570° C. inclusive. or in an atmosphere containing oxidizing gas at 10 ppm or more, 1% or more, or 10% or more. The first heat treatment may be performed under reduced pressure. Alternatively, the first heat treatment may be performed under an inert gas atmosphere. After heat treatment, oxidizing gas is added at 10 ppm or more, 1% or more, or more to compensate for the oxygen that has been removed. The heat treatment may be performed in an atmosphere containing 10% or more of metal oxide. It is possible to increase the crystallinity of materials 431 and 432 and remove impurities such as hydrogen and water. become.

[0125] FIG. 9 shows an example of a three-layer structure of the metal oxide 430, but is not limited to this. The oxide 430 can be a two-layer structure without the metal oxide 431 or the metal oxide 433. Alternatively, the metal oxide 430 may be formed on or under the metal oxide 430 or at least in one portion of the layer. A single layer or a laminate of the metal oxides exemplified as the metal oxides 31 to 433 is provided to form an n-layer structure. (n is an integer greater than 3).

[0126] <Substrate> The substrate 450 may be, for example, an insulating substrate, a semiconductor substrate, or a conductive substrate. Examples of the insulating substrate include a glass substrate, a quartz substrate, a sapphire substrate, and a stabilized zirconia substrate. There are also semiconductor substrates, such as zirconia substrates stabilized with yttria, and resin substrates. The plate may be, for example, a single semiconductor substrate such as silicon or germanium, or silicon carbide. , silicon germanium, gallium arsenide, indium phosphide, zinc oxide, gallium oxide Furthermore, there are compound semiconductor substrates having an insulating region inside the aforementioned semiconductor substrate. Semiconductor substrates, such as SOI (Silicon On Insulator) substrates Conductive substrates include graphite substrates, metal substrates, alloy substrates, conductive resin substrates, etc. Alternatively, there are substrates having metal nitrides, substrates having metal oxides, etc. a substrate in which a conductor or a semiconductor is provided on an insulating substrate; a substrate in which a conductor or an insulator is provided on a semiconductor substrate; A substrate in which a semiconductor or an insulator is provided on a conductive substrate, or a substrate in which a semiconductor or an insulator is provided on a conductive substrate, etc. The substrate may have elements mounted thereon. These include elements, resistor elements, rectifier elements, switch elements, light-emitting elements, and memory elements.

[0127] A flexible substrate may be used as the substrate 450. As a method for providing the transistor, a transistor is formed on a non-flexible substrate, and then the transistor is Alternatively, the substrate 450 may be peeled off and transferred to a flexible substrate 450. A peeling layer may be provided between the substrate and the transistor. Alternatively, a sheet, film, or foil containing the same may be used. In addition, the substrate 450 has a property of returning to its original shape when bending or pulling is stopped. The thickness of the substrate 450 may be, for example, For example, the thickness may be 5 μm or more and 700 μm or less, and preferably 10 μm or more and 500 μm or less. More preferably, the thickness is 15 μm or more and 300 μm or less. The device can be made lighter. In addition, by making the substrate 450 thinner, it is possible to use glass or the like. It may have elasticity even when bent or pulled, or it may return to its original shape when bending or pulling is stopped. Therefore, damage to the semiconductor device on the substrate 450 due to dropping or the like may occur. It is possible to reduce shocks, etc. In other words, a robust semiconductor device can be provided.

[0128] The flexible substrate that can be used as the substrate 450 is, for example, a metal, an alloy, a resin, or a glass. The substrate is made of these fibers. The lower the linear expansion coefficient of a flexible substrate, the less deformation it will undergo due to the environment. The flexible substrate is preferably a substrate having a linear expansion coefficient of, for example, 1×10 -3 / K or less, 5 ×10 -5 / K or less, or 1×10 -5 / K or less. For example, polyester, polyolefin, polyamide (nylon, aramid, etc.), Polyimide, polycarbonate, acrylic, polytetrafluoroethylene (PTFE) In particular, since aramid has a low linear expansion coefficient, it is suitable for use as the substrate 450, which is a flexible substrate. This is preferable.

[0129] <Undercoating insulating film> The insulating film 401 has a function of electrically isolating the substrate 450 and the conductive film 414. The insulating film 401 or the insulating film 402 is formed of an insulating film having a single layer structure or a multilayer structure. Examples of materials that can be used include aluminum oxide, magnesium oxide, silicon oxide, and oxynitride. Silicon, silicon oxide nitride, silicon nitride, gallium oxide, germanium oxide, and indium oxide tritium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, tantalum oxide The insulating film 402 is made of TEOS (Tetra-Ethyl-O rtho-Silicate) or silane, etc., reacted with oxygen or nitrous oxide, etc. Alternatively, a silicon oxide film having good step coverage formed by reacting the silicon oxide film with the insulating film 402 may be used. In order to improve the flatness of the upper surface, a flattening process using a CMP method or the like is performed after the insulating film 402 is formed. You may go.

[0130] In this specification, the term "oxynitride" refers to a compound that contains more oxygen than nitrogen. The term "nitride oxide" refers to a compound that contains more nitrogen than oxygen.

[0131] The insulating film 404 preferably contains an oxide. In particular, the insulating film 404 preferably contains an oxide from which oxygen is released by heating. Preferably, the oxide material contains more oxygen than meets the stoichiometric composition. It is preferable to use an oxide containing more oxygen than the stoichiometric composition. When the insulating film 404 is heated, some of the oxygen is released. 430, it becomes possible to reduce oxygen vacancies in the metal oxide 430. As a result, In this way, fluctuations in the electrical characteristics of the transistor can be suppressed, and the reliability can be improved.

[0132] The oxide film containing more oxygen than the stoichiometric composition has a TDS (Th Thermal Desorption Spectroscopy (DSA) analysis revealed that oxygen atoms The converted amount of oxygen released is 1.0 x 10 18 atoms / cm 3 Above 3.0, preferably 3.0 ×10 20 atoms / cm 3 The oxide film is as above. The surface temperature of the film in the test is 100°C or more and 700°C or less, or 100°C or more and 500°C or less. is preferred.

[0133] The insulating film 404 preferably contains an oxide capable of supplying oxygen to the metal oxide 430. For example, it is preferable to use a material containing silicon oxide or silicon oxynitride. Alternatively, the insulating film 404 may be formed of aluminum oxide, aluminum oxynitride, or gallium oxide. , gallium oxide, yttrium oxide, yttrium oxide nitride, hafnium oxide, A metal oxide such as hafnium nitride may be used. In order to achieve this, the insulating film 404 may be formed in an oxygen atmosphere, for example. Oxygen may be introduced into the insulating film 404 to form an area containing excess oxygen, or both of these methods may be used. Combinations are also possible.

[0134] For example, oxygen (at least oxygen radicals, oxygen atoms, oxygen ions, etc.) may be added to the insulating film 404 after the film formation. A region containing excess oxygen is formed by introducing oxygen into the film. These include ion implantation, ion doping, plasma immersion ion implantation, and plasma For oxygen introduction, a gas containing oxygen can be used. Examples of oxygen-containing gases include oxygen, nitrous oxide, nitrogen dioxide, and carbon dioxide. In the oxygen introduction process, a gas containing oxygen can be used. A rare gas may be contained in the gas. Alternatively, hydrogen or the like may be contained in the gas. For example, carbon dioxide, hydrogen In order to improve the flatness of the top surface of the insulating film 404, a mixed gas of argon and argon may be used. For this purpose, after the insulating film 404 is formed, planarization treatment using a CMP method or the like may be performed.

[0135] The insulating film 403 serves as a passivation function to prevent the oxygen contained in the insulating film 404 from decreasing. Specifically, the insulating film 403 prevents oxygen contained in the insulating film 404 from The insulating film 403 prevents oxygen, hydrogen, water, It has the function of blocking alkali metals, alkaline earth metals, etc. By this, oxygen can be diffused from the metal oxide 430 to the outside and oxygen can be diffused from the outside to the metal oxide 430. The insulating film 403 can prevent hydrogen, water, and the like from entering the insulating film 403. The insulating material may be an oxide, an oxide or an oxynitride. Silicon nitride, silicon oxynitride, aluminum nitride, aluminum oxynitride, oxide Aluminum, aluminum oxynitride, gallium oxide, gallium oxynitride, yttrium oxide Examples of oxides that can be used include yttrium oxide, yttrium oxide nitride, hafnium oxide, and hafnium oxide nitride.

[0136] The transistor 400a controls the threshold voltage by injecting electrons into the charge trapping layer. The charge trap layer is preferably provided in the insulating film 402 or the insulating film 403. For example, the insulating film 403 may be made of hafnium oxide, aluminum oxide, tantalum oxide, aluminum oxide, or the like. By forming the layer from tungsten silicate or the like, it can function as a charge trapping layer.

[0137] <Back gate electrode, gate electrode, source electrode, and drain electrode> The conductive films 411 to 414 and the conductive films 421 to 424 are made of copper (Cu), tungsten (Tungsten), and tungsten (Tungsten) and are preferably made of tungsten. Stainless steel (W), molybdenum (Mo), gold (Au), aluminum (Al), manganese (M n), titanium (Ti), tantalum (Ta), nickel (Ni), chromium (Cr), lead (P b), tin (Sn), iron (Fe), cobalt (Co), ruthenium (Ru), platinum (Pt) , iridium (Ir), strontium (Sr) It is preferable to form a single layer or a multilayer of a conductive film containing a compound having these as a main component. It is preferable to use a high melting point material such as tungsten or molybdenum, which has both heat resistance and electrical conductivity. It is also preferable to form the insulating layer 11 from a low-resistance conductive material such as aluminum or copper. Furthermore, when a Cu-Mn alloy is used, manganese oxide is formed at the interface with the insulator containing oxygen, Manganese oxide is preferred because it has the function of suppressing the diffusion of Cu.

[0138] The conductive films 421 to 424 can contain iridium oxide, ruthenium oxide, strontium oxide, or the like. It is preferable to use conductive oxides containing noble metals, such as ruthenium ruthenate. Conductive oxides do not remove oxygen from oxide semiconductors even when they are in contact with them. It is difficult to create oxygen vacancies in semiconductors.

[0139] <Low resistance area> In the regions 441 and 442, for example, the conductive films 421 and 423 are formed of the metal oxides 431 and 432. It is formed by extracting oxygen. The higher the temperature at which it is heated, the easier it is to extract oxygen. The manufacturing process of the transistor 400a includes several heating steps. Oxygen vacancies are formed at 441 and 442. In addition, hydrogen is generated at the oxygen vacancy sites by heating. As a result, the carrier concentration in the regions 441 and 442 increases. 41 and 442 have low resistance.

[0140] <Gate insulating film> The insulating film 406 preferably has a high dielectric constant. gallium oxide, hafnium oxide, oxides containing aluminum and hafnium, aluminum oxynitrides having silicon and hafnium; oxides having silicon and hafnium; Alternatively, it is preferable to form the insulating film from an oxynitride containing silicon and hafnium.

[0141] The insulating film 406 is a product of silicon oxide or silicon oxynitride and an insulator having a high dielectric constant. It is preferable that the layer structure be formed. Silicon oxide and silicon oxynitride are thermally stable. Therefore, by combining it with an insulator with a high dielectric constant, it is possible to obtain a thermally stable and high dielectric constant multilayer structure. It can be a layer structure. For example, aluminum oxide, gallium oxide or hafnium oxide. By having the metal oxide 433 on the metal oxide side, the This can prevent silicon from being mixed into the metal oxide 432.

[0142] For example, by having silicon oxide or silicon oxynitride on the metal oxide 433 side, the oxide Aluminum, gallium oxide or hafnium oxide, and silicon oxide or silicon oxynitride A trap center may be formed at the interface between the first and second electrodes. When the threshold voltage of a transistor can be shifted in the positive direction by capturing There is.

[0143] <Interlayer insulating film, protective insulating film> The insulating film 405 preferably has an insulator with a low relative dielectric constant. For example, the insulating film 405 The material may be silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, or resin. Alternatively, the insulating film 405 is preferably made of silicon oxide or silicon oxynitride. It is preferable that the insulating film has a laminate structure of a silicon oxide and a resin. It is thermally stable, so by combining it with resin, a laminated structure with thermal stability and low dielectric constant can be created. Examples of the resin include polyester, polyolefin, polya, etc. (nylon, aramid, etc.), polyimide, polycarbonate, or acrylic. do.

[0144] The insulating film 407 blocks oxygen, hydrogen, water, alkali metals, alkaline earth metals, etc. The insulating film 407 prevents oxygen from the metal oxide 430 from escaping to the outside. It is possible to prevent diffusion and the intrusion of hydrogen, water, etc. into the metal oxide 430 from the outside. The film 407 is formed of an insulator having, for example, a nitride, a nitride oxide, an oxide, or an oxynitride. The insulating material may be silicon nitride, silicon oxynitride, aluminum nitride, or the like. Aluminum, aluminum oxide nitride, aluminum oxide, aluminum oxynitride, gallium oxide , gallium oxide, yttrium oxide, yttrium oxide nitride, hafnium oxide, Hafnium nitride, etc. Aluminum oxide film is a thin film that can remove impurities such as hydrogen and moisture, and oxygen. Since it has a high blocking effect of preventing the penetration of both, it is suitable for use as the insulating film 407. .

[0145] The insulating film 407 is formed by using plasma containing oxygen, such as by sputtering or CVD. This makes it possible to add oxygen to the side surfaces and surfaces of the insulating films 405 and 406. After the insulating film 407 is formed, a second heat treatment is performed at any time. By the second heat treatment, oxygen added to the insulating films 405 and 406 is preferably The oxygen diffuses through the insulating film, reaches the metal oxide 430, and reduces the oxygen vacancies in the metal oxide 430. This makes it possible.

[0146] The insulating film 407 has a function of blocking oxygen and prevents oxygen from diffusing above the insulating film 407. Similarly, the insulating film 403 has a function of blocking oxygen, and oxygen is prevented from entering the insulating film. Prevents spreading below 403.

[0147] Note that the second heat treatment is performed so that oxygen added to the insulating films 405 and 406 is converted into the metal oxide 430. For example, the description of the first heat treatment can be referred to. Alternatively, the second heat treatment is preferably performed at a temperature lower than that of the first heat treatment. The temperature difference between the heat treatment and the second heat treatment may be 20° C. or more and 150° C. or less, and preferably The temperature is 40° C. or higher and 100° C. or lower. This prevents excess oxygen from being released from the insulating film 404. The second heat treatment can suppress the heat generation during the deposition of each layer. In some cases, this may not be necessary if the metal oxide can be used for both purposes. The oxide 430 is supplied with oxygen from above and below by the formation of the insulating film 407 and the second heat treatment. In addition, a film containing indium oxide, such as In-M-Zn oxide, can be used. By forming the insulating film 407 from the above, oxygen may be added to the insulating films 405 and 406 .

[0148] The insulating film 408 may be made of aluminum oxide, aluminum nitride oxide, magnesium oxide, or oxide. Silicon, silicon oxynitride, silicon nitride oxide, silicon nitride, gallium oxide, gallium oxide Rumanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, An insulator containing one or more selected from hafnium, tantalum oxide, and the like can be used. The insulating film 408 is made of a resin such as polyimide resin that can be used for the insulating film 405. The insulating film 408 may also be a stack of the above materials.

[0149] <<Transistor configuration example 2>> In the transistor 400a illustrated in FIG. 8, the conductive film 414 and the insulating films 402 and 403 are omitted. An example of this case is shown in FIG. 10A. FIG. 10A is a top view of a transistor 400b. 10B is a cross-sectional view taken along line A1-A2 in FIG. 10A, and FIG. 10C is a cross-sectional view taken along line A3-A4 in FIG. 10A. Cross-sectional view.

[0150] <<Transistor configuration example 3>> In the transistor 400a shown in FIG. 8, the conductive films 421 and 423 are gate electrodes (conductive The thickness of the film overlapping with the film 411 to 413 may be thinned. An example of this case is shown in FIG. FIG. 11A is a top view of transistor 400c. FIG. 11B is a top view of A1-A2 in FIG. FIG. 11C is a cross-sectional view taken along line A3-A4.

[0151] As shown in FIG. 11B, in the transistor 400c, the conductive film 4 21 is thinned and covered with a conductive film 422. Similarly, the portion overlapping the gate electrode The conductive film 423 is thinned and covered with the conductive film 424. By this, the distance between the gate electrode and the source electrode or the distance between the gate electrode and the drain electrode The distance between the gate electrode and the source and drain electrodes can be increased. This makes it possible to reduce the parasitic capacitance formed between the transistors. It will be possible to obtain a transistor.

[0152] <<Transistor configuration example 4>> 12A is a top view of transistor 400d, and 12B is a cross-sectional view of line A1-A2 of FIG. FIG. 12C is a cross-sectional view taken along line A3-A4. Transistor 400a and the like are transistors having an s-channel structure. In FIG. 00d, an insulating film 409 is provided in contact with the side surface of a conductive film 412 that constitutes a gate electrode. The insulating film 409 and the conductive film 412 are covered with the insulating film 407 and the insulating film 408. The insulating film 409 functions as a sidewall insulating film of the transistor 400d. Similarly to the transistor 400a, the transistor 400d also has a gate electrode formed of the conductive film 411 to the conductive film 412. A laminate of films 413 may also be used.

[0153] At least a part of the insulating film 406 and the conductive film 412 is a conductive film 414 and a metal oxide film 432. The side end of the conductive film 412 in the channel length direction and the side end of the insulating film 406 in the channel length direction overlap with each other. It is preferable that the side edges are approximately aligned. The conductive film 412 functions as a gate insulating film of the transistor 400d. It functions as such.

[0154] The metal oxide 432 overlaps with the conductive film 412 with the metal oxide 433 and the insulating film 406 interposed therebetween. The periphery of the metal oxide 431 roughly coincides with the periphery of the metal oxide 432. The outer periphery of the oxide 433 is located outside the outer periphery of the metal oxide 431 and the metal oxide 432. In this embodiment, the outer periphery of the metal oxide 433 is preferably larger than the outer periphery of the metal oxide 431. However, the transistor shown in this embodiment is not limited to this. For example, the outer periphery of metal oxide 431 may be located outside the outer periphery of metal oxide 433. In addition, the side edge of the metal oxide 431 and the side edge of the metal oxide 433 are substantially aligned with each other. It may also be in the form of

[0155] FIG. 12D shows a partial enlarged view of FIG. 12B. As shown in FIG. 12D, the metal oxide 430 has , regions 461a, 461b, 461c, 461d, and 461e are formed. Region 4 The regions 61b to 461e have a higher dopant concentration than the region 461a, and have a lower resistance. Furthermore, the regions 461b and 461c are connected to the regions 461d and 461e. For example, the region 461a has a higher hydrogen concentration and a lower resistance than the region 461b or 461c, a region having a dopant concentration of 5% or less relative to the maximum dopant concentration of the region 461b or 461c; % or less, or 1% or less. These may also be referred to as donors, acceptors, impurities or elements.

[0156] As shown in FIG. 12D, in the metal oxide 430, the region 461a is roughly adjacent to the conductive film 412. The regions 461b, 461c, 461d, and 461e are overlapping regions. The region 461b and the region 461c are regions excluding the region 461a. The upper surface of 433 contacts the insulating film 407. The upper surface of the oxide 433 contacts the insulating film 409 or the insulating film 406. That is, as shown in FIG. In this way, the boundary between the region 461b and the region 461d is the side edge of the insulating film 407 and the insulating film 409. The same applies to the boundary between region 461c and region 461e. Here, a part of the region 461d and a part of the region 461e overlap with the conductive film 412 of the metal oxide 432. For example, the region 461d and the region 461c are preferably overlapped with each other. The side edge of the region 461e in the channel length direction is spaced a distance d from the side edge of the conductive film 412. It is preferable that the insulating film 406 is located on the inner side of the conductive film 412. 406 and the distance d is 0.25H 406 <d<H 406 It is preferable that the following is satisfied.

[0157] In this manner, the metal oxide 430 is partially overlapped with the conductive film 412 in the region 461d and the region As a result, a channel forming region and a resistor region 461e of the transistor 400d are formed. The regions 461d and 461e are in contact with each other, and the regions 461d and 461e are in contact with each other. Since no high-resistance offset region is formed between transistor 400d and 461a, In addition, the on-current of the region 461d and the region 461e can be increased. By forming the side end portion in the longitudinal direction of the filter so as to satisfy the above range, the region 461d and the region 4 61e is formed too deep relative to the channel formation region, resulting in constant conduction. can also be prevented.

[0158] The regions 461b, 461c, 461d, and 461e are formed by ion implantation or the like. As a result, as shown in FIG. The boundary between the region 461a and the metal oxide 433 is a depth from the upper surface of the metal oxide 433 toward the lower surface of the metal oxide 431. As the distance increases, the area may approach the boundary between the area 461d and the area 461b. The distance d is the distance between the area 46 1d and the boundary between the region 461a and the conductive film 412 on the A1 side in the dashed line A1-A2 direction. Similarly, the boundary between the region 461e and the region 461a is the distance from the side edge of the metal oxide 4 As the depth increases from the upper surface of the metal oxide 431 toward the lower surface of the metal oxide 431, the regions 461e and 461f are In this case, the distance d is The boundary between the region 461e and the region 461a, which is closest to the innermost part of the conductive film 412, and the conductive film 41 2, the distance between the end of the side surface on the A2 side in the direction of the dashed dotted line A1-A2.

[0159] In this case, for example, the regions 461d and 461e formed in the metal oxide 431 are conductive. In some cases, the metal oxide 431 or the gold film 412 may not be formed in the region where the metal oxide 431 or the gold film 412 overlaps. At least a part of the region 461d and the region 461e formed in the metal oxide 432 is a conductive film 4 It is preferable that the second insulating film 12 is formed in the area overlapping the first insulating film 12.

[0160] In addition, the boundaries between the metal oxide 431, the metal oxide 432, and the metal oxide 433 and the insulating film 407 It is preferable that a low resistance region 451 and a low resistance region 452 are formed near the surface. The region 451 and the low resistance region 452 contain at least one of the elements contained in the insulating film 407. A part of the low resistance region 451 and the low resistance region 452 is a conductive film 412 of a metal oxide 432. It is preferable that the insulating layer 11 be in contact with the region (channel formation region) that overlaps with the insulating layer 11 or overlap with a part of the region. It is.

[0161] In addition, since the metal oxide 433 has a large area in contact with the insulating film 407, the low-resistance region 451 and The low resistance region 452 is easily formed in the metal oxide 433. The resistance region 451 and the low resistance region 452 are formed by the low resistance region 451 and the low resistance region 452 of the metal oxide 433. From a region other than the region 452 (for example, a region of the metal oxide 433 overlapping with the conductive film 412) The concentration of the element contained in the insulating film 407 is high.

[0162] A low resistance region 451 is formed in the region 461b, and a low resistance region 452 is formed in the region 461c. The ideal structure of the metal oxide 430 is, for example, a region with the highest concentration of the added element. The low-resistance regions 451 and 452 are the regions with the next highest concentration, the regions 461b and 461 The region 461 is the region that does not include the low resistance regions 451 and 452 of FIG. The additive element is a dopant for forming the regions 461b and 461c. The elements added to the low resistance regions 451 and 452 from the insulating film 407 correspond to this.

[0163] In addition, the transistor 400d is configured to have low resistance regions 451 and 452. However, the transistors described in this embodiment are not limited to those described above. When the resistance of the region 461c is sufficiently low, the low resistance region 451 and the low resistance region 452 are formed. There is no need.

[0164] <<Transistor configuration example 5>> An example of the configuration of a transistor is shown in FIG. 13B is a cross-sectional view taken along line y1-y2 of FIG. 13A, and FIG. 13C is a cross-sectional view taken along line x1-x2 of FIG. FIG. 13D is a cross-sectional view taken along line x3-x4.

[0165] The transistor 400e is an s-channel transistor, similar to the transistor 400a. The transistor 400e includes a conductive film 471 and a conductive film 472. The conductive films 471 and 472 function as a source electrode and a drain electrode, respectively. Similar to the transistor 400a, the gate electrode is a stack of the conductive films 411 to 413. This is also fine.

[0166] The metal oxide 430 is formed by stacking the metal oxide 431, the metal oxide 432, and the metal oxide 433 in this order. The conductive films 471 and 472 are formed by overlaying the metal oxide 431 and the metal oxide 4 The metal oxide 433 is provided on a stack of the metal oxides 431, 432. The insulating film 406 is formed so as to cover the metal oxide 471 and the conductive films 472. Here, the metal oxide 433 and the insulating film 406 are etched using the same mask. It is being checked.

[0167] The conductive films 471 and 472 are formed by stacking the metal oxide 431 and the metal oxide 432. Therefore, the conductive films 471 and 472 are made of gold. The metal oxide 431 and the metal oxide 432 do not have a region adjacent to the side of the metal oxide 431 and the metal oxide 432. For example, Through such steps, metal oxides 431 and 432 and conductive films 471 and 472 can be produced. Two-layer oxide semiconductor films constituting metal oxides 431 and 432 are formed. A single-layer or multi-layer conductive film is formed on the semiconductor film. This conductive film is etched to form a hard mask. The two-layer oxide semiconductor film is etched using this hard mask. A stack of metal oxide 431 and metal oxide 432 is formed. Next, the hard mask is etched. Then, conductive films 471 and 472 are formed.

[0168] Fourth embodiment In this embodiment, a device structure in which a Si transistor and an OS transistor are stacked is used. Here, the electronic device of the first embodiment will be described as an example. An example of the structure is shown below.

[0169] 14A and 14B are cross-sectional views showing the device structure of an electronic device, typically a circuit 13. (transistors M2, M4, and capacitive element C1). FIG. 14A shows the electronic device 100. FIG. 14B is a cross-sectional view in the channel length direction of a transistor constituting the transistor. 14A and 14B are cross-sectional views of the electronic device 100 in the channel width direction. The orientation of the transistors constituting the electronic device 100 is as shown in the figure. There may not be.

[0170] The electronic device 100 includes, from the bottom up, layers 781 to 789. The layer 781 is a substrate 700. a transistor M2 formed on a substrate 700; an element isolation layer 701; and a plug 710. Layer 781 contains a number of plugs, such as 711, for forming Si transistors, such as transistor M2. is the element layer in which

[0171] The substrate 700 may be a single crystal semiconductor substrate made of silicon or silicon carbide, or a polycrystalline semiconductor The substrate is a compound semiconductor substrate made of silicon germanium or an SOI substrate. The substrate 700 may be, for example, a glass substrate, a quartz substrate, or a plastic substrate. , metal substrates, flexible substrates, laminated films, paper containing fibrous materials, or base film Alternatively, a semiconductor element may be formed using a certain substrate, and then a different substrate may be used. In this embodiment, as an example, a single crystal silicon wafer is placed on the substrate 700. An example using Eha is shown.

[0172] FIG. 15 shows an example of the configuration of the transistor M2. FIG. 15A shows the channel length of the transistor M2. FIG. 15B shows a cross-sectional view of the transistor M2 in the channel width direction. The transistor M2 has a channel forming region 1793 provided in a well 1792 and a low A high-concentration impurity region 1794 and a high-concentration impurity region 1795 (collectively referred to as an impurity region) A conductive region 1796 is provided in contact with the impurity region, and a channel forming A gate insulating film 1797 is provided on the region 1793. A gate electrode 1790 and a sidewall insulating layer 1798 provided on the side of the gate electrode 1790. The conductive region 1796 has a sidewall insulating layer 1799. It may be used.

[0173] The channel forming region 1793 of the transistor M2 has a convex shape, and the side and top surfaces of the channel forming region 1793 are A gate insulating film 1797 and a gate electrode 1790 are provided on the gate insulating film 1797. A transistor having this structure is called a FIN type transistor. In the above example, a part of the SOI substrate is processed to form a convex portion. A semiconductor layer may be formed.

[0174] The transistor M2 is not limited to a FIN type transistor. For example, in FIG. It may be a planar transistor as shown in FIG. 15D. FIG. 15D is a cross-sectional view of transistor M1 in the channel length direction, and FIG. 15C is a cross-sectional view of transistor M2 in the channel width direction. FIG.

[0175] Layer 782 includes a number of interconnects, such as interconnects 730 and 731. Layer 783 includes plug 712. , 713, and a number of wirings (not shown).

[0176] The layer 784 includes the insulating films 702 to 705, the transistor M4, and the plugs 714 and 7 Layer 784 includes a plurality of plugs, such as transistor M4. Here, transistor M4 is transistor 400c. It has a device structure similar to that shown in FIG.

[0177] Layer 785 includes a number of interconnects, such as interconnects 732, 733, etc. Layer 786 includes plug 716. Layer 787 includes a plurality of plugs such as wiring 734, and a plurality of wirings (not shown). The layer 788 includes a capacitor element C1 and a plurality of plugs such as a plug 717. The layer 788 is an element layer in which the capacitive element C1 of the circuit 13 is formed. C1 includes an electrode 751, an electrode 752, and an insulating film 753. A layer 789 includes a wiring 735, etc. The wiring includes a plurality of wirings.

[0178] It is preferable that the insulating films 704 and 705 have a blocking effect against hydrogen, water, etc. Water, hydrogen, etc. are factors that generate carriers in oxide semiconductors. By providing a blocking layer against the Insulators that have a blocking effect against hydrogen, water, etc. include, for example, Aluminum oxide, aluminum oxynitride, gallium oxide, gallium oxynitride, yttrium oxide Hafnium oxide, hafnium oxide nitride, yttria stabilized Examples include yttrium-silicate zirconia (YSZ).

[0179] The wiring 730 to the wiring 735 and the plugs 710 to 717 are made of copper (Cu), W, Molybdenum (Mo), Gold (Au), Aluminum (Al), Manganese (Mn), titanium (Ti), tantalum (Ta), nickel (Ni), chromium (Cr), lead (Pb), tin (Sn), iron (Fe), and cobalt (Co) are low-resistance materials. It is preferable to use a single layer or a multilayer of a conductive film containing a metal or alloy, or a compound having these as a main component. In particular, high melting point materials such as tungsten and molybdenum, which have both heat resistance and electrical conductivity, are used. It is preferable to use a low-resistance conductive material such as aluminum or copper. Furthermore, when a Cu-Mn alloy is used, manganese oxide is formed at the interface with the insulator containing oxygen. Manganese oxide is preferred because it has the function of suppressing the diffusion of Cu.

[0180] In FIG. 14, the regions without symbols and hatching patterns are made of insulating material. The insulators include aluminum oxide, aluminum oxide nitride, and magnesium oxide. silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, gallium oxide , germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide The insulator contains one or more materials selected from the group consisting of zinc oxide, hafnium oxide, and tantalum oxide. In addition, the region may be made of polyimide resin, polyamide resin, acrylic resin, etc. Resins such as grease, siloxane resins, epoxy resins, and phenolic resins can also be used.

[0181] Fifth embodiment In this embodiment, a structure of an oxide semiconductor will be described. Semiconductors are divided into single-crystal oxide semiconductors and non-single-crystal oxide semiconductors. , CAAC-OS(c-axis-aligned crystalline oxide e semiconductor, polycrystalline oxide semiconductor, nc-OS (nanocry stalline oxide semiconductor), pseudo-amorphous oxide semiconductor body(a-like OS:amorphous-like oxide semicon From another point of view, the oxide semiconductor is an amorphous oxide semiconductor. Crystalline oxide semiconductors are classified into crystalline oxide semiconductors and other crystalline oxide semiconductors. Examples of the oxide semiconductors include single crystal oxide semiconductors, CAAC-OS, polycrystalline oxide semiconductors, and nc-OS. do.

[0182] In general, an amorphous structure is an isotropic, metastable arrangement of atoms that does not have a heterogeneous structure. The positions are not fixed, the bond angles are flexible, and there is short-range order but no long-range order. In other words, a stable oxide semiconductor is a completely amorphous It cannot be called an oxide semiconductor. The oxide semiconductor, which has a periodic structure in a microscopic region, is a completely amorphous oxide semiconductor. On the other hand, a-like OS is not isotropic, but has voids. In terms of being unstable, a-like OS is physically amorphous. It is close to a high-quality oxide semiconductor.

[0183] <caac-os> CAAC-OS is an oxide semiconductor that has multiple crystal parts (also called pellets) aligned along the c-axis. It is a type of conductor.

[0184] (XRD) CAAC-OS was analyzed by X-ray diffraction (XRD). For example, the InGaZnO4, which is classified into the space group R-3m, The structure of CAAC-OS with crystals is analyzed by the out-of-plane method. A peak appears at a diffraction angle (2θ) of about 31°. This peak is due to the formation of InGaZnO4. Since the crystal orientation is attributed to the (009) plane of the CAAC-OS, the crystal orientation is considered to be c-axis oriented. The c-axis is approximately perpendicular to the surface on which the CAAC-OS film is formed (also referred to as the surface on which the CAAC-OS film is formed) or to the upper surface. In addition to the peak at 2θ of 31°, there is also a peak at 2θ of 3 A peak may also appear around 6°. The peak at 2θ around 36° is in the space group Fd-3 m. Therefore, CAAC-OS does not show this peak. It is preferred.

[0185] On the other hand, in-pla, X-rays are incident on the CAAC-OS in a direction parallel to the surface on which the film is to be formed. When the structure is analyzed by the NE method, a peak appears at 2θ of about 56°. This peak is I The lattice constant is assigned to the (110) plane of the nGaZnO4 crystal. The 2θ is fixed at around 56°. The analysis (φ scan) is performed while rotating the sample around the axis (φ axis) of the normal vector of the sample surface. No clear peaks were observed when the 2θ angle was set to approximately 56° for single-crystal InGaZnO4. When the φ scan was performed with the sample fixed close to the substrate, six peaks were observed that were assigned to the crystal plane equivalent to the (110) plane. Therefore, the structure analysis using XRD shows that CAAC-OS has a-axis and It can be seen that the orientation of the b-axis is irregular.

[0186] (Electron Diffraction) For example, for CAAC-OS with InGaZnO4 crystals, When an electron beam with a probe diameter of 300 nm is incident parallel to the grown surface, a diffraction pattern (selected field of view) This diffraction pattern may show a pattern similar to that of InGaZ. The spots are due to the (009) plane of the nO4 crystal. However, the pellets contained in the CAAC-OS have a c-axis orientation, and the c-axis is aligned with the surface on which the film is formed or the upper surface. The probe diameter is 300 nm and is perpendicular to the sample surface. When an electron beam is incident, a ring-shaped diffraction pattern appears. Therefore, when the probe diameter is 3 The a-axis of the crystal part in CAAC-OS was also confirmed by electron diffraction using a 0.00 nm electron beam. It can be seen that the b-axis has no orientation.

[0187] (High resolution TEM image) Transmission Electron Microscope (TEM) A combined analysis image (TE) of the bright-field image and diffraction pattern of CAAC-OS was obtained by using a microscope. When observing the M image, multiple crystals can be confirmed. Even in a TEM image, the boundaries between crystalline parts, that is, grain boundaries (also called grain boundaries), are not visible. ) may not be clearly identified. Therefore, the grain boundaries of CAAC-OS are It can be said that the decrease in electron mobility caused by the sphericity is unlikely to occur. Spherical Aberration Corrector function Here, a high-resolution TEM image using a spherical aberration correction function is obtained by using Cs This is called a corrected high-resolution TEM image.

[0188] A high-resolution TEM image of the cross section of CAAC-OS observed from a direction approximately parallel to the sample surface revealed that The crystals, which are regions where metal atoms are arranged in layers, can be seen. It has been confirmed that there are crystal parts of 3 nm or more and crystal parts of 5 nm or more. The part can also be called a nanocrystal (nc). -OS, CANC (C-Axis Aligned nanocrystals) The crystal part is a surface on which the CAAC-OS is formed or a top surface of the CAAC-OS. It reflects the unevenness and is parallel to the surface on which the CAAC-OS is formed or the top surface.

[0189] A Cs-corrected high-resolution TEM image of the CAAC-OS plane observed from a direction approximately perpendicular to the sample surface. By image processing, it can be confirmed that the crystals are hexagonal. The shape is not necessarily a regular hexagon, but is often a non-regular hexagon. As follows:

[0190] A fast Fourier transform (FFT) image is obtained by processing the Cs-corrected high-resolution TEM image. In the acquired FFT image, the origin is used as the reference point, and the distance is 2.8 nm. -1 From 5.0 nm -1 Between The masked FFT image is then subjected to inverse fast Fourier transform (IFF T) to obtain an image (FFT filtered image). The FFT filtered image is This image shows the lattice arrangement because it is an image of periodic components extracted from a Cs-corrected high-resolution TEM image. do.

[0191] No clear grain boundaries were identified in the acquired FFT filtered image. The existence of the angular crystals suppresses the formation of grain boundaries by distorting the lattice arrangement. This is because the atomic arrangement is not dense in the ab-plane direction. In addition, the substitution of metal elements changes the bond distance between atoms, and this leads to the formation of CAAC This is thought to be because -OS can tolerate distortion.

[0192] As described above, the CAAC-OS has a c-axis orientation and multiple crystals in the ab-plane direction. A number of crystal parts (nanocrystals) are connected to form a distorted crystal structure. C-OS, CAA crystal(c-axis-aligned ab-pla It can also be called an oxide semiconductor having a ne-anchored crystal. .

[0193] CAAC-OS is a highly crystalline oxide semiconductor. The crystallinity of oxide semiconductors is improved by the incorporation of impurities. CAAC-OS is a material that can be degraded by impurities and defects (oxidation, etc.). The oxide semiconductor can be said to have few electron vacancies.

[0194] The impurities are elements other than the main components of the oxide semiconductor, such as hydrogen, carbon, silicon, and transition metals. For example, silicon and other metal elements that form oxide semiconductors have a higher affinity with oxygen than do metal elements that form oxide semiconductors. Elements with strong bonding forces disrupt the atomic arrangement of oxide semiconductors by taking oxygen from them. In addition, heavy metals such as iron and nickel, argon, carbon dioxide, etc. Since the atomic radius (or molecular radius) of elements is large, they disrupt the atomic arrangement of oxide semiconductors and cause crystal This can lead to a decline in sexuality.

[0195] When an oxide semiconductor has impurities or defects, its characteristics may vary due to light, heat, etc. For example, impurities contained in oxide semiconductors can act as carrier traps or can trap carriers. For example, oxygen vacancies in oxide semiconductors can become carrier traps. In some cases, they act as carrier generation sources by capturing hydrogen.

[0196] CAAC-OS, which has few impurities and oxygen vacancies, is an oxide semiconductor with low carrier density. Specifically, 8×10 11 pieces / cm 3 Less than 1 x 10 11 / cm 3 Less than More preferably, 1×10 10 pieces / cm 3 Less than 1 x 10 -9 pieces / cm 3 More than Such an oxide semiconductor can be a high-purity intrinsic or The CAAC-OS is essentially a high-purity intrinsic oxide semiconductor. In other words, it can be said that the oxide semiconductor has stable characteristics.

[0197] <nc-os> (XRD) For example, when the structure of nc-OS is analyzed by the out-of-plane method, the orientation In other words, the crystals of nc-OS do not have any orientation. The nc-OS with GaZnO4 crystals was sliced, and the area with a thickness of 34 nm was When an electron beam with a probe diameter of 50 nm is incident parallel to the grown surface, a ring-shaped diffraction pattern is observed. In addition, when an electron beam with a probe diameter of 1 nm is incident on the same sample, a ring-shaped Multiple spots are observed within the area. Therefore, nc-OS is No order was observed when an electron beam with a probe diameter of 1 nm was injected. The order is confirmed by injecting light.

[0198] In addition, when an electron beam with a probe diameter of 1 nm is incident on an area with a thickness of less than 10 nm, In some cases, electron diffraction patterns are observed in which the spots are arranged in a roughly regular hexagonal shape. In the range of thickness less than 10 nm, the nc-OS has highly ordered regions, i.e., crystals. In addition, because the crystals are oriented in various directions, regular electron diffraction patterns are not observed. There are also areas where no precipitation is observed.

[0199] (High resolution TEM image) In the Cs-corrected high-resolution TEM image of the cross section of nc-OS, the crystals can be seen in the following areas: It can be seen that there are areas where crystals are clearly visible, and areas where no clear crystals can be seen. The crystal parts contained in the are 1 nm to 10 nm in size, and especially 1 nm to 3 nm in size. In most cases, the size of the crystal part is greater than 10 nm and less than 100 nm. The oxide semiconductor below is called a microcrystalline oxide semiconductor (microcrystalline oxide In high-resolution TEM images, nc In some cases, the grain boundaries of the CAAC-OS cannot be clearly identified. The crystal part of nc-OS may have the same origin as that of the crystalline part of the pellet. It is sometimes called a 't'.

[0200] In this way, the nc-OS can be used in microscopic regions (e.g., regions of 1 nm to 10 nm, especially The atomic arrangement has periodicity in the region of 1 nm to 3 nm. There is no regularity in the crystal orientation between different crystal parts. Therefore, no orientation is observed throughout the film. Therefore, depending on the analytical method, nc-OS may be classified as a-like OS or amorphous acid. In some cases, it is difficult to distinguish them from semiconductors made of ferroelectrics. Therefore, nc-OS is a Random Aligned Nanoc oxide semiconductor having rhystals or NANC (Non-Aligned na Alternatively, the oxide semiconductor may be referred to as an oxide semiconductor having no crystals.

[0201] The structure of nc-OS is more ordered than that of amorphous oxide semiconductors. , the density of defect states is lower than that of a-like OS and amorphous oxide semiconductors. Since the OS has no regularity in the crystal orientation between different crystal parts, the nc-OS is CAAC-O The defect level density is higher than that of S.

[0202] <a-like OS> The a-like OS is an oxide semiconductor that has a structure between the nc-OS and the amorphous oxide semiconductor. For example, the structural regularity of a-like OS is lower than that of nc-OS, but The a-like OS is higher than the nc-OS and CAAC-OS. In addition, a-like OS has a more unstable structure than nc-OS and CAAC. This is because a-like OS has porosity (low density area). The porosity can be confirmed by high-resolution cross-sectional TEM images.

[0203] The density of a-like OS is 78.6% to 92.3% of the density of a single crystal of the same composition. The densities of the nc-OS and CAAC-OS are 92 times smaller than the densities of single crystals with the same composition. 0.3% or more and less than 100%. An oxide semiconductor whose density is less than 78% of the density of a single crystal is Therefore, the film formation itself is difficult.

[0204] For example, the density of single crystal InGaZnO4 with a rhombohedral crystal structure is 6.357 g / cm 3 in Therefore, in the case of an oxide semiconductor that satisfies the atomic ratio of In:Ga:Zn=1:1:1, , the density of a-like OS is 5.0g / cm 3 More than 5.9g / cm 3 Less than nc The density of -OS and CAAC-OS is 5.9g / cm 3 More than 6.3g / cm 3 Less than be.

[0205] If single crystals of the same composition do not exist, single crystals of different compositions can be combined in any ratio. By doing so, it is possible to estimate the density equivalent to a single crystal with a desired composition. For example, the weighted average density of single crystals with different compositions is calculated based on the ratio of the combination of these single crystals. The density can be estimated by combining as few types of single crystals as possible. It is preferable to have

[0206] As described above, oxide semiconductors have various structures and each has various characteristics. For example, an oxide semiconductor film used in a semiconductor device such as an OS transistor can be formed by, for example, CA A single layer film made of AC-OS, nc-OS, a-like OS, or amorphous oxide semiconductor. Alternatively, a stacked film composed of oxide semiconductors having different structures may be used.

[0207] The following are matters related to this specification. In this specification, the terms "first," "second," and " Ordinal numbers such as "third" may be used to indicate order. In some cases, ordinal numbers are used to avoid confusion, in which case the use of ordinal numbers limits the number of components. In addition, for example, "first" may be replaced with "second" or By replacing this with "third," one embodiment of the present invention can be described.

[0208] In this specification, the terms "above" and "below" that indicate the positional relationship between components are used. In some cases, the above is used for convenience in describing the drawings with reference to the drawings. The relationship changes depending on the direction in which each component is depicted. The above words are not limited to those used above, but can be rephrased appropriately depending on the situation.

[0209] In this specification, the words "film" and "layer" may be used interchangeably. For example, the term "conductive layer" may be used interchangeably with the term "conductive layer" as appropriate. In some cases, it may be possible to change the term to "conductive film". For example, the term "insulating film" may be used. It may be possible to change the term to "insulating layer."

[0210] Voltage is the potential difference between a certain potential and a reference potential (e.g., ground potential or source potential). Therefore, voltage can be called potential. Therefore, even if it is written as ground potential (GND), it does not necessarily mean 0V. Sometimes it has no taste.

[0211] In the drawings, the size, layer thickness, or area may be exaggerated for clarity. Therefore, the scale is not necessarily limited to that shown in the drawings. The figures are not limited to the shapes or values ​​shown in the drawings. For example, the signal due to noise may be Variations in signal, voltage, or current, or timing differences can include current variations, etc.

[0212] In this specification, "parallel" means that two straight lines are arranged at an angle of -10° or more and 10° or less. Therefore, it includes the case where the angle is between -5° and 5°. "Parallel" refers to two lines that are arranged at an angle between -30° and 30°. Also, "perpendicular" means that two straight lines are arranged at an angle of 80° or more and 100° or less. Therefore, it also includes the case where the angle is between 85° and 95°. This refers to a state in which two straight lines are arranged at an angle of 60° or more and 120° or less.

[0213] In addition, in this specification, when the crystal is a trigonal or rhombohedral crystal, it is represented as a hexagonal crystal system. . [Explanation of symbols]

[0214] Circuits 10, 11, and 13 30-35 Memory Cells 100―102 Electronic equipment 111 Artificial Neural Array (ANA) 112 Line Decoder 113 Column Decoder 114 Input circuit 115 Output circuit 116 Analog signal processing circuit 130 Memory 131 Memory Cell Array 132 Line Decoder 133 Column Decoder 140 Wiring switch array 141 Wiring Switch 144-146 Wiring < / ana>

Claims

1. Multiple circuits are arranged in a matrix, The circuit comprises: a capacitor having one electrode electrically connected to a node and the other electrode electrically connected to a wiring; a transistor to which a signal corresponding to a weight value is inputted to one of a source or a drain, and the other of the source or the drain is electrically connected to the node; the transistor includes an oxide semiconductor containing at least one of indium and zinc in a channel formation region; An electronic device in which an input value which is an analog voltage signal that is not a discrete value is input to the circuit from the wiring, and which outputs a calculation result based on the input value input from the wiring and the potential held at the node.

2. Multiple circuits are arranged in a matrix, The circuit comprises: a capacitor having one electrode electrically connected to a node and the other electrode electrically connected to a wiring; a first transistor, one of a source or a drain of which receives a signal corresponding to a weight value and the other of which is electrically connected to the node; a second transistor having a gate electrically connected to the node; the first transistor has a channel formation region formed of an oxide semiconductor containing at least one of indium and zinc; the second transistor has silicon in a channel formation region; An electronic device in which an input value which is an analog voltage signal that is not a discrete value is input to the circuit from the wiring, and a calculation result based on the input value input from the wiring and the potential held at the node is output from the source or drain of the second transistor.

3. Multiple circuits are arranged in a matrix, The circuit comprises: a capacitor having one electrode electrically connected to a node and the other electrode electrically connected to a wiring; a transistor to which a signal corresponding to a weight value is inputted to one of a source or a drain, and the other of the source or the drain is electrically connected to the node; the transistor includes an oxide semiconductor containing at least one of indium and zinc in a channel formation region; An electronic device in which an input value which is an analog voltage signal having a continuous value is input to the circuit from the wiring, and which outputs a calculation result based on the input value input from the wiring and the potential held at the node.

4. Multiple circuits are arranged in a matrix, The circuit comprises: a capacitor having one electrode electrically connected to a node and the other electrode electrically connected to a wiring; a first transistor, one of a source or a drain of which receives a signal corresponding to a weight value and the other of which is electrically connected to the node; a second transistor having a gate electrically connected to the node; the first transistor has a channel formation region formed of an oxide semiconductor containing at least one of indium and zinc; the second transistor has silicon in a channel formation region; An electronic device in which an input value which is an analog voltage signal which is a continuous value is input to the circuit from the wiring, and a calculation result based on the input value input from the wiring and the potential held at the node is output from the source or drain of the second transistor.

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