Semiconductor memory device and method of manufacturing the semiconductor memory device

Abstract

To provide a semiconductor memory device capable of improving fatigue characteristics and imprint characteristics, and a method of manufacturing the semiconductor memory device.SOLUTION: A semiconductor memory device has a transistor and a ferroelectric capacitor connected to the transistor. The ferroelectric capacitor has: a first electrode and a second electrode, one of which is connected to the transistor; a PZT-based first ferroelectric film provided between the first electrode and the second electrode; and a PZT-based second ferroelectric film provided between the first electrode and the first ferroelectric film. The second ferroelectric film contains, as an additive, La, Ca, Ir, or Ru, or any combination thereof, and Sr. A concentration of each of La, Ca, Ir, Ru, and Sr in the first ferroelectric film is lower than a concentration of each of La, Ca, Ir, Ru, and Sr in the second ferroelectric film. The semiconductor memory device can be used, for example, as a nonvolatile memory.SELECTED DRAWING: Figure 8

Description

[Technical field]

[0001] The present disclosure relates to a semiconductor memory device and a method for manufacturing a semiconductor memory device. [Background technology]

[0002] Ferroelectric memories having ferroelectric capacitors are known as one type of semiconductor memory device. In one example of the ferroelectric capacitor, a PZT film containing no additive and a PZT-based film containing an additive such as La are provided between an upper electrode and a lower electrode. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 10-335596 [Patent Document 2] JP 2007-103722 A [Patent Document 3] Special Publication No. 2008-522426 Summary of the Invention [Problem to be solved by the invention]

[0004] In recent years, there has been an increasing demand for improved fatigue and imprint characteristics of ferroelectric capacitors.

[0005] An object of the present disclosure is to provide a semiconductor memory device and a method for manufacturing a semiconductor memory device that can improve fatigue characteristics and imprint characteristics. [Means for solving the problem]

[0006] According to one embodiment of the present disclosure, there is provided a semiconductor memory device comprising: a transistor; and a ferroelectric capacitor connected to the transistor, the ferroelectric capacitor comprising a first electrode and a second electrode, one of which is connected to the transistor, a PZT-based first ferroelectric film provided between the first electrode and the second electrode, and a PZT-based second ferroelectric film provided between the first electrode and the first ferroelectric film, the second ferroelectric film containing La, Ca, Ir, or Ru or any combination thereof, and Sr as an additive, and the respective concentrations of La, Ca, Ir, Ru, and Sr in the first ferroelectric film are lower than the respective concentrations of La, Ca, Ir, Ru, and Sr in the second ferroelectric film. Effect of the Invention

[0007] According to the present disclosure, it is possible to improve fatigue properties and imprint properties. [Brief description of the drawings]

[0008] [Figure 1] 1 is a cross-sectional view showing a semiconductor memory device according to a first embodiment. [Diagram 2] 1A to 1C are cross-sectional views (part 1) illustrating a method for manufacturing a semiconductor memory device according to a first embodiment. [Diagram 3] 5A to 5C are cross-sectional views (part 2) illustrating the method for manufacturing the semiconductor memory device according to the first embodiment. [Figure 4] 5A to 5C are cross-sectional views (part 3) illustrating the method for manufacturing the semiconductor memory device according to the first embodiment. [Diagram 5] FIG. 11 is a cross-sectional view showing a semiconductor memory device according to a second embodiment. [Figure 6] 11A to 11C are cross-sectional views (part 1) illustrating a method for manufacturing a semiconductor memory device according to a second embodiment. [Figure 7] 11A to 11C are cross-sectional views (part 2) illustrating the method for manufacturing the semiconductor memory device according to the second embodiment. [Figure 8] FIG. 11 is a cross-sectional view showing a semiconductor memory device according to a third embodiment. [Figure 9]11A to 11C are cross-sectional views (part 1) illustrating a method for manufacturing a semiconductor memory device according to a third embodiment. [Figure 10] 13A to 13C are cross-sectional views (part 2) illustrating the method for manufacturing the semiconductor memory device according to the third embodiment. [Figure 11] FIG. 1 is a cross-sectional view showing the structure of Sample No. 1. [Figure 12] FIG. 1 is a cross-sectional view showing the configuration of Sample No. 2. [Figure 13] FIG. 13 is a diagram showing the measurement results of polarization characteristics in a first test. [Figure 14] FIG. 1 is a diagram showing an example of a hysteresis loop. [Figure 15] FIG. 1 is a graph showing the measurement results of fatigue properties in a first test. [Figure 16] FIG. 13 is a diagram showing the measurement results of imprint characteristics in a first test. [Figure 17] FIG. 13 is a diagram showing the measurement results of leakage current in a first test. [Figure 18] FIG. 13 is a diagram showing the measurement results of polarization characteristics in a second test. [Figure 19] FIG. 13 is a graph showing the measurement results of fatigue properties in a second test. [Figure 20] FIG. 13 is a diagram showing the measurement results of imprint characteristics in a second test. [Figure 21] FIG. 1 shows the measurement results of polarization characteristics in the third test (part 1). [Figure 22] FIG. 2 is a second diagram showing the measurement results of the polarization characteristics in the third test. [Diagram 23] FIG. 13 is a diagram showing the measurement results of imprint characteristics in a third test. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. In this specification and the drawings, components having substantially the same functional configurations are denoted by the same reference numerals, and redundant description may be omitted.

[0010] (First embodiment) First, a first embodiment will be described. The first embodiment relates to a semiconductor memory device including a ferroelectric capacitor, that is, a ferroelectric memory. Fig. 1 is a cross-sectional view showing the semiconductor memory device according to the first embodiment.

[0011] 1, the semiconductor memory device 100 according to the first embodiment includes a transistor Tr1, a transistor Tr2, a ferroelectric capacitor Cap1, and a ferroelectric capacitor Cap2. The ferroelectric capacitor Cap1 is connected to the transistor Tr1, and the ferroelectric capacitor Cap2 is connected to the transistor Tr2.

[0012] The semiconductor memory device 100 has a semiconductor substrate 1, a p-type well 2, two n-type source regions 15, and an n-type drain region 16. The semiconductor substrate 1 is, for example, a silicon (Si) substrate. An element isolation insulating film 3 is formed in the well 2, and an element active region is defined by the element isolation insulating film 3. The source region 15 and the drain region 16 are provided in the element active region. The source region 15 and the drain region 16 are provided in the surface layer portion of the well 2, and the drain region 16 is provided between the two source regions 15. One of the source regions 15 is included in the transistor Tr1, the other source region 15 is included in the transistor Tr2, and the drain region 16 is shared by the transistors Tr1 and Tr2. A silicide layer 17 is formed on the upper surface of the source region 15, and a silicide layer 18 is formed on the upper surface of the drain region 16.

[0013] Each of the transistors Tr1 and Tr2 has a gate insulating film 11, a gate electrode 12, a silicide layer 13, and a sidewall insulating film 14. The gate insulating film 11 is provided on a channel between a source region 15 and a drain region 16, the gate electrode 12 is provided on the gate insulating film 11, and the silicide layer 13 is formed on the upper surface of the gate electrode. The sidewall insulating film 14 covers the side surfaces of the stack of the gate insulating film 11, the gate electrode 12, and the silicide layer 13. The gate insulating film 11 and the sidewall insulating film 14 are insulating films such as silicon oxide (SiO2) films. The gate electrode 12 is, for example, a polycrystalline silicon (polysilicon) film.

[0014] The semiconductor memory device 100 has a cover film 21, an interlayer insulating film 22, an etching stopper film 23, an interlayer insulating film 24, an oxidation suppression film 25, and an interlayer insulating film 26. The cover film 21 covers the transistors Tr1 and Tr2. The cover film 21 is an insulating film such as a silicon nitride (SiN) film. The interlayer insulating film 22 is provided on the cover film 21. The interlayer insulating film 22 is an insulating film such as a SiO2 film. The etching stopper film 23 is provided on the interlayer insulating film 22. The etching stopper film 23 is an insulating film such as a SiN film. The interlayer insulating film 24 is provided on the etching stopper film 23. The interlayer insulating film 24 is an insulating film such as a SiO2 film. The oxidation suppression film 25 is provided on the interlayer insulating film 24. The oxidation suppression film 25 is an insulating film such as a SiN film. The interlayer insulating film 26 is provided on the oxidation suppression film 25. The interlayer insulating film 26 is an insulating film such as a SiO2 film.

[0015] The semiconductor memory device 100 has two conductive plugs 31 and a conductive plug 32. One conductive plug 31 penetrates the interlayer insulating film 22 and the cover film 21, contacts the silicide layer 17 of the transistor Tr1, and is electrically connected to the source region 15 of the transistor Tr1. The other conductive plug 31 penetrates the interlayer insulating film 22 and the cover film 21, contacts the silicide layer 17 of the transistor Tr2, and is electrically connected to the source region 15 of the transistor Tr2. The conductive plug 32 penetrates the interlayer insulating film 22 and the cover film 21, contacts the silicide layer 18, and is electrically connected to the drain region 16. The conductive plugs 31 and 32 have a conductive film such as a tungsten (W) film.

[0016] The semiconductor memory device 100 has a wiring 33 and two conductive plugs 34. The wiring 33 penetrates the interlayer insulating film 24 and the etching stopper film 23, contacts the conductive plug 32, and is electrically connected to the drain region 16. The wiring 33 is covered with an oxidation suppression film 25. One conductive plug 34 penetrates the interlayer insulating film 26, the oxidation suppression film 25, the interlayer insulating film 24, and the etching stopper film 23, contacts one conductive plug 31, and is electrically connected to the source region 15 of the transistor Tr1. The other conductive plug 34 penetrates the interlayer insulating film 26, the oxidation suppression film 25, the interlayer insulating film 24, and the etching stopper film 23, contacts the other conductive plug 31, and is electrically connected to the source region 15 of the transistor Tr2. The wiring 33 and the conductive plug 34 have a conductive film such as a W film. The wiring 33 is used as a bit line.

[0017] Each of the ferroelectric capacitors Cap1 and Cap2 includes a lower electrode 41, a ferroelectric film 42, a ferroelectric film 43, and an upper electrode 45.

[0018] The lower electrode 41 of the ferroelectric capacitor Cap1 contacts one of the conductive plugs 34 and is electrically connected to the source region 15 of the transistor Tr1. The lower electrode 41 of the ferroelectric capacitor Cap2 contacts one of the conductive plugs 34 and is electrically connected to the source region 15 of the transistor Tr2. The lower electrode 41 includes, for example, an iridium (Ir) film. The thickness of the lower electrode 41 is, for example, about 50 nm to 200 nm. In this embodiment, the lower electrode 41 is an example of a first electrode.

[0019] The ferroelectric film 42 is provided on the lower electrode 41. The ferroelectric film 42 is in direct contact with the lower electrode 41. The ferroelectric film 42 is a lead zirconate titanate (PZT)-based ferroelectric film containing an additive. The ferroelectric film 42 contains lanthanum (La), calcium (Ca), iridium (Ir), ruthenium (Ru), or any combination thereof, and strontium (Sr) as an additive. The thickness of the ferroelectric film 42 is, for example, 0.5 nm or more and 10 nm or less. In this embodiment, the ferroelectric film 42 is an example of a second ferroelectric film.

[0020] For example, the ferroelectric film 42 contains La, Ca, Ir, or Ru, or any combination thereof, at a total concentration of 0.1 mol % or more, and Sr at a concentration of 0.5 mol % to 5 mol % or less. For example, the concentration of La in the ferroelectric film 42 is 5 mol % or less, the concentration of Ca is 8% or less, the concentration of Ir is 1% or less, and the concentration of Ru is 1% or less.

[0021] The ferroelectric film 43 is provided on the ferroelectric film 42. The ferroelectric film 43 is in direct contact with the ferroelectric film 42. The ferroelectric film 43 is a PZT-based ferroelectric film. The ferroelectric film 43 does not contain any additives. The thickness of the ferroelectric film 43 is, for example, not less than 40 nm and not more than 70 nm. In this embodiment, the ferroelectric film 43 is an example of a first ferroelectric film.

[0022] The upper electrode 45 is provided on the ferroelectric film 43. The upper electrode 45 is in direct contact with the ferroelectric film 43. The upper electrode 45 includes, for example, an Ir film. The upper electrode 45 has a thickness of, for example, about 50 nm to 200 nm. In this embodiment, the upper electrode 45 is an example of a second electrode.

[0023] Next, a method for manufacturing the semiconductor memory device 100 according to the first embodiment will be described. Figures 2 to 4 are cross-sectional views showing the method for manufacturing the semiconductor memory device 100 according to the first embodiment.

[0024] 2, an element isolation insulating film 3 and transistors Tr1 and Tr2 are formed on a semiconductor substrate 1. Next, a cover film 21 and an interlayer insulating film 22 are formed, conductive plugs 31 and 32 are formed, an etching stopper film 23 and an interlayer insulating film 24 are formed, wiring 33 is formed, an oxidation suppression film 25 and an interlayer insulating film 26 are formed, and a conductive plug 34 is formed.

[0025] 3, a lower electrode 41A is formed on the interlayer insulating film 26 and the conductive plug 34, a ferroelectric film 42A is formed on the lower electrode 41A, a ferroelectric film 43A is formed on the ferroelectric film 42A, and an upper electrode 45A is formed on the ferroelectric film 42A. After that, the lower electrode 41 is formed from the lower electrode 41A, the ferroelectric film 42 is formed from the ferroelectric film 42A, the ferroelectric film 43 is formed from the ferroelectric film 43A, and the upper electrode 45 is formed from the upper electrode 45A. For example, the lower electrode 41A, the ferroelectric film 42A, and the upper electrode 45A can be formed by a sputtering method, and the ferroelectric film 43A can be formed by a metal organic chemical vapor deposition (MOCVD) method. The ferroelectric film 42A formed by the sputtering method is amorphous. Therefore, between the formation of the ferroelectric film 42A and the formation of the ferroelectric film 43A, annealing is performed to crystallize the ferroelectric film 42A. For this heat treatment, for example, rapid thermal annealing (RTA) is performed in a mixed gas atmosphere of inert gas and oxygen (O2) gas at a temperature of, for example, 400° C. to 800° C. As the inert gas, argon (Ar) gas or nitrogen (N2) gas can be used.

[0026] Thereafter, the stack of the upper electrode 45A, the ferroelectric film 43A, the ferroelectric film 42A, and the lower electrode 41A is etched. As a result, as shown in Fig. 4, ferroelectric capacitors Cap1 and Cap2 each having the upper electrode 45, the ferroelectric film 43, the ferroelectric film 42, and the lower electrode 41 are formed. Then, a protective film 48 is formed to cover the ferroelectric capacitors Cap1 and Cap2.

[0027] Next, the interlayer insulating film 27, the conductive plugs 35, the wiring 50, and the interlayer insulating film 28 are formed (see FIG. 1).

[0028] In this manner, the semiconductor memory device 100 according to the first embodiment can be manufactured.

[0029] In the semiconductor memory device 100 according to the first embodiment, the ferroelectric film 42 is a PZT-based film containing additives, so that the fatigue characteristics and imprint characteristics can be improved. In particular, Sr contributes to the improvement of the fatigue characteristics and imprint characteristics. However, if only Sr is contained, it is difficult to sufficiently improve the fatigue characteristics and imprint characteristics while suppressing the decrease in the amount of inversion charge. In the semiconductor memory device 100, La, Ca, Ir, Ru, or any combination thereof is further contained, so that the fatigue characteristics and imprint characteristics can be further improved while suppressing the decrease in the amount of inversion charge. In addition, if the ferroelectric film between the lower electrode 41 and the upper electrode 45 is only the ferroelectric film 42, there is a risk that the amount of inversion charge will decrease, but the semiconductor memory device 100 has the ferroelectric film 43, which is a PZT film containing no additives, so that the decrease in the amount of inversion charge can be suppressed.

[0030] The Sr concentration in the ferroelectric film 42 is preferably 0.5 mol % or more and 5 mol % or less. If the Sr concentration is lower than 0.5 mol %, sufficient fatigue characteristics and imprint characteristics may not be obtained, and if the Sr concentration is higher than 5 mol %, the amount of inversion charge is likely to decrease. The Sr concentration in the ferroelectric film 42 is more preferably 1 mol % or more and 4 mol % or less, and further preferably 2 mol % or more and 3 mol % or less.

[0031] The concentration of La, Ca, Ir, or Ru, or any combination thereof, in the ferroelectric film 42 is preferably 0.1 mol% or more in total. If the concentration is lower than 0.1 mol%, sufficient fatigue characteristics and imprint characteristics may not be obtained. The concentration of La, Ca, Ir, or Ru, or any combination thereof, in the ferroelectric film 42 is more preferably 0.5 mol% or more, and further preferably 1 mol% or more. For example, La tends to contribute to improving fatigue characteristics and the amount of inversion charge, Ca tends to contribute to improving fatigue characteristics and imprint characteristics, and Ir and Ru tend to contribute to improving the amount of inversion charge. When the ferroelectric film 42 contains Ir and Ru, even if the concentration of Sr is relatively high in order to improve the fatigue characteristics and imprint characteristics, the decrease in the amount of inversion charge can be suppressed.

[0032] The ferroelectric film 43 may be a PZT-based film containing a small amount of additives, and if the concentrations of La, Ca, Ir, Ru, and Sr in the ferroelectric film 43 are lower than the concentrations of La, Ca, Ir, Ru, and Sr in the ferroelectric film 42, the effect of suppressing a decrease in the amount of inversion charge can be obtained.

[0033] The ratio of the Zr content to the Ti content in the ferroelectric film 43 may be different from the ratio of the Zr content to the Ti content in the ferroelectric film 42. For example, the ratio of the Zr content to the Ti content in the ferroelectric film 43 (Zr / Ti ratio) may be larger than the Zr / Ti ratio in the ferroelectric film 42. As an example, the Zr / Ti ratio in the ferroelectric film 43 may be 45 / 55 and the Zr / Ti ratio in the ferroelectric film 42 may be 40 / 60 in molar ratio. In general, the higher the Zr / Ti ratio, the more abruptly the polarization amount rises with respect to the applied voltage, the more easily the imprint characteristics are improved, and the more easily the leakage current is reduced. Also, the lower the Zr / Ti ratio, the more easily the saturated inversion charge amount is improved. By making the Zr / Ti ratio different between the ferroelectric film 42 and the ferroelectric film 43, it is possible to make the polarization amount rise with respect to the applied voltage in a well-balanced manner, improve the imprint characteristics, reduce the leakage current, and improve the saturated inversion charge amount. The Zr / Ti ratio in the ferroelectric film 43 may be smaller than the Zr / Ti ratio in the ferroelectric film .

[0034] Second embodiment Next, a second embodiment will be described. The second embodiment differs from the first embodiment mainly in the configuration of the ferroelectric capacitor. Fig. 5 is a cross-sectional view showing a semiconductor memory device according to the second embodiment.

[0035] As shown in FIG. 5, in the semiconductor memory device 200 according to the second embodiment, each of the ferroelectric capacitors Cap1 and Cap2 has a lower electrode 41, a ferroelectric film 43, a ferroelectric film 44, and an upper electrode 45.

[0036] In the semiconductor memory device 200, the ferroelectric film 43 is provided on the lower electrode 41. The ferroelectric film 43 is in direct contact with the lower electrode 41.

[0037] The ferroelectric film 44 is provided on the ferroelectric film 43. The ferroelectric film 44 is in direct contact with the ferroelectric film 43. The ferroelectric film 44 is a PZT-based ferroelectric film containing an additive. The ferroelectric film 44 contains La, Ca, Ir, Ru, or any combination of these, and Sr as an additive. The thickness of the ferroelectric film 44 is, for example, 0.5 nm or more and 10 nm or less.

[0038] For example, the ferroelectric film 44 contains La, Ca, Ir, or Ru, or any combination thereof, at a total concentration of 0.1 mol% or more, and Sr at a concentration of 0.5 mol% to 5 mol% or less. For example, the concentration of La in the ferroelectric film 44 is 5 mol% or less, the concentration of Ca is 8% or less, the concentration of Ir is 1% or less, and the concentration of Ru is 1% or less.

[0039] An upper electrode 45 is provided on the ferroelectric film 44. The upper electrode 45 is in direct contact with the ferroelectric film 44.

[0040] Other configurations of the second embodiment are similar to those of the first embodiment.

[0041] In this embodiment, the lower electrode 41 is an example of a second electrode, the ferroelectric film 43 is an example of a first ferroelectric film, the ferroelectric film 44 is an example of a second ferroelectric film, and the upper electrode 45 is an example of a first electrode.

[0042] Next, a method for manufacturing the semiconductor memory device 200 according to the second embodiment will be described. Figures 6 to 7 are cross-sectional views showing the method for manufacturing the semiconductor memory device 200 according to the second embodiment.

[0043] 6, similarly to the first embodiment, an element isolation insulating film 3 and transistors Tr1 and Tr2 are formed on a semiconductor substrate 1. Next, a cover film 21 and an interlayer insulating film 22 are formed, conductive plugs 31 and 32 are formed, an etching stopper film 23 and an interlayer insulating film 24 are formed, wiring 33 is formed, an oxidation suppression film 25 and an interlayer insulating film 26 are formed, and a conductive plug 34 is formed.

[0044] Then, as shown in FIG. 6, a lower electrode 41A is formed on the interlayer insulating film 26 and the conductive plug 34, a ferroelectric film 43A is formed on the lower electrode 41A, a ferroelectric film 44A is formed on the ferroelectric film 43A, and an upper electrode 45A is formed on the ferroelectric film 44A. Then, a lower electrode 41 is formed from the lower electrode 41A, a ferroelectric film 43 is formed from the ferroelectric film 43A, a ferroelectric film 44 is formed from the ferroelectric film 44A, and an upper electrode 45 is formed from the upper electrode 45A. For example, the lower electrode 41A, the ferroelectric film 44A, and the upper electrode 45A can be formed by a sputtering method, and the ferroelectric film 43A can be formed by an MOCVD method. The ferroelectric film 44A formed by the sputtering method is amorphous. Therefore, after the formation of the upper electrode 45A, annealing is performed to crystallize the ferroelectric film 44A. For this heat treatment, RTA is performed in a mixed gas atmosphere of an inert gas and O2 gas at a temperature of, for example, 400°C to 800°C. The inert gas may be Ar gas or N2 gas.

[0045] Thereafter, the stack of the upper electrode 45A, the ferroelectric film 44A, the ferroelectric film 43A, and the lower electrode 41A is etched. As a result, as shown in Fig. 7, ferroelectric capacitors Cap1 and Cap2 each having the upper electrode 45, the ferroelectric film 44, the ferroelectric film 43, and the lower electrode 41 are formed. Then, a protective film 48 is formed to cover the ferroelectric capacitors Cap1 and Cap2.

[0046] Next, the interlayer insulating film 27, the conductive plugs 35, the wiring 50, and the interlayer insulating film 28 are formed (see FIG. 5).

[0047] In this manner, the semiconductor memory device 200 according to the second embodiment can be manufactured.

[0048] In the semiconductor memory device 200 according to the second embodiment, the ferroelectric film 44 is a PZT-based film containing an additive, and therefore the fatigue characteristics and imprint characteristics can be improved as in the first embodiment. Furthermore, if the ferroelectric film between the lower electrode 41 and the upper electrode 45 is only the ferroelectric film 44, there is a risk of the amount of inversion charge decreasing, but since the semiconductor memory device 200 has the ferroelectric film 43, which is a PZT film containing no additive, the decrease in the amount of inversion charge can be suppressed.

[0049] Furthermore, in the second embodiment, in the manufacturing process, the amorphous ferroelectric film 44A is formed by a sputtering method, and the ferroelectric film 44A is crystallized by annealing after the upper electrode 45A is formed, so that the diffusion of elements from the upper electrode 45A to the ferroelectric film 44A can be easily suppressed, and therefore the leakage current can also be reduced.

[0050] The Zr / Ti ratio in the ferroelectric film 43 may be different from the Zr / Ti ratio in the ferroelectric film 44. For example, the Zr / Ti ratio in the ferroelectric film 43 may be larger than the Zr / Ti ratio in the ferroelectric film 44. As an example, the Zr / Ti ratio in the ferroelectric film 43 may be 45 / 55 and the Zr / Ti ratio in the ferroelectric film 44 may be 40 / 60 in molar ratio. By making the Zr / Ti ratio different between the ferroelectric film 44 and the ferroelectric film 43, the polarization amount can be made to rise sharply with respect to the voltage in a well-balanced manner, the imprint characteristics can be improved, the leakage current can be reduced, and the saturated inversion charge amount can be improved. The Zr / Ti ratio in the ferroelectric film 43 may be smaller than the Zr / Ti ratio in the ferroelectric film 44.

[0051] Third embodiment Next, a third embodiment will be described. The third embodiment differs from the first embodiment mainly in the configuration of the ferroelectric capacitor. Fig. 8 is a cross-sectional view showing a semiconductor memory device according to the third embodiment.

[0052] As shown in FIG. 8, in the semiconductor memory device 300 according to the third embodiment, each of the ferroelectric capacitors Cap1 and Cap2 has a lower electrode 41, a ferroelectric film 42, a ferroelectric film 43, a ferroelectric film 44, and an upper electrode 45.

[0053] In the semiconductor memory device 300, a ferroelectric film 42 is provided on a lower electrode 41. The ferroelectric film 42 is in direct contact with the lower electrode 41. A ferroelectric film 43 is provided on the ferroelectric film 42. The ferroelectric film 43 is in direct contact with the ferroelectric film 42. A ferroelectric film 44 is provided on the ferroelectric film 43. The ferroelectric film 44 is in direct contact with the ferroelectric film 43. An upper electrode 45 is provided on the ferroelectric film 44. The upper electrode 45 is in direct contact with the ferroelectric film 44.

[0054] Other configurations of the third embodiment are similar to those of the first embodiment. That is, the third embodiment has a configuration in which the first embodiment and the second embodiment are combined.

[0055] In this embodiment, the lower electrode 41 is an example of either the first electrode or the second electrode, the ferroelectric film 42 is an example of either the second ferroelectric film or the third ferroelectric film, the ferroelectric film 43 is an example of the first ferroelectric film, the ferroelectric film 44 is an example of the other of the second ferroelectric film or the third ferroelectric film, and the upper electrode 45 is an example of the other of the first electrode or the second electrode.

[0056] Next, a method for manufacturing the semiconductor memory device 300 according to the third embodiment will be described. Figures 9 and 10 are cross-sectional views showing the method for manufacturing the semiconductor memory device 300 according to the third embodiment.

[0057] 9, similarly to the first embodiment, an element isolation insulating film 3 and transistors Tr1 and Tr2 are formed on a semiconductor substrate 1. Next, a cover film 21 and an interlayer insulating film 22 are formed, conductive plugs 31 and 32 are formed, an etching stopper film 23 and an interlayer insulating film 24 are formed, wiring 33 is formed, an oxidation suppression film 25 and an interlayer insulating film 26 are formed, and a conductive plug 34 is formed.

[0058] 9, a lower electrode 41A is formed on the interlayer insulating film 26 and the conductive plug 34, a ferroelectric film 42A is formed on the lower electrode 41A, a ferroelectric film 43A is formed on the ferroelectric film 42A, a ferroelectric film 44A is formed on the ferroelectric film 43A, and an upper electrode 45A is formed on the ferroelectric film 44A. Then, the lower electrode 41 is formed from the lower electrode 41A, the ferroelectric film 42 is formed from the ferroelectric film 42A, the ferroelectric film 43 is formed from the ferroelectric film 43A, the ferroelectric film 44 is formed from the ferroelectric film 44A, and the upper electrode 45 is formed from the upper electrode 45A. For example, the lower electrode 41A, the ferroelectric film 42A, the ferroelectric film 44A, and the upper electrode 45A can be formed by a sputtering method, and the ferroelectric film 43A can be formed by an MOCVD method. The ferroelectric film 42A and the ferroelectric film 44A formed by the sputtering method are amorphous. Therefore, between the formation of the ferroelectric film 42A and the formation of the ferroelectric film 43A, annealing is performed to crystallize the ferroelectric film 42A, and after the formation of the upper electrode 45A, annealing is performed to crystallize the ferroelectric film 44A. As these heat treatments, for example, RTA is performed in a mixed gas atmosphere of an inert gas and O2 gas at a temperature of, for example, 400°C to 800°C. As the inert gas, Ar gas or N2 gas can be used.

[0059] Thereafter, the stack of the upper electrode 45A, the ferroelectric film 44A, the ferroelectric film 43A, the ferroelectric film 42A, and the lower electrode 41A is etched. As a result, as shown in Fig. 10, ferroelectric capacitors Cap1 and Cap2 each having the upper electrode 45, the ferroelectric film 44, the ferroelectric film 43, the ferroelectric film 42, and the lower electrode 41 are formed. Then, a protective film 48 is formed to cover the ferroelectric capacitors Cap1 and Cap2.

[0060] Next, the interlayer insulating film 27, the conductive plugs 35, the wiring 50, and the interlayer insulating film 28 are formed (see FIG. 8).

[0061] In this manner, the semiconductor memory device 300 according to the third embodiment can be manufactured.

[0062] In the semiconductor memory device 300 according to the third embodiment, the ferroelectric film 42 and the ferroelectric film 44 are PZT-based films containing additives, and therefore the fatigue characteristics and imprint characteristics can be improved as in the first embodiment. Furthermore, if the ferroelectric film 42 and the ferroelectric film 44 are the only ferroelectric films between the lower electrode 41 and the upper electrode 45, there is a risk of the amount of inversion charge decreasing, but since the semiconductor memory device 300 has the ferroelectric film 43, which is a PZT film containing no additives, the decrease in the amount of inversion charge can be suppressed.

[0063] Furthermore, the third embodiment can also reduce the leakage current in the same manner as the second embodiment.

[0064] Next, the results of tests actually carried out by the inventors of the present invention will be described.

[0065] (First test) In the first test, two types of ferroelectric capacitor samples (sample No. 1 and sample No. 2) were fabricated, and the polarization characteristics, imprint characteristics, fatigue characteristics, and leakage current were measured. Fig. 11 is a cross-sectional view showing the structure of sample No. 1. Fig. 12 is a cross-sectional view showing the structure of sample No. 2.

[0066] As shown in FIG. 11, sample No. 1 has a lower electrode 61, a ferroelectric film 63, a ferroelectric film 64, and an upper electrode 65. The lower electrode 61 is an Ir electrode. The ferroelectric film 63 is a PZT film containing no additives, and the thickness of the ferroelectric film 63 is 65 nm. The ferroelectric film 64 is a PZT-based film containing 2.5 mol % Sr, 2 mol % La, and 5 mol % Ca as additives, and the thickness of the ferroelectric film 64 is 10 nm. The upper electrode 65 is an Ir electrode. Sample No. 1 is a sample imitating the ferroelectric capacitors Cap1 and Cap2 of the second embodiment. In the preparation of sample No. 1, the ferroelectric film 63 was formed by the MOCVD method, and the lower electrode 61, the ferroelectric film 64, and the upper electrode 65 were formed by the sputtering method. In addition, after the formation of the upper electrode 65, annealing was performed to crystallize the ferroelectric film 64.

[0067] As shown in FIG. 12, sample No. 2 has a lower electrode 61, a ferroelectric film 66, and an upper electrode 65. The lower electrode 61 is an Ir electrode. The ferroelectric film 66 is a PZT film containing no additives, and the thickness of the ferroelectric film 66 is 75 nm. The upper electrode 65 is an Ir electrode. In producing sample No. 2, the ferroelectric film 66 was formed by the MOCVD method, and the lower electrode 61 and the upper electrode 65 were formed by the sputtering method.

[0068] In the measurement of the polarization characteristics, the amount of polarization Q was measured while changing the applied voltage V in sample No. 1 and sample No. 2, and a hysteresis loop was obtained. The results are shown in Fig. 13. In Fig. 13, the horizontal axis represents the applied voltage V, and the vertical axis represents the amount of polarization Q. As shown in Fig. 13, the same polarization characteristics were obtained in sample No. 1 as in sample No. 2.

[0069] In the measurement of fatigue properties, hysteresis loops were obtained while applying stress to Sample No. 1 and Sample No. 2, and the inversion charge Qsw was calculated from the hysteresis loop. The inversion charge Qsw was calculated from the following formula (1) using the values ​​P, U, N, and D obtained from the hysteresis loop shown in FIG. 14. In FIG. 14, P is the value of the maximum polarization inversion amount of the ferroelectric capacitor when a voltage is applied in the positive direction, and U is the value of the polarization non-inversion amount of the ferroelectric capacitor when a voltage is applied in the positive direction. Furthermore, N is the value of the maximum polarization inversion amount of the ferroelectric capacitor when a voltage is applied in the negative direction, and D is the value of the polarization non-inversion amount of the ferroelectric capacitor when a voltage is applied in the negative direction. Qsw = ((PU) + (ND)) / 2 (1)

[0070] As stress, a voltage of 4.5 V was applied for 20 ns at a frequency of 10 MHz at a temperature of 125°C. The measurement voltage was 1.8 V. The fatigue property measurement results are shown in Figure 15. In Figure 15, the horizontal axis indicates the number of repeated stress applications, and the vertical axis indicates the amount of inversion charge Qsw normalized by the maximum value. As shown in Figure 15, sample No. 1 achieved a stable amount of inversion charge Qsw even when the number of repeated stress applications was greater than that of sample No. 2.

[0071] The imprint characteristics were measured by a Q123 test.

[0072] Here, the Q123 test will be explained. In the Q123 test, a ferroelectric capacitor is used as a cell capacitor of a 2T2C type memory. Hereinafter, two adjacent cell capacitors are referred to as Cap-A and Cap-B. In the Q123 test, data is written to these capacitors so that the polarization directions of Cap-A and Cap-B are opposite to each other.

[0073] First, write data "0" to Cap-A and Cap-B with +1.8V and -1.8V respectively, then bake these capacitors at 150°C for acceleration. No voltage is applied to Cap-A and Cap-B during baking. Then, after various times have elapsed while still baking, a +1.8V pulse is applied to each of Cap-A and Cap-B to perform reading. The difference in the amount of polarization change between Cap-A and Cap-B at this time is Q2.

[0074] Following the measurement of Q2, write data "1" in the opposite direction to that before baking to each of Cap-A and Cap-B. In this example, to write, apply a pulse of -1.8V to Cap-A and +1.8V to Cap-B, and leave for 30 seconds.

[0075] If imprinting has progressed, the polarization will return to its original state during this time, causing a large depolarization. After leaving it for 30 seconds, a +1.8V pulse is applied again to read out data "1," and the difference in the amount of polarization change between Cap-A and Cap-B measured by this readout is defined as Q3. Q3 represents how much polarization remains after depolarization due to imprinting, and is an index of whether data can be read out from Cap-A and Cap-B.

[0076] The results are shown in Figure 16. In Figure 16, the horizontal axis represents the heating time, and the vertical axis represents the value of Q3. As shown in Figure 16, the change in Q3 was smaller in Sample No. 1 than in Sample No. 2, and good imprint resistance was obtained.

[0077] In measuring the leakage current, a voltage of 2 V was applied between the lower electrode 61 and the upper electrode 65 in sample No. 1 and sample No. 2. The results of measuring the leakage current are shown in Fig. 17. In Fig. 17, the horizontal axis indicates the leakage current, and the vertical axis indicates the cumulative probability. As shown in Fig. 17, the leakage current in sample No. 1 was suppressed to be lower than that in sample No. 2.

[0078] (Second Exam) In the second test, two types of ferroelectric capacitor samples (samples No. 3 and No. 4) were prepared and their polarization, imprint, and fatigue characteristics, as well as leakage current, were measured. Sample No. 3 has only a PZT-based film between the lower and upper electrodes, with a thickness of 75 nm and containing 2.5 mol% Sr, 2 mol% La, and 5 mol% Ca as additives. Sample No. 4 has only a PZT-based film between the lower and upper electrodes, with a thickness of 75 nm and containing 2 mol% La as an additive.

[0079] In the measurement of the polarization characteristics, the inversion charge Qsw was measured for Sample No. 3 and Sample No. 4 while changing the read voltage at 25°C. The results are shown in FIG. 18. In FIG. 18, the horizontal axis indicates the read voltage, and the vertical axis indicates the inversion charge Qsw. The read voltage V50 at which the inversion charge Qsw becomes 50% of the saturated inversion charge was specified for Sample No. 3 and Sample No. 4. The read voltage V50 for Sample No. 4 was about 0.7V, while the read voltage V50 for Sample No. 3 was about 0.5V. That is, the inversion charge Qsw rose more steeply with respect to the applied voltage V in Sample No. 3 than in Sample No. 4. This indicates that Sample No. 3 is more suitable for low-voltage operation than Sample No. 4.

[0080] In the measurement of fatigue properties, hysteresis loops were obtained while applying stress to sample No. 3 and sample No. 4, and the amount of inversion charge Qsw was calculated from the hysteresis loop. As the stress, a voltage of 7 V was applied at a frequency of 10 MHz at a temperature of 85°C. The measurement voltage was 1.8 V. The measurement results of fatigue properties are shown in FIG. 19. In FIG. 19, the horizontal axis indicates the number of times stress was applied repeatedly, and the vertical axis indicates the amount of inversion charge Qsw. As shown in FIG. 19, sample No. 3 obtained a stable amount of inversion charge Qsw even when the number of times stress was applied repeatedly was greater than that of sample No. 4. This indicates that sample No. 3 is more suitable for improving the amount of inversion charge Qsw than sample No. 4.

[0081] To measure the imprint characteristics, a Q123 test was performed as in the first test. The results are shown in Figure 20. In Figure 20, the horizontal axis indicates the heating time, and the vertical axis indicates the Q3 value. As shown in Figure 20, the change in Q3 was smaller in sample No. 3 than in sample No. 4. In other words, the Q3 rate, which is the slope of the graph in Figure 20, was -5.9 for sample No. 3 and -12.0 for sample No. 4. This indicates that the imprint resistance of sample No. 3 is higher than that of sample No. 4.

[0082] (Third Test) In the third test, three types of ferroelectric capacitor samples (samples No. 5, 6, and 7) were prepared and the polarization and imprint characteristics were measured. Sample No. 5 has only a PZT film between the lower and upper electrodes, which is 85 nm thick, does not contain any additives, and has a Zr / Ti ratio of 45 / 55. Sample No. 6 has only a PZT film between the lower and upper electrodes, which is 85 nm thick, does not contain any additives, and has a Zr / Ti ratio of 40 / 60. Sample No. 7 has only a PZT film between the lower and upper electrodes, which is 85 nm thick, does not contain any additives, and has a Zr / Ti ratio of 35 / 65.

[0083] In the measurement of the polarization characteristics, the polarization amount Q was measured while changing the applied voltage V in Sample No. 5, Sample No. 6, and Sample No. 7, and a hysteresis loop was obtained. The results are shown in FIG. 21. In FIG. 21, the horizontal axis indicates the applied voltage V, and the vertical axis indicates the polarization amount Q. FIG. 22 also shows the relationship between the applied voltage V and the polarization amount Q1. In FIG. 22, the horizontal axis indicates the applied voltage V, and the vertical axis indicates the polarization amount Q1. The polarization amount Q1 is a value corresponding to "PU" in FIG. 14. Then, the read voltage V50 at which the inversion charge amount Qsw becomes 50% of the saturated inversion charge amount was compared. As a result, the read voltage V50 of Sample No. 5 was lower than the read voltage V50 of Sample No. 6, and the read voltage V50 of Sample No. 6 was lower than the read voltage V50 of Sample No. 7. That is, the polarization amount Q1 tends to rise more steeply with respect to the applied voltage V in sample No. 6 than in sample No. 7, and the polarization amount Q1 tends to rise more steeply with respect to the applied voltage V in sample No. 5 than in sample No. 6. This indicates that sample No. 6 is more suitable for low-voltage operation than sample No. 7, and sample No. 5 is more suitable for low-voltage operation than sample No. 6.

[0084] In measuring the imprint characteristics, heating was performed at 150°C, and the average change in the positive coercive voltage and the negative coercive voltage (shift amount Vshift) was measured for various heating times. The results are shown in Fig. 23. In Fig. 23, the horizontal axis represents the heating time, and the vertical axis represents the shift amount Vshift. As shown in Fig. 23, the shift amount Vshift was smaller in sample No. 6 than in sample No. 7, and the shift amount Vshift was smaller in sample No. 5 than in sample No. 6. This indicates that the imprint resistance of sample No. 6 is higher than that of sample No. 7, and the imprint resistance of sample No. 5 is higher than that of sample No. 6.

[0085] The semiconductor memory device can be used, for example, as a non-volatile memory.

[0086] Although the preferred embodiments have been described in detail above, the present invention is not limited to the above-described embodiments, and various modifications and substitutions can be made to the above-described embodiments without departing from the scope of the claims.

[0087] Various aspects of the present disclosure are summarized below as appendices.

[0088] (Appendix 1) A transistor; a ferroelectric capacitor connected to the transistor; having The ferroelectric capacitor is a first electrode and a second electrode, one of which is connected to the transistor; a PZT-based first ferroelectric film provided between the first electrode and the second electrode; a PZT-based second ferroelectric film provided between the first electrode and the first ferroelectric film; having the second ferroelectric film contains La, Ca, Ir, Ru or any combination thereof, and Sr as an additive; A semiconductor memory device, wherein the first ferroelectric film has a lower concentration of each of La, Ca, Ir, Ru and Sr than the second ferroelectric film. (Appendix 2) 2. The semiconductor memory device according to claim 1, wherein the second ferroelectric film has a thickness of 0.5 nm or more and 10 nm or less. (Appendix 3) 3. The semiconductor memory device according to claim 1, wherein a ratio of a Zr content to a Ti content in the first ferroelectric film is greater than a ratio of a Zr content to a Ti content in the second ferroelectric film. (Appendix 4) 3. The semiconductor memory device according to claim 1, wherein a ratio of Zr content to Ti content in the first ferroelectric film is different from a ratio of Zr content to Ti content in the second ferroelectric film. (Appendix 5) a PZT-based third ferroelectric film provided between the second electrode and the first ferroelectric film; the third ferroelectric film contains La, Ca, Ir, Ru or any combination thereof, and Sr as an additive; 5. The semiconductor memory device according to claim 1, wherein the concentrations of La, Ca, Ir, Ru and Sr in the first ferroelectric film are lower than the concentrations of La, Ca, Ir, Ru and Sr in the third ferroelectric film. (Appendix 6) 6. The semiconductor memory device according to claim 5, wherein the third ferroelectric film has a thickness of 0.5 nm or more and 10 nm or less. (Appendix 7) 7. The semiconductor memory device according to claim 5, wherein a ratio of Zr content to Ti content in the first ferroelectric film is greater than a ratio of Zr content to Ti content in the second ferroelectric film. (Appendix 8) 7. The semiconductor memory device according to claim 5, wherein a ratio of Zr content to Ti content in the first ferroelectric film is different from a ratio of Zr content to Ti content in the second ferroelectric film. (Appendix 9) 9. The semiconductor memory device according to claim 1, wherein the first ferroelectric film does not contain La, Ca, Ir, Ru, or Sr. (Appendix 10) forming a transistor; forming a ferroelectric capacitor connected to the transistor; having The step of forming a ferroelectric capacitor includes: forming a first electrode and a second electrode, one of which is connected to the transistor; forming a PZT-based first ferroelectric film between the first electrode and the second electrode; forming a PZT-based second ferroelectric film between the first electrode and the first ferroelectric film; having the second ferroelectric film contains La, Ca, Ir, Ru or any combination thereof, and Sr as an additive; A method for manufacturing a semiconductor memory device, wherein the first ferroelectric film has a lower concentration of each of La, Ca, Ir, Ru and Sr than the second ferroelectric film. (Appendix 11) In the step of forming the ferroelectric capacitor, the first electrode is connected to the transistor; After the first electrode is formed, the second ferroelectric film is formed in an amorphous state on the first electrode; After the second ferroelectric film is formed in an amorphous state, the second ferroelectric film is crystallized by annealing; After the second ferroelectric film is crystallized, the first ferroelectric film is formed on the second ferroelectric film; 11. The method for manufacturing a semiconductor memory device according to claim 10, wherein the second electrode is formed on the first ferroelectric film after the first ferroelectric film is formed. (Appendix 12) In the step of forming the ferroelectric capacitor, the first electrode is connected to the transistor; After the first electrode is formed, the first ferroelectric film is formed on the first electrode; After the first ferroelectric film is formed, the second ferroelectric film is formed in an amorphous state on the first ferroelectric film; After the second ferroelectric film is formed, the second electrode is formed on the second ferroelectric film; 11. The method for manufacturing a semiconductor memory device according to claim 10, wherein after the second electrode is formed, the second ferroelectric film is crystallized by annealing. (Appendix 13) the step of forming the ferroelectric capacitor includes the step of forming a PZT-based third ferroelectric film between the second electrode and the first ferroelectric film, the third ferroelectric film contains La, Ca, Ir, Ru or any combination thereof, and Sr as an additive; 11. The method for manufacturing a semiconductor memory device according to claim 10, wherein the concentrations of La, Ca, Ir, Ru and Sr in the first ferroelectric film are lower than the concentrations of La, Ca, Ir, Ru and Sr in the third ferroelectric film. (Appendix 14) In the step of forming the ferroelectric capacitor, the first electrode is connected to the transistor; After the first electrode is formed, the second ferroelectric film is formed on the first electrode; After the second ferroelectric film is formed, the first ferroelectric film is formed on the second ferroelectric film; After the first ferroelectric film is formed, the third ferroelectric film is formed in an amorphous state on the first ferroelectric film; After the third ferroelectric film is formed, the second electrode is formed on the third ferroelectric film; 14. The method for manufacturing a semiconductor memory device according to claim 13, wherein after the second electrode is formed, the third ferroelectric film is crystallized by annealing. (Appendix 15) 15. The method for manufacturing a semiconductor memory device according to claim 13, wherein the third ferroelectric film is formed by a sputtering method. (Appendix 16) the second ferroelectric film is formed by a sputtering method, 16. The method for manufacturing a semiconductor memory device according to claim 10, wherein the first ferroelectric film is formed by metal-organic chemical vapor deposition. [Explanation of symbols]

[0089] 1: Semiconductor substrate 41, 41A, 61: Lower electrode 42, 42A, 43, 43A, 44, 44A, 63, 64: Ferroelectric film 45, 45A, 65: Upper electrode 100, 200, 300: Semiconductor memory device

Claims

1. A transistor; a ferroelectric capacitor connected to the transistor; having The ferroelectric capacitor is a first electrode and a second electrode, one of which is connected to the transistor; a first ferroelectric film of PZT system provided between the first electrode and the second electrode; a PZT-based second ferroelectric film provided between the first electrode and the first ferroelectric film; having the second ferroelectric film contains La, Ca, Ir, Ru, or any combination thereof, and Sr as an additive; A semiconductor memory device, wherein the concentrations of La, Ca, Ir, Ru and Sr in the first ferroelectric film are lower than the concentrations of La, Ca, Ir, Ru and Sr in the second ferroelectric film.

2. 2. The semiconductor memory device according to claim 1, wherein the second ferroelectric film has a thickness of 0.5 nm to 10 nm.

3. 3. The semiconductor memory device according to claim 1, wherein a ratio of a Zr content to a Ti content in the first ferroelectric film is greater than a ratio of a Zr content to a Ti content in the second ferroelectric film.

4. a third ferroelectric film of PZT system provided between the second electrode and the first ferroelectric film; the third ferroelectric film contains La, Ca, Ir, Ru, or any combination thereof, and Sr as an additive; 3. The semiconductor memory device according to claim 1, wherein the first ferroelectric film has a lower concentration of each of La, Ca, Ir, Ru and Sr than the third ferroelectric film.

5. 5. The semiconductor memory device according to claim 4, wherein the third ferroelectric film has a thickness of 0.5 nm to 10 nm.

6. 5. The semiconductor memory device according to claim 4, wherein a ratio of the Zr content to the Ti content in the first ferroelectric film is greater than a ratio of the Zr content to the Ti content in the second ferroelectric film.

7. 3. The semiconductor memory device according to claim 1, wherein the first ferroelectric film does not contain La, Ca, Ir, Ru, or Sr.

8. forming a transistor; forming a ferroelectric capacitor connected to the transistor; having The step of forming a ferroelectric capacitor includes: forming a first electrode and a second electrode, one of which is connected to the transistor; forming a PZT-based first ferroelectric film between the first electrode and the second electrode; forming a PZT-based second ferroelectric film between the first electrode and the first ferroelectric film; having the second ferroelectric film contains La, Ca, Ir, Ru, or any combination thereof, and Sr as an additive; A method for manufacturing a semiconductor memory device, wherein the concentrations of La, Ca, Ir, Ru and Sr in the first ferroelectric film are lower than the concentrations of La, Ca, Ir, Ru and Sr in the second ferroelectric film.

9. In the step of forming the ferroelectric capacitor, the first electrode is connected to the transistor; After the first electrode is formed, the second ferroelectric film is formed in an amorphous state on the first electrode; After the second ferroelectric film is formed in an amorphous state, the second ferroelectric film is crystallized by annealing; After the second ferroelectric film is crystallized, the first ferroelectric film is formed on the second ferroelectric film; 9. The method for manufacturing a semiconductor memory device according to claim 8, wherein the second electrode is formed on the first ferroelectric film after the first ferroelectric film is formed.

10. In the step of forming the ferroelectric capacitor, the first electrode is connected to the transistor; After the first electrode is formed, the first ferroelectric film is formed on the first electrode; After the first ferroelectric film is formed, the second ferroelectric film is formed in an amorphous state on the first ferroelectric film; After the second ferroelectric film is formed, the second electrode is formed on the second ferroelectric film; 9. The method for manufacturing a semiconductor memory device according to claim 8, wherein the second ferroelectric film is crystallized by annealing after the second electrode is formed.

11. the second ferroelectric film is formed by a sputtering method, 10. The method for manufacturing a semiconductor memory device according to claim 8, wherein the first ferroelectric film is formed by metal organic chemical vapor deposition.

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