modulator

Abstract

To provide a modulator capable of reducing the effect of offset caused by switch variations in a configuration in which chopping is performed at both ends of an integral capacitance.SOLUTION: An integrator 4 is configured by connecting a first switch φ1e between an input terminal and output terminal of a differential amplifier 1, and connecting a series circuit of a second switch φ2e, a system CHOP switch 2, an integral capacitance Cint, and a system CHOP switch 3 between the input terminal and output terminal of the differential amplifier 1. The switches 2 and 3 include m and n unit switches CHL1 and CHL2, respectively. A control circuit chops an input chopping switch 14 and an output chopping switch 15 at a frequency fchop, chops each of the unit switches CHL1 of the switch 2 at a frequency fchop / m, and chops each of the n unit switches CHL2 of the switch 3 at a frequency fchop / n.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a modulator including a differential amplifier, an integral capacitor, and a chopping switch. [Background technology]

[0002] For example, Non-Patent Document 1 discloses a current sensor configured using a modulator in which a feedback system is added to the integrator as described above, as shown in Figures 6 and 7. In this configuration, in order to reduce the offset voltage of the differential amplifier, chopping is performed by a switch Φ2e at the input of the differential amplifier, a switch Φ1e between the input and output, and a switch CHL at both ends of the integral capacitance Cint1. Patent Documents 1 and 2 also disclose similar configurations. [Prior art documents] [Non-patent literature]

[0003] [Non-Patent Document 1] Z. Tang, R. Zamparette, Y. Furuta, T. Nezuka and KAA Makinwa, "A ±25A Versatile Shunt-Based Current Sensor with 10kHz Bandwidth and ±0.25% Gain Error from -40°C to 85°C Using 2-Current Calibration," 2022 IEEE International Solid- State Circuits Conference (ISSCC), 2022, pp. 66-68, doi: 10.1109 / ISSCC42614.2022.9731777. [Patent documents]

[0004] [Patent Document 1] U.S. Patent Publication No. 2022 / 0263520 [Patent Document 2] U.S. Patent No. 8,665,130 Summary of the Invention [Problem to be solved by the invention]

[0005] However, if there is variation in the characteristics of the switches that perform chopping on the input and output sides of the integral capacitance, such as the on-resistance, this can become a factor in generating an offset. The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a modulator capable of reducing the influence of offset caused by switch variations in a configuration in which chopping is performed at both ends of an integral capacitance. [Means for solving the problem]

[0006] According to the modulator of claim 1, a first switch is connected between the input terminal and the output terminal of a differential amplifier, and a series circuit of a second switch, an input switch for capacitive chopping, an integral capacitor, and an output switch for capacitive chopping is connected between the input terminal and the output terminal of the differential amplifier to configure an integrator. The input switch for capacitive chopping and the output switch for capacitive chopping each include m and n unit switches, respectively.

[0007] The control circuit chops the input chopping switch and the output chopping switch at a frequency fchop, chops each of the m unit switches of the input switch for capacitance chopping at a frequency fchop / m, and chops each of the n unit switches of the output switch for capacitance chopping at a frequency fchop / n. In this way, by providing multiple unit switches for at least either the input or output switch for capacitance chopping, it is possible to level out the variations in the characteristics of the unit switches. Therefore, it is possible to reduce the offset caused by the variations in characteristics between the unit switches on the input and output sides.

[0008] According to the modulator of claim 2, by setting (m ≠ n), the combination of unit switches of the capacitive chopping input and output switches changes every time chopping is performed, so that the variation in characteristics can be further averaged out.

[0009] According to the modulator of claim 4, m is set to be greater than n. When the second switch is turned on, charge flows into the integral capacitance via the input switch for capacitance chopping. For this reason, the offset can be reduced more effectively by increasing the number of unit switches in the input switch for capacitance chopping. [Brief description of the drawings]

[0010] [Figure 1] FIG. 3 is a diagram showing the configuration of a modulator in a simplified form, in accordance with the first embodiment, of the integrator shown in FIG. [Diagram 2] A diagram showing the configuration of an integrator with a differential amplifier as the differential input and output. [Diagram 3] A diagram showing the system CHOP switch symbols and their corresponding combinations [Figure 4] A diagram showing the timing at which each unit switch CHL of the system CHOP switch 3 is chopped based on the frequency fchop. [Diagram 5] FIG. 13 is a diagram showing the configuration of a modulator in the second embodiment; [Figure 6] FIG. 1 shows the configuration of a modulator disclosed in Non-Patent Document 1. [Figure 7] A timing chart showing the operation of the modulator. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011] (First embodiment) The amplifiers used in the following embodiments are differential amplifiers as shown in Fig. 2, but for ease of explanation, they are shown as a single-ended type with positive and negative switches grouped together as shown in Fig. 1. As shown in Fig. 2, the inverting and non-inverting side configurations of differential amplifier 1 are symmetrical. The symbols for the inverting and negative side configurations are marked with (-), and the symbols for the non-inverting and positive side configurations are marked with (+), but when there is no need to particularly distinguish between the two, the symbols may not be marked with (-) or (+).

[0012] 2, an input voltage is applied via a coupling capacitor Cin to each input terminal of the differential amplifier 1. A first switch Φ1e is connected between the input terminal and the output terminal, and a series circuit of a second switch Φ2e, a system CHOP switch 2, an integral capacitance Cint, and a system CHOP switch 3 is also connected between the input terminal and the output terminal.

[0013] The system CHOP switches 2 and 3, which are symbolically shown in Fig. 2, are equipped with four unit switches. As shown in Fig. 3, the system CHOP switches are made up of two switches CHL(+) and CHL1(-) connected in series to the inverting side and non-inverting side, respectively, and two switches CHL(+) and CHL1(-) connected in a cross-connect state between the inverting side and non-inverting side. The system CHOP switch 2 corresponds to an input switch for capacitive chopping, and the system CHOP switch 3 corresponds to an output switch for capacitive chopping. Each switch is made up of, for example, an N-channel MOSFET.

[0014] In Fig. 1, the unit switch of system CHOP switch 2 is shown collectively as CHL1, and the unit switch of system CHOP switch 3 is shown collectively as CHL2. System CHOP switch 2 is configured with m unit switches CHL1(1) to CHL1(m) connected in parallel, and system CHOP switch 3 is configured with n unit switches CHL2(1) to CHL1(n) connected in parallel. In the above configuration, differential amplifier 1, integral capacitance Cint connected between its input / output terminals, system CHOP switches 2 and 3, etc., together constitute integrator 4. Integrator 4 is of a correlated double sampling type.

[0015] In addition, the correlated double sampling type integrator is also shown in, for example, FIG. 30 of JP 2018-109647 A and FIG. 1 of JP 2021-209475 A. By configuring the modulator 11 in this way, the effects of the offset voltage of the differential amplifier 1, flicker noise, etc. can be reduced.

[0016] The modulator 11 of this embodiment is configured by adding a feedback system to the integrator 4. A quantizer 12 is connected to the output terminal of the differential amplifier 1, and a D / A converter 13 is connected to the output terminal of the quantizer 12. The output terminal of the D / A converter 13 is connected to the non-inverting input terminal of the differential amplifier 1 via a switch and a capacitor Cin2 (not shown). An input chopping switch 14 is connected to the front stage of the capacitor Cin1, and an output chopping switch 15 is connected to the output terminal of the quantizer 12.

[0017] Next, the operation of this embodiment will be described. A control circuit (not shown) of the modulator 11 operates the switches Φ1e and Φ2e at an operating frequency fs. As shown in FIG. 1, the input chopping switch 14 and the output chopping switch 15 chop at a frequency fchop. The system CHOP switch 2 chops each of the m unit switches CHL1(1) to CHL1(m) by sequentially switching them at a frequency fchop / m. The system CHOP switch 3 chops each of the n unit switches CHL2(1) to CHL1(n) by sequentially switching them at a frequency fchop / n. The frequency fchop is sufficiently low compared to the frequency fs, and is set to, for example, about fchop=fs / 256.

[0018] 4 shows the timing when n unit switches CHL2(1) to CHL1(n) in system CHOP switch 3 are chopped in sequence according to frequency fchop. For example, assume that (n≧5) and (m=n+1). In this case, when system CHOP switches 2 and 3 are chopped in sequence at frequencies fchop / m and fchop / n, respectively, as described above, first, unit switch CHL1(1) of system CHOP switch 2 and unit switch CHL2(1) of system CHOP switch 3 are chopped simultaneously.

[0019] After that, the unit switches CHL1 and CHL2 are switched for each frequency fchop, and when the unit switch CHL1(m) of the system CHOP switch 2 is chopped, the unit switch of the system CHOP switch 3 that is chopped at the same time becomes CHL2(1). Next, the unit switch of the system CHOP switch 3 that is chopped at the same time as the unit switch CHL1(1) of the system CHOP switch 2 becomes CHL2(2).

[0020] In this way, there is a shift of one cycle of the frequency fchop between the input chopping cycle in which all of the unit switches CHL1(1) to CHL1(m) of the system CHOP switch 2 are chopped, and the output chopping cycle in which all of the unit switches CHL2(1) to CHL2(n) of the system CHOP switch 3 are chopped. As a result, the combination of the unit switch CHL1 of the system CHOP switch 2 and the unit switch CHL2 of the system CHOP switch 3 changes every time the input chopping cycle is repeated.

[0021] That is, by having m unit switches CHL1 of the system CHOP switch 2 in parallel and n unit switches CHL2 of the system CHOP switch 3 in parallel, the variation in characteristics such as the on-resistance of the N-channel MOSFET is statistically reduced to 1 / (√m) or 1 / (√n). In addition, when m and n are mutually prime, as described above, the combination of the unit switches CHL1 and CHL2 in the system CHOP switches 2 and 3 changes each time the input side chopping period is repeated, thereby further reducing the variation in characteristics. Therefore, the effect of offset caused by the variation is also reduced.

[0022] As described above, according to this embodiment, the first switch φ1e is connected between the input terminal and output terminal of the differential amplifier 1, and a series circuit of the second switch φ2e, the system CHOP switch 2, the integral capacitance Cint, and the system CHOP switch 3 is connected between the input terminal and output terminal of the differential amplifier 1 to configure the integrator 4. The system CHOP switches 2 and 3 include m and n unit switches CHL1 and CHL2, respectively.

[0023] The control circuit chops the input chopping switch 14 and the output chopping switch 15 at a frequency fchop, chops each of the unit switches CHL1 of the system CHOP switch 2 at a frequency fchop / m, and chops each of the n unit switches CHL2 of the system CHOP switch 3 at a frequency fchop / n.

[0024] In this way, by providing multiple unit switches CHL1 and CHL2 in the system CHOP switches 2 and 3, respectively, the variation in characteristics of the unit switches CHL1 and CHL2 can be averaged. Therefore, the offset caused by the variation in characteristics can be reduced. In addition, when the second switch φ2e is turned on, charge flows into the integral capacitance Cint via the system CHOP switch 2, so by setting (m>n) and increasing the number of unit switches CHL1 in the system CHOP switch 2, the offset reduction effect can be further improved.

[0025] Second embodiment As shown in Fig. 5, the modulator 21 of the second embodiment is the modulator 11 of the first embodiment, in which an amplifier 22 for amplifying an input signal is connected between the input chopping switch 14 and the capacitor Cin1, and a second-order integrator 23 is connected between the output terminal of the differential amplifier 1 and the quantizer 12. An analog signal is provided to the input terminal of the amplifier 22 and a capacitor (not shown) of the second-order integrator 23 through D / A converters 24 and 25 that perform D / A conversion of the output signal of the quantizer 12, similar to the D / A converter 13. If the modulator 11 is the first integrator, the second-order integrator 23 corresponds to the second integrator. By configuring the modulator 21 in this way, the quantization noise can be shifted to a higher frequency region and its influence can be eliminated.

[0026] (Other embodiments) It is not necessary to set (m>n). At least one of them may be "1", for example, (m=2, n=1). It may be set to (m=n), in which case both m and n must be equal to or greater than 2. Even when set to (m=n), the effect of leveling out the variation in the unit switches is achieved.

[0027] Each switch is not limited to an N-channel MOSFET, and may be composed of other semiconductor elements. In the second embodiment, the amplifier 22 may be omitted. In the second embodiment, the second-order integrator 23 may be omitted. Although the present disclosure has been described based on the embodiment, it is understood that the present disclosure is not limited to the embodiment or structure. The present disclosure also includes various modifications and modifications within the equivalent range. In addition, various combinations and forms, and other combinations and forms including only one element, more than one element, or less than one element, are also within the scope and concept of the present disclosure. [Explanation of symbols]

[0028] In the drawing, 1 denotes a differential amplifier, 2 and 3 denote system CHOP switches, 4 denotes an integrator, CHL1 and CHL2 denote chopping switches, φ1e denotes a first switch, φ2e denotes a second switch, Cint denotes an integral capacitance, and CHL1 and CHL2 denote unit switches.

Claims

1. A first switch (φ1e) connected between an input terminal and an output terminal of the differential amplifier (1); an integrator (4) having a series circuit of a second switch (φ2e), a capacitive chopping input switch (CHL1), an integral capacitance (Cint), and a capacitive chopping output switch (CHL2) connected between the input terminal and the output terminal of the differential amplifier; an input chopping switch (14) arranged on the input side of the integrator; an output chopping switch (15) disposed on the output side of the integrator; A control circuit for controlling chopping by each of the switches, The capacitive chopping input switch has m unit switches. The capacitive chopping output switch has n unit switches (where m and n are both natural numbers, at least one of which is 2 or more), The control circuit chops the input chopping switch and the output chopping switch at a frequency f chop ; Each of the m unit switches of the capacitive chopping input switch is chopped at a frequency f chop / m, A modulator that chops each of the n unit switches of the capacitive chopping output switch at a frequency fchop / n.

2. 2. The modulator according to claim 1, wherein m is set to (m ≠ n).

3. 3. The modulator according to claim 2, wherein m and n are mutually prime.

4. 3. The modulator according to claim 2, wherein m is set to (m>n).

5. 5. The modulator according to claim 1, wherein the integrator is of the correlated double sampling type.

6. If an integrator configured around the differential amplifier is a first integrator, 5. The modulator according to claim 1, further comprising a second integrator (23) disposed after the first integrator.

7. 7. The modulator of claim 6, further comprising an amplifier (22) preceding the first integrator for amplifying the input signal.

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