Printed circuit board

Abstract

To provide a printed circuit board in which a wiring layer formed on a glass layer can be formed with a fine circuit.SOLUTION: A printed circuit board 100A includes: a glass layer 111 having a through-hole penetrating between an upper and lower surfaces thereof; a through-via 130 including a via metal layer 131 arranged on a wall surface of the through-hole and a first insulating material 132 filling at least a portion of a space between portions of the via metal layer in the through-hole; a first wiring layer 121 arranged on the upper surface of the glass layer, at least a portion of first wiring layer connected to an upper side of the through-via; a second wiring layer 122 arranged on the lower surface of the glass layer, at least a portion of the second wiring layer connected to a lower side of the through-via; and a second insulating material 112 covering at least a portion of an external surface of the glass layer, and the first and second insulating materials include substantially the same material.SELECTED DRAWING: Figure 3

Description

[Technical field]

[0001] The present invention relates to printed circuit boards. [Background technology]

[0002] Packaging technology is constantly evolving, and in particular, there are ongoing attempts to move away from the traditional organic materials used in manufacturing boards and use glass materials. However, in the case of conventional printed circuit boards using glass cores, the process of forming through vias in the glass core is somewhat complicated, and there are also limitations to achieving fine line widths directly in the glass core. In addition, there is a high possibility of the glass core being damaged during the process, and the exposed side surface of the glass core in the finished product is vulnerable to impacts. Summary of the Invention [Problem to be solved by the invention]

[0003] One of the various objects of the present invention is to provide a printed circuit board in which the wiring layer formed on the glass layer can be formed with fine circuits.

[0004] Another of the various objects of the present invention is to provide a printed circuit board which allows for simplified processes and is advantageous in controlling warpage.

[0005] It is yet another of the various objects of the present invention to provide a printed circuit board capable of preventing damage to the glass layer and protecting the outer surface of the glass layer. [Means for solving the problem]

[0006] One of the solutions proposed in the present invention is to form a through via in a glass layer, planarize it using CMP (Chemical Mechanical Polishing) or the like, and then form a circuit on the glass layer using SAP (Semi Additive Process).

[0007] Another of several solutions proposed in the present invention is to simultaneously carry out the process of filling the glass layer and the process of plugging the through holes in the glass layer.

[0008] Still another of several solutions proposed in the present invention is to use a reinforcing layer such as a copper clad laminate (CCL) as a jig to perform the glass layer embedding process and the through hole plugging process.

[0009] For example, one example of a printed circuit board includes a glass layer having a through hole penetrating between an upper surface and a lower surface, a through via including a via metal layer arranged on a wall surface of the through hole and a first insulating material filling at least a portion of the space between the via metal layer in the through hole, a first wiring layer arranged on the upper surface of the glass layer and at least a portion of which is connected to an upper side of the through via, a second wiring layer arranged on the lower surface of the glass layer and at least a portion of which is connected to a lower side of the through via, and a second insulating material covering at least a portion of an outer surface of the glass layer, wherein the first and second insulating materials may comprise substantially the same material.

[0010] For example, a printed circuit board according to one example includes a through via including a via metal layer and a first insulating material filling at least a portion of a space between the via metal layer, a glass layer including a first through portion in which the through via is arranged, a second insulating material including a second through portion in which the through via and the glass layer are arranged, a first wiring layer arranged on an upper surface of the glass layer and at least a portion of which is connected to an upper side of the through via, a second wiring layer arranged on a lower surface of the glass layer and at least a portion of which is connected to a lower side of the through via, a first insulating layer arranged on each of the upper surfaces of the glass layer and the second insulating material and covering at least a portion of the first wiring layer, and a second insulating layer arranged on each of the lower surfaces of the glass layer and the second insulating material and covering at least a portion of the second wiring layer, and the first and second insulating materials may be substantially made of the same material. Effect of the Invention

[0011] Among the various effects of the present invention, one effect is that it is possible to provide a printed circuit board in which the wiring layer formed on the glass layer can be formed with a fine circuit.

[0012] Another advantage of the present invention, among the various advantages thereof, is that the process can be simplified and a printed circuit board that is advantageous in terms of warpage control can be provided.

[0013] Among the various effects of the present invention, still another effect is that it is possible to provide a printed circuit board capable of preventing damage to a glass layer and protecting an outer surface of the glass layer. [Brief description of the drawings]

[0014] [Figure 1] FIG. 1 is a block diagram illustrating a schematic example of an electronic device system. [Diagram 2] FIG. 1 is a perspective view illustrating an example of an electronic device. [Diagram 3] FIG. 1 is a cross-sectional view illustrating an example of a printed circuit board. [Figure 4] 4 is a schematic cross-sectional plan view of the printed circuit board of FIG. 3 taken along the line II'. FIG. [Figure 5a] 4 is a process diagram illustrating an example of a method for manufacturing the printed circuit board of FIG. 3. [Figure 5b] 4 is a process diagram illustrating an example of a method for manufacturing the printed circuit board of FIG. 3. [Figure 5c] 4 is a process diagram illustrating an example of a method for manufacturing the printed circuit board of FIG. 3. [Figure 5d] 4 is a process diagram illustrating an example of a method for manufacturing the printed circuit board of FIG. 3. [Figure 5e] 4 is a process diagram illustrating an example of a method for manufacturing the printed circuit board of FIG. 3. [Figure 5f] 4 is a process diagram illustrating an example of a method for manufacturing the printed circuit board of FIG. 3. [Figure 5g] 4 is a process diagram illustrating an example of a method for manufacturing the printed circuit board of FIG. 3. [Figure 5h]4 is a process diagram illustrating an example of a method for manufacturing the printed circuit board of FIG. 3. [Figure 5i] 4 is a process diagram illustrating an example of a method for manufacturing the printed circuit board of FIG. 3. [Figure 6] FIG. 11 is a cross-sectional view illustrating another example of a printed circuit board. [Figure 7] 7 is a schematic cross-sectional plan view of the printed circuit board of FIG. 6 taken along the line II-II'. [Figure 8a] 7 is a process diagram illustrating an example of a manufacturing method for the printed circuit board of FIG. 6. [Figure 8b] 7 is a process diagram illustrating an example of a manufacturing method for the printed circuit board of FIG. 6. [Figure 9] FIG. 11 is a cross-sectional view illustrating another example of a printed circuit board. [Figure 10a] 10 is a process diagram illustrating an example of a method for manufacturing the printed circuit board of FIG. 9. [Figure 10b] 10 is a process diagram illustrating an example of a method for manufacturing the printed circuit board of FIG. 9. [Figure 11] FIG. 11 is a cross-sectional view illustrating another example of a printed circuit board. [Figure 12a] 12 is a process diagram illustrating an example of a manufacturing method for the printed circuit board of FIG. 11. [Figure 12b] 12 is a process diagram illustrating an example of a manufacturing method for the printed circuit board of FIG. 11. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0015] The present invention will now be described with reference to the accompanying drawings, in which the shapes and sizes of elements may be exaggerated or reduced for clarity.

[0016] electronic equipment FIG. 1 is a block diagram illustrating an example of an electronic device system.

[0017] Referring to the drawing, an electronic device 1000 accommodates a main board 1010. Chip-related components 1020, network-related components 1030, and other components 1040 are physically and / or electrically connected to the main board 1010. These are also connected to other electronic components described below to form various signal lines 1090.

[0018] The chip-related components 1020 include, but are not limited to, memory chips such as volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), and flash memory; application processor chips such as central processors (e.g., CPU), graphic processors (e.g., GPU), digital signal processors, encryption processors, microprocessors, and microcontrollers; and logic chips such as analog-to-digital converters and ASICs (application-specific ICs). Needless to say, the chip-related components 1020 may include other types of chip-related electronic components. Needless to say, these chip-related components 1020 may be combined with each other. The chip-related components 1020 may be in the form of a package including the above-mentioned chips and electronic components.

[0019] The network-related components 1030 may include, but are not limited to, any other wireless and wired protocols designated as Wi-Fi (e.g., IEEE 802.11 family), WiMAX (e.g., IEEE 802.16 family), IEEE 802.20, LTE (long term evolution), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPS, GPRS, CDMA, TDMA, DECT, Bluetooth, 3G, 4G, 5G, and beyond, as well as any of a number of other different wireless or wired standards and protocols. It should be understood that the network-related components 1030 may also be combined with the chip-related components 1020 and with each other.

[0020] The other components 1040 include high-frequency inductors, ferrite inductors, power inductors, ferrite beads, LTCC (low temperature co-firing ceramics), EMI (electromagnetic interference) filters, MLCC (multi-layer ceramic capacitors), etc. However, the other components 1040 are not limited to these, and may also include passive elements in the form of chip components used for various other different applications. It goes without saying that the other components 1040 may be combined with the chip-related components 1020 and / or the network-related components 1030.

[0021] Depending on the type of electronic device 1000, the electronic device 1000 may include other electronic components that may or may not be physically and / or electrically coupled to the main board 1010. Examples of other electronic components include, but are not limited to, a camera module 1050, an antenna module 1060, a display 1070, and a battery 1080. The other electronic components may include, but are not limited to, an audio codec, a video codec, a power amplifier, a compass, an accelerometer, a gyroscope, a speaker, a mass storage device (e.g., a hard disk drive), a compact disk (CD), a digital versatile disk (DVD), and the like. Needless to say, other electronic components used for various purposes may be included depending on the type of electronic device 1000.

[0022] The electronic device 1000 may be a smart phone, a personal digital assistant, a digital video camera, a digital still camera, a network system, a computer, a monitor, a tablet, a laptop, a netbook, a television, a video game, a smart watch, an automotive, etc. However, the electronic device 1000 is not limited to these, and may be any other electronic device that processes data.

[0023] FIG. 2 is a perspective view that illustrates an example of an electronic device.

[0024] Referring to the drawings, the electronic device may be, for example, a smartphone 1100. A motherboard 1110 is housed inside the smartphone 1100, and various components 1120 are physically and / or electrically connected to the motherboard 1110. In addition, other components such as a camera module 1130 and / or a speaker 1140 that may or may not be physically and / or electrically connected to the motherboard 1110 are housed inside the smartphone 1100. Some of the components 1120 may be the above-mentioned chip-related components, for example, a component package 1121, but are not limited thereto. The component package 1121 may be in the form of a printed circuit board on which electronic components including active components and / or passive components are surface-mounted. Alternatively, the component package 1121 may be in the form of a printed circuit board in which active components and / or passive components are built-in. Meanwhile, it goes without saying that the electronic device is not necessarily limited to the smartphone 1100, and may be other electronic devices as described above.

[0025] Printed Circuit Board FIG. 3 is a cross-sectional view that shows a schematic example of a printed circuit board, and FIG. 4 is a schematic plan view of the printed circuit board shown in FIG. 3 taken along the line II'.

[0026] 1, a printed circuit board 100A according to an example includes a glass layer 111 having a through hole H penetrating between its upper and lower surfaces, a through via 130 including a via metal layer 131 disposed on a wall surface of the through hole H and a first insulating material 132 filling at least a portion of a space G between the via metal layer 131 in the through hole H, a first wiring layer 121 disposed on the upper surface of the glass layer 111 and at least a portion of which is connected to an upper side of the through via 130, and a second wiring layer 121 disposed on the lower surface of the glass layer 111 and at least a portion of which is connected to the lower side of the through via 130. the second wiring layer 122 connected to the glass layer 111, a second insulating material 112 covering at least a portion of the outer surface of the glass layer 111, a third insulating material 113 covering at least a portion of the outer surface of the second insulating material 112, a first insulating layer 141 arranged on the upper surfaces of the glass layer 111, the second insulating material 112, and the third insulating material 113 and covering at least a portion of the first wiring layer 121, and a second insulating layer 151 arranged on the lower surfaces of the glass layer 111, the second insulating material 112, and the third insulating material 113 and covering at least a portion of the second wiring layer 122.

[0027] The through hole H of the glass layer 111 may be a first through portion h1. A through via 130 including a via metal layer 131 and a first insulating material 132 may be disposed in the first through portion h1. From a similar viewpoint, the second insulating material 112 may have a second through portion h2. A through via 130 including a via metal layer 131 and a first insulating material 132 and a glass layer 111 may be disposed in the second through portion h2. From a similar viewpoint, the third insulating material 113 may have a third through portion h3. A through via 130 including a via metal layer 131 and a first insulating material 132, a glass layer 111, and a second insulating material 112 may be disposed in the third through portion h3.

[0028] The first and second insulating materials 132, 112 may include substantially the same material. For example, the first and second insulating materials 132, 112 may include substantially the same material because they can be formed by simultaneously performing a process of filling the glass layer 111 and a process of plugging the through hole H through ABF (Ajinomoto Build-up Film) or the like, as exemplified in a process described later. They may also have substantially the same degree of hardening. Therefore, the process can be simplified and furthermore, it may be more advantageous in controlling warpage during the process. Whether the filling and the plugging are simultaneously formed of substantially the same material, for example, ABF, can be confirmed by, for example, analyzing the size and dispersion degree of the filler in the ABF and the resin hardening degree (measured by FT-IR, etc.).

[0029] The third insulating material 113 may include a material different from the first and second insulating materials 132 and 112. For example, the third insulating material 113 may have a larger elastic modulus than the first and second insulating materials 132 and 112. The elastic modulus may mean a ratio of stress to deformation, and may be measured by a standard tensile test specified in, for example, JIS C-6481, KS M 3001, KS M 527-3, ASTM D882, etc. For example, the third insulating material 113 may include a material having excellent rigidity, such as an insulating material of CCL (Copper Clad Laminate), as exemplified in the process described later. In this case, the embedding process of the glass layer 111 and the plugging process of the through hole H can be performed using the third insulating material 113 as a jig. Therefore, the glass layer can be prevented from being damaged during the process, and the outer surface of the glass layer can be protected together with the second insulating material 112.

[0030] The via metal layer 131 can include a first seed layer S1 disposed on the wall surface of the through hole H, and a first metal layer M1 disposed on the side surface of the first seed layer S1. The first wiring layer 121 can include a second seed layer S2 disposed on the upper surface of the glass layer 111, and a second metal layer M2 disposed on the upper surface of the second seed layer S2. The second wiring layer 122 can include a third seed layer S3 disposed on the lower surface of the glass layer 111, and a third metal layer M3 disposed on the lower surface of the third seed layer S3. In at least a part of the first wiring layer 121, the second seed layer S2 can cover at least a part of the upper surfaces of the first seed layer S1, the first metal layer M1, and the first insulating material 132. In at least a part of the second wiring layer 122, the third seed layer S3 can cover at least a part of the lower surfaces of the first seed layer S1, the first metal layer M1, and the first insulating material 132. The first seed layer S1 may have boundaries with second and third seed layers S2, S3, respectively.

[0031] The upper surfaces of the glass layer 111, the first insulating material 132, the second insulating material 112, the first seed layer S1, and the first metal layer M1 can be substantially coplanar with each other. For example, the upper surfaces of the glass layer 111, the via metal layer 131, the first insulating material 132, the second insulating material 112, and the third insulating material 113 can be substantially coplanar with each other. The lower surfaces of the glass layer 111, the first insulating material 132, the second insulating material 112, the first seed layer S1, and the first metal layer M1 can be substantially coplanar with each other. For example, the lower surfaces of the glass layer 111, the via metal layer 131, the first insulating material 132, the second insulating material 112, and the third insulating material 113 can be substantially coplanar with each other. For example, as will be exemplified in the process described later, after the through via 130 is formed in the glass layer 111, it can be planarized using CMP (Chemical Mechanical Polishing) or the like. In this case, a circuit can be formed on the glass layer by SAP (Semi Additive Process) instead of tenting. Therefore, the first and second wiring layers 121 and 122 can be formed with fine circuits. In addition, the pads of the first and second wiring layers 121 and 122 can be directly formed on the through vias 130, ensuring freedom in terms of design.

[0032] The components of the example printed circuit board 100A are described in more detail below with reference to the drawings.

[0033] The glass layer 111 may include glass, which is a non-crystalline solid. Glass may include, for example, pure silicon dioxide (about 100% SiO2), soda-lime glass, borosilicate glass, alumino-silicate glass, etc. Alternative glass materials, such as, but not limited to, fluoride glass, phosphate glass, chalcogenide glass, etc., may also be used. Other additives may also be included to form glasses with specific physical properties. Such additives may include calcium carbonate (e.g., lime) and sodium carbonate (e.g., soda), as well as magnesium, calcium, manganese, aluminum, lead, boron, iron, chromium, potassium, sulfur, and antimony, and carbonates and / or oxides of these and other elements.

[0034] The glass layer 111 may be a layer distinct from an organic insulating material including glass fiber (glass fiber, glass cloth, glass fabric), for example, CCL (Copper Clad Laminate), PPG (Prepreg), etc. For example, the glass layer 111 may include plate glass. The glass layer 111 may be a core layer. For example, it may be a glass core.

[0035] The through hole H may penetrate the glass layer 111 in the thickness direction. For example, the through hole H may penetrate between the upper surface and the lower surface of the glass layer 111. The through hole H may have one or more holes. The through hole H may have a shape of an elliptical cylinder or a circular cylinder, but is not limited thereto, and may have an hourglass-like column shape, etc.

[0036] The first to third seed layers S1, S2, and S3 may each include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and / or an alloy thereof, and may preferably include copper (Cu), but are not limited thereto. The first to third seed layers S1, S2, and S3 may be separate layers having a boundary with each other. The first to third seed layers S1, S2, and S3 may each be formed by electroless plating (e.g., chemical copper plating) and / or sputtering. The first to third seed layers S1, S2, and S3 may each be thinner than the first to third metal layers M1, M2, and M3.

[0037] The first to third metal layers M1, M2, and M3 may each include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and / or an alloy thereof, and may preferably include copper (Cu), but is not limited thereto. The first to third metal layers M1, M2, and M3 may each be formed by electrolytic plating (e.g., copper electroplating). The first to third metal layers M1, M2, and M3 may each be thicker than the first to third seed layers S1, S2, and S3.

[0038] The first and second wiring layers 121 and 122 may each perform various functions according to the design. For example, they may include a signal pattern, a power pattern, a ground pattern, etc., and these patterns may each have various forms such as a line (or trace), a plane (or plate), a pad (or land), etc. The first and second wiring layers 121 and 122 may each include an electroless plating layer (or chemical copper) and an electrolytic plating layer (or electrolytic copper). If necessary, they may include a sputtering layer instead of the electroless plating layer (or chemical copper), or may include both the electroless plating layer (or chemical copper) and the sputtering layer.

[0039] The via metal layer 131 can perform various functions depending on the design. For example, it can include a ground via, a power via, a signal via, etc. The via metal layer 131 can include an electroless plating layer (or chemical copper) and an electrolytic plating layer (or electrolytic copper). If necessary, it can include a sputtering layer instead of the electroless plating layer (or chemical copper), or it can include both the electroless plating layer (or chemical copper) and the sputtering layer.

[0040] The first to third insulating materials 132, 112, and 113 may include organic insulating materials that are the same or different from each other. The organic insulating material may include a thermosetting resin such as an epoxy resin, a thermoplastic resin such as a polyimide, or a material including an inorganic filler, an organic filler, and / or glass fiber (glass fiber, glass cloth, glass fabric) together with a resin. For example, the organic insulating material may be a non-photosensitive insulating material such as an insulating material such as ABF (Ajinomoto Build-up Film), PPG (Prepreg), or CCL (Copper Clad Laminate), but is not limited thereto, and other polymer materials may be used. The organic insulating material may also be a photosensitive insulating material such as PID (Photo Imageable Dielectric).

[0041] The first and second insulating layers 141, 151 may also include the organic insulating material described above. The first and second insulating layers 141, 151 may include substantially the same material as each other. If necessary, the first and second insulating layers 141, 151 may include substantially the same material as the first and second insulating materials 132, 112. In this case, the boundaries between the first and second insulating layers 141, 151 and the first and second insulating materials 132, 112 may be distinct.

[0042] 5a to 5i are process diagrams that outline an example of a method for manufacturing the printed circuit board of FIG.

[0043] Referring to FIG. 5a, a third insulating material 113 having a third through-hole h3 formed therein is prepared. The third insulating material 113 may be, but is not limited to, a CCL (Copper Clad Laminate) insulating material as described above. First and second mark patterns m1 and m2 may be formed on the upper and lower surfaces of the third insulating material 113, respectively, so that the third through-hole h3 can be formed more precisely at a desired position. The third insulating material 113 may be a panel-level layer, in which case the third through-hole h3 may be multiple. The third insulating material 113 may be used as a jig.

[0044] 5b, a tape 210 is attached to the lower side of the third insulating material 113. The tape 210 can close the lower side of the third through hole h3. The tape 210 may be a known adhesive, for example, an epoxy material, but is not limited thereto.

[0045] 5c, a glass layer 111 having a first through portion h1 formed thereon is prepared, and a first seed layer S1 and a first metal layer M1 are sequentially formed on the glass layer 111 by electroless plating, electrolytic plating, or the like. Next, the glass layer 111 having the first through portion h1, the first seed layer S1, and the first metal layer M1 formed thereon is disposed in the third through portion h3 of the third insulating material 113 using a tape 210. When there are a plurality of third through portions h3, a plurality of glass layers 111 having the first through portion h1, the first seed layer S1, and the first metal layer M1 formed thereon may be prepared and then disposed in each of the third through portions h3.

[0046] 5d, a process of laminating the second insulating material 112 to embed the glass layer 111 is performed, and at the same time, a process of plugging the first through-hole h1 is performed. For example, through the lamination process, the second insulating material 112 can cover at least a portion of each of the glass layer 111 and the third insulating material 113, and can fill at least a portion of the space G between the first metal layers M1 in the first through-hole h1.

[0047] Referring to FIG. 5e, after removing the tape 210, the upper and lower surfaces of the glass layer 111, the first seed layer S1, the first metal layer M1, the second insulating material 112, and the third insulating material 113 are planarized by a planarization process such as CMP (Chemical Mechanical Polishing). For example, the first seed layer S1, the first metal layer M1, and the first and second mark patterns m1 and m2 disposed on the upper and lower surfaces of the glass layer 111, the second insulating material 112, and the third insulating material 113 may be removed by the planarization process. As a result, a through via 130 including the via metal layer 131 and the first insulating material 132 may be formed. In addition, the second insulating material 112 may have a second through portion h2 after the fact.

[0048] Referring to FIG. 5f, second and third seed layers S2, S3 are formed on the upper and lower surfaces of the planarized glass layer 111, the first seed layer S1, the first metal layer M1, the first insulator 132, the second insulator 112, and the third insulator 113, respectively, by electroless plating or the like.

[0049] 5g, second and third metal layers M2 and M3 are formed on the second and third seed layers S2 and S3, respectively, by electrolytic plating, etc. For example, a semi-additive process (SAP) can be applied, and as a result, first and second wiring layers 121 and 122 including fine circuits can be formed.

[0050] Referring to FIG. 5h, first and second insulating layers 141, 151 are formed on the upper and lower surfaces of the glass layer 111, the second insulating material 112 and the third insulating material 113, respectively, by a lamination process or the like.

[0051] 5i, at least a portion of each of the third insulating material 113 and the first and second insulating layers 141, 151 is cut. Through a series of processes, the printed circuit board 100A according to the above-mentioned example can be manufactured. As mentioned above, if the third insulating material 113 is at the panel level, the cutting process can include singulation, thereby forming a plurality of board units.

[0052] The other details are substantially the same as those described in the printed circuit board 100A according to the above-mentioned example, and therefore will not be described again.

[0053] FIG. 6 is a cross-sectional view that shows a schematic diagram of another example of a printed circuit board, and FIG. 7 is a schematic plan view of the printed circuit board shown in FIG. 6, taken along line II-II'.

[0054] Referring to the drawings, the printed circuit board 100B according to another example omits the third insulating material 113 in the printed circuit board 100A according to the above example. For example, the second insulating material 112 may be disposed on the outermost side of the board. This allows the board to be manufactured more compactly.

[0055] The other details are substantially the same as those described in the printed circuit board 100A according to the above-mentioned example, and therefore will not be described again.

[0056] 8a and 8b are process diagrams that diagrammatically show an example of the manufacture of the printed circuit board of FIG.

[0057] Referring to FIG. 8a, a laminate before a cutting step is formed by substantially the same steps as those shown in FIGS. 5a to 5h described above.

[0058] 8b, the third insulating material 113 and at least a portion of each of the first and second insulating layers 141, 151 are cut so that the third insulating material 113 does not remain on the substrate. Through a series of processes, the printed circuit board 100B according to the above-mentioned another example can be manufactured. As mentioned above, if the third insulating material 113 is at the panel level, the cutting process can include singulation, thereby forming a plurality of substrate units.

[0059] The other contents are substantially the same as those described in the example of the printed circuit board 100A and the manufacturing method thereof described above, so that a duplicated description will be omitted.

[0060] FIG. 9 is a cross-sectional view that illustrates a schematic diagram of still another example of a printed circuit board.

[0061] Referring to the drawings, a printed circuit board 100C according to another example is the printed circuit board 100A according to the above example, in which the first and second insulating layers 141, 151 are each arranged in a plurality of layers. Also, the printed circuit board 100C further includes a plurality of third wiring layers 142 arranged on or within the plurality of first insulating layers 141, respectively, and a plurality of fourth wiring layers 152 arranged on or within the plurality of second insulating layers 151, respectively. Also, the printed circuit board 100C further includes a plurality of first via layers 143 each penetrating at least one of the plurality of first insulating layers 141, and a plurality of second via layers 153 each penetrating at least one of the plurality of second insulating layers 151, respectively. It also includes a first resist layer 161 arranged on the upper surface of the first insulating layer 141 that is arranged at the uppermost side of the multiple first insulating layers 141 and having a first opening 161h that exposes at least a portion of the third wiring layer 142 that is arranged at the uppermost side of the multiple third wiring layers 142, and a second resist layer 162 arranged on the lower surface of the second insulating layer 151 that is arranged at the uppermost side of the multiple second insulating layers 151 and having a second opening 162h that exposes at least a portion of the fourth wiring layer 152 that is arranged at the lowermost side of the multiple fourth wiring layers 152.

[0062] Each of the third and fourth wiring layers 142, 152 may include a metal. The metal may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and / or an alloy thereof. Preferably, the metal may include copper (Cu), but is not limited thereto. Each of the third and fourth wiring layers 142, 152 may perform various functions according to the design. For example, the metal may include a signal pattern, a power pattern, a ground pattern, and the like. Each of these patterns may have various forms, such as a line, a plane, and a pad. Each of the third and fourth wiring layers 142, 152 may include an electroless plating layer (or chemical copper) and an electrolytic plating layer (or electrolytic copper). Alternatively, the metal may include a metal foil (or copper foil) and an electrolytic plating layer (or electrolytic copper). Alternatively, the metal may include a metal foil (or copper foil), an electroless plating layer (or chemical copper), and an electrolytic plating layer (or electrolytic copper). A sputtered layer may be included instead of the electroless plated layer (or chemical copper), or both may be included.

[0063] Each of the first and second via layers 143, 153 may include a metal. The metal may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and / or an alloy thereof. Preferably, the metal may include copper (Cu), but is not limited thereto. Each of the first and second via layers 143, 153 may include a filled via that fills a via hole, but may also include a conformal via that is disposed along the wall surface of the via hole. The first and second via layers 143, 153 may perform various functions according to the design. For example, they may include a ground via, a power via, a signal via, and the like. The first and second via layers 143, 153 may have tapered shapes in opposite directions on a cross section. The first and second via layers 143, 153 may each include an electroless plating layer (or chemical copper) and an electrolytic plating layer (or electrolytic copper). A sputtering layer may be included instead of the electroless plating layer (or chemical copper), or both may be included.

[0064] The first and second resist layers 161 and 162 may include, but are not limited to, a liquid or film type solder resist, and other types of insulating materials may be used. Surface treatment layers P1 and P2 may be formed on the patterns exposed in the first opening 161h and / or the second opening 162h, as necessary.

[0065] The other details are substantially the same as those described in the printed circuit board 100A according to the above-mentioned example, and therefore will not be described again.

[0066] 10a and 10b are process diagrams that diagrammatically show an example of a method for manufacturing the printed circuit board of FIG.

[0067] Referring to FIG. 10a, a laminate before a cutting step is formed by substantially the same steps as those shown in FIGS. 5a to 5h described above.

[0068] Referring to FIG. 10b, a plurality of first and second insulating layers 141, 151, a plurality of third and fourth wiring layers 142, 152, a plurality of first and second via layers 143, 153, and a first and second resist layer 161, 162 are formed by a build-up process. Next, at least a portion of each of the third insulating material 113, the plurality of first and second insulating layers 141, 151, and the first and second resist layers 161, 162 is cut. Through a series of processes, the printed circuit board 100C according to the above-mentioned further example can be manufactured. As described above, when the third insulating material 113 is at the panel level, the cutting process can include singulation, thereby forming a plurality of board units.

[0069] The other details are substantially the same as those described in the example of the printed circuit board 100A and the manufacturing example thereof described above, so that a duplicated description will be omitted.

[0070] FIG. 11 is a cross-sectional view that illustrates a schematic diagram of still another example of a printed circuit board.

[0071] Referring to the drawings, a printed circuit board 100D according to another example is the same as the printed circuit board 100B according to the above-mentioned another example, except that the first and second insulating layers 141, 151 are each arranged in a plurality of layers. Also, the printed circuit board 100D further includes a plurality of third wiring layers 142 arranged on or within the plurality of first insulating layers 141, and a plurality of fourth wiring layers 152 arranged on or within the plurality of second insulating layers 151. Also, the printed circuit board 100D further includes a plurality of first via layers 143 each penetrating at least one of the plurality of first insulating layers 141, and a plurality of second via layers 153 each penetrating at least one of the plurality of second insulating layers 151. It also includes a first resist layer 161 arranged on the upper surface of the first insulating layer 141 that is arranged at the uppermost side of the multiple first insulating layers 141 and having a first opening 161h that exposes at least a portion of the third wiring layer 142 that is arranged at the uppermost side of the multiple third wiring layers 142, and a second resist layer 162 arranged on the lower surface of the second insulating layer 151 that is arranged at the uppermost side of the multiple second insulating layers 151 and having a second opening 162h that exposes at least a portion of the fourth wiring layer 152 that is arranged at the lowermost side of the multiple fourth wiring layers 152.

[0072] The other details are substantially the same as those described above for the printed circuit boards 100A, 100B, and 100C, and therefore will not be described again.

[0073] 12a and 12b are process diagrams that diagrammatically show an example of a method for manufacturing the printed circuit board of FIG.

[0074] Referring to FIG. 12a, a laminate before a cutting step is formed by substantially the same steps as those shown in FIGS. 5a to 5h described above.

[0075] Referring to FIG. 12b, a plurality of first and second insulating layers 141, 151, a plurality of third and fourth wiring layers 142, 152, a plurality of first and second via layers 143, 153, and a first and second resist layer 161, 162 are formed by a build-up process. Next, at least a portion of each of the third insulating material 113, the plurality of first and second insulating layers 141, 151, and the first and second resist layers 161, 162 is cut so that the third insulating material 113 does not remain on the substrate. Through a series of processes, the printed circuit board 100D according to the above-mentioned further example can be manufactured. As described above, when the third insulating material 113 is at the panel level, the cutting process can include singulation, thereby forming a plurality of substrate units.

[0076] The other details are substantially the same as those described in the above-mentioned printed circuit boards 100A, 100B, and 100C and the example of the manufacture thereof, and therefore a duplicated description will be omitted.

[0077] In the present invention, the depth, thickness, width, length, etc. can be measured using a scanning microscope, optical microscope, etc. based on a cross section obtained by polishing or cutting the printed circuit board. The cut section may be a vertical section or a horizontal section, and each value can be measured based on the required cut section. When the value is not constant, the value can be determined as the average value of values ​​measured at any five points.

[0078] In the present invention, the term "cover" can include not only the case of covering entirely, but also the case of covering at least a part, and further, can include not only the case of covering directly, but also the case of covering indirectly. Furthermore, the term "fill" can include not only the case of filling completely, but also the case of filling almost entirely, for example, the case where some gaps or voids are present.

[0079] In the present invention, the judgment can be made by taking into account process errors, positional deviations, measurement errors, etc. that occur in the manufacturing process. For example, "substantially coplanar" can include not only cases where the two are on a completely identical plane, but also cases where the two are on an almost identical plane. Furthermore, "substantially the same material" can include not only cases where the composition and hardening degree of the material are completely the same, but also cases where the material is almost the same.

[0080] In the present invention, the meaning of "on a cross section" can mean the cross-sectional shape of an object cut vertically, or the cross-sectional shape of an object cut vertically, or the cross-sectional shape of an object when viewed from a side, and the meaning of "on a plane" can mean the planar shape of an object cut horizontally, or the planar shape of an object when viewed from a top or bottom.

[0081] In the present invention, for convenience, the terms lower, bottom, and bottom surface are used to mean the downward direction based on the cross section of the drawing, and the terms upper, top, and top surface are used to mean the opposite direction. However, this is a definition of the direction for convenience of explanation, and the scope of the claims is not particularly limited by the description of the direction, and the concepts of upper and lower can be changed at any time.

[0082] In the present invention, "connected" is a concept including not only direct connection but also indirect connection via an adhesive layer or the like. Furthermore, "electrically connected" is a concept including both physical connection and no connection. Furthermore, expressions such as "first, second" are used to distinguish one component from another component, and do not limit the order and / or importance of the components. In some cases, the first component may be named the second component, and similarly, the second component may be named the first component, within the scope of the right.

[0083] The term "one example" used in the present invention does not mean the same embodiment, but is provided to emphasize and describe unique features that are different from each other. However, the above-mentioned one example does not exclude that it is realized in combination with the features of another example. For example, even if the matter described in a specific example is not described in another example, it can be understood as a description related to the other example, unless there is a description in the other example that is opposite or contradictory to the matter.

[0084] The terms used in the present invention are merely used to describe an example and are not intended to limit the present invention. In this case, a singular expression includes a plural expression unless the context clearly indicates otherwise. [Explanation of symbols]

[0085] 1000:Electronic equipment 1010: Main board 1020: Chip related parts 1030: Network related parts 1040:Other parts 1050: Camera 1060:Antenna 1070:Display 1080: Battery 1090: Signal line 1100: Smartphone 1110: Motherboard 1120: Parts 1121: Parts package 1130: Camera module 1140: Speaker 100A, 100B, 100C, 100D: Printed circuit boards 111: Glass layer 112, 113: Insulation material 121, 122: Wiring layer 130:Through via 131: Via metal layer 132: Insulation material S1, S2, S3: seed layers M1, M2, M3: Metal layer 141, 151: Insulating layer 142, 152: Wiring layer 143, 153: via layer 161, 162: resist layer 161h, 162h: Opening P1, P2: Surface treatment layer H: Through hole G: Space h1, h2, h4: Penetration part 210: Tape m1, m2: mark pattern

Claims

1. a glass layer having a through hole penetrating between an upper surface and a lower surface; a through via including a via metal layer disposed on a wall surface of the through hole and a first insulating material filling at least a portion of the space between the via metal layer in the through hole; a first wiring layer disposed on the upper surface of the glass layer and at least a portion of the first wiring layer is connected to an upper side of the through via; a second wiring layer disposed on the lower surface of the glass layer and at least a portion of the second wiring layer connected to the lower side of the through via; a second insulating material covering at least a portion of the outer surface of the glass layer; The first insulating material and the second insulating material comprise the same material.

2. The printed circuit board of claim 1 , wherein the glass layer comprises plate glass.

3. the via metal layer includes a first seed layer disposed on a wall surface of the through hole and a first metal layer disposed on a side surface of the first seed layer; the first wiring layer includes a second seed layer disposed on an upper surface of the glass layer and a second metal layer disposed on an upper surface of the second seed layer; The printed circuit board of claim 1 , wherein the second wiring layer includes a third seed layer disposed on the lower surface of the glass layer and a third metal layer disposed on the lower surface of the third seed layer.

4. At least a portion of the first wiring layer is formed such that the second seed layer covers at least a portion of the top surfaces of the first seed layer, the first metal layer, and the first insulating material, The printed circuit board according to claim 3 , wherein at least a portion of the second wiring layer is formed such that the third seed layer covers at least a portion of the lower surfaces of the first seed layer, the first metal layer, and the first insulating material.

5. The printed circuit board of claim 4 , wherein the first seed layer has boundaries with the second seed layer and the third seed layer, respectively.

6. an upper surface of each of the glass layer, the first insulating material, the second insulating material, the first seed layer, and the first metal layer are coplanar with one another; 5. The printed circuit board of claim 4, wherein the bottom surfaces of the glass layer, the first insulating material, the second insulating material, the first seed layer, and the first metal layer are coplanar with each other.

7. a third insulating material covering at least a portion of an outer surface of the second insulating material; The printed circuit board of claim 1 , wherein the third insulating material comprises a different material than the first insulating material and the second insulating material.

8. The printed circuit board of claim 7 , wherein the third insulating material has a greater elastic modulus than the first insulating material and the second insulating material.

9. the upper surfaces of the glass layer, the via metal layer, the first insulating material, the second insulating material, and the third insulating material are coplanar with one another; 8. The printed circuit board of claim 7, wherein the bottom surfaces of the glass layer, the via metal layer, the first insulating material, the second insulating material, and the third insulating material are coplanar with each other.

10. one or more first insulating layers disposed on upper surfaces of the glass layer and the second insulating material, respectively, and covering at least a portion of the first wiring layer; 2. The printed circuit board according to claim 1, further comprising one or more second insulating layers disposed on the lower surfaces of the glass layer and the second insulating material, respectively, and covering at least a portion of the second wiring layer.

11. one or more third wiring layers disposed on or within the one or more first insulating layers, respectively; one or more first via layers each penetrating at least one of the one or more first insulating layers; one or more fourth wiring layers disposed on or within the one or more second insulating layers; The printed circuit board of claim 10 , further comprising one or more second via layers each penetrating at least one of the one or more second insulating layers.

12. a first resist layer disposed on an upper surface of the first insulating layer that is disposed on the uppermost side of the one or more first insulating layers, the first resist layer having a first opening that exposes at least a part of the third wiring layer that is disposed on the uppermost side of the one or more third wiring layers; 12. The printed circuit board according to claim 11, further comprising: a second resist layer disposed on a lower surface of a second insulating layer disposed on the lowest side of the one or more second insulating layers, the second resist layer having a second opening that exposes at least a portion of a fourth wiring layer disposed on the lowest side of the one or more fourth wiring layers.

13. a through via including a via metal layer and a first insulating material filling at least a portion of a space between the via metal layer; a glass layer including a first penetrating portion in which the through via is disposed; a second insulating material including a second through portion in which the through via and the glass layer are disposed; a first wiring layer disposed on the upper surface of the glass layer and at least a portion of the first wiring layer is connected to an upper side of the through via; a second wiring layer disposed on the lower surface of the glass layer and at least a portion of the second wiring layer connected to the lower side of the through via; a first insulating layer disposed on an upper surface of the glass layer and an upper surface of the second insulating material, the first insulating layer covering at least a portion of the first wiring layer; a second insulating layer disposed on a lower surface of each of the glass layer and the second insulating material and covering at least a portion of the second wiring layer; The first insulating material and the second insulating material comprise the same material.

14. The printed circuit board of claim 13 , wherein the first insulating material and the second insulating material comprise Ajinomoto Build-up Film (ABF).

15. a third insulating material including a third through portion in which the through via, the glass layer, and the second insulating material are disposed; The printed circuit board of claim 13 , wherein the third insulating material comprises a different material than the first insulating material and the second insulating material.

16. The printed circuit board of claim 15 , wherein the third insulating material comprises a copper clad laminate (CCL) insulating material.

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