Lookup Tables for Nonlinear Systems

Abstract

In the illustrated example, the circuit (100) includes a multiplexer (112). The multiplexer (112) receives an input voltage (110) and a calibration signal. An analog-to-digital converter (ADC) (106) is coupled to the multiplexer (112) and generates an output code in response to the calibration signal. A storage circuit (108) is coupled to the ADC (106) and stores an input code representing the calibration signal at an address corresponding to the output code. The stored input code includes an index value and a coarse value.

Description

[Technical field]

[0001] This specification relates generally to analog-to-digital converters, and more specifically to the use of look-up tables (LUTs) in ADCs. [Background technology]

[0002] In many electronic devices, an analog input voltage is converted to a digital output signal using an analog-to-digital converter (ADC). The ADCs used to digitize signals in radio frequency (RF) sampling receivers may be required to operate at high speeds. These speeds may be on the order of gigasamples per second. However, for ADCs to operate at such high speeds, it is necessary to correct for the nonlinearities of the high speed ADC. Summary of the Invention

[0003] In the illustrated example, the circuit includes a multiplexer. The multiplexer receives an input voltage and a calibration signal. An analog-to-digital converter (ADC) is coupled to the multiplexer and generates an output code in response to the calibration signal. A storage circuit is coupled to the ADC and stores an input code representing the calibration signal at an address corresponding to the output code. The stored input code includes an index value and a coarse value.

[0004] The present disclosure also relates to a method that includes receiving an input voltage and a calibration signal, generating an output code by an analog-to-digital converter (ADC) in response to the calibration signal, and storing an input code representing the calibration signal at an address corresponding to the output code, the stored input code including an index value and a coarse value.

[0005] The present disclosure also relates to a device including a processor, a memory coupled to the processor, and a circuit coupled to the processor and the memory. The circuit includes a multiplexer. The multiplexer receives an input voltage and a calibration signal. An analog-to-digital converter (ADC) is coupled to the multiplexer and generates an output code in response to the calibration signal. A storage circuit is coupled to the ADC and stores an input code representing the calibration signal at an address corresponding to the output code. The stored input code includes an index value and a coarse value. [Brief description of the drawings]

[0006] [Figure 1] FIG. 2 is a block diagram illustrating a circuit according to an example embodiment.

[0007] [Diagram 2] FIG. 2 is a block diagram illustrating how a lookup table is used in a storage circuit to convert raw data to a final output according to one embodiment.

[0008] [Diagram 3] 2 is a block diagram of a portion of the circuit shown in FIG. 1 according to one embodiment.

[0009] [Figure 4] 4 is a flow chart of a method of operation of a circuit according to one embodiment.

[0010] [Diagram 5] FIG. 1 is a block diagram illustrating an example device in which some aspects of the example embodiments may be implemented.

[0011] [Figure 6] FIG. 2 is a block diagram of a back-end analog-to-digital converter in accordance with an example embodiment.

[0012] [Figure 7] 7 is a block diagram of a combiner for connecting the multi-bit stage shown in FIG. 6 to a first one of the single-bit stages, according to an example embodiment.

[0013] [Figure 8] 7 is a graph illustrating an AND gate delay and a comparator delay generated by an AND gate and a delay comparator, respectively, of the back-end ADC of FIG. 6, in accordance with an example embodiment, where the AND gate delay and the comparator delay are functions of the input signal delay.

[0014] [Figure 9] 9 is a graph illustrating output signal delay as a function of input signal delay of FIG. 8 in accordance with an example embodiment.

[0015] [Figure 10] FIG. 7 is a circuit diagram of an example of a comparator circuit merged with a sign-out and delay-out circuit for the back-end ADC of FIG. 6 in accordance with an example embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0016] The same reference numbers or other reference designators are used in the drawings to designate the same or similar features (functionally and / or structurally).

[0017] Commonly owned U.S. application Ser. No. 17 / 568,972, filed Jan. 5, 2022, entitled “Calibration Scheme for Nonlinear ADCs” (TI-100164), is hereby incorporated by reference in its entirety. [Patent Document 1] U.S. Application No. 17 / 568,972

[0018] 1 is a block diagram of a circuit 100 according to an example embodiment. The circuit 100 includes a calibration engine 102, a digital-to-analog converter (DAC) 104, an analog-to-digital converter (ADC) 106, and a storage circuit 108. The DAC 104 is coupled to the calibration engine 102. The ADC 106 is coupled to the calibration engine 102, the storage circuit 108, and the DAC 104 (via a multiplexer M112). The storage circuit 108 is also coupled to the calibration engine 102. In an example embodiment, the storage circuit 108 may implement a LUT (look up table).

[0019] The multiplexer M112 is coupled between the DAC 104 and the ADC 106. The multiplexer M112 is also coupled to the calibration engine 102. The multiplexer M112 receives an input voltage Vin110 and selectively outputs the input voltage Vin110 or the output of the DAC 104. The ADC 106 includes a preamplifier array 116, a delay multiplexer DM120, and a back-end ADC 124. The preamplifier array 116 is coupled to the multiplexer M112 and includes a plurality of preamplifiers. The delay multiplexer DM120 is coupled to the preamplifier array 116. The back-end ADC 124 is coupled to the delay multiplexer DM120. The storage circuit 108 is coupled to the back-end ADC 124. The storage circuit 108 may be constructed of digital memory circuits (e.g., RAM, ROM), registers, and / or flip-flops. The storage circuit 108 may be part of a conventional memory circuit or part of a digital processor system. The calibration engine 102, in one example, is or is part of a processing unit, a digital signal processor (DSP), a processor, and / or a programmable logic device. The calibration engine 102 may include memory and logic. In some example embodiments, the ADC 106 may be implemented as a voltage-to-delay converter ("V2D"). Examples of such V2D converters are described in commonly assigned U.S. Patent Nos. 10,284,188, 10,673,456, 10,673,452, and 10,673,453, each of which is incorporated herein by reference in its entirety. [Patent Document 2] U.S. Patent No. 10,284,188 [Patent Document 3] No. 10,673,456 [Patent Document 4] No. 10,673,452 [Patent Document 5] No. 10,673,453

[0020] In some example embodiments, each of the components of ADC 106 can communicate independently with calibration engine 102 and with other components of circuit 100. However, for the sake of brevity, these connections are not discussed herein. Each block or component of circuit 100 can also be coupled to other blocks in FIG. 1, but for the sake of brevity, those connections are not described herein. Circuit 100 can include one or more conventional components that are not described herein for the sake of brevity.

[0021] In one example, the circuit 100 is an analog-to-digital converter. The circuit 100 operates in a calibration mode and a mission mode (also referred to as a "normal" mode of operation). In the calibration mode, the calibration engine 102 generates a plurality of input codes, each corresponding to a known analog voltage. The DAC 104 generates a calibration signal (e.g., an analog voltage) in response to the plurality of input codes. For example, the DAC 104 generates a first calibration signal in response to a first input code of the plurality of input codes. The multiplexer M112 provides the first calibration signal to the ADC 106 in the calibration mode. The preamplifier array 116 and the delay multiplexer DM120 generate a delayed signal in response to the first calibration signal. In one example, the delayed signal represents a value of the analog input signal based on an amount of delay in the generated signal. The back-end ADC 124 generates a first output code in response to the delayed signal. The storage circuit 108 stores the first output code corresponding to the first input code. The storage circuit 108 stores an output code corresponding to each input code of the plurality of input codes. In one example embodiment, the storage circuit 108 maintains a look-up table (LUT) for storing an output code corresponding to each input code. In an example embodiment, the output of the ADC 106 ("ADC Raw Code") may be M bits, and the output of the storage circuit 108 ("Corrected Output") may be N bits.

[0022] Similarly, the DAC 104 generates a second calibration signal in response to a second input code (of the multiple input codes) generated by the calibration engine 102. The preamplifier array 116 and delay multiplexer DM 120 generate a delayed signal in response to the second calibration signal. The back-end ADC 124 generates a second output code in response to the delayed signal. The storage circuit 108 stores a second output code corresponding to the second input code. The first output code is stored in a first location in the storage circuit 108, and the second output code is stored in a second location in the storage circuit 108. Thus, for each input code generated by the calibration engine 102, an output code is stored in a look-up table in the storage circuit 108. The look-up table in the storage circuit 108 is populated in the calibration mode with the input code and the corresponding output code. This look-up table is used by the circuit 100 in the mission mode, as discussed in the detailed description below.

[0023] The following Table 1 is an example to illustrate the operation of circuit 100 while operating in calibration mode. Table 1 illustrates input codes generated by calibration engine 102 and corresponding output codes generated by ADC 106 and stored in a lookup table in storage circuit 108. [Table 1]

[0024] As shown in Table 1, for an input code 0 generated by the calibration engine 102, an output code 0 is stored in the storage circuit 108. Similarly, for an input code 2, the output code is 10, which is stored in the storage circuit 108. The storage circuit 108 stores an output code for each input code generated by the calibration engine 102. It is understood that both the input and output codes are stored and processed in binary form in the circuit 100, and decimal values ​​are considered for ease of understanding. In one example, each input code is N bits and each output code is N+n bits, where N and n are both integers and greater than zero. This reduces the nonlinearity of the ADC 106. As shown in Table 1, when N is 13, the lookup table in the storage circuit 108 is (2 N ) corresponding to the input code (2 N In Table 1, N is 13 and n is 2, so the range of output codes stored in the storage circuit 108 is from 0 to 32767 (e.g., 32768 (2 13+2 )). In Table 1, the input codes are addresses and the output codes are data. The advantage of having a lookup table as shown in Table 1 is that the memory requirements are reduced. The memory requirements for a lookup table are approximately 120k (2 13 x15=2 N ×(N+n)=number of storage locations × number of bits of data. However, a lookup table such as that shown in Table 1 is more suitable for the slow operation of circuit 100.

[0025] A solution to overcome this problem is to populate the lookup table shown in Table 1 in an inverse fashion (where the address for each of the stored values ​​is provided by the output code). This is shown in Table 2, which is another example to illustrate the operation of circuit 100 while operating in calibration mode. Table 2 shows the input codes generated by calibration engine 102 and the output codes generated by back-end ADC 124 that correspond to the input codes. [Table 2]

[0026] As shown in Table 2, for an input code 0, an output code 0 is generated, and the input code 0 is stored in the storage circuit 108 at the address of the output code, which is 0. Similarly, for an input code 1, the output code generated is 8. The input code 1 is stored in the storage circuit 108 at the corresponding address of the output code, which is 8. Thus, in Table 2, the input codes are data and the output codes are addresses. Compared with the lookup table shown in Table 1, the lookup table shown in Table 2 enables faster operation of the circuit 100. However, as shown in Table 2, the lookup table requires an increased memory area in the storage circuit 108. The memory requirement of the lookup table is approximately 420k (2 15 ×13=2 N+n ×(N), where N is 13 and n is 2.

[0027] To reduce memory requirements in storage circuit 108 and to enable high speed operation of circuit 100, the following scheme is used in some example embodiments. Table 3 below is an example to illustrate the operation of circuit 100 while operating in a calibration mode. Table 3 illustrates input codes generated by calibration engine 102 and output codes generated by back-end ADC 124 corresponding to the input codes. In the example embodiment illustrated in Table 3, a value of "0" (e.g., logic low or logic 0) or "1" (e.g., logic high or logic "1") is stored in each location for the input code. A value of "1" specifies an increment of 1 (relative to the previously stored value for the input code), while a value of "0" specifies that the input code is the same as the previous value for the input code. [Table 3]

[0028] As shown in Table 3, for input code 0, output code 0 is generated and input code 0 is stored in storage circuit 108 at the address of the output code, which is 0. Similarly, the input codes corresponding to output codes 1 through 7 remain 0. Thus, the input codes corresponding to storage locations 1 through 7 remain "0". However, when the input code is 1, the output code is 8. Since the input code is 1 greater than the input codes corresponding to output codes 0 through 7, the input code corresponding to address 8 (the value of the output code) is "1". Since the input code is 1, the output code is 9, so the value of "0" is stored at address 9 since the input code is the same as the previous input code (e.g., the input code corresponding to output code 8). When the input code is 2, the output code is 10. Since the input code increases (compared to the input code corresponding to the input code for output code 9), the value stored at address 10 is "1". In Table 3, as in Table 2, the input codes are data and the output codes are addresses. To calculate the output code for a particular input code, the input codes need to be summed at all memory locations before the input code that corresponds to the particular output code. For example, when the output code is 10, the sum of all input codes up to the current address (or output code 10) is 2. Thus, the lookup table allows for fast operation of the circuit 100. However, this solution requires large computational power since a summation operation needs to be performed for each memory location. The memory requirement of the lookup table in Table 3 is approximately 32k (2 15 =2 N+n where N is 13 and n is 2).

[0029] To enable high speed operation of circuit 100, the following scheme is used. Table 4 below is an example to illustrate the operation of circuit 100 while operating in calibration mode. Table 4 shows the input codes generated by calibration engine 102 and the output codes generated by back-end ADC 124 that correspond to the input codes. As discussed with reference to Tables 2 and 3, the output codes are addresses for the corresponding input codes (data). [Table 4]

[0030] Similar to Tables 1-3, in Table 4, output code 0 is generated for input code 0, and output code 8 is generated for input code 1. The input codes are stored as data, and the output codes are stored as addresses, e.g., the input codes are stored at the corresponding addresses of the output codes. The stored input codes include an index value and a coarse value (e.g., a cumulative sum of the index values). The index values ​​are represented in Table 4 (in the column for the input code) as "0", "1", "0", etc., and the coarse values ​​are represented as "0000X", "0001X", etc. Similar to the values ​​for the input codes in Table 3, when the input code corresponding to the current output code is not equal to the input code corresponding to the previous output code, the index value is 1. When the input code corresponding to the current output code is equal to the input code corresponding to the previous output code, the index value is 0. For example, as shown in Table 2, for all output codes 1 to 7, the input code is 0. When the output code is 8, the input code is 1. Thus, the index value remains 0 for output codes 1 through 7, and when the output code is 8, the index value is 1. Whenever the input code corresponding to the current output code (e.g., output code 8) is not equal to the input code corresponding to the previous output code (e.g., output code 7), the index value is 1.

[0031] The coarse value for the current output code is the sum of the index values ​​generated corresponding to all previous output codes in addition to the index value corresponding to the current output code. The coarse value represents a cumulative sum of the input codes. For example, the coarse value for the current output code (e.g., output code 10) is the sum of all index values ​​generated corresponding to all previous output codes (e.g., index values ​​generated corresponding to output codes 1 through 9) plus the index value corresponding to the current output code (e.g., output code 10). The sum of all index values ​​up to output code 10 is 0002. The memory requirement for the lookup table in Table 4 is approximately 450k (2 15 x14=2 N+n × the number of bits stored for each input code, where N is 13 and n is 2.

[0032] To further refine the lookup table shown in Table 4, the following exemplary embodiment shown in Table 5 may be used. The output code includes a sum of M (e.g., most significant) bits and L (e.g., least significant) bits, where M and L are both integers greater than or equal to 1. The output code is reduced to M bits, and the index value is supplemented with L bits. The reduced output code is called the block index (BI). The coarse value is 2^L (e.g., 2 L ) bits. For example, when the output code is 15 bits (N+n) (as explained above with reference to Tables 1-4), M is 10 bits and L is 5 bits. The output code is reduced to 10 bits and the index value is supplemented with 5 bits. This is shown in Table 5 below. The reduced output code therefore ranges from 0 to 1023 (2 10 ), and the index value is 32 bits (2 5 ) The coarse value is stored for each 32 bits, for example for each block index. The coarse value represents the cumulative sum of the input codes. [Table 5]

[0033] The input codes are generated by the calibration engine 102, and the output codes (corresponding to the input codes) are generated by the back-end ADC 124. Similar to Table 4, in Table 5, for input code 0, output code 0 is generated, and for input code 1, output code 8 is generated. The input codes are stored as data, and the output codes are stored as addresses. The stored input codes include an index value and a coarse value. Similar to the embodiment described with reference to Tables 2-4, when the input code corresponding to the current output code is not equal to the input code corresponding to the previous output code, the index value is 1. When the input code corresponding to the current output code is equal to the input code corresponding to the previous output code, the index value is 0. As shown in Table 5 (and with reference to Table 4), when the output code is 0 and the index value continues to be 0 for output codes 1 through 7, the index value is 0. When the output code is 8, the index value is 1. Similarly, when the output code is 10, the index value is 1, and when the output code is 11, the index value is 1.

[0034] A coarse value is stored for every 32 bits of the index value. Thus, a coarse value is stored for each block index. The coarse value is the sum of all index values ​​generated corresponding to all previous block indexes. For example, when BI is 0, the coarse value is 0, and when BI is 1, the coarse value is 5, which is the sum of all index values ​​generated corresponding to BI 0. Similarly, when BI is 2, the coarse value is 16, which is the sum of all index values ​​generated corresponding to BI 0 and 1. The memory requirement for the lookup table in Table 5 is approximately 45k (2 10 ×(32+13)=2 M ×(2 L +N).

[0035] Thus, the lookup table represented in Table 5 requires less memory than conventional solutions and also supports high speed operation of circuit 100. In one exemplary embodiment, circuit 100 is an ADC and the lookup table shown in Table 5 enables the ADC to operate at GSPS speeds. Thus, the lookup table in storage circuit 108 is populated in calibration mode with input codes and corresponding output codes as shown in Table 5. This lookup table is used by circuit 100 in mission mode, as discussed in the next paragraph.

[0036] In the mission mode, the multiplexer M112 provides the input voltage Vin110 to the multiplexer M112. In one exemplary embodiment, the multiplexer M112 is controlled by the calibration engine 102. The combination of the preamplifier array 116 and the delay multiplexer DM120 generates a delayed signal in response to the input voltage Vin110. The back-end ADC 124 generates a low code (ADC low code) in response to the delayed signal. The input code stored at an address corresponding to the low code in the look-up table (similar to the look-up table represented in Table 5) in the storage circuit 108 is generated as the final output 130 (corrected output) by the circuit 100. For each value of the input voltage Vin110, the low code is matched with the address of the output code, and the input code stored at the address is provided as the final output 130. Thus, the mission mode, in one version, represents normal operation of the circuit 100, in which an analog signal (such as a radio frequency analog signal) is received as Vin 110 and converted to a digital representation (e.g., binary) via the ADC 106 and storage circuit 108. The final output 130 is thus a digital representation of the analog signal Vin 110.

[0037] The multiplexer M112, the ADC 106, and the storage circuit 108 form one channel in the circuit 100. The circuit 100 can be implemented with two or more channels. In one example embodiment, each channel can be implemented in parallel with the other channel. The second channel would include a second multiplexer (e.g., similar to the multiplexer 112), a second ADC (e.g., similar to the ADC 106), and a second storage circuit (e.g., similar to the storage circuit 108). The second back-end ADC in the second channel could be similar to the back-end ADC 124 in the first channel, but both are calibrated separately because they may have different transfer functions due to manufacturing variations. Multiple channels can provide flexibility, such as operating one channel in a calibration mode and another channel in a mission mode. Thus, when one channel is being calibrated, the other channel is used in the mission mode for analog-to-digital conversion. In one example, all channels are calibrated using DAC 104, and all channels are controlled by calibration engine 102. In some example embodiments, the back-end ADC in each channel is independently calibrated, so there is no need to perform any matching between channels, which also reduces the requirements for back-end estimation and calibration algorithms.

[0038] In one example, the combination of the preamplifier array 116, the delay multiplexer DM 120, and the back-end ADC 124 acts as a nonlinear ADC or a delay-based ADC. Although this combination is highly nonlinear, the circuit 100 is highly linear and operates at high speed with relaxed area and power requirements. The circuit 100 scales well with technology nodes. The circuit 100 pushes high linearity requirements on the DAC 104. This is advantageous because it is relatively easy to design and implement analog circuits for operation at low speed with linearity and accuracy. In accordance with the present disclosure, the back-end ADC 124 can be designed to perform at high speed by compromising on linearity. However, the back-end ADC 124 is operating in conjunction with a look-up table in the storage circuit 108, and the circuit 100 behaves like a linear analog-to-digital converter (ADC). Similarly, the storage circuit 108 can be implemented in digital circuitry and configured for high speed.

[0039] Interfacing external analog signals to high-speed digital processing cores generally requires an ADC. Faster speeds in the transmission of data may require ADCs to operate at much higher speeds and with good signal-to-noise ratios. Without the benefit of some example embodiments, such constraints result in high power dissipation and large area requirements to support integrated circuits. These issues may be particularly pronounced at high sampling rates (e.g., sampling rates on the order of giga samples per second (GSPS)) due to analog non-idealities that may limit performance. Example embodiments of circuit 100 provide a look-up table approach to back-end ADC 124 that can be calibrated to provide the superior performance of a highly linear ADC, while allowing a wide range of architectures to be utilized using one or more nonlinear ADCs.

[0040] In calibration mode, the look-up table in the storage circuit 108 is populated as shown in Table 5, and in mission mode, the circuit 100 uses the high-speed ADC 106 and the storage circuit 108 to generate an output code corresponding to the input voltage Vin 110. Thus, the circuit 100 does not use any complex algorithms or hardware for digital conversion of the input voltage Vin 110. This reduces the area and power requirements of the circuit 100. Thus, the circuit 100 can be used in RF sampling receivers operating at GSPS speeds. The circuit 100 scales well with technology nodes and can support high GSPS transfer rates in future technology nodes.

[0041] FIG. 2 is a block diagram 200 to illustrate how to convert raw data to a final output using a lookup table in a storage circuit according to one embodiment. The block diagram 200 is described in relation to the circuit 100 shown in FIG. 1 and represents the digital conversion of an input voltage Vin 110 to a final output 130. The storage circuit 108 stores data as shown in Table 5. In one example, a sum memory 204, a secondary adder 206, and a primary adder 210 are part of the storage circuit 108. A 15-bit raw code is received from the back-end ADC 124. Five LSBs (least significant bits) are provided to the secondary adder 206, and ten MSBs (most significant bits) are provided to the sum memory 204.

[0042] The sum memory 204 determines a block index (BI) based on the MSB and accordingly provides a corresponding coarse value (e.g., in the form of 13 bits) to the primary adder 210. The 32 index values ​​corresponding to the BI are provided from the sum memory 204 to the secondary adder 206. The secondary adder 206 performs an AND operation on the 32 index values ​​and a bit mask. The bit mask is obtained from the 5-bit LSB. The secondary adder 206 sums the bits obtained after the AND operation, and the summed value is provided (in the form of 5 bits) to the primary adder 210. The primary adder sums the 13 bits received from the sum memory 204 and the 5 bits received from the secondary adder 206 to generate the final output 230. The method will now be explained with the help of an example using Table 5 described in connection with FIG. 1.

[0043] As an example, when the received input voltage Vin110 is equivalent to a decimal value of 34 (which represents an analog voltage level), the raw code will be represented as 000000000100010. The first 10 bits (0000000001) are the most significant bits (MSBs) and the last 5 bits (00010) are the least significant bits (LSBs). In the sum memory 204, the block index (BI) is determined from the MSB. MSB 0000000001 represents BI 1, whose coarse value is 5 (from Table 5). The coarse value is provided to the primary adder 210 in the form of 13 bits. Based on the block index (BI), the sum memory provides 32 bits of the index value to the secondary adder 206. The 32 bits provided when BI is 1 are 1000 0001 1100 0011 0111 0000 0100 0010. The secondary adder 206 performs an AND operation on the 32 bits received from the sum memory 204 and the bit mask, which in this example is 1110 0000 0000 0000 0000 0000 0000 0000. The bit mask is taken from the LSBs (e.g., the 5 LSBs in this example). The binary value of the 5 LSBs is 2. The number of ones in the bit mask is therefore the binary value of the LSBs plus 1 (so, for example, the value is 3 in this example). Thus, the first 3 bits of the bit mask are ones and the remaining bits are zero. The bits taken after the AND operation are summed. In this example, the sum of the ANDed bits results in a sum of ones. This sum of ones is provided to the primary adder 210 in the form of five bits.

[0044] The primary adder 210 sums the coarse value received from the sum memory 204 and the sum value from the secondary adder 206 to generate the final output 230. In this example, the primary adder 210 receives a 5 from the sum memory 204 and a 1 from the secondary adder 206, which sum is 6, so the primary adder 210 generates a binary representation of 6 as the final output 230. The sum of the index values ​​up to 34 bits (from Table 5) results in a sum of 6, which verifies that the resulting final output 230 is correct. Thus, the lookup table storage represented in Table 5 requires less memory compared to conventional solutions and also supports high speed operation of the circuit 100. In one exemplary embodiment, the circuit 100 is an ADC, and the lookup table shown in Table 5 enables the ADC to operate at GSPS speeds.

[0045] FIG. 3 is a block diagram of a portion of the circuit 100 shown in FIG. 1 according to an example embodiment. The preamplifier array 116 includes a plurality of preamplifiers, numbered 1 through n, where n is an integer. Each of the preamplifiers has one input coupled to an input voltage Vin 110 and another input coupled to a reference voltage (Vt1, Vt2, ... Vtn, etc.). These preamplifiers are labeled preamplifier 316a, preamplifier 316b...preamplifier 316n. A delay multiplexer DM120 is coupled to the plurality of preamplifiers in the preamplifier array 116 (via the differential outputs of each preamplifier, such as OUT_P1 and OUT_M1 for preamplifier 316a). The back-end ADC 124 is coupled to the delay multiplexer DM120 by differential signal lines, OUT_P and OUT_M. Calibration engine 102 is coupled to each preamplifier in preamplifier array 116 via input line 340, delay multiplexer DM 120, and back-end ADC 124. Calibration engine 102 provides a timing signal to each preamplifier via input line 340, which in one exemplary embodiment is used to reset the preamplifier.

[0046] In operation, the preamplifier 116 receives the input voltage Vin110 from the multiplexer M112. Similar to amplifiers 54-60 of U.S. Patent No. 10,673,456 (which is hereby incorporated by reference in its entirety), each preamplifier receives a different threshold voltage. For example, preamplifier 316a receives the threshold voltage Vt1, preamplifier 316b receives the threshold voltage Vt2, and preamplifier 316n receives the threshold voltage Vtn. In one example, Vt1 < Vt2 < Vtn. The threshold voltages Vt1, Vt2 - Vtn are generated using a voltage divider 330 in one exemplary embodiment. Each preamplifier generates first and second output signals based on the difference between the input voltage Vin110 and the threshold voltage. For example, preamplifier 316a generates a differential signal, i.e., a first output signal OUT_M1 and a second output signal OUT_P1. Similarly, preamplifier 316n generates a differential signal, i.e., a first output signal OUT_Mn and a second output signal OUT_Pn.

[0047] Similar to the operation of the multiplexer 211 in U.S. Pat. No. 10,673,452 (incorporated herein by reference in its entirety), the delay multiplexer DM120 receives first and second output signals from each preamplifier of the plurality of preamplifiers. The delay multiplexer DM1220 generates delayed signals (e.g., OUT_M and OUT_P) based on the output of one of the preamplifiers. The delayed signals include a first delayed signal OUT_M and a second delayed signal OUT_P, which correspond to the output signal of the preamplifier whose threshold voltage is closest to the input voltage Vin110. For example, when the input voltage Vin110 is closest to the threshold voltage Vt1 of the preamplifier 316a, the first delayed signal OUT_M and the second delayed signal OUT_P correspond to the first and second output signals OUT_M1 and OUT_P1 of the preamplifier 316a. On the other hand, when the input voltage Vin110 is closest to the threshold voltage Vt2 of the preamplifier 316b, the first delayed signal OUT_M and the second delayed signal OUT_P correspond to the first and second output signals OUT_M2 and OUT_P2 of the preamplifier 316b. In one example, the calibration engine 102 enables the delay multiplexer DM120 to select the output signal of the preamplifier whose threshold voltage is closest to the input voltage Vin110. The back-end ADC 124 generates a first raw code in response to the delayed signal.

[0048] The preamplifiers preamplifiers 316a, 316b, 316n in the preamplifier array 116 have varying gain as a result of various factors that may include design, process, input voltage VIN, and / or temperature (e.g., "gain" as used herein may mean voltage gain, current gain, or delay; as discussed in more detail below, the amplifiers / comparators have different delays based on the input signal). In one example, the gain and range of the preamplifiers preamplifiers 316a, 316b, 316n may be adjustable and preferably matched across the preamplifier array 116. The preamplifier array 116 and back-end ADC 124 enable the circuit 100 to operate as a high-speed and high-performance analog-to-digital converter (ADC).

[0049] FIG. 4 is a flowchart 400 of a method of operation of a circuit according to an example embodiment. The flowchart 400 is described with reference to the circuit 100 of FIG. 1. In step 402, an input voltage and a calibration signal are received. In the circuit 100, the multiplexer M112 receives the input voltage Vin110 and the calibration signal from the DAC 104. The circuit 100 as shown in FIG. 1 includes only a single channel. This signal channel operates in either a calibration mode or a mission mode. In an alternative embodiment, as described above, the circuit 100 may include multiple channels (each channel may include the multiplexer 112 and the ADC 106, may share a calibration engine or have a dedicated calibration engine, and may share a storage circuit or have a dedicated storage circuit) and each channel may operate in a mission mode and / or a calibration mode. In the calibration mode, the calibration engine 102 generates multiple input codes. The DAC 104 generates a first calibration signal in response to a first input code of the plurality of input codes. In step 404, an output code is generated by an analog-to-digital converter (ADC) in response to the calibration signal. In the circuit 100, the multiplexer M112 provides the first calibration signal to the ADC 106 in a calibration mode. The preamplifier array 116 and the delay multiplexer DM120 generate a delayed signal in response to the first calibration signal. The back-end ADC 124 generates a first output code in response to the delayed signal.

[0050] In step 406, the input code is stored at an address corresponding to the output code. The stored input code includes an index value and a coarse value. The storage circuit 108 stores a first output code corresponding to the first input code in the circuit 100. The storage circuit 108 stores an output code corresponding to each input code of the plurality of input codes. In one exemplary embodiment, the storage circuit 108 maintains a look-up table to store an output code corresponding to each input code. As discussed in connection with Tables 4 and 5, the input code is stored as data and the output code is stored as an address. The input code is stored at a corresponding address of the output code. The stored input code includes an index value and a coarse value.

[0051] The index value is a binary "0" when the input code corresponding to the current output code is equal to the input code corresponding to the previous output code. The coarse value for the current output code is the sum of the index values ​​generated corresponding to all previous output codes and the index value corresponding to the current output code. The coarse value represents the cumulative sum of the input codes. Table 5 represents a lookup table in the storage circuit 108, which requires less memory compared to conventional solutions and also supports high speed operation of the circuit 100. The output code comprises a sum of M and L bits, where M and L are both integers greater than or equal to 1.

[0052] The output code is reduced to M bits, and the index value is supplemented with L bits. The coarse value is stored every 2^L bits. For example, when the output code is 15 bits, M is 10 bits, and L is 5 bits. The output code is reduced to 10 bits, while the index value is supplemented with 5 bits. The memory requirement for the lookup table in Table 5 is approximately 45k (2 10 ×(32+13)).

[0053] Thus, the lookup table in the storage circuit 108 is populated in the calibration mode with the input codes and corresponding output codes as shown in Table 5. This lookup table is used by the circuit 100 in the mission mode. In the mission mode, an analog signal (such as a radio frequency analog signal) is received as Vin 110 and converted to a digital (e.g., binary) representation via the ADC 106 and the storage circuit 108. The circuit 100 uses a high speed ADC and a lookup table in the storage circuit for conversion of the input voltage Vin which reduces the area and power requirements of the circuit 100. In one example, the circuit 100 can be used in an RF sampling receiver operating at GSPS speeds.

[0054] 5 is a block diagram of an example device 500 in which some aspects of the example embodiments can be implemented. Device 500 may be, be incorporated into, or be part of a server farm, a vehicle, a communication device, a transceiver, a personal computer, a gaming platform, a computing device, or any other type of electronic system. Device 500 may include one or more conventional components not described herein for the sake of brevity.

[0055] In one example, the device 500 includes a microcontroller unit 502 and a memory 506. The microcontroller unit 502 can be a CISC (Complex Instruction Set Computer) CPU, a RISC (Reduced Instruction Set Computer) CPU, a Digital Signal Processor (DSP), a processor, a CPLD (Programmable Complex Logic Device), or an FPGA (Field Programmable Gate Array).

[0056] The memory 506 (which may be memory such as RAM, flash memory, or disk storage) stores one or more software applications (e.g., embedded applications) that, when executed by the microcontroller unit 502, perform any suitable functions associated with the device 500.

[0057] The microcontroller unit 502 may include memory and logic to store information that is frequently accessed from memory 506. The device 500 includes circuitry 510. In one example, the microcontroller unit 502 may be located on the same PCB or module as the circuitry 510. In another example, the microcontroller unit 502 is external to the device 500. The circuitry 510 may function as an analog to digital converter. The circuitry 510 may include additional analog circuitry, digital circuitry, memory, and / or software.

[0058] The circuit 510 may include circuit elements similar in connection and operation to the circuit 100 of FIG. 1. The circuit 510 includes a calibration engine, a digital-to-analog converter (DAC), an analog-to-digital converter (ADC), a multiplexer, and a storage circuit. The multiplexer receives an input voltage Vin. The ADC includes a preamplifier array, a delay multiplexer, and a back-end ADC. The preamplifier array includes a plurality of preamplifiers.

[0059] The circuit 510 operates in a calibration mode and a mission mode. In the calibration mode, the calibration engine generates a plurality of inputs. The DAC generates a first calibration signal in response to a first input code of the plurality of input codes. The multiplexer provides the first calibration signal to the ADC in the calibration mode. The preamplifier array and delay multiplexer generate a delayed signal in response to the first calibration signal. The back-end ADC generates a first output code in response to the delayed signal. The storage circuit stores the first output code corresponding to the first input code. The storage circuit stores an output code corresponding to each input code of the plurality of input codes.

[0060] The input codes are stored as data and the output codes are stored as addresses. The input codes are stored at the corresponding addresses of the output codes. The stored input codes include an index value and a coarse value. When the input code corresponding to the current output code is equal to the input code corresponding to the previous output code, the index value is 0. The coarse value for the current output code is the sum of the index values ​​generated corresponding to all previous output codes and the index value corresponding to the current output code. The coarse value represents the accumulation of the input codes.

[0061] The output code comprises a sum of M and L bits, where M and L are both integers greater than or equal to 1. The output code is reduced to M bits, and the index value is supplemented with L bits. The coarse value is stored every 2^L bits. For example, when the output code is 15 bits, M is 10 bits, and L is 5 bits. The output code is reduced to 10 bits, while the index value is supplemented with 5 bits. The memory requirement for the lookup table is approximately 45k (2 10 ×(32+13)). Thus, the lookup table requires less memory than conventional solutions and also supports high speed operation of circuit 510. In one exemplary embodiment, circuit 510 is an ADC and the lookup table enables the ADC to operate at GSPS speeds.

[0062] Thus, a look-up table in the storage circuitry is populated in the calibration mode with an input code and a corresponding output code. This look-up table is used by the circuitry 510 in the mission mode. In the mission mode, an input voltage Vin (such as a radio frequency analog signal) is received and converted to a digital (e.g., binary) representation via the ADC and storage circuitry. The circuitry 510 uses a high-speed ADC and a look-up table in the storage circuitry for conversion of the input voltage Vin, which reduces the area and power requirements of the circuitry 510. In one example, the device 500 is an RF sampling receiver and the circuitry 510 enables the device 500 to operate at GSPS speeds.

[0063] FIG. 6 is a block diagram of a back-end analog-to-digital converter 600 according to an example embodiment. The back-end ADC 600 is similar in connection and operation to the back-end ADC 124 shown in FIG. 1. The ADC 106 shown in FIG. 1 has a front end and a back end. The front end may perform a voltage delay function. In one example, the front end includes a preamplifier array and a delay multiplexer as shown in FIG. 1. The back end may perform a delay digital function. According to one aspect of the disclosure, the front end of the ADC 106 converts the analog signal Vin received from the multiplexer M112 into a delayed signal similar to the signals OUT_P and OUT_M generated in FIG. 3. In FIG. 6, these delayed signals are represented as A0 and B0 on ​​lines 788 and 790, such that the timing of the delayed signals A0 and B0 represents the input voltage Vin. A front end that may be used to generate the delayed signals A0 and B0 based on the input voltage Vin may be constructed and operated, for example, as described in U.S. Patent No. 10,673,456 (based on U.S. Patent No. 16 / 410,698). The front end may include, for example, the conversion and folding circuit described in U.S. Patent No. 10,673,456, which includes a voltage-delay converter block including a preamplifier for converting a voltage signal into a delayed signal, and a folding block including a logic gate coupled to the preamplifier for selecting earlier arriving and later arriving ones of the delayed signals.

[0064] An example of a voltage delay device that may be incorporated within the front end of the ADC 106 and used to generate the delayed signals A0 and B0 based on the input voltage Vin is shown in U.S. Patent Application No. 17 / 131,981, filed December 23, 2020. A voltage delay device constructed in accordance with U.S. Patent Application No. 17 / 131,981 may have first and second comparators connected to first and second lines carrying complementary voltages representative of the input voltage Vin to generate first and second output signals during an active phase when the complementary voltages reach appropriate threshold voltages, such that the delay between the output signals is representative of the input voltage Vin. However, the present disclosure is not limited to the devices and processes described in detail herein. Other suitable devices may perform suitable voltage delay functions within the front end of the ADC 106. As previously mentioned, the entire disclosures of U.S. Patent No. 10,673,456 and U.S. Patent Application No. 17 / 131,981 are incorporated herein by reference. [Patent Document 6] U.S. Patent Application No. 17 / 131,981

[0065] The back-end ADC 106 may, for example, include a multi-bit stage 798 and first through i-th single-bit stages 7102 and 7104 connected in series with the multi-bit stage 798. If desired, the back-end may include three, four, or more such single-bit stages (i=3, 4, or more). The single-bit stages 7102 and 7104 shown in FIG. 6 are examples of successive non-linear stages. The back-end ADC 600 receives delayed signals A0 and B0 from a front-end voltage delay circuit. The timing of the delayed signals A0 and B0 has a delay that represents the input voltage Vin. The back-end ADC 600 works with a calibration engine 602 (similar to the calibration engine 102 shown in FIG. 1) and a storage circuit (similar to the storage circuit 108 shown in FIG. 1) to generate a corresponding multi-bit digital code that is generated as the final output 130 (FIG. 1). Thus, the final output 130 corresponds to a value that closely approximates the input voltage Vin.

[0066] Multi-bit stage 798 may include delay circuits and delay converters operating in parallel to generate M bits of digital information on lines 630, 632, 634, and 636. In the example shown, M=2. However, M may be greater than two. This disclosure is not limited to the example shown. The delayed remainders from multi-bit stage 798 may be combined by combiner 604 and applied to a first single-bit stage 7102. If desired, the first through i-th single-bit stages 7102 and 7104 may be constructed and operated as successive stages to provide respective bits of digital information to calibration engine 602.

[0067] The first stage 798 may have, for example, four delay comparators 606, 608, 610, and 612 and is connected to the combiner 604. Some example embodiments may be implemented with a first stage having fewer or more than four delay comparators. In the example embodiment shown in the figure, the first stage 798 generates two bits of digital information for the calibration engine 602. In the example embodiment shown, each of the successive stages 7102 and 7104 generates a single bit of digital information for the calibration engine 602.

[0068] In the example shown, the rising edge of signal B0 on ​​line 790 precedes the rising edge of signal A0 on line 788. The first signal A0 is applied to threshold inputs 794 of delay comparators 606, 608, 610, and 612. In the configuration shown, by way of example, delay comparators 606, 608, 610, and 612 are essentially identical to one another. The second signal B0 is applied to four different delay circuits 614, 616, 618, and 620 which generate four corresponding signals B04, B03, B02, and B01 on respective lines 622, 624, 626, and 628.

[0069] The timing of corresponding signals B04, B03, B02, and B01 are delayed relative to the timing of signal B0 on ​​line 790 by different known amounts, each of which is less than or equal to the maximum gain of the front end. The delayed signals B04, B03, B02, and B01 are applied to first inputs 792 of respective delay comparators 606, 608, 610, and 612. The first delay comparator 606 issues a sign signal on line 630 representing which signal (B04 or A0) arrives first at the first delay comparator 606. Similarly, the second delay comparator 608 issues a sign signal on line 632 representing which signal (B03 or A0) arrives first at the second delay comparator 608. Similarly, the third and fourth delay comparators 610 and 612 issue sign signals on lines 634 and 612 that indicate which signal arrives at the third and fourth delay comparators 610 and 612 first.

[0070] Because delay circuits 614, 616, 618, and 620 are different from one another, the timing of the rising edges of delayed signals B04, B03, B02, and B01 are different from one another. Each of delay comparators 606, 608, 610, and 612 issues a sign signal to calibration engine 602 on respective lines 630, 632, 634, and 636. The sign signals on lines 630, 632, 634, and 636 are functionally related to the timing difference between the rising edges of input signals A0 and B0, and therefore are functionally related to the input voltage Vin.

[0071] Because the amount of delay provided by the four delay comparators 606, 608, 610, and 612 differ from one another, the sign signals 630, 632, 634, and 636 provide four binary data points for determining a two-bit output. For example, if B0 leads A0 and B01 leads A0, the calibration engine 602 determines that the delay between the timing of signals A0 and B0 is greater than the delay contributed by the fourth delay circuit 620. Similarly, if B0 leads A0 and A0 leads B02, B03, and B04, the calibration engine 602 determines that the delay between the timing of signals A0 and B0 is less than each of the delays contributed by the third, second, and first delay circuits 618, 616, and 614.

[0072] If desired, the structure and operation of delay comparators 606, 608, 610, and 612 may be similar to that of delay comparator 782, described below. In operation, delay comparators 606, 608, 610, and 612 generate respective delayed signals IN4, IN3, IN2, and IN1 on respective output lines 638, 640, 642, and 644. Delay signals IN4, IN3, IN2, and IN1 are applied to combiner 604 by output lines 638, 640, 642, and 644. In the configuration shown, delay comparators 606, 608, 610, and 612 are essentially the same, while delay circuits 614, 616, 618, and 620 are different from one another and contribute different amounts of delay. Thus, the timing of the rising edges of delayed signals IN4, IN3, IN2, and IN1 are different from one another.

[0073] FIG. 7 is a block diagram of a combiner 604 for connecting the multi-bit stage shown in FIG. 6 to a first single-bit stage of the single-bit stages according to an exemplary embodiment. The combiner 604 is similar in connection and operation to the combiner 604 shown in FIG. 6. The combiner 604 has two fifth delay circuits 650 and 652, two AND gates 654 and 656, and a sixth delay circuit 658. In the configuration shown, the fifth delay circuits 650 and 652 are essentially identical to each other. However, the disclosure is not limited to the details of the configuration shown and described herein. The third and fourth delay signals IN2 and IN1 are applied to the fifth delay circuits 650 and 652 on output lines 642 and 644, and the first and second delay signals IN4 and IN3 are applied to the AND gates 654 and 656 on output lines 638 and 640. The output signals from the fifth delay circuits 650 and 652 are also applied to AND gates 654 and 656 on conductive lines 662 and 664, respectively. The output signal from one AND gate 656 is applied to a sixth delay circuit 658 on conductive line 660, and the other AND gate 654 produces a signal A1 on conductive line 788A1. The sixth delay circuit 658 produces a signal B1 on conductive line 790B1.

[0074] In operation, the timing of the rising edges of the signals output from the fifth and sixth delay circuits 650, 652, and 658 on conductive lines 662, 664, and 790B1 are delayed relative to the respective timing of the rising edges of the signals input to the delay circuits 650, 652, and 658. The timing of the rising edges of the signals output from the AND gates 654 and 656 on lines 788A1 and 660 correspond to the respective timing of the later arriving signals input to the AND gates 654 and 656. The relative timing of the rising edges of the signals A1 and B1 on lines 788A1 and 790B1 is functionally (i.e., predictably) related to the input voltage Vin (FIG. 1). In other words, delay circuits 650, 652, and 658 and logic gates 654 and 656 establish a transfer function between the delay of the incoming signals IN4, IN3, IN2, and IN1 and the delay of the first and second signals A1 and B1.

[0075] For the configuration shown, the transfer functions are as follows: [A] If the timing of the signal on line 638 precedes the timing of the signal on line 662 (the timing of the signal on line 662 corresponds to the timing of the signal on line 642 delayed by the fifth delay circuit 650), then the timing of the signal on line 788A1 corresponds to the timing of the signal on line 662, but if the timing of the signal on line 662 precedes the timing of the signal on line 638, then the timing of the signal on line 788A1 corresponds to the timing of the signal on line 638. [B] If the timing of the signal on line 640 precedes the timing of the signal on line 664 (the timing of the signal on line 664 corresponds to the timing of the signal on line 644 delayed by the fifth delay circuit 652), then the timing of the signal on line 660 corresponds to the timing of the signal on line 664, but if the timing of the signal on line 664 precedes the timing of the signal on line 640, then the timing of the signal on line 660 corresponds to the timing of the signal on line 640. [C] The timing of the signal on line 790B1 corresponds to the timing of the signal on line 660 delayed by the sixth delay circuit 658.

[0076] The amount by which the delay circuits 650, 652, and 658 delay the signals passing through them can be selected to maximize or improve as much as possible the gain of the first and second signals A1 and B1. The combiner 604 operates in a delay mode, where the gain is related to the delay (not the voltage). If the gain of the first and second signals A1 and B1 is too low, it means that the timing of the first and second signals A1 and B1 is too close to each other, and the information represented by the relative timing of those signals may be difficult to resolve.

[0077] One aspect of the disclosure is that the timing of signals on lines 788A1 and 790B1 are functionally (i.e., predictably) related to the timing of signals on lines 638, 640, 642, and 644. If a certain set of signal timings on lines 638, 640, 642, and 644 results in a first set of signal timings on lines 788A1 and 790B1, then it can be predicted that the same first set of signal timings will occur on lines 788A1 and 790B1 whenever the same set of signal timings occurs on lines 638, 640, 642, and 644. Similarly, if another set of signal timings on lines 638, 640, 642, and 644 results in a second set of signal timings on lines 788A1 and 790B1, then it can be predicted that the second set of signal timings will occur on lines 788A1 and 790B1 whenever the other set of signal timings occurs on lines 638, 640, 642, and 644. Also, because the timings of the signals on lines 638, 640, 642, and 644 are functionally (i.e., predictably) related to the input voltage Vin, the timings of the signals on lines 788A1 and 790B1 are also functionally related to the input voltage Vin.

[0078] 6, signals A1 and B1 produced by combiner 604 (similar to combiner 604 of FIG. 7) are applied to a second stage 7102 on output lines 788A1 and 790B1, respectively, similar to lines 788A1 and 790B1 (of FIG. 7). The second stage (first remainder stage) 7102 is coupled to the first stage 798 (via combiner 604), and the i-th stage 7104 (which is the second remainder stage in the illustrated example) is coupled to the second stage 7102.

[0079] In the illustrated example, the 2nd through i-th stages 7102 and 7104 each include an AND gate (such as AND gate 776 for stage 7102 and AND gate 778 for stage 7104) and a delay comparator (such as delay comparator 782 for stage 7102 and delay comparator 784 for stage 7104). However, the illustrated AND gates are merely examples of logic gates that may be used in accordance with the present disclosure. If desired, the present disclosure may be implemented with or without AND gates and / or with or without gates other than AND gates.

[0080] Also, in the illustrated configuration, AND gates 776 and 778 may be essentially identical to one another, and delay comparators 782 and 784 may be essentially identical to one another. Conductive output lines 788A1 and 790B1 from combiner 604 are coupled to inputs of a first AND gate 776 and a delay comparator 782. Specifically, conductive line 788A1 is coupled to a first input 792 of delay comparator 782, and conductive line 790B1 is coupled to a threshold input 794 of delay comparator 782.

[0081] An output line 788A2 from the AND gate 776 is electrically coupled to one of the inputs of the AND gate 778 and to an input 792 of the delay comparator 784. A conductive line 790B2 from the first delay comparator 782 is electrically coupled to the other of the inputs of the AND gate 778 and to a threshold input 794 of the delay comparator 784. The pattern produced by the second and third stages 7102 and 7104 can be continued for as many additional stages as desired. Each successive stage has AND gates and delay comparators essentially identical to the AND gates and delay comparators of the second and third stages 7102 and 7104 and are similarly electrically coupled to the AND gates and delay comparators of the preceding stage.

[0082] In operation, signals AN and BN (with N=1, 2, 3... for stages 7102 and 7104..., respectively) are applied to respective ones of AND gates 776 and 778, causing the AND gates 776 and 778 to generate a corresponding signal AN+1. For each of the AND gates 776 and 778, the timing of the rising edge of signal AN+1 tracks the timing of the rising edge of the later arriving one of signals AN and BN. In particular, for each of the AND gates 776 and 778, the timing of the rising edge of signal AN+1 is equal to the timing of the rising edge of the earlier arriving one of signals AN and BN plus an amount of time related to the degree to which the rising edge of the later arriving one of signals AN and BN lags behind the rising edge of the earlier arriving one of signals AN and BN.

[0083] 8 is a graph showing the AND gate delay and comparator delay generated by the AND gate and delay comparator, respectively, of the back-end ADC of FIG. 6, according to an example embodiment, where the AND gate delay and comparator delay are functions of the input signal delay. The graph includes an X-axis (T_IN) and a Y-axis (output delay). The AND gate (e.g., AND gates 776, 778) delay and the comparator (e.g., delay comparators 782, 784) delay are functions of the input signal delay, according to an example embodiment. The input signal delay is the delay between the signals received by the AND gate or by the delay converter. As shown, the AND gate delay 7100 contributed by each AND gate is linearly related to the absolute value of the input signal delay T_IN, which is the timing difference between the signals AN and BN input to each AND gate, where N is an integer, N is equal to 1 for stage 7102, and N is equal to 2 for stage 7104. In the configuration shown, the relationship of AND gate delay 7100 to the input T_IN is linear regardless of whether AN or BN precedes or follows.

[0084] Signals AN and BN are also applied to inputs 792 and threshold inputs 794 of delay comparators 782 and 784, respectively, causing delay comparators 782 and 784 to generate corresponding signals BN+1. For each of delay comparators 782 and 784, the timing of the rising edge of signal BN+1 tracks the timing of the rising edge of the earlier arriving one of signals AN and BN. In particular, for each one of delay comparators 782 and 784, the timing of the rising edge of signal BN+1 is equal to (1) the timing of the rising edge of the earlier arriving one of signals AN and BN plus (2) a comparator delay 7200 that is logarithmically inversely related to the absolute value of the input signal delay T_IN (in other words, the comparator delay is larger for more similar input values ​​and the comparator delay is less when the difference between the two inputs to the comparator is larger).

[0085] 9 is a graph showing the output signal delay as a function of the input signal delay of FIG. 8 according to an example embodiment. The AND gate delay 7100 is subtracted from the comparator delay 7200 to produce the output signal delay T_OUT for any given single bit stage 7102 and 7104. When the absolute value of the input signal delay T_IN is less than the threshold delay T_THRES, the output signal delay T_OUT is positive (meaning that the rising edge of the signal BN+1 generated by the respective delay comparators 782 and 784 precedes the rising edge of the signal AN+1 generated by the respective AND gates 776 and 778). On the other hand, when the absolute value of the input signal delay T_IN is greater than the threshold delay T_THRES, the output signal delay T_OUT is negative (meaning that the rising edge of the signal BN+1 lags the rising edge of the corresponding signal AN+1). The positive or negative sign of the output signal delay T_OUT is reported to the calibration engine 602 on the successive delay comparator signal lines.

[0086] In operation, the first delay comparator 782 issues a first code signal ("1" or "0") on the digital line 708 (an example of a digital output) to the calibration engine 602. The first code signal (an example of a digital signal described in this disclosure) is based on which of the rising edges of signals A1 and B1 is received first by the first delay comparator 782, such that the first code signal reflects the order of the rising edges of signals A1 and B1 applied to the first input 792 and the threshold input 794 of the delay comparator 782. The AND gate 776 and the delay comparator 782 generate signals A2 and B2 that are applied to the AND gate 778 and the delay comparator 784 of the third stage 7104. The delay comparator 784 outputs a second code signal ("1" or "0") on the second digital line 712 to the calibration engine 602. The second code signal is based on which of the rising edges of signals A2 and B2 is received first by the second delay comparator 784, and the second code signal reflects the order in which the rising edges of signals A2 and B2 are applied to inputs 792 and 794 of the second delay comparator 784.

[0087] Since the delay between signals A1 and B1 is predictable or inverse as a function of the input voltage Vin, and since the delay between signals AN+1 and BN+1 output by successive stages is predictable or inverse as a function of the signals AN and BN received from the preceding stage, the sign signal output by the delay comparator of the cascade of stages is predictable or inverse as a function of the input voltage Vin. Thus, a code consisting of the sign signal can be reliably compared with a predetermined correlation to determine an approximation of the input voltage Vin. In operation, the timing of the signals on lines 788A1 and 790B1 is functionally (i.e., predictably) related to the timing of the signals on lines 788 and 790, as described above. The timing of the signals on lines 788A2 and 790B2 is functionally (i.e., predictably) related to the timing of the signals on lines 788A1 and 790B1. The timing of the signals on lines 788A3 and 790B3 is functionally (ie, predictably) related to the timing of the signals on lines 788A2 and 790B2, and so on.

[0088] Also, if a certain set of signal timings on lines 788 and 790 results in a first set of signal timings on lines 788A1, 790B1, 788A2, 790B2, 788A3, 790B3, etc., it can be predicted that whenever the same set of signal timings occurs on lines 788 and 790, the same first set of signal timings will occur on lines 788A1, 790B1, 788A2, 790B2, 788A3, 790B3, etc. Similarly, if another different set of signal timings on lines 788 and 790 results in a second set of signal timings on lines 788A1, 790B1, 788A2, 790B2, 788A3, 790B3, etc., then it can be predicted that the same second set of signal timings will occur on lines 788A1, 790B1, 788A2, 790B2, 788A3, 790B3, etc. whenever the other set of signal timings occurs on lines 788 and 790. Also, because the timing of the signals on lines 788 and 790 are functionally (i.e., predictably) related to the input voltage Vin, the timing of the signals on lines 788A1, 790B1, 788A2, 790B2, 788A3, 790B3, etc. that determine the code signals used to construct the output code are also functionally related to the input voltage Vin.

[0089] 10 is a circuit diagram illustrating an example of a comparator circuit merged with the sign-out and delay-out circuits for the back-end ADC of FIG. 6 according to an example embodiment. The delay comparator 782 includes a comparator circuit 2083 having first, second, third, fourth, fifth, sixth, seventh, and eighth transistors 2400, 2402, 2404, 2406, 2408, 2410, 2412, and 2414. In the illustrated example, the timing of the delay comparator 782 is controlled by a signal from a clock (CLK) applied to the gates of the first and fourth transistors 2400, 2406 on conductive line 2122. The first and second signals A1, B1 on lines 788A1 and 790B1 are applied to the gates of the sixth and fifth transistors 2410 and 2408, respectively. The drains of the first, second, and fifth transistors 2400, 2402, and 2408 are electrically connected to each other and to the gates of the third and eighth transistors 2404 and 2414 via a first conductive line 2416. The drains of the third, fourth, and sixth transistors 2404, 2406, and 2410 are similarly electrically connected to each other and to the gates of the second and seventh transistors 2402 and 2412 via a second conductive line 2418.

[0090] The first and second conductive lines 2416 and 2418 of the comparator circuit 2083 are electrically connected to the sign-out circuit 2420 via third and fourth conductive lines 2422 and 2424, respectively. As shown, the sign-out circuit 2420 is merged with the comparator circuit 2083. The sign-out circuit 2420 includes first, second, third and fourth transistors 2426, 2428, 2430 and 2432. The third conductive line 2422 is electrically connected to the gates and sources of the first and second transistors 2426 and 2428 of the sign-out circuit 2420, respectively, while the fourth conductive line 2424 is electrically connected to the sources and gates of the first and second transistors 2426 and 2428 of the sign-out circuit 2420, respectively.

[0091] In operation, when the delay comparator 782 is enabled by the clock signal on line 2122, a sign signal is generated in the sign out circuit 2420 on line 708. The sign signal is forwarded on line 708 to the calibration engine 602 and represents the order in which the output signals A1 and B1 arrive at the first and threshold inputs 792 and 794 of the delay comparator 782. The operation of the sign out circuit 2420 is controlled by an inverted clock signal CLKZ applied to the gates of the third and fourth transistors 2430 and 2432 of the sign out circuit 2420. The inverted clock signal CLKZ is an inverted version of the clock signal applied to the comparator circuit 2083 on line 2122.

[0092] The third and fourth conductive lines 2422 and 2444 are also electrically connected to the delay out circuit 2450. As shown, the delay out circuit 2450 is merged with the comparator circuit 2083. The delay out circuit 2450 includes first, second and third transistors 2442, 2444 and 2446. The third conductive line 2422 is electrically connected to the gates and sources of the first and second transistors 2442 and 2444 of the delay out circuit 2450, respectively, while the fourth conductive line 2424 is electrically connected to the sources and gates of the first and second transistors 2442 and 2444 of the delay out circuit 2450, respectively.

[0093] In operation, a delayed signal B2 is generated on line 790B2 that is electrically connected to the drains of both the first and second transistors 2442 and 2444 of the delay out circuit 2450. The timing of the rising edge of the delayed signal B2 on line 790B2 relative to the timing of its arrival ahead of the rising edges of the signals A1 and B2 on the inputs 792 and 794 is the comparator delay 7102. The operation of the delay out circuit 2450 is controlled by the same inverted clock signal CLKZ that is applied to the third and fourth transistors 2430, 2432 of the sign out circuit 2420. The inverted clock signal CLKZ is applied to the gate of the third transistor 2446 of the delay out circuit 2450. The drain of the third transistor 2446 of the delay out circuit 2450 is electrically connected to the drains of the first and second transistors 2442, 2444 of the delay out circuit 2450.

[0094] The term "coupled" is used throughout. This term may encompass a connection, communication, or signal path that enables a functional relationship consistent with this specification. For example, in a first example, device A is coupled to device B if device A provides a signal to control device B to perform a certain action, or in a second example, device A is coupled to device B via an intervening component C if the intervening component C does not substantially change the functional relationship between device A and device B, such that device B is controlled by device A via a control signal provided by device A.

[0095] A device that is "configured to" perform a certain task or function may be configured (e.g., programmed and / or hardwired) to perform that function at the time of manufacture by a manufacturer and / or may be configurable (or reconfigurable) by a user after manufacture to perform that function and / or other additional or alternative functions. Such configuration may be through the device's firmware and / or software programming, through the structure and / or layout of the hardware components and interconnections of the device, or through a combination thereof.

[0096] As used herein, the terms "terminal," "node," "interconnect," "pin," and "lead" are used interchangeably. Unless otherwise noted, these terms are used generally to mean an interconnection or termination between device elements, circuit elements, integrated circuits, devices, or other electronic circuit or semiconductor components.

[0097] A circuit or device described herein as including certain components may instead be adapted to be coupled to those elements to form the described circuit element or device. For example, a structure described as including one or more semiconductor elements (such as transistors), one or more passive elements (such as resistors, capacitors, and / or inductors), and / or one or more sources (voltage and / or current sources) may instead include only the semiconductor elements in a single physical device (e.g., a semiconductor die and / or integrated circuit (IC) package) and may be adapted to be coupled to at least some of the passive elements and / or sources to form the described structure, e.g., either at the time of manufacture or after the time of manufacture by an end user and / or third party.

[0098] Although the use of particular transistors is described herein, other transistors (or equivalent devices) may be used instead. For example, p-type metal oxide silicon FETs ("MOSFETs") may be used instead of n-type MOSFETs with little or no changes to the circuit. Also, other types of transistors (such as bipolar junction transistors (BJTs) may be used.

[0099] Although the use of particular transistors is described herein, other transistors (or equivalent devices) may be used instead with little or no changes to the remaining circuit elements. For example, metal-oxide-silicon FETs ("MOSFETs" (such as n-channel MOSFET, nMOSFET, or p-channel MOSFET, pMOSFET), bipolar junction transistors (BJTs - e.g., NPN or PNP), insulated gate bipolar transistors (IGBTs), and / or junction field effect transistors (JFETs) may be used in place of or in conjunction with the devices disclosed herein. The transistors may be depletion mode devices, drain extension devices, enhancement mode devices, natural transistors, or other types of device structure transistors. Also, the devices may be implemented in / on a silicon substrate (Si), a silicon carbide substrate (SiC), a gallium nitride substrate (GaN), or a gallium arsenide substrate (GaAs). While some example embodiments suggest that certain elements are included in an integrated circuit and other elements are external to the integrated circuit, in other example embodiments, additional or fewer features may be incorporated into the integrated circuit. In addition, some or all of the features shown as being external to the integrated circuit may be included in the integrated circuit and / or some features shown as being internal to the integrated circuit may be integrated external to the integrated circuit. As used herein, the term "integrated circuit" means one or more circuits (i) integrated in / on a semiconductor substrate, (ii) integrated in a single semiconductor package, (iii) integrated in the same module, and / or (iv) integrated in / on the same printed circuit board.

[0100] The circuits described herein are reconfigurable to include replacement components to provide functionality at least partially similar to that available prior to the replacement of the component. A component depicted as a resistor generally represents any one or more elements coupled in series and / or parallel to provide the amount of impedance represented by the depicted resistor, unless otherwise noted. For example, a resistor or capacitor depicted and described herein as a single component may instead be multiple resistors or capacitors, respectively, coupled in parallel between the same nodes. For example, a resistor or capacitor depicted and described herein as a single component may instead be multiple resistors or capacitors, respectively, coupled in series between the same two nodes as a single resistor or capacitor.

[0101] Use of the term "ground" in the preceding description includes chassis ground, earth, floating ground, virtual ground, digital ground, common ground, and / or any other form of ground connection applicable or suitable to the teachings of this description. Unless otherwise specified, "about," "approximately," or "substantially" preceding a value means + / - 10 percent of the indicated value.

[0102] Variations in the described embodiments are possible, and other embodiments are possible within the scope of the claims.

Claims

1. 1. A circuit comprising: a multiplexer configured to receive an input voltage and a calibration signal; an analog-to-digital converter (ADC) coupled to the multiplexer, the ADC configured to generate an output code in response to the calibration signal; a storage circuit coupled to the ADC, the storage circuit configured to store an input code representing the calibration signal at an address corresponding to the output code, the stored input code including an index value and a coarse value; and The circuit includes:

2. 2. The circuit of claim 1, a calibration engine coupled to the memory circuit and to the ADC, the calibration engine configured to generate a plurality of input codes; a digital-to-analog converter (DAC) coupled to the calibration engine, the DAC configured to generate the calibration signal in response to an input code of the plurality of input codes; The circuit further comprises:

3. 2. The circuit of claim 1, A circuit in which the output code is stored as an address and the input code is stored as data.

4. 2. The circuit of claim 1, a circuit having an index value of 1 when an input code corresponding to a current output code is not equal to an input code corresponding to a previous output code, and an index value of 0 when an input code corresponding to said current output code is equal to an input code corresponding to said previous output code.

5. 2. The circuit of claim 1, A circuit in which a coarse value for a current output code is a sum of index values ​​generated corresponding to all previous output codes and an index value generated corresponding to the current output code.

6. 2. The circuit of claim 1, The circuit wherein the output code comprises M bits and L bits.

7. 7. A circuit according to claim 6, comprising: A circuit in which the output code is reduced to M bits, the index value is supplemented with L bits, and the coarse value is stored every 2 L bits.

8. 2. The circuit of claim 1, The ADC is a plurality of preamplifiers, each preamplifier configured to compare one of an input voltage and the calibration signal to a threshold voltage; a delay multiplexer coupled to the plurality of preamplifiers, the delay multiplexer configured to generate a delayed signal based on an output of one of the plurality of preamplifiers; and a back-end ADC configured to generate the output code in response to the delayed signal; The circuit includes:

9. 9. The circuit of claim 8, A circuit in which each preamplifier has a different threshold voltage.

10. 9. The circuit of claim 8, The circuitry is configured to operate in a mission mode, wherein in the mission mode: the multiplexer is further configured to provide the input voltage to the ADC; The circuit, wherein the ADC is further configured to generate a low code in response to the input voltage, and an input code stored at an address corresponding to the low code is generated as a final output.

11. 1. A method comprising: receiving an input voltage and a calibration signal; generating an output code with an analog-to-digital converter (ADC) in response to the calibration signal; storing an input code representing the calibration signal at an address corresponding to the output code, the stored input code including an index value and a coarse value; A method comprising:

12. 12. The method of claim 11, generating a plurality of input codes; generating a calibration signal with a digital-to-analog converter (DAC) in response to an input code of the plurality of input codes; The method further comprises:

13. 12. The method of claim 11, The method further comprising storing the output code as an address and storing the input code as data.

14. 12. The method of claim 11, storing said index value as one when the current output code is not equal to the previous output code; storing the index value as 0 when the current output code is equal to the previous output code; The method further comprises:

15. 15. The method of claim 14, The method further comprising summing all index values ​​generated corresponding to all previous output codes to obtain a coarse value for a current output code.

16. 12. The method of claim 11, The method of claim 1, wherein the output code comprises M bits and L bits.

17. 17. The method of claim 16, reducing the output code to M bits; supplementing said index value with L bits; storing said coarse value every 2L bits; The method further comprises:

18. 12. The method of claim 11, providing the input voltage to the ADC; generating a raw code by the ADC in response to the input voltage; generating as a final output the input code stored at an address corresponding to the raw code; The method further comprises:

19. A device, comprising: A processor; a memory coupled to the processor; a circuit coupled to the processor and the memory, the circuit comprising: a multiplexer configured to receive an input voltage and a calibration signal; an analog-to-digital converter (ADC) coupled to the multiplexer, the ADC configured to generate an output code in response to the calibration signal; a storage circuit coupled to the ADC, the storage circuit configured to store an input code representing the calibration signal at an address corresponding to the output code, the stored input code including an index value and a coarse value; the circuit comprising: Including, the device.

20. 20. The device of claim 19, The circuit, a calibration engine coupled to the memory circuit and to the ADC, the calibration engine configured to generate a plurality of input codes; a digital-to-analog converter (DAC) coupled to the calibration engine, the DAC configured to generate the calibration signal in response to an input code of the plurality of input codes; The device further comprises:

Images