Method and structure for three-dimensional dynamic random access memory.

Abstract

A method for forming a three-dimensional dynamic random access memory (3D DRAM) structure utilizing a grid pattern of high aspect ratio holes to form subsequent features of the 3D DRAM. The method may include depositing alternating layers of crystalline silicon (c-Si) and crystalline silicon germanium (c-SiGe) on a substrate using a heteroepitaxy process and HAR etching a pattern of holes into the substrate, the holes being configured to provide chemical access to laterally etch or deposit material to form the 3D DRAM features, without the need for subsequent HAR etching of the holes to form the 3D DRAM features.

Description

[Technical field]

[0001]

[0001] Embodiments of the present principles relate generally to semiconductor manufacturing. [Background technology]

[0002]

[0002] Data storage and retrieval is a limiting factor for many aspects of the computing industry. Memory devices allow for easy scaling of the overall performance of modern computing devices. To increase memory speed, memory structures have been shrunk to extremely small sizes, dramatically increasing the density of memory structures. Two-dimensional memory structures are beginning to reach their theoretical limits in terms of memory structure density. The inventors have realized that three-dimensional memory structures may be the key to further increasing memory density. However, three-dimensional memory devices require significant changes in structure and processing compared to two-dimensional memory devices.

[0003]

[0003] We have now provided a method and structure for three-dimensional memories with scalable dimensions that enable memory densities beyond the capabilities of current technology. Summary of the Invention

[0004]

[0004] Provided herein are methods and apparatus for forming three-dimensional memory structures having scalable dimensions.

[0005]

[0005] In some embodiments, a method for forming a three-dimensional dynamic random access memory (3D RAM) structure may include depositing alternating layers of crystalline silicon (c-Si) material and crystalline silicon germanium (c-SiGe) material on a substrate using a heteroepitaxy process; and etching a pattern of holes into the substrate having at least one high aspect ratio (HAR) hole, the pattern of holes being configured to provide chemical access to the alternating layers of c-Si material and c-SiGe material for laterally etching or depositing material to form 3D DRAM features of the 3D DRAM structure, and thereafter forming the 3D DRAM features without HAR etching of the holes in the substrate.

[0006]

[0006] In some embodiments, the method further includes integrating portions of the pattern of holes formed by etching the material between portions of the pattern of holes to form active area isolation slots of the 3D DRAM structure; depositing different materials into different holes to block or enable lateral or vertical recess formation processes for 3D DRAM cell formation; forming isolation slots having a liner of a first dielectric material removable by exposure to hydrogen fluoride (HF), the isolation slots having ends filled with a second dielectric material impermeable to HF, the isolation slots configured to provide lateral cell isolation and provide structural support to the 3D DRAM structure; forming a bottom electrode of a capacitor of the 3D DRAM structure supported on one or more ends of the isolation slots filled with the second dielectric material; removing the liner of the first dielectric material of the isolation slots to remove the liner of the first dielectric material of the isolation slots while maintaining structural support of the bottom electrode of the 3D DRAM structure. This may include providing space to be filled with high-k top electrode material for increased DRAM cell capacity, etching a pattern of holes using a mask and etch process that etches both the c-Si and c-SiGe materials, selectively etching the c-SiGe material from inside the at least one HAR hole to form lateral features extending from sidewalls of the at least one HAR hole, and / or etching the c-Si and c-SiGe materials in the at least one HAR hole to increase a size of the at least one HAR hole, a height of the lateral features, and a width of subsequent features extending into the c-SiGe material.

[0007] In some embodiments, a method of forming a three-dimensional dynamic random access memory (3D RAM) structure includes depositing alternating layers of crystalline silicon (c-Si) and crystalline silicon germanium (c-SiGe) materials on a substrate using a heteroepitaxy process; etching a pattern of holes into the substrate having at least one high aspect ratio (HAR) hole, the pattern of holes being configured to provide chemical access to the alternating layers of c-Si and c-SiGe materials for laterally etching or depositing material to form a 3D DRAM feature of the 3D DRAM structure, and thereafter forming the 3D DRAM feature without HAR etching of the hole in the substrate; and integrating a portion of the pattern of holes formed by etching material between portions of the pattern of holes to form a 3D DRAM feature of the 3D DRAM structure. The method may include forming slot features of a DRAM structure; forming an isolation slot from at least one slot feature having a liner of a first dielectric material removable by exposure to hydrogen fluoride (HF), the isolation slot having an end filled with a second dielectric material impermeable to HF, the isolation slot configured to provide lateral cell isolation and provide structural support to the 3D DRAM structure; forming a bottom electrode of a capacitor of the 3D DRAM structure supported on one or more ends of the isolation slot filled with the second dielectric material; and removing the liner of the first dielectric material of the isolation slot to provide a space for filling with a high-k top electrode material for increasing the capacitance of the 3D DRAM cell while maintaining structural support of the bottom electrode.

[0008]

[0008] In some embodiments, the method further includes etching a wordline hole between the two isolation slots to form a wordline structure; selectively etching the c-SiGe material through an upper opening of the wordline hole to form a lateral wordline feature extending into the two isolation slots; forming a source / drain and spacer of a 3D DRAM structure by extending the lateral wordline feature until it is limited by the two isolation slots; depositing a conformal layer of doped oxide in the wordline hole; and etching back the conformal layer of doped oxide to form a 3D DRAM structure. leaving doped regions for source / drains of DRAM structures; depositing a gate oxide layer in the wordline holes; depositing a gate electrode to fill the wordline holes; anisotropically etching a slit between two wordline structures to form a bitline structure; selectively etching laterally the c-SiGe material in the slit from the top opening of the slit; forming the bitline structures by chemically depositing and etching from the top opening of the slit; forming a conductive shield layer on the bitline structures to reduce noise coupling between multiple bitlines; and etching both the c-Si and c-SiGe materials using a mask and etch process. selectively etching the c-SiGe material from inside the at least one HAR hole to form a lateral feature extending from a sidewall of the at least one HAR hole; selectively etching the c-Si material in the at least one HAR hole to increase a size of the at least one HAR hole and a height of the lateral feature, or etching the c-Si material and the c-SiGe material in the at least one HAR hole to increase a size of the at least one HAR hole, a height of the lateral feature, and a width of subsequent features extending into the c-SiGe material; and / or depositing different materials in different holes to block or enable lateral or vertical recess formation processes for 3D DRAM cell formation.

[0009]

[0009] In some embodiments, a structure for use in a three-dimensional dynamic random access memory (3D DRAM) comprises at least one vertical wordline feature of the 3D DRAM formed through a high aspect ratio (HAR) central hole in a stack of alternating layers of crystalline silicon (c-Si) and crystalline silicon germanium (c-SiGe), and at least one horizontal bitline feature of the 3D DRAM orthogonally adjacent to the at least one vertical wordline feature of the 3D DRAM.

[0010]

[0010] In some embodiments, the structure further includes at least one vertical wordline feature of the 3D DRAM having at least one gate-all-around (GAA) transistor structure, the at least one GAA transistor structure having lateral source / drain doped regions and spacers, the lateral source / drain doped regions and spacers being symmetrical and self-aligned with respect to the HAR central hole, at least one horizontal bitline feature of the 3D DRAM having a shield formed over the at least one horizontal bitline feature, the shield configured to reduce noise coupling, and / or at least one vertical wordline feature of the 3D DRAM being positioned between two isolation features configured to provide structural support to the 3D DRAM.

[0011]

[0011] Other and further embodiments are disclosed below.

[0012]

[0012] The embodiments of the present principles can be understood by referring to the exemplary embodiments of the principles briefly summarized above, discussed in more detail below, and illustrated in the accompanying drawings. However, the accompanying drawings show only typical embodiments of the principles, and should not be considered as limiting the scope, since other equally effective embodiments of the principles may be recognized. [Brief description of the drawings]

[0013] [Figure 1] 1 shows a cross-sectional view of alternating heteroepitaxial layers of silicon and silicon germanium, in accordance with some embodiments of the present principles; [Diagram 2] 13A-13C show cross-sectional views of HAR hole formation for features according to some embodiments of the present principles. [Diagram 3] 1 shows a cross-sectional view of a silicon / silicon germanium stack having features according to some embodiments of the present principles. [Figure 4] 1 shows a top view of an exemplary 3D DRAM layout, in accordance with some embodiments of the present principles. [Diagram 5] 1A-1D show top and cross-sectional views of slot formation by holes versus slot etching according to some embodiments of the present principles; [Figure 6] 13 illustrates a slot forming process with holes according to some embodiments of the present principles; [Figure 7] 1 shows a top view of an isolation feature hole, according to some embodiments of the present principles. [Figure 8] 13A-13C show top views of isolation feature holes after slots have been formed, according to some embodiments of the present principles. [Figure 9] 1 shows a top view of an isolation feature hole after a low temperature oxide layer has been formed in the slot, in accordance with some embodiments of the present principles. [Figure 10] 13A-13C show top views of isolation feature holes after some holes have been enlarged, in accordance with some embodiments of the present principles. [Figure 11] 1 shows a top view of an isolation feature hole after deposition of a dielectric material within the hole, according to some embodiments of the present principles. [Figure 12] 13A-13C show top views of wordline feature holes after deposition and resist removal processes according to some embodiments of the present principles. [Figure 13] 1 shows a cross-sectional view of a wordline feature hole in a silicon / silicon germanium stack, in accordance with some embodiments of the present principles. [Figure 14]1 shows a top view of a first lateral etch area of ​​a silicon / silicon germanium stack, according to some embodiments of the present principles. [Figure 15] 1A-1C show cross-sectional views of lateral selective etching of silicon germanium layers in accordance with some embodiments of the present principles. [Figure 16] 1A-1C show cross-sectional views of an etching process that increases the etched gap size, in accordance with some embodiments of the present principles. [Figure 17] 1A-1C illustrate top views of the formation of source / drain regions and spacer regions of a transistor according to some embodiments of the present principles. [Figure 18] 1A-1C show cross-sectional views of selective etching of silicon germanium layers in accordance with some embodiments of the present principles. [Figure 19] 1A-1C show cross-sectional views of conformal coating of wordline feature holes with doped oxide in accordance with some embodiments of the present principles. [Figure 20] 1A-1C illustrate cross-sectional views of etching back a conformal coating in a wordline feature hole to form doped regions of a transistor according to some embodiments of the present principles. [Figure 21] 1 illustrates a cross-sectional view of an oxide layer deposited in a wordline feature hole in accordance with some embodiments of the present principles. [Figure 22] 1A-1C show cross-sectional views of a dielectric layer deposited in a wordline feature hole in accordance with some embodiments of the present principles; [Figure 23] 1A-1C show cross-sectional views of the removal of a portion of a dielectric layer and an oxide layer according to some embodiments of the present principles. [Figure 24] 1A-1D show cross-sectional views of the deposition of gate oxide and gate electrode materials according to some embodiments of the present principles; [Diagram 25] FIG. 1 shows a top view of a bitline slit formed between two 3D DRAM transistors according to some embodiments of the present principles. [Figure 26]1 shows a cross-sectional view of a bitline slit formed in a silicon / silicon germanium stack, according to some embodiments of the present principles. [Figure 27] 1A-1D show cross-sectional views for silicon germanium and source / drain doping region removal according to some embodiments of the present principles. [Figure 28] 1A-1C show cross-sectional views of etching to widen and heighten the lateral channels of the bitline features followed by widening of the bitline features and deposition of a first dielectric layer, according to some embodiments of the present principles. [Figure 29] 1A-1C show cross-sectional views of the deposition of a second dielectric layer to isolate bitline features according to some embodiments of the present principles. [Diagram 30] 1A-1D show cross-sectional views of silicon tip formation at bitline features according to some embodiments of the present principles; [Diagram 31] 1A-1C illustrate cross-sectional views of removing a second dielectric layer in an isolation gap in a bitline feature according to some embodiments of the present principles. [Diagram 32] 1A-1D show cross-sectional views of silicon recess formation in bitline features according to some embodiments of the present principles; [Diagram 33] 1A-1D show cross-sectional views of ohmic contact formation in bitline features according to some embodiments of the present principles; [Diagram 34] 1A-1C show cross-sectional views of the deposition of a titanium nitride / tungsten layer in a bitline feature in accordance with some embodiments of the present principles. [Diagram 35] 1A-1C show cross-sectional views of an etch-back of a titanium nitride / tungsten layer into a bitline feature in accordance with some embodiments of the present principles. [Diagram 36] 1A-1D show cross-sectional views of a dielectric barrier layer formation in a bitline feature according to some embodiments of the present principles; [Figure 37] 13A-13C illustrate cross-sectional views of deposition of a third dielectric layer formation and conductive shield formation between bitline features according to some embodiments of the present principles. [Figure 38] 1 illustrates a top view of a horizontal bit line structure interfacing with a vertical word line structure interfacing with a capacitor structure (thereby forming a 3D DRAM structure) according to some embodiments of the present principles. [Figure 39] 1 shows a cross-sectional view of a capacitor structure having a bottom electrode according to some embodiments of the present principles; [Diagram 40] 1 shows a cross-sectional view of a 3D DRAM structure according to some embodiments of the present principles. [Diagram 41] 1 illustrates a method for forming a 3D DRAM structure according to some embodiments of the present principles. [Diagram 42] 1 shows an isometric view of a 3D DRAM structure, in accordance with some embodiments of the present principles. [Diagram 43] 1 illustrates an isometric view of a gate-all-around formation of a wordline transistor according to some embodiments of the present principles. [Diagram 44] 1 illustrates an isometric view of gate rounding of wordline transistor processing for channel reveal, channel thinning and gate dielectric formation according to some embodiments of the present principles.

[0014] For ease of understanding, the same reference numerals have been used, where possible, to designate identical elements common to the figures. The drawings are not necessarily drawn to scale and may be simplified for clarity. Elements and features of one embodiment may be beneficially incorporated in other embodiments without further remarks. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0015]

[0058] The methods and structures enable three-dimensional (3D) dynamic random access memory (DRAM) cells using economical materials and process methods, with a resolution of approximately 1300 μm per megabit. 2Memory arrays that meet D1d memory densities above 3D DRAM can be fabricated. Two-dimensional (2D) DRAM scaling is becoming very difficult to fabricate and its cost is constantly increasing. Below the D1d DRAM node, feature sizes become so small that even self-aligned quadruple patterning (SAQP) is not a viable option. Even with extreme ultraviolet (EUV) lithography, EUV lithography needs to be at least self-aligned double patterning (SADP), if not SAQP at most levels. 3D DRAM is a concept that is being widely studied in the DRAM industry beyond D1d, but proposed solutions cannot be processed with economical materials and processes at the dimensions required to reach memory densities comparable to 2D DRAM.

[0016]

[0059] In the method and structure of the present principles, a 3D DRAM structure is formed using gate-all-around (GAA) transistors incorporating alternating crystalline silicon (c-Si) and crystalline silicon germanium (c-SiGe) heteroepitaxially grown layers. As shown in cross-sectional view 100 of FIG. 1, a first c-Si layer 102A is formed, followed by a first c-SiGe layer 104A. This process is repeated with a second c-Si layer 102B, followed by a second c-SiGe layer 104B. Similarly, a third c-Si layer 102C is then formed, followed by a third c-SiGe layer, and a fourth c-Si layer 102D. The layers continue to alternate to form as many layers as needed for one or more specific structures, providing significant flexibility in the design of memory structures. In some embodiments, the c-Si layer may have a thickness 106 of about 40 nm to about 60 nm, and the c-SiGe layer may have a thickness 108 of about 5 nm to about 20 nm. In some embodiments, the c-Si layer may have a thickness 106 of about 50 nm, and the c-SiGe layer may have a thickness 108 of about 10 nm. The thicknesses may vary depending on the design of a given memory structure. By using alternating heteroepitaxy of silicon and silicon germanium, the many layers of the memory cell can be easily constructed in a cost-effective manner.

[0017]

[0060] The cross-sectional view 200 of FIG. 2 illustrates the beginning of the formation of memory structure features. In some memory structures, a high aspect ratio (HAR) hole 202 may be formed in a Si / SiGe stack 206. The HAR hole 202 may be formed into vertical wordlines, horizontal bitlines, capacitors, etc. The HAR hole 202 may be formed, for example, using a mask and etch process that etches both c-Si and c-SiGe. In the cross-sectional view 300 of FIG. 3, the HAR hole 202 is further processed to form various lateral features from within the HAR hole 202. The features shown are just one example of how the Si / SiGe stack 206 may be used in the formation of 3D DRAM features. These examples are not intended to be limiting in any way. A first feature 304A may be formed by using a selective removal process (SRP) that selectively removes only the SiGe. By tuning the selective removal process, the amount of lateral etching 308 may be precisely controlled. The second feature 304B may be formed by increasing the size of the second feature 304B using an etching process that etches Si. The etching process used may be selective to Si, or both Si and SiGe may be etched depending on the desired size or shape of the feature. The third feature 304C may be formed using SRP to selectively remove additional lateral portions of the SiGe layer 104C. By using selective and non-selective etching processes with the Si / SiGe stack 206, many different types of features can be easily and economically formed in the Si / SiGe stack 206.

[0018]

[0061] In FIG. 4, a top view 400 shows an example layout 408 for forming 3D DRAM memory features in a Si / SiGe stack 402. The etching process can be used to open different holes or different sets of holes depending on the type of desired feature in the Si / SiGe stack 402 to be formed at a given point in the formation process. In some embodiments, a first hole location 404 can be defined and etched into the top dielectric anti-reflective coating (DARC) layer 414 using a first argon fluoride (ArF) exposure mask followed by a second hole location 406 to allow for a smaller hole pitch than can be directly printed with ArF lithography. In some embodiments, the features can be holes or short slots and can be used to define active areas, word lines, capacitors, and bit line areas. In some embodiments, most or all of the holes can go through a deep (HAR) etch simultaneously, and then selected areas (e.g., first region 424, second region 426, third region 428, and / or fourth region 430) can be filled or covered with resist to prevent processing of the holes in the selected areas to sequentially define active areas, wordlines, capacitors, and bitlines. Subsequent processes can remove the resist from the second hole locations 406, allowing the second hole locations 406 to be deep etched at a later time, allowing for great flexibility in 3D DRAM layout. Methods and structures of the present principles allow deep etching of the layout and main structures to be performed first, eliminating the need to intersperse deep etches in the structure formation process, reducing processing time and cost.

[0019]

[0062] As described below, hole pattern etching is used to form the basic structure of many different types of features, including slots. In the exemplary layout shown in top view 400, an alternating photolithography pattern is used, but one skilled in the art would also understand that all hole locations could be printed simultaneously. Alternating patterning of holes allows for a cheaper lithography process. Printing holes for different purposes at once, or printing a grid of holes, eliminates alignment errors of holes for multiple purposes. Preformed holes can be opened or closed at any point in the process to form slits or slots, or to increase a dimension in any direction (e.g., X-direction or Y-direction), or to allow for localized selective etching of the SiGe layer. In FIG. 4, top view 400 also shows 3D DRAM memory regions for active areas, word lines, capacitors, and bit lines formed in Si / SiGe stack 402 for some embodiments. A first region 424 of Si / SiGe stack 402 includes vertical word lines. A second region 426 of the Si / SiGe stack 402 includes an active area. A third region 428 of the Si / SiGe stack 402 includes a capacitor area. A fourth region 430 of the Si / SiGe stack 402 includes a horizontal bitline. By using different sets of holes as described above, the sets of holes can be opened and processed at different times to form active area slots, capacitor slits, wordline slits, and / or bitline slits, etc.

[0020]

[0063] Forming slots or slits from deep etched holes provides a building block for 3D DRAM feature construction. In FIG. 5, top view 500A and cross-sectional view 500B show the contrast between forming slots by holes and by slot etching. A hole 504 etched in a substrate 502 has a relatively constant diameter 516 throughout the length 522 of the hole 504 with straight sidewalls 506. In contrast, when forming a slot 508 by etching, the opening dimensions (opening width 534 and opening length 532) at the surface of the substrate are not constant throughout the depth 520 of the slot 508. The sidewalls 510 of the slot 508 are irregular, and due to the irregularities in the etch, the opening width 534 tends to increase to the inner width 512 and the opening length 532 tends to decrease to the inner length 514. The inventors have found that forming the slots using holes provides slots with improved dimensional accuracy throughout the depth of the slot. 6 illustrates a process for forming slots 610 using hole etching. In a first process 600A, a series of holes 620 are etched into a substrate, closely spaced apart. For example, in some embodiments, the hole diameter 622A may be about 30 nm, and the spacing 624 between the hole edges may be about 20 nm. In a second process 600B, each of the series of holes 620 is enlarged. For example, in some embodiments, the increased hole diameter 622B may be about 50 nm. In a third process 600C, the diameter of the holes is increased such that slots 610 are formed in the substrate.

[0021]

[0064] FIG. 41 is a method 4100 of forming vertical wordline features 4002 for a 3D DRAM using alternating heteroepitaxial stacks 4008 of c-Si and c-SiGe (illustrated in cross-sectional view 4000 of FIG. 40). References to FIGS. 1-24, 40, and 42-44 may be made during the description of method 4100. In block 4102, isolation features 1102 are formed in a Si / SiGe stack 704, as shown in top view 1100 of FIG. 11. The isolation features 1102 start out as a series of etch holes 702, as shown in top view 700 of FIG. 7. The outer holes 706 are filled / blocked with resist. The inboard holes 708 are further etched, expanding the size of the inboard holes 708, until they join to form slots 802, as shown in top view 800 of FIG. 8. The slots 802 are then conformally coated with a low temperature oxide layer 902 (such as, but not limited to, silicon dioxide) as shown in top view 900 of Figure 9. The resist is then removed from the outer holes 706, which are then etched wide until they contact the low temperature oxide layer 902 as shown in top view 1000 of Figure 10, thus completing the formation of the isolation slots.

[0022]

[0065] The enlarged outer holes 706A and slots 802 are then filled with a dielectric 1104 (such as, but not limited to, a nitride) as shown in FIG. 11. The dielectric 1104 provides a skeletal backbone to support other features in the 3D DRAM. The dielectric 1104 also provides an etch stop during subsequent lateral etching to form various features of the 3D DRAM. In some embodiments, the dielectric 1104 is selected from a material that allows selective removal of silicon and / or silicon germanium without removing the dielectric 1104. In some situations, such as during the formation of a capacitor for a 3D DRAM, the low temperature oxide layer 902 may be selectively removed after the formation of the isolation features 1102 (discussed below). In some embodiments, the entire isolation slot has a central portion of its length with a silicon dioxide liner that allows vertical paths to connect with subsequently formed wordline features if a hydrofluoric (HF) etch is used, but the ends of the isolation slot are filled with a dielectric, such as nitride, that does not etch with HF to preserve lateral cell isolation and structural support.

[0023]

[0066] In block 4104 of FIG. 41, features for vertical wordline features 4002, e.g., GAA transistor features 2402, are formed as shown in cross-sectional view 2400 of FIG. 24. In an example of forming a wordline feature, the wordline hole 1202 located between two isolation features is processed as shown in top view 1200 of FIG. 12. Although not shown in the previous figures for simplicity, the wordline hole 1202 may be etched at the same time as the isolation feature hole and may be covered with resist to protect the wordline hole 1202. The resist and any deposited material are removed and the wordline hole 1202 is opened to allow access for lateral etching chemistry from the top of the substrate. Cross-sectional line 1204 shows a cut line for the views of FIGS. 13, 15, 16, and 18-24. Subsequent transistor formation is self-aligned, resulting in low leakage and high drive current capability. Self-aligned source / drain doping is also achieved from the vertical wordline channel formation, and in some embodiments, a thin phosphosilicate glass (PSG) fill process and removal is used to form a plug of PSG for doping the silicon material. Formation of self-aligned dielectric spacers (e.g., but not limited to, nitride spacers) is also achieved by a thin dielectric to fill the pre-formed SiGe gap to form a dielectric plug.

[0024]

[0067] In the cross-sectional view 1300 of FIG. 13, a wordline feature hole 1302 is formed in a Si / SiGe stack 1308 of alternating Si layers 1304 and SiGe layers 1306. The wordline feature hole 1302 allows chemical access to the Si / SiGe stack 1308 from a top surface 1310 of the Si / SiGe stack 1308. In the top view 1400 of FIG. 14, a first lateral etch region 1402 is shown inside the Si / SiGe stack 1308. In FIG. 15, a cross-sectional view 1500 shows a lateral selective etch of the SiGe layer 1306. The etchant is selective to SiGe over silicon and the dielectric 1104 acting as an etch stop. The etch distance 1502A of the wordline feature hole 1302 from the centerline 1504 can be controlled by the etch rate of the etchant and / or the duration of the etching process. The etched gap has a height 1506A that follows the thickness of the SiGe layer 1306 due to the selective etchant used. An etching process is then performed to remove both the Si and SiGe, increasing the etched gap as shown in cross-sectional view 1600 of FIG. 16. The etched gap increases in height 1506B and length to etch distance 1502B. As seen in top view 1400 of FIG. 14, the first lateral etch region 1402 extends into the dielectric 1104 and into the low-temperature oxide layer 902. When the Si and SiGe etch completely forms the first lateral etch region 1402 as shown in top view 1400, the dielectric 1104 and low-temperature oxide layer 902 are exposed. During the previous etching sequence, a gate-all-around space for the gate oxide is created as discussed below with respect to FIG. 44. The process continues by forming a second lateral etch region 1702 to form the source / drain and spacer regions of the transistor, as depicted in top view 1700 of Figure 17. The second lateral etch region 1702 extends the first lateral etch region 1402.The second lateral etch region 1702 is formed by selectively etching the SiGe layer 1306 to increase the etch distance 1502C, as shown in cross-sectional view 1800 of FIG.

[0025]

[0068] A conformal layer of doped oxide 1902 (e.g., but not limited to, PSG) is deposited in the wordline feature opening 1302 as shown in cross-sectional view 1900 of FIG. 19. ALD or CVD deposition processes may be used depending on the dimensions (ALD is preferred for smaller dimensions). The conformal layer 1902 completely fills the narrow portion 1904 of the lateral gap along the wordline feature opening 1302. The conformal layer 1902 is then etched back leaving doped region 2002 as shown in cross-sectional view 2000 of FIG. 20. A thin oxide layer 2102 is then deposited or grown along the wordline feature opening 1302 as shown in cross-sectional view 2100 of FIG. 21. The oxide may be formed on a silicon surface (e.g., thermal oxide) or may be deposited on silicon. A dielectric layer 2202 (such as, but not limited to, nitride) is then conformally deposited in the wordline feature hole 1302, filling the narrow portion 2204 of the gap, as shown in cross-sectional view 2200 of FIG. 22. The dielectric layer 2202 is then removed along with the oxide to protect the silicon in the main portion 2302 of the gap. The thin oxide layer 2102 is then removed, leaving the dielectric layer 2202 and a portion of the thin oxide layer 2102 in the narrow portion 1904 of the gap, as shown in cross-sectional view 2300 of FIG. 23. A gate oxide layer 2404 is grown or deposited in the wordline feature hole 1302 using an ALD deposition process, as shown in cross-sectional view 2400 of FIG. 24. The source / drain doping regions 2002 and the newly formed spacers 2408 are formed symmetrically within the Si / SiGe stack 1308. A gate electrode 2406 is then deposited in the wordline feature opening 1302 using an ALD process until the wordline feature opening 1302 is filled. The gate electrode 2406 can be, but is not limited to, titanium nitride (TiN), or the like.

[0026]

[0069] Returning to FIG. 41, in block 4106, a capacitor feature for a 3D DRAM is formed. With reference to FIG. 38 and FIG. 40, the formation of the capacitor feature 4006 of FIG. 40 for a 3D DRAM is described. In some embodiments, the capacitor feature is a support structure for a bottom electrode of a capacitor. The top view 3800 of FIG. 38 shows a horizontal bit line structure 3802 interfacing with a vertical word line structure 3804 interfacing with the capacitor structure 3806, thereby forming a 3D DRAM structure 3808. A support structure 3812 for the capacitor structure 3806 is formed, as well as an isolation slot having a different dielectric around the word line feature. Briefly, the slot structure 3818 is coated with a dielectric material (e.g., low temperature oxide), and the ends of the slot structure 3818 (support pillars 3816) are filled with a second dielectric material 3814 (e.g., nitride) that acts as a structural support. The first dielectric material (not shown) is then coated with SiO 2 A selective etching process is used to etch away the material, for example but not limited to using Hydrogen Fluoride (HF), leaving a void 3810 surrounding the second dielectric material 3814 and separating the bottom electrode 3820 from the second dielectric material 3814. A second end 3826 of the bottom electrode 3820 is then supported by silicon 3828. In some embodiments, the void 3810 can be filled with a high-k dielectric material to form a top electrode 3902 to increase the 3D DRAM capacity while still maintaining structural support for the bottom electrode 3820. As shown in the cross-sectional view 3900 of FIG. 39, the capacitor structure 3806 and the bottom electrode 3820 are supported at a first end 3824 by the side 3822 of the support post 3816 and at a second end 3826 by silicon 3828. The top electrode 3902 and the bottom electrode 3820 are separated by a capacitor dielectric layer 3904 .

[0027]

[0070] In block 4108 of FIG. 41, bitline features of a 3D DRAM are formed. With reference to FIGS. 25-37 and FIG. 40, the formation of horizontal bitline features 4004 of FIG. 40 of a 3D DRAM is described. In the top view 2500 of FIG. 25, two 3D DRAM transistors 2502 (vertical wordline features) are formed in a substrate 2506 using the methods described above. Then, bitline slits 2504 are formed between the two 3D DRAM transistors. As shown in the cross-sectional view 2600 of FIG. 26, the bitline slits 2504 run from the top surface 1310 downward into the Si / SiGe stack 1308. In some embodiments, anisotropic etching is used to form the bitline slits 2504. In some embodiments, isotropic etching is used in conjunction with a hard mask to form the bitline slits 2504. The Si / SiGe stack 1308 is then etched through the bitline slits 2504 to selectively remove any remaining portions of the SiGe layer 1306, as shown in cross-sectional view 2700 of Figure 27. The removal of the SiGe layer 1306 exposes the source / drain doping regions 2002 of the two 3D DRAM transistors 2502.

[0028]

[0071] Next, a silicon etching process is performed on all surfaces to widen and heighten the lateral channels 2702, forming gaps for isolating the bitline features. During the silicon etching process, the bitline slits 2504 are also widened from the first width 2704 to a second width 2806. Next, the source / drain doping regions 2002 of the two 3D DRAM transistors are removed by etching, leaving the isolation gaps 2802, as shown in the cross-sectional view 2800 of FIG. 28. A first dielectric layer 2804 (e.g., but not limited to, a nitride layer) is deposited on the surfaces of the bitline slits 2504 using an ALD deposition process to form a thin layer. Next, a second dielectric layer 2902 is deposited on the first dielectric layer to isolate the bitline features and fill the isolation gaps 2802, leaving spaces 2904 in the bitline slits 2504, as shown in the cross-sectional view 2900 of FIG. 29. The spaces 2904 allow chemical access to the inner surfaces of the bitline slits 2504 for further processing.

[0029]

[0072] The second dielectric layer 2902 is then etched to expose the first dielectric layer 2804, leaving a portion of the second dielectric layer 2902 in the isolation gap 2802. In some embodiments, the partial etching of the second dielectric layer 2902 may be accomplished using an isotropic etch to expose the first dielectric layer 2804, or the bitline slits may be patterned and an anisotropic etch may be used to remove the second dielectric layer 2902 to expose the first dielectric layer 2804. The first dielectric layer 2804 is then partially etched back to form the silicon chip 3002 between the isolation gap 2802, as shown in cross-sectional view 3000 of FIG. 30. In some embodiments, the remaining portion of the second dielectric layer 2902 in the isolation gap 2802 is removed, as shown in cross-sectional view 3100 of FIG. In an alternative embodiment, the remaining portions of the second dielectric layer 2902 in the isolation gap 2802 may be left in place (not shown) and covered to function similarly to an air isolation gap. The silicon chip 3002 is then etched back to form a recess 3202 using an etch selective to silicon over the material used for the first dielectric layer 2804, as shown in cross-sectional view 3200 of FIG.

[0030]

[0073] Next, a titanium silicon phosphorus (TiSiP) layer 3302 is selectively deposited on the silicon to form an ohmic contact between a subsequently deposited titanium nitride (TiN) / tungsten (W) layer and the silicon using an ALD deposition process, as shown in cross-sectional view 3300 of FIG. 33. The TiSiP layer 3302 serves as a doping process. A TiN / W layer 3402 is deposited on all surfaces within the bitline slits 2504 such that the recesses 3202 are filled, but the isolation gaps 2802 are not completely filled, leaving horizontal spaces 3404 for chemical access during subsequent processing, as shown in cross-sectional view 3400 of FIG. 34. The TiN / W layer 3402 is then etched back from the isolation gaps 2802, but remains within the recesses 3202, as shown in cross-sectional view 3500 of FIG. 35. The residue of the TiN / W layer 3402 in the isolation gaps 2802 after the etch-back process does not affect the performance of the 3D DRAM structure. Next, a dielectric barrier layer 3602 is deposited on the surfaces within the bitline slits 2504, as shown in cross-sectional view 3600 of FIG. 36. The dielectric barrier layer 3602 can be, but is not limited to, a nitride barrier layer, or the like. A third dielectric layer 3702 (such as, but is not limited to, an oxide layer) is deposited on the surfaces of the bitline slits 2504 such that spaces 3706 remain within the isolation gaps 2802, which can be filled by the subsequent deposition of a conductive shielding layer 3704, as shown in cross-sectional view 3700 of FIG. 37. Next, a conductive shielding layer 3704 is deposited using an ALD process such that the conductive shielding layer 3704 is deposited on the third dielectric layer 3702, filling the spaces 3706 within the isolation gaps 2802. The conductive shielding layer 3704 acts as a shield to reduce noise coupling between the bitlines, completing the horizontal bitline feature 4004.

[0031]

[0074] FIG. 42 shows an isometric view 4200 of a 3D DRAM structure according to some embodiments. A capacitor section 4212 is connected to a wordline feature section 4214 that connects with a horizontal bitline feature section 4216. The wordline feature section 4214 includes two source / drain regions 4210. A cut line 4202 is shown in the isometric view 4300 of FIG. 43 to illustrate the internal structure of the 3D DRAM structure through the wordline feature. The wordline hole 4204 is centered with respect to the channel and forms two GAA channels 4302 at each intersection of the vertical wordline feature 4306 and the horizontal bitline feature 4208. The vertical wordline features 4306 are separated by an isolation feature 4304. As the aforementioned process of forming the wordline features is performed, the GAA channels 4302 are also formed. In the following, the formation of the GAA channels 4302 during the aforementioned wordline feature process will be described from different perspectives. The formation of the GAA channel 4302 is shown in the first isometric view 4400A, the second isometric view 4400B, and the third isometric view 4400C in FIG. 44. In the first isometric view 4400A, the SiGe layer 1306 is etched back to reach the isolation feature 4304 as described above (the dielectric 1104 acts as an etch stop). The etch back process also removes a portion of the low temperature oxide layer 902 previously deposited in the isolation feature 4304 as described above. In the second isometric view 4400B, the silicon layer 1304 is also etched to increase the gap space, thereby removing additional portions of the low temperature oxide layer 902 and forming a space all around the GAA channel 4302. In the third isometric view 4400C, the gate oxide layer 2404 is formed in the wordline feature and surrounds the GAA channel 4302. The space surrounding the GAA channel and the gate oxide layer 2404 is then filled with gate electrode material as described above for the wordline features.

[0032]

[0075] Embodiments according to the present principles may be implemented in hardware, firmware, software, or any combination thereof. Embodiments may also be implemented as instructions stored using one or more computer-readable media, which may be read and executed by one or more processors. A computer-readable medium may include any mechanism for storing or transmitting information in a form readable by a machine (e.g., a computing platform, or a "virtual machine" running on one or more computing platforms). For example, a computer-readable medium may include any suitable form of volatile or non-volatile memory. In some embodiments, a computer-readable medium may include a non-transitory computer-readable medium.

[0033]

[0076] While the forgoing is directed to embodiments of the present principles, other and further embodiments of the present principles may be devised without departing from the basic scope thereof.

Claims

1. 1. A method for forming a three dimensional dynamic random access memory (3D DRAM) structure, comprising: depositing alternating layers of crystalline silicon (c-Si) and crystalline silicon germanium (c-SiGe) materials onto a substrate using a heteroepitaxy process; Etching a pattern of holes in the alternating layers of c-Si and c-SiGe materials, the pattern of holes having at least one high aspect ratio (HAR) hole extending from a top surface of the alternating layers into the alternating layers, the pattern of holes being configured to allow for later etching or depositing material through the at least one HAR hole to form a 3D DRAM feature of a 3D DRAM structure, without subsequently HAR etching a hole in the substrate, and integrating portions of the pattern of holes formed by etching material between portions of the pattern of holes to form active area isolation slots of a 3D DRAM structure. A method comprising:

2. A method for forming a three dimensional dynamic random access memory (3D DRAM) structure, comprising: depositing alternating layers of crystalline silicon (c-Si) and crystalline silicon germanium (c-SiGe) materials onto a substrate using a heteroepitaxy process; Etching a pattern of holes in the alternating layers of c-Si and c-SiGe materials, the pattern of holes having at least one high aspect ratio (HAR) hole extending from a top surface of the alternating layers into the alternating layers, the pattern of holes being configured to allow for later etching or depositing material through the at least one HAR hole to form a 3D DRAM feature of a 3D DRAM structure, without subsequently HAR etching a hole in the substrate, and Depositing different materials into different holes to block or enable lateral or vertical recess formation processes for 3D DRAM cell formation A method comprising:

3. A method for forming a three dimensional dynamic random access memory (3D DRAM) structure, comprising: depositing alternating layers of crystalline silicon (c-Si) and crystalline silicon germanium (c-SiGe) materials onto a substrate using a heteroepitaxy process; Etching a pattern of holes in the alternating layers of c-Si and c-SiGe materials, the pattern of holes having at least one high aspect ratio (HAR) hole extending from a top surface of the alternating layers into the alternating layers, the pattern of holes being configured to allow for later etching or depositing material through the at least one HAR hole to form a 3D DRAM feature of a 3D DRAM structure, without subsequently HAR etching a hole in the substrate, and forming an isolation slot having a liner of a first dielectric material removable by exposure to Hydrogen Fluoride (HF), the isolation slot having an end filled with a second dielectric material impervious to HF, the isolation slot configured to provide lateral cell isolation and structural support for a 3D DRAM structure; A method comprising:

4. forming a bottom electrode of a capacitor of a 3D DRAM structure supported on one or more ends of the isolation slot filled with the second dielectric material; and removing the liner of the first dielectric material in the isolation slot to provide a space to be filled with a high-k dielectric material for increasing 3D DRAM cell capacitance of a 3D DRAM structure while maintaining structural support for the bottom electrode; The method of claim 3 further comprising:

5. A method for forming a three dimensional dynamic random access memory (3D DRAM) structure, comprising: depositing alternating layers of crystalline silicon (c-Si) and crystalline silicon germanium (c-SiGe) materials onto a substrate using a heteroepitaxy process; Etching a pattern of holes in the alternating layers of c-Si and c-SiGe materials, the pattern of holes having at least one high aspect ratio (HAR) hole extending from a top surface of the alternating layers into the alternating layers, the pattern of holes being configured to allow for later etching or depositing material through the at least one HAR hole to form a 3D DRAM feature of a 3D DRAM structure, without subsequent HAR etching of the hole in the substrate; Selectively etching the c-SiGe material from within the at least one HAR hole to form a lateral feature extending from a sidewall of the at least one HAR hole; and Selectively etching the c-Si material in the at least one HAR hole to increase a size of the at least one HAR hole and a height of the lateral feature; A method comprising:

6. A method for forming a three dimensional dynamic random access memory (3D DRAM) structure, comprising: depositing alternating layers of crystalline silicon (c-Si) and crystalline silicon germanium (c-SiGe) materials onto a substrate using a heteroepitaxy process; Etching a pattern of holes in the alternating layers of c-Si and c-SiGe materials, the pattern of holes having at least one high aspect ratio (HAR) hole extending from a top surface of the alternating layers into the alternating layers, the pattern of holes being configured to allow for later etching or depositing material through the at least one HAR hole to form a 3D DRAM feature of a 3D DRAM structure, without subsequent HAR etching of the hole in the substrate; Selectively etching the c-SiGe material from within the at least one HAR hole to form a lateral feature extending from a sidewall of the at least one HAR hole; and Etching the c-Si and c-SiGe materials in the at least one HAR hole to increase a size of the at least one HAR hole, a height of the lateral features, and a width of the lateral features extending into the c-SiGe material; A method comprising:

7. The method of claim 1, wherein the hole pattern is etched using a mask and etch process that etches both c-Si and c-SiGe materials.

8. 1. A method for forming a three dimensional dynamic random access memory (3D DRAM) structure, comprising: depositing alternating layers of crystalline silicon (c-Si) and crystalline silicon germanium (c-SiGe) materials onto a substrate using a heteroepitaxy process; Etching a pattern of holes in the alternating layers of c-Si and c-SiGe materials, the pattern of holes having at least one high aspect ratio (HAR) hole extending from a top surface of the alternating layers into the alternating layers, the pattern of holes being configured to allow for later etching or depositing material through the at least one HAR hole to form a 3D DRAM feature of a 3D DRAM structure, without subsequent HAR etching of the hole in the substrate; integrating portions of the pattern of holes formed by etching material between portions of the pattern of holes to form slot features of a 3D DRAM structure; forming an isolation slot from at least one slot feature having a liner of a first dielectric material removable by exposure to hydrogen fluoride (HF), the isolation slot having an end filled with a second dielectric material impervious to HF, the isolation slot configured to provide lateral cell isolation and structural support for a 3D DRAM structure; forming a bottom electrode of a capacitor of a 3D DRAM structure supported on one or more ends of the isolation slot filled with the second dielectric material; and removing the liner of the first dielectric material in the isolation slot to provide a space to be filled with a high-k dielectric material for 3D DRAM cell capacitance increase while maintaining structural support for the bottom electrode; A method comprising:

9. Etching a wordline hole between the two isolation slots to form a wordline structure; selectively etching the c-SiGe material through an upper opening of the wordline hole to form a lateral wordline feature extending into the two isolation slots; forming source / drains and spacers of a 3D DRAM structure by extending the lateral wordline features until they are limited by the two isolation slots; depositing a conformal layer of doped oxide in said wordline opening; Etching back the conformal layer of doped oxide to leave doped regions for source / drains of a 3D DRAM structure; depositing a gate oxide layer in the wordline opening; and depositing a gate electrode to fill said wordline hole; The method of claim 8 , further comprising:

10. anisotropically etching a slit between two word line structures to form a bit line structure; selectively etching laterally the c-SiGe material in the slit from a top opening of the slit; forming the bit line structure by chemically depositing and etching from the top opening of the slit; and forming a conductive shield layer on the bit line structure to reduce noise coupling between a plurality of bit lines; The method of claim 9 further comprising:

11. The method of claim 8, wherein the pattern of holes is etched using a mask and etch process that etches both c-Si and c-SiGe materials.

12. selectively etching the c-SiGe material from within the at least one HAR hole to form a lateral feature extending from a sidewall of the at least one HAR hole; The method of claim 8 , further comprising:

13. Selectively etching the c-Si material in the at least one HAR hole to increase the size of the at least one HAR hole and the height of the lateral features; or Etching the c-Si and c-SiGe materials in the at least one HAR hole to increase a size of the at least one HAR hole, a height of the lateral features, and a width of the lateral features extending into the c-SiGe material; The method of claim 12 further comprising:

14. Depositing different materials into different holes to block or enable lateral or vertical recess formation processes for 3D DRAM cell formation; The method of claim 8 , further comprising:

Images