Multi-step post-exposure treatment to improve dry developability of metal-containing resists

Abstract

Various embodiments described herein relate to methods, apparatus, and systems for treating metal-containing photoresist to modify the material properties of the photoresist. The metal-containing photoresist can be treated with a post-exposure bake process that involves at least two thermal operations. At least one of the post-exposure bake operations includes exposing the metal-containing photoresist to a moderately elevated temperature in an oxygen-rich atmosphere. This operation is followed by a post-exposure bake operation that includes exposing the metal-containing photoresist to a highly elevated temperature in an inert gas atmosphere. The multi-step post-exposure bake operation improves the etch selectivity in a subsequent dry development process.

Description

[Technical field]

[0001] Incorporation by Reference A PCT application is being filed contemporaneously herewith as a part of this application, and each application identified in that contemporaneously filed PCT application to which this application claims benefit or priority is hereby incorporated by reference in its entirety for all purposes.

[0002] FIELD OF THE DISCLOSURE Embodiments herein relate to the processing of photoresist materials, and more particularly, to the processing of metal-containing photoresist materials after exposure in semiconductor fabrication. [Background technology]

[0003] The fabrication of semiconductor devices, such as integrated circuits, is a multi-step process that involves photolithography. In general, the process involves depositing material on a wafer and patterning the material by lithographic techniques to form the structural features (e.g., transistors and circuits) of the semiconductor device. The steps of a typical photolithography process known in the art include preparing a substrate on which a photoresist is applied, such as by spin coating, exposing the photoresist to light in a desired pattern to render the exposed areas of the photoresist somewhat soluble in a developer, developing by applying a developer to remove either the exposed or unexposed areas of the photoresist, and subsequent processing, such as by etching or material deposition, to form features on the areas of the substrate from which the photoresist was removed.

[0004] The evolution of semiconductor design is driven by the need for, and ability to, form ever smaller features on semiconductor substrate materials. This technological advance is characterized in "Moore's Law" as the doubling of transistor density in high-density integrated circuits every two years. In fact, chip design and manufacturing have advanced so that modern microprocessors can contain billions of transistors and other circuit features on a single chip. Individual features on such chips can be on the order of 22 nanometers (nm) or less, and in some cases less than 10 nm.

[0005] One challenge in fabricating devices with such small features is the ability to reliably and reproducibly form photolithography masks with sufficient resolution. Current photolithography processes typically use 193 nm ultraviolet (UV) light to expose photoresist. The fact that the light has a wavelength significantly longer than the desired size of the features to be created on the semiconductor substrate creates inherent problems. Achieving feature sizes smaller than the wavelength of the light requires the use of complex resolution enhancement techniques such as multi-patterning. Thus, there has been great interest and research effort in developing photolithography techniques that use short wavelength light, such as extreme ultraviolet (EUV) light, with wavelengths of 10 nm to 15 nm, e.g., 13.5 nm.

[0006] However, EUV photolithography processes may present challenges such as reduced power and loss of light during patterning. Conventional organic chemically amplified resists (CARs), similar to those used in 193 nm UV lithography, have potential drawbacks when used in EUV lithography because they have low absorption coefficients, especially in the EUV region, and diffusion of photoactivated chemical species can result in blurring or line edge roughness. Furthermore, to provide the etch resistance required to pattern underlying device layers, small features patterned with conventional CAR materials may result in high aspect ratios with risk of pattern collapse. Thus, there remains a need for improved EUV photoresist materials with properties such as reduced thickness, greater absorbance, and greater etch resistance.

[0007] The Background provided herein is intended to provide a general overview of the contents of the present disclosure. Work by the currently named inventors within the scope of what is described in this Background, as well as aspects of the description that may not otherwise be regarded as prior art at the time of filing, are not admitted, expressly or impliedly, as prior art against the present technology. Summary of the Invention

[0008] Provided herein is a method of processing a metal-containing extreme ultraviolet (EUV) photoresist, the method including disposing a substrate in a process chamber, the substrate being a semiconductor substrate comprising a substrate layer and a metal-containing EUV photoresist positioned on the substrate layer, exposing the metal-containing EUV photoresist to a first elevated temperature in an oxygen-containing environment in the process chamber, and exposing the metal-containing EUV photoresist to a second elevated temperature in an inert gas environment, the second elevated temperature being higher than the first elevated temperature.

[0009] In some embodiments, the metal-containing EUV photoresist includes an EUV exposed portion and an EUV non-exposed portion, and the exposure to a first elevated temperature in an oxygen-containing environment and a second elevated temperature in an inert gas environment increases the etch selectivity between the EUV exposed portion and the EUV non-exposed portion in a subsequent dry development process. In some embodiments, the exposure to a first elevated temperature in an oxygen-containing environment and a second elevated temperature in an inert gas environment reduces line edge roughness (LER) and reduces dose to size (DtS) in a subsequent dry development process. In some embodiments, the method further includes exposing the metal-containing EUV photoresist to EUV radiation before placing the substrate in a process chamber to form the EUV exposed and EUV non-exposed regions. In some embodiments, the first wait time between the exposure to EUV radiation and the exposure to the first elevated temperature is less than about 20 minutes, and the second wait time between the exposure to the first elevated temperature and the exposure to the second elevated temperature is less than about 1 hour. In some embodiments, the first elevated temperature is between about 150° C. and about 220° C., and the second elevated temperature is between about 220° C. and about 250° C. In some embodiments, the oxygen-containing environment includes an oxygen-containing species, and a partial pressure of the oxygen-containing species is at least about 100 Torr in the oxygen-containing environment. In some embodiments, the oxygen-containing environment includes oxygen (O2), ozone (O3), water (H2O), hydrogen peroxide (H2O2), carbon monoxide (CO), carbon dioxide (CO2), or a combination thereof. In some embodiments, the inert gas environment includes nitrogen (N2), helium (He), neon (Ne), argon (Ar), xenon (Xe), or a combination thereof. In some embodiments, each of the oxygen-containing environment and the inert gas environment is moisture-free or substantially moisture-free. In some embodiments, the metal-containing EUV photoresist is a metal oxide-containing EUV photoresist. In some embodiments, the oxygen-containing environment comprises oxygen radicals and ions generated from a remote plasma source, and the metal-containing EUV photoresist is exposed to the oxygen radicals and ions.In some embodiments, exposing the metal-containing EUV photoresist to a second elevated temperature in an inert gas environment is performed in the same process chamber as exposing the metal-containing EUV photoresist to a first elevated temperature in an oxygen-containing environment. In some embodiments, the method further comprises repeating the steps of exposing the metal-containing EUV photoresist to an oxygen-containing environment and exposing the metal-containing EUV photoresist to an inert gas environment one or more times. In some embodiments, the method further comprises dry developing the metal-containing EUV photoresist to selectively remove portions of the metal-containing EUV photoresist, wherein the exposure to the first elevated temperature in the oxygen-containing environment and the exposure to the second elevated temperature in the inert gas environment is a post-exposure bake (PEB) operation performed prior to the dry developing.

[0010] An apparatus for processing a metal-containing EUV photoresist is also provided. The apparatus includes a process chamber including a substrate support configured to support a semiconductor substrate comprising a substrate layer and a metal-containing EUV photoresist positioned on the substrate layer, a process gas source connected to the process chamber and associated gas flow control hardware, substrate thermal control hardware, and a controller. The controller is configured with instructions to perform the following operations: exposing the metal-containing EUV photoresist to a first elevated temperature in an oxygen-containing environment in the process chamber, and exposing the metal-containing EUV photoresist to a second elevated temperature in an inert gas environment, the second elevated temperature being higher than the first elevated temperature.

[0011] In some embodiments, the first elevated temperature is between about 150° C. and about 220° C., and the second elevated temperature is between about 220° C. and about 250° C. In some embodiments, each of the oxygen-containing environment and the inert gas environment is moisture-free or substantially moisture-free. In some embodiments, the partial pressure of the oxygen-containing species is at least about 100 Torr in the oxygen-containing environment. In some embodiments, the oxygen-containing environment includes an oxygen-containing species, the concentration of the oxygen-containing species is at least 20% by volume in the oxygen-containing environment, and the oxygen-containing species is oxygen (O2), ozone (O3), water (H2O), hydrogen peroxide (H2O2), carbon monoxide (CO), carbon dioxide (CO2), or a combination thereof. [Brief description of the drawings]

[0012] [Figure 1] FIG. 1 provides a flow chart for a method of processing a substrate in accordance with various embodiments.

[0013] [Diagram 2] FIG. 2 illustrates a substrate during several processing steps in which a post-application treatment is used, according to certain embodiments.

[0014] [Diagram 3] FIG. 3 illustrates a substrate during several processing steps in which post-exposure treatment is used, according to various embodiments.

[0015] [Figure 4] FIG. 4 provides a flow chart for a method of processing a substrate in a multi-step post-exposure bake process according to various embodiments.

[0016] [Figure 5A] FIG. 5A illustrates a processing chamber in which certain thermal-based steps may be performed.

[0017] [Figure 5B]FIG. 5B illustrates a processing chamber in which various steps may be performed, including thermal-based steps as well as plasma-based steps.

[0018] [Figure 6] FIG. 6 is a diagram illustrating a cluster tool having a number of different modules configured to perform different operations in accordance with certain embodiments of the present disclosure.

[0019] [Figure 7A] FIG. 7A shows scanning electron microscope (SEM) images illustrating the improved material contrast and selectivity between unexposed and exposed portions of the photoresist layer that can be achieved by controlling the temperature during the post-exposure bake process. [Figure 7B] FIG. 7B shows a scanning electron microscope (SEM) image illustrating the improved material contrast and selectivity between the unexposed and exposed portions of the photoresist layer that can be achieved by controlling the temperature during the post-exposure bake process. [Figure 7C] FIG. 7C shows a scanning electron microscope (SEM) image illustrating the improved material contrast and selectivity between the unexposed and exposed portions of the photoresist layer that can be achieved by controlling the temperature during the post-exposure bake process. [Figure 7D] FIG. 7D shows a scanning electron microscope (SEM) image illustrating the improved material contrast and selectivity between the unexposed and exposed portions of the photoresist layer that can be achieved by controlling the temperature during the post-exposure bake process. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0020] Reference will be made in detail herein to certain embodiments of the present disclosure. Examples of certain embodiments are illustrated in the accompanying drawings. Although the present disclosure will be described in conjunction with these specific embodiments, it will be understood that it is not intended to limit the present disclosure to such specific embodiments. On the contrary, it is intended to cover alternatives, modifications, and equivalents that may be included within the spirit and scope of the present disclosure. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present disclosure. The present disclosure may be practiced without some or all of these specific details. In other instances, well-known process operations have not been described in detail so as not to unnecessarily obscure the present disclosure.

[0021] Processing of metal-containing resists Patterning of thin films in semiconductor processing is often a critical step in the fabrication of semiconductors. Patterning involves lithography. In conventional photolithography, such as 193 nm photolithography, a pattern is printed onto a light-sensitive photoresist film by exposing the photoresist in selective areas defined by a photomask to photons, thereby causing a chemical reaction in the exposed photoresist, creating a chemical contrast that can be exploited in a development step to remove certain portions of the photoresist to form the pattern. The patterned and developed photoresist film can then be used as an etch mask to transfer the pattern to an underlying film composed of metal, oxide, etc.

[0022] Advanced technology nodes (as defined by the International Technology Roadmap for Semiconductors) include the 22 nm, 16 nm, and beyond. For example, at the 16 nm node, a typical via or line width in a damascene structure is typically about 30 nm or less. The scaling of features on advanced semiconductor integrated circuits (ICs) and other devices drives lithography to improve resolution.

[0023] Extreme ultraviolet (EUV) lithography can extend lithography techniques by moving to shorter imaging source wavelengths than are achievable with traditional photolithography methods. EUV sources with wavelengths of approximately 10-20 nm, or 11-14 nm, for example 13.5 nm, can be used in state-of-the-art lithography tools, also called scanners. EUV radiation is strongly absorbed by a wide range of solid and fluid materials, including quartz and water vapor, and therefore operates in a vacuum.

[0024] EUV lithography utilizes an EUV resist that is patterned to form a mask for use in etching the underlying layer. The EUV resist may be a polymer-based chemically amplified resist (CAR) obtained by a liquid-based spin-on technique. An alternative to CAR is a directly photopatternable metal oxide-containing film, such as those available from Inpria Corp. (Corvallis, Oregon) and described in, for example, U.S. Patent Application Publication No. 2017 / 0102612, U.S. Patent Application Publication No. 2016 / 021660, and U.S. Patent Application Publication No. 2016 / 0116839, which are incorporated herein by reference at least for their disclosure of photopatternable metal oxide-containing films. Such films may be provided by spin-on techniques or dry vapor deposition. Metal oxide-containing films can be directly patterned (i.e., without the use of a separate photoresist) by EUV exposure in a vacuum atmosphere providing patterning resolution of less than 30 nm, as described, for example, in U.S. Patent No. 9,996,004, issued June 12, 2018, and entitled EUV PHOTOPATTERNING OF VAPOR-DEPOSITED METAL OXIDE-CONTAINING HARD MASKS, and / or International Patent Application No. PCT / US2019 / 31618, filed May 9, 2019, and entitled METHODS FOR MAKING EUV PATTERNABLE HARD MASKS, the disclosures above relating at least to the composition, deposition, and patterning of directly photopatternable metal oxide films to form EUV resist masks are incorporated herein by reference. In general, patterning involves exposing an EUV resist to EUV radiation to form a photopattern in the resist, followed by development to remove portions of the resist according to the photopattern to form a mask.

[0025] These directly photopatternable EUV resists may be composed of or contain highly EUV absorbing metals and their organometallic oxides / hydroxides and other derivatives. Upon EUV exposure, EUV photons as well as generated secondary electrons can induce chemical reactions such as beta-H elimination reactions in SnOx-based resists (and other metal oxide-based resists), providing chemical functions that promote crosslinking and other changes in the resist film. These chemical changes can then be exploited in a development step to selectively remove exposed or unexposed areas of the resist film, creating an etch mask for pattern transfer.

[0026] Metal oxide-containing films can be patterned directly (i.e., without the use of a separate photoresist) by EUV exposure in a vacuum atmosphere providing patterning resolution of less than 30 nm, as described, for example, in U.S. Patent No. 9,996,004, issued June 12, 2018, and entitled EUV PHOTOPATTERNING OF VAPOR-DEPOSITED METAL OXIDE-CONTAINING HARDMASKS, the disclosures above relating at least to the composition, deposition, and patterning of directly photopatternable metal oxide films to form EUV resist masks, are incorporated herein by reference. In general, patterning involves exposing an EUV resist to EUV radiation to form a photopattern in the resist, followed by development to remove portions of the resist according to the photopattern to form a mask.

[0027] It should also be understood that the present disclosure relates to lithographic patterning techniques and materials exemplified by EUV lithography, but is also applicable to other next-generation lithography techniques. In addition to EUV, including the standard 13.5 nm EUV wavelength currently used and developed, the most relevant radiation sources for such lithography are DUV (deep UV), which generally refers to the use of 248 nm or 193 nm excimer laser sources, X-ray, formally including EUV in the lower energy range of the X-ray range, and e-beam, which can cover a wide energy range. Such methods include contacting a substrate having exposed hydroxyl groups with a hydrocarbyl-substituted tin capping agent to form a hydrocarbyl-terminated SnOx film as an imaging / PR layer on the surface of the substrate. The specific method may depend on the particular materials and applications used in the semiconductor substrate and the final semiconductor device. Thus, the methods described in this application are merely exemplary of methods and materials that may be used in the present technology.

[0028] Directly photopatternable EUV resists may consist of or contain metals and / or metal oxides mixed within an organic component. Metals / metal oxides hold great promise in that they can enhance the absorption of EUV photons, generate secondary electrons, and / or exhibit high etch selectivity to the underlying film stack and device layers. To date, these resists have been developed using wet (solvent) approaches, which require the wafer to travel on a track where it is exposed to a developing solvent, dried, and baked. Wet development not only limits productivity, but can also cause line collapse due to surface tension effects during evaporation of the solvent between fine features.

[0029] Dry development techniques have been proposed to overcome these issues by eliminating substrate delamination and interface defects. Dry development has its own challenges, including etch selectivity between unexposed and EUV-exposed resist materials, which can result in higher size-to-dose requirements for effective resist exposure when compared to wet development. Suboptimal selectivity can also result in rounding of photoresist corners due to prolonged exposure under etching gases, which can increase line critical dimension (CD) variation in the subsequent transfer etch step.

[0030] According to various aspects of the present disclosure, one or more post-treatments on metal and / or metal oxide based photoresists after deposition (e.g., post-apply bake (PAB)) and / or exposure (e.g., post-exposure bake (PEB)) can increase the difference in material properties between exposed and unexposed photoresists (PR), thus reducing dose to size (DtS), improving PR profile, and improving line edge and line width roughness (LER / LWR) after subsequent dry development. Such treatments can involve thermal processes that control one or more of temperature, gas atmosphere, and moisture, resulting in improved dry development performance in subsequent processing. In some cases, remote plasma may be used.

[0031] In the case of post-application treatment (e.g., PAB), a thermal process that controls one or more of temperature, gas atmosphere (e.g., using one or more of the gases described herein), pressure, and moisture can be used after deposition and before exposure to modify the composition of the unexposed metal and / or metal oxide-containing photoresist. This modification increases the EUV sensitivity of the material, and thus allows for lower dose to size and line edge roughness to be achieved after exposure and dry development.

[0032] In the case of post-exposure treatment (e.g., PEB), a thermal process that controls one or more of temperature, gas atmosphere (e.g., using one or more of the gases described herein), pressure, and moisture can be used to alter the composition of both the unexposed and exposed photoresists. In some cases, the treatment can preferentially change the composition and / or material properties of the exposed photoresist compared to the unexposed photoresist, such that the change in composition and / or material properties is greater in the exposed photoresist than in the unexposed photoresist. In some other cases, the treatment can preferentially change the composition / material properties of the unexposed photoresist compared to the exposed photoresist, such that the change in composition and / or material properties is greater in the unexposed photoresist than in the exposed photoresist. These preferential interactions can occur due to chemical changes that occur during EUV exposure, such as loss of alkyl groups in the photoresist. The changes that occur during treatment can increase the difference in composition / material properties between the unexposed and exposed photoresists, thereby increasing the difference in etch rates between the unexposed and exposed photoresists. This allows for higher etch selectivity (e.g., during dry development of a pattern in photoresist) to be achieved. Improved selectivity can result in squarer photoresist profiles with improved surface roughness and / or less photoresist residue / scum.

[0033] In either case, in alternative embodiments, the thermal process can be replaced or supplemented by a remote plasma process. The remote plasma process acts to increase reactive species, thereby lowering the energy barrier for the desired reaction and increasing productivity. The remote plasma generates more reactive radicals, and therefore can reduce the reaction temperature / time for the process (e.g., compared to processes that rely only on thermal energy), leading to increased productivity.

[0034] Thus, one or more processes can be applied to modify the photoresist itself, increasing the selectivity of the dry development. This thermal and / or radical modification can increase the contrast between the unexposed and exposed materials, thus increasing the selectivity of the subsequent dry development step. The resulting difference between the material properties of the unexposed and exposed materials can be adjusted by adjusting one or more process conditions, including temperature, gas flow, moisture, pressure, and / or RF power. The large process latitude enabled by dry development, which is not limited by material solubility in the wet development solvent, allows more aggressive conditions to be applied during processing, further enhancing the material contrast that can be achieved. The resulting high material contrast feeds back a wider process window for dry development, thus enabling increased productivity, reduced costs, and better defectivity performance.

[0035] A practical limitation of wet-developed resist films is the limited temperature bake. Wet development relies on the difference in material solubility between exposed and unexposed areas of the photoresist. Heating the photoresist to high temperatures can significantly increase the degree of crosslinking in both exposed and unexposed areas of the metal-containing photoresist film. When the photoresist is heated to a temperature of about 220°C or higher, both exposed and unexposed areas of the photoresist become insoluble in wet development solvents, and therefore the photoresist film cannot be reliably developed using wet development techniques.

[0036] In contrast, for dry-developed resist films, where the difference in dry etch rate between exposed and unexposed areas of the photoresist (i.e., selectivity) depends on the removal of only the exposed or unexposed portions of the resist, the processing temperature in PAB or PEB can be varied over a much wider window, since the limitations that apply to solubility in wet development solvents do not apply to dry etching techniques. Thus, for dry development, the processing process can be adjusted / optimized over a relatively wide temperature range. For example, the processing temperature can range from about 90°C to about 250°C, e.g., from about 90°C to about 190°C for PAB, and from about 150°C to about 250°C or higher for PEB. It has been found that a decrease in etch rate and an increase in etch selectivity occur at higher processing temperatures within the described ranges.

[0037] 7A-7D illustrate experimental results showing the improvement in material contrast and selectivity between unexposed and exposed portions of a photoresist layer that can be achieved by controlling the temperature during PEB. In each example, a substrate was exposed to a PEB where the temperature of the substrate was controlled (e.g., by controlling the temperature of the substrate support). The photoresist layer on each substrate was then developed using dry techniques to form a series of photoresist features on the substrate. In FIG. 7A, the temperature was controlled at about 235° C. In FIG. 7B, the temperature was controlled at about 220° C. In FIG. 7C, the temperature was controlled at about 205° C. In FIG. 7D, the temperature was controlled at about 190° C. At the lower processing temperatures, the photoresist profile exhibited significant tapered / rounded features. In contrast, at the higher processing temperatures, the photoresist profile was significantly improved, with features that were much less tapered / rounded and more squared off. Higher PEB temperatures result in greater material contrast between exposed and unexposed portions of the photoresist, thereby providing greater selectivity when the photoresist is developed. Additionally, substrates processed at higher PEB temperatures exhibit higher critical dimensions of lines after development, which corresponds to a lower dose to size. In other words, higher processing temperatures can be used to achieve desired critical dimensions with lower EUV radiation doses than would be required to achieve the same critical dimensions if the substrate were processed at a lower temperature (or not processed at all). As mentioned above, dry development techniques were used after PEB processing. In many cases, wet development techniques cannot develop photoresist layers that have been processed with PEB at high temperatures, e.g., >180° C., for the reasons mentioned above.

[0038] In certain embodiments, the PAB and / or PEB processes can be performed with a gas ambient flow in the range of 100-10,000 sccm. In these or other embodiments, the moisture content in the ambient environment can be controlled between about a few percent up to 100% (e.g., in some cases between about 20%-50%). In these or other embodiments, the pressure during the process can be controlled, for example, below atmospheric pressure (e.g., using a vacuum to achieve a subatmospheric pressure). In some cases, the pressure during the process can be about 0.1-760 Torr, for example, about 0.1-10 Torr, or in some cases about 0.1-1 Torr. In these or other embodiments, the duration of the process can be controlled to about 1-15 minutes, for example, about 2-5 minutes, or about 2 minutes.

[0039] These findings can be used to adjust process conditions and tailor or optimize the process for specific materials and circumstances. For example, the selectivity achieved for a given EUV dose by performing a PEB thermal treatment at 220°C-250°C for about 2 minutes in air with about 20% humidity can be similar to the selectivity for about 30% higher EUV doses without such thermal treatment. Thus, depending on the selectivity requirements / constraints of the semiconductor processing operation, thermal treatments as described herein can be used to lower the required EUV dose. Alternatively, if higher selectivity is required and a higher dose is tolerable, much higher selectivity can be obtained than with wet development (e.g., dry etch selectivity of up to 100:1 in exposed vs. unexposed areas of the photoresist). Remote plasma-based processing may provide the same or similar benefits.

[0040] 1 illustrates a process flow for a method of processing a semiconductor substrate, an embodiment of the present disclosure. The method 100 involves providing a metal-containing photoresist on a substrate layer of a semiconductor substrate in a process chamber in block 101. The substrate may be, for example, a partially fabricated semiconductor device film stack fabricated by any suitable method. In block 103, the metal-containing photoresist is treated to modify the material properties of the metal-containing photoresist to increase etch selectivity in a subsequent post-exposure dry development process. For example, the treatment may increase cross-linking in the metal-containing photoresist.

[0041] In some embodiments, the treatment may involve a thermal process that controls the temperature, gas atmosphere, and / or moisture. The gas atmosphere may be a mixture of reactive gas species, such as air, water (H2O), hydrogen (H2), oxygen (O2), ozone (O3), hydrogen peroxide (H2O2), carbon monoxide (CO), carbon dioxide (CO2), carbonyl sulfide (COS), sulfur dioxide (SO2), chlorine (Cl2), ammonia (NH3), nitrous oxide (NO), nitric oxide (NO), methane (CH4), methylamine (CH3NH2), dimethylamine ((CH3)2NH), trimethylamine (N(CH3)3), ethylamine (CH3CH2NH2), diethylamine ((CH3CH2)2NH), triethylamine (N(CH2CH3)3), pyridine (C5H5N), alcohol (C5H5N), or the like. n H 2n+1 OH, including but not limited to methanol, ethanol, propanol, and butanol), acetylacetone (CH3COCH2COCH3), formic acid (HCOOH), oxalyl chloride ((COCl)2), carboxylic acids (C n H 2n+1 COOH), and other low molecular weight amines (NR 1 R 2 R 3 , R 1 , R 2 , and R 3may include hydrogen, hydroxyl, aliphatic, haloaliphatic, haloheteroaliphatic, heteroaliphatic, aromatic, aliphatic-aromatic, heteroaliphatic-aromatic, or any combination thereof), etc. Substitutional forms of any of these reactive gases may also be used. In some cases, a substrate may be exposed to more than one reactive gas during a processing operation.

[0042] In embodiments where reactive gases are used to treat photoresist, the reactive gases may interact with the photoresist via oxidation, coordination, or acid / base chemistry.

[0043] In various embodiments, the gas atmosphere may include an inert gas, such as nitrogen (N2), argon (Ar), helium (He), neon (Ne), krypton (Kr), xenon (Xe), and the like. In some cases, the inert gas may be provided along with one or more of the reactive gases listed above. In other cases, the gas atmosphere may be inert or substantially inert. For example, the gas atmosphere may be free or substantially free of reactive gases. As used herein, a gas atmosphere may be considered to be substantially free of reactive gases if such gases are present only in trace amounts. In various cases where an inert atmosphere is used, the inert atmosphere can increase contrast in composition and / or material properties by reducing excess oxidation in relevant areas of the photoresist. For example, if the photoresist is heat treated in an inert atmosphere after exposing the photoresist to patterning radiation, the inert atmosphere promotes an increase in material contrast (e.g., composition and / or material properties) by reducing excess oxidation present in unexposed areas of the photoresist.

[0044] Any of the embodiments described herein may include a reduction step that may operate to reduce oxidized or over-oxidized regions of the photoresist. Such a reduction step may be particularly useful after a step of oxidizing the photoresist (or a portion thereof). In various embodiments, the reduction step may involve exposing the substrate to a reducing or inert atmosphere. In some cases, the reduction step may involve heating the substrate and / or exposing the substrate to a plasma. The plasma may be generated from an inert gas and / or a reducing gas.

[0045] In various embodiments, as illustrated in FIG. 2, a treatment may be applied after the photoresist 202a is applied to the substrate 201 and before the photoresist 202a is exposed to patterning radiation. For example, in one example where the treatment is a thermal treatment, the treatment may be referred to as a post-apply bake (PAB). The treatment modifies the photoresist 202a to form a modified version of the photoresist 202b. Compared to the photoresist 202a before the treatment, the modified version of the photoresist 202b exhibits improved properties. For example, the modified version of the photoresist 202b may be more sensitive to EUV radiation than the unmodified version of the photoresist 202a. As a result of this increased EUV sensitivity, the modified version of the photoresist may exhibit a lower dose to size during EUV exposure and result in lower line edge roughness after development.

[0046] The treatments may be performed at different times. In various embodiments, as illustrated in FIG. 3, the treatment may be applied after the photoresist 302a is deposited and patterned by partial exposure to radiation (e.g., EUV), such that the treated substrate includes both exposed and unexposed portions 302c and 302b of the EUV photoresist. For example, in one example where the treatment is a thermal treatment, the treatment may be referred to as a post-exposure bake (PEB). The treatment may modify both exposed and unexposed portions 302c and 302b of the EUV photoresist, thereby forming modified versions of exposed and unexposed portions 302e and 302d. The modification caused by the treatment may increase the etch rate of the photoresist material in the dry development etching gas. Alternatively or additionally, the modification caused by the treatment may increase the difference in composition / material properties between the unexposed and exposed portions of the photoresist. In other words, the difference between the composition / material properties of (1) the modified version of the unexposed portion 302d of the photoresist after processing compared to (2) the modified version of the exposed portion 302e of the photoresist after processing is greater than the difference between the composition / material properties of (1) the unexposed portion 302b of the photoresist before processing compared to (2) the exposed portion 302c of the photoresist before processing.

[0047] In addition, the rate of increase of bake temperature in either the PAB or PEB process is another useful process parameter that can be manipulated to fine-tune the crosslinking / etch selectivity results. The PAB and PEB thermal processes can be performed in either a single run or multiple runs. When multiple runs are used, different process conditions may be provided during the individual runs. Exemplary process conditions that can be varied between individual runs include, but are not limited to, the identity and concentration of the atmospheric gas or mixture adjacent to the substrate, moisture level, temperature, pressure, etc. These process conditions can be controlled to tune the photoresist properties and therefore the different etch selectivities.

[0048] In alternative embodiments, either or both of the post-coating and post-exposure treatments may involve a remote plasma process, along with or instead of a thermal treatment, to generate radicals to react with the metal-containing photoresist, thereby modifying its material properties. With reference to FIG. 2, in some embodiments, the remote plasma treatment process occurs after the photoresist 202a is deposited and before it is exposed to EUV radiation. In this case, the treatment may be referred to as a post-coating plasma treatment. With reference to FIG. 3, in some embodiments, the remote plasma treatment process occurs after the photoresist 302a is deposited and exposed to EUV radiation to form exposed and unexposed portions 302c and 302b. In this case, the treatment may be referred to as a post-exposure plasma treatment.

[0049] In embodiments where a remote plasma is used to treat the photoresist, the radicals may be generated from the same or different gas species as described herein with respect to the thermal treatment.

[0050] In some embodiments, multiple treatments may be used. For example, a first treatment may occur after photoresist deposition and before EUV exposure (as shown in FIG. 2), and a second treatment may occur after EUV exposure and before development (as shown in FIG. 3). One or more of the treatment conditions may be controlled as described herein during the first treatment and / or the second treatment.

[0051] Multi-step post-exposure processing of metal-containing resists PEB processes are often performed to further increase the contrast in etch selectivity between exposed and unexposed portions of the metal-containing photoresist after exposure (e.g., EUV exposure). For example, the metal-containing photoresist can be heat treated in the presence of chemical species to promote crosslinking in the EUV-exposed portions. In the case of tin oxide photoresists, this is designed to drive the evaporation of organic fragments generated during EUV exposure, oxidize any Sn-H, Sn-Sn, or Sn radical species generated by the EUV exposure to metal hydroxides, and promote crosslinking between adjacent Sn-OH groups to form a more densely crosslinked SnO2-like network. However, if the temperature is too high in the presence of an oxidizing atmosphere, the EUV-unexposed portions of the metal-containing photoresist will become over-oxidized. Over-oxidation reduces material contrast, increases roughness, and increases defects in the subsequent dry development process. If the temperature is too low in the presence of an oxidizing atmosphere, the EUV-exposed portions of the metal-containing photoresist will not crosslink sufficiently. As a result, there is insufficient material contrast during exposure to the dry development etch gases. When the PEB process is performed in an inert atmosphere at high temperatures, the EUV-exposed portions of the metal-containing photoresist cannot receive enough oxygen. Less oxygen in the EUV-exposed portions leads to less crosslinking, making the EUV-exposed portions softer and less dense. The softer resist further increases roughness, which causes even larger pattern deformations (e.g., line wobble) and defects.

[0052] In the present disclosure, the photoresist on the substrate can be subjected to multiple PEB treatments or multiple steps in a PEB treatment process. The multiple bake steps may be performed at different temperatures and / or with different chemicals. The first bake step can be performed at a moderately elevated bake temperature in an oxygen-rich environment. The second bake step can be performed at a highly elevated bake temperature that is higher than the moderately elevated bake temperature and in an inert environment. In some embodiments, the moderately elevated bake temperature can be from about 150° C. to about 220° C., and the highly elevated bake temperature can be from about 220° C. to about 250° C. By sequentially exposing the metal-containing photoresist to a first bake step and a second bake step, material contrast is improved and higher etch selectivity is achieved during dry development.

[0053] 4 provides a flow chart for a method of processing a substrate in a multi-step post-exposure bake process according to various embodiments. The operations of process 400 may be performed in a different order and / or with a different, fewer, or additional number of operations. One or more operations of process 400 may be performed using an apparatus as described in any one of FIGS. 5A, 5B, and 6. In some embodiments, the operations of process 400 may be implemented, at least in part, according to software stored on one or more non-transitory computer-readable media.

[0054] In block 401 of process 400, a substrate is provided in a process chamber, the substrate being a semiconductor substrate having a metal-containing photoresist on a substrate layer of the semiconductor substrate. In some implementations, the substrate layer is a layer to be etched, the substrate layer may include spin-on carbon (SoC), spin-on glass (SOG), amorphous carbon, silicon, silicon oxide, silicon nitride, silicon carbide, or silicon oxynitride. The metal-containing photoresist may be dry or wet deposited on the substrate layer. The metal-containing photoresist may be provided as a positive or negative resist having EUV exposed and non-EUV exposed regions after EUV exposure. After exposure and optional PEB treatment, the metal-containing photoresist may undergo development to selectively remove portions of the metal-containing photoresist (e.g., non-EUV exposed portions) to form a patterned mask on the substrate layer. In some implementations, the metal-containing photoresist is a metal-containing EUV photoresist, the metal-containing EUV photoresist is an organometallic oxide or organometallic containing film. For example, a metal-containing EUV photoresist may contain Sn, O, and C atoms.

[0055] In some embodiments, the process 400 further includes exposing a metal-containing EUV photoresist to EUV radiation before placing the substrate in the process chamber to form EUV exposed and non-EUV exposed regions. After wet or dry deposition of the metal-containing photoresist, the metal-containing photoresist can be photopatterned in an EUV lithography chamber (scanner) or module. The metal-containing photoresist can be an EUV-sensitive metal or metal oxide-containing film, such as an organotin oxide. The EUV-sensitive metal or metal oxide-containing film can be directly photopatterned by EUV exposure in a vacuum atmosphere.

[0056] After photopatterning the metal-containing photoresist, the metal-containing photoresist is thermally treated or baked in a post-exposure bake (PEB) operation. This creates a greater chemical contrast for development. Rather than performing a single bake operation, the PEB process may proceed in two or multiple steps of bake operations, with each step exposing the metal-containing photoresist to different processing conditions. Such processing conditions may include, but are not limited to, the identity and concentration of the atmospheric gas or mixture proximate the substrate, moisture level, temperature, pressure, etc. One of the steps may expose the substrate to at least a different temperature and a different atmospheric gas. For example, one of the bake steps may expose the substrate to a low temperature or a moderately elevated temperature in an oxidizing atmosphere, while another of the bake steps may expose the substrate to a highly elevated temperature in a non-oxidizing atmosphere. These steps may be performed in sequence as shown in blocks 403 and 405 below.

[0057] In block 403 of the process 400, the metal-containing photoresist is exposed to a first elevated temperature in an oxygen-containing environment in a process chamber. The first elevated temperature provides a low to medium bake. The low to medium bake can prevent over-oxidation of the non-exposed portions of the metal-containing photoresist. In some embodiments, the first elevated temperature is about 150° C. to about 220° C., or about 180° C. to about 220° C. The oxygen-containing environment can promote oxygen incorporation into the exposed portions of the metal-containing photoresist. Generally, the higher the oxygen concentration, the higher the oxygen incorporation. In some embodiments, the oxygen-containing environment includes an oxygen-containing species or oxidizing agent. The oxygen partial pressure in the oxygen-containing environment can be at least about 100 Torr, such as about 100 Torr to about 600 Torr. Depending on the oxygen partial pressure, the oxidizing agent can occupy a certain concentration of the total gas concentration. In some embodiments, the concentration of the oxidizing agent can be at least 20% by volume in the oxygen-containing environment. For example, the concentration of the oxidizing agent may be about 25% to about 100% by volume, or about 50% to about 100% by volume. In some embodiments, the oxygen-containing environment includes oxygen (O2), ozone (O3), water (H2O), hydrogen peroxide (H2O2), carbon monoxide (CO), carbon dioxide (CO2), or a combination thereof.

[0058] High bake temperatures generally increase the material contrast between exposed and unexposed portions of the metal-containing photoresist. However, if the bake temperature is too high, over-oxidation of the unexposed portions of the metal-containing photoresist occurs. Without being limited by any theory regarding organometallic-containing films, cleavage of metal-carbon bonds can occur at excessively high bake temperatures, leaving metal hydride sites that can be converted to metal hydroxides in the presence of an oxygen-containing environment. The metal hydroxides may crosslink to form metal oxide moieties. As a result, the unexposed and exposed portions of the metal-containing photoresist are less differentiated in terms of chemical structure, which reduces the etch contrast during the subsequent dry development process. The reduced etch contrast can be attributed to increased line CD variation, photoresist corner rounding, and increased dose to size. In addition, the reduced etch contrast due to over-oxidation can be attributed to poor pattern development, increased likelihood of residue formation in unexposed portions, increased line edge roughness, and line bridging, which further increases the defect rate in the patterned photoresist. Therefore, it is desirable to limit the bake temperature in an oxygen-containing environment to a low or moderate bake temperature (eg, less than about 220° C.) that prevents excessive oxidation of the unexposed portions of the metal-containing photoresist.

[0059] The presence of oxygen-containing species (e.g., O2, O3, etc.) generally results in increased material contrast between exposed and unexposed portions of the metal-containing photoresist. An oxygen-rich bake increases the partial pressure of the oxygen-containing species, which reduces the temperature required to incorporate the same amount of oxygen into the exposed portions of the metal-containing photoresist. Operating at a lower temperature prevents over-oxidation of the unexposed portions of the metal-containing photoresist. The oxygen-containing species promotes cross-linking in the exposed portions of the metal-containing photoresist. Without being limited by any theory, oxygen bonds to metal hydride sites to form metal hydroxides. The metal hydroxides (e.g., Sn-OH) form cross-links to produce metal oxide moieties (e.g., Sn-O-Sn) and water (H2O). A more densely cross-linked metal oxide network provides greater etch contrast between exposed and unexposed portions of the metal-containing photoresist. The increased etch contrast increases etch selectivity, which reduces line CD variation, makes the photoresist profile more square, and reduces dose to size. Furthermore, increased etch contrast improves pattern development, reduces the likelihood of residue formation in unexposed areas, reduces line edge roughness, and reduces defectivity.

[0060] The duration of exposure to the first elevated temperature in the oxygen-containing environment can be adjusted to optimize the PEB process. In some embodiments, the duration of exposure can be from about 30 seconds to about 10 minutes, or from about 1 minute to about 5 minutes. Increasing the exposure time can allow more oxygen to be incorporated into the exposed portions of the metal-containing photoresist, improving material contrast. Conversely, too long an exposure time can cause over-oxidation of the unexposed portions of the metal-containing photoresist.

[0061] The pressure in the process chamber can be controlled during exposure to the oxygen-containing environment to optimize the PEB process. Specifically, the partial pressure of the oxygen-containing species can be adjusted to incorporate a desired amount of oxygen into the exposed portion of the metal-containing photoresist. For example, the partial pressure of the oxygen-containing species can be from about 10 Torr to about 760 Torr, at least about 100 Torr, or from about 100 Torr to about 600 Torr. The oxygen-containing species can be flowed into the process chamber with a balance of inert gas. In some embodiments, the concentration of the oxygen-containing species can be at least 20% by volume and up to 100% by volume. In some cases, the partial pressure of the oxygen-containing species can control the PEB process performance regardless of the total chamber pressure. As an example, a chamber pressure of 600 Torr with an oxygen concentration of 20% by volume can result in the same PEB process performance as a chamber pressure of 120 Torr with an oxygen concentration of 100% by volume.

[0062] The moisture level in the process chamber can be adjusted during exposure to the oxygen-containing environment to optimize the PEB process. In some cases, increased moisture results in reduced line CD or other adverse consequences. Without being limited by any theory, increased humidity levels inhibit crosslinking of exposed portions of the metal-containing photoresist, thereby reducing material contrast. Thus, the moisture level in the process chamber is minimized. In some embodiments, the process chamber is moisture-free or substantially moisture-free.

[0063] The waiting time between the exposure of the metal-containing photoresist for photopatterning and the exposure of the metal-containing photoresist to the oxygen-containing environment can be minimized to optimize the PEB process. Longer waiting times result in higher dose to size and increased roughness. Therefore, it is desirable to have as short a waiting time as possible between the EUV exposure in the oxygen-containing environment and the PEB process. For example, the waiting time between the EUV exposure in the oxygen-containing environment and the PEB process is less than about 3 hours, less than about 2 hours, less than about 1 hour, less than about 20 minutes, or less than about 10 minutes.

[0064] In some embodiments, the low to medium bake (i.e., the first high temperature) can be replaced or supplemented with a remote plasma. The remote plasma can be used to increase oxygen radicals and increase productivity. The oxygen radicals provide reactive species for incorporation into exposed portions of the metal-containing photoresist. The oxygen radicals can be generated in a remote plasma source and delivered to the substrate in the process chamber.

[0065] The process chamber may include one or more heaters for temperature control. In some implementations, the one or more heaters may be coupled to a heating assembly facing the substrate in the process chamber for substrate temperature control. For example, the heating assembly may be positioned below the substrate support or between the substrate support and the substrate. In some embodiments, the substrate temperature may be controlled using a radiative heating assembly, such as an IR lamp or one or more LEDs.

[0066] In block 405 of process 400, the metal-containing photoresist is exposed to a second elevated temperature in an inert gas environment, the second elevated temperature being higher than the first elevated temperature. The exposure to the inert gas environment may occur in the same process chamber as the exposure to the oxygen-containing environment or in a different process chamber. The second elevated temperature enables a high temperature bake. The high temperature bake provides sufficient thermal energy to promote crosslinking in the exposed portions of the metal-containing photoresist. In some embodiments, the second elevated temperature is from about 220° C. to about 300° C., or from about 220° C. to about 250° C. The inert gas environment is free of oxygen-containing species or is substantially free of oxygen-containing species to avoid excessive oxidation of the unexposed portions of the metal-containing photoresist. In some embodiments, the inert gas environment includes nitrogen (N2), helium (He), neon (Ne), argon (Ar), krypton (Kr), xenon (Xe), or a combination thereof.

[0067] Exposure to an inert gas environment at a second elevated temperature (also referred to as the "second bake") follows exposure to an oxygen-containing environment at a first elevated temperature (also referred to as the "first bake"). The first bake incorporates oxygen into the exposed portions while preventing over-oxidation in the non-exposed portions of the metal-containing photoresist. The second bake, performed in the inert gas environment, promotes reaction between the incorporated oxygen and the metal centers in the exposed portions of the metal-containing photoresist, thereby promoting cross-linking to form a more densely cross-linked metal oxide network. Additionally, the inert gas environment prevents over-oxidation in the non-exposed portions of the metal-containing photoresist. The second bake increases the difference between the non-exposed and exposed portions of the metal-containing photoresist, increasing the etch contrast during the subsequent dry development process. The increased etch contrast and dry development selectivity feed back the process window width for dry development, which can improve productivity, cost reduction, lower dose to size, and better defectivity performance.

[0068] In some implementations, the process 400 further includes repeating the first bake and the second bake multiple times. Multiple cycles of the first bake and the second bake can further increase the etch contrast.

[0069] The duration of exposure to the second elevated temperature in the inert gas environment can be adjusted to optimize the PEB process. In some embodiments, the duration of exposure can be from about 30 seconds to about 10 minutes, or from about 1 minute to about 5 minutes. A longer exposure time allows more crosslinking in the exposed portions of the metal-containing photoresist, improving material contrast. However, if the exposure time is too long, a crosslinked metal oxide network may eventually form in the unexposed portions of the metal-containing photoresist.

[0070] The inert gas environment can be controlled to minimize the amount of reactive species. The concentration of reactive species, including oxygen-containing species, in the inert gas environment can be limited to avoid over-oxidation. The oxygen partial pressure can be about 20 Torr or less, about 10 Torr or less, or about 5 Torr or less. In some embodiments, the concentration of oxygen-containing species is about 10% by volume or less, about 5% by volume or less, about 1% by volume or less, or about 0.5% by volume or less. The reactive species may be present in trace amounts compared to the inert gas species in the inert gas environment.

[0071] The moisture level in the process chamber can be adjusted during exposure to the inert gas environment to optimize the PEB process. As mentioned above, increased humidity can lead to reduced etch contrast. Therefore, the process chamber for performing the second bake can be moisture-free or substantially moisture-free.

[0072] It is possible to optimize the PEB process by minimizing the wait time between exposure of the metal-containing photoresist to an oxygen-containing environment and exposure of the metal-containing photoresist to an inert gas environment. Longer wait times increase line CD and increase roughness. Dose to size is less sensitive to long wait times. Nevertheless, short wait times between the first and second bakes are generally desirable. For example, the wait time between the first and second bakes is less than about 3 hours, less than about 2 hours, less than about 1 hour, less than about 20 minutes, or less than about 10 minutes.

[0073] Overall, performing a sequence of a first bake followed by a second bake improves PEB processing performance compared to a single bake operation. Performing a first bake and a second bake improves the etch contrast and improves the etch selectivity between EUV exposed and non-EUV exposed portions in the subsequent dry development process. Additionally, performing a first bake and a second bake can reduce line edge roughness and reduce dose to size in the subsequent dry development process.

[0074] Device 5A and 5B illustrate schematic diagrams of different embodiments of process stations that may be used to perform the processes described herein. The process station 580 shown in FIG. 5A may be used for thermal-based processes, such as post-apply bake or post-exposure bake. The process station 500 shown in FIG. 5B may be used for thermal-based processes, remote plasma processes, or both. These processes may include post-apply processes as well as post-exposure processes. These processes may further include multi-step post-exposure processes as described above. The process stations shown in FIG. 5A and 5B may also be used for other processes described herein. For steps that require plasma, the process station 500 in FIG. 5B may be used. For steps that do not require plasma, either the process station 500 in FIG. 5B or the process station 580 in FIG. 5A may be used.

[0075] FIG. 5A presents a simplified diagram of a processing chamber 580 according to one embodiment. In this example, the processing chamber 580 is an enclosed chamber with a controllable atmosphere. A substrate 581 can be positioned on a substrate support 582, which can also heat and / or cool the substrate. In some cases, alternative or additional heating and cooling elements may be provided. Processing gases enter the processing chamber 580 through an inlet 583. Materials are removed from the processing chamber 580 through an outlet 584, which can be connected to a vacuum source (not shown). The operation of the processing chamber 580 can be controlled by a controller 586, which is described further below. Additionally, a sensor 585 can be provided, for example, to monitor the temperature and / or composition of the atmosphere within the processing chamber 580. Readings from the sensor 585 can be used by the controller 586 in an active feedback loop. In various embodiments, the processing chamber 580 can be modified by including a remote plasma chamber (not shown) in fluid communication with the processing chamber 580. In such a case, the plasma may be generated in a remote plasma chamber before being delivered to the processing chamber 580.

[0076] The chamber in which the processing takes place can be configured in a number of ways. In some embodiments, the chamber is the same chamber used to deposit the photoresist, and / or the same chamber used to expose the photoresist to EUV radiation, and / or the same chamber used to develop the photoresist. In some embodiments, the chamber is a dedicated bake or remote plasma processing chamber that is not used for other processes such as deposition, etching, EUV exposure, or photoresist development. The chamber may be a standalone chamber or may be integrated into a larger processing tool, such as a deposition tool used to deposit the photoresist, an EUV exposure tool used to expose the photoresist to EUV radiation, and / or a development tool used to develop the photoresist. The chamber used to process the photoresist can be combined with any one or more of these tools, for example in a cluster tool, as desired for a particular application. In some cases, the chamber may be provided in a common low pressure process tool environment that provides low pressure for multiple chambers.

[0077] 5B illustrates generally a cross-sectional view of an inductively coupled plasma apparatus 500 suitable for performing certain embodiments or aspects of embodiments, such as gas phase (dry) deposition, thermal treatment as described herein, plasma treatment as described herein, dry development, and / or etching, an example of which is the Kiyo® reactor manufactured by Lam Research, Inc. of Fremont, Calif. In other embodiments, other tools or tool types capable of performing one or more operations of the dry deposition, treatment (thermal or remote plasma), development, and / or etching processes described herein may be performed using other tools or tool types.

[0078] The inductively coupled plasma apparatus 500 includes an overall process chamber 524 structurally defined by a chamber wall 501 and a window 511. The chamber wall 501 can be fabricated from stainless steel or aluminum. The window 511 can be fabricated from quartz or other dielectric materials. An optional internal plasma grid 550 divides the overall process chamber into an upper subchamber 502 and a lower subchamber 503. In certain embodiments, the plasma grid 550 can be removed, thereby utilizing the chamber space created in the subchambers 502 and 503. Where the plasma grid 550 is present, the plasma grid 550 can be used to shield the substrate from the plasma generated directly in the upper subchamber 502, such that the substrate is treated with a remote plasma in the lower subchamber 503. In this example, the plasma present in the lower subchamber 503 can be considered a remote plasma because it is initially generated at a location (e.g., the upper subchamber 502) upstream of the location (e.g., the lower subchamber 503) where the substrate is treated with the plasma.

[0079] A chuck 517 is positioned within the lower sub-chamber 503 near the bottom inner surface. The chuck 517 is configured to receive and hold a semiconductor wafer 519 on which etching and deposition processes are performed. The chuck 517, if present, may be an electrostatic chuck for supporting the wafer 519. In some embodiments, an edge ring (not shown) surrounds the chuck 517 and has a top surface that is approximately planar with a top surface of the wafer 519, if present on the chuck 517. The chuck 517 also includes an electrostatic electrode for chucking and dechucking the wafer 519. For this purpose, a filter and DC clamp power supply (not shown) may be provided. Other control systems for lifting the wafer 519 from the chuck 517 may also be provided. The chuck 517 may be charged using an RF power supply 523. The RF power supply 523 is connected to a matching circuit 521 through connection 527. The matching circuit 521 is connected to the chuck 517 through connection 525. In this manner, the RF power supply 523 is connected to the chuck 517. In various embodiments, the bias power of the electrostatic chuck may be set to about 50 V, or may be set to different bias powers depending on the process being performed according to the disclosed embodiments. For example, the bias power may be from about 20 V to about 100 V, or from about 30 V to about 150 V.

[0080] The elements for plasma generation include a coil 533 positioned over the window 511. In some embodiments, a coil is not used. In some such embodiments, an alternative mechanism for generating the plasma may be provided, for example to provide a capacitively coupled plasma, a microwave plasma, or the like. If an inductively coupled plasma is used, the coil 533 is fabricated from a conductive material and includes at least one complete turn. The example coil 533 shown in FIG. 5B includes three turns. A cross section of the coil 533 is shown symbolically, with the coil having an "X" rotating and extending into the page, while the coil having a "●" rotating and extending out of the page. The elements for plasma generation also include an RF power source 541 configured to provide RF power to the coil 533. Generally, the RF power source 541 is connected to a matching circuit 539 through connection 545. The matching circuit 539 is connected to the coil 533 through connection 543. In this manner, the RF power source 541 is connected to the coil 533.

[0081] An optional Faraday shield 549a is positioned between the coil 533 and the window 511. The Faraday shield 549a can be maintained in a spaced apart relationship to the coil 533. In some embodiments, the Faraday shield 549a is disposed directly above the window 511. In some embodiments, the Faraday shield 549b is between the window 511 and the chuck 517. In some embodiments, the Faraday shield 549b is not maintained in a spaced apart relationship to the coil 533. For example, the Faraday shield 549b can be directly below the window 511 with no gap. The coil 533, the Faraday shield 549a, and the window 511 are each configured to be substantially parallel to one another. The Faraday shield 549a can prevent metals or other species from depositing on the window 511 of the process chamber 524.

[0082] Process gases can enter the process chamber through one or more main gas inlets 560 and / or one or more side gas inlets 570 positioned in the upper subchamber 502. Similarly, similar gas inlets, not explicitly shown, can be used to supply process gases to the capacitively coupled plasma processing chamber. A vacuum pump, e.g., a one or two stage mechanical dry pump and / or turbomolecular pump 540, can be used to draw process gases from the process chamber 524 and maintain pressure within the process chamber 524. For example, the vacuum pump can be used to evacuate the overall process chamber 524 or the lower subchamber 503 during a purge operation. A valve controlled conduit can be used to fluidly connect the vacuum pump to the process chamber 524 to selectively control application of the vacuum environment provided by the vacuum pump. This can be done with a closed loop controlled flow restriction device, such as a throttle valve (not shown) or a pendulum valve (not shown), during plasma processing operations. Similarly, a vacuum pump and a valve controlled fluid connection to the capacitively coupled plasma processing chamber can also be used.

[0083] During operation of the apparatus 500, one or more process gases may be supplied through the gas inlets 560 and / or 570. In certain embodiments, the process gases may be supplied only through the main gas inlet 560 or only through the side gas inlet 570. In some cases, the gas inlets shown in the figure may be replaced by more complex gas inlets, such as one or more showerheads. The Faraday shield 549a and / or the optional grid 550 may include internal channels and holes that allow delivery of process gases 524 to the process chamber. Either or both of the Faraday shield 549a and the optional grid 550 may function as a showerhead for delivering process gases. In some embodiments, a liquid vaporization and delivery system may be located upstream of the process chamber 524, whereby once the liquid reactants or precursors are vaporized, the vaporized reactants or precursors are introduced into the process chamber 524 via the gas inlets 560 and / or 570.

[0084] In some embodiments, a remote plasma generating unit may be provided upstream of the process chamber 524, and radicals formed by the remote plasma may be supplied to the process chamber via gas inlets 560 and / or 570.

[0085] Radio frequency power is supplied from RF power supply 541 to coil 533, causing an RF current to flow through coil 533. The RF current flowing through coil 533 generates an electromagnetic field around coil 533. The electromagnetic field generates an induced current in upper subchamber 502. Physical and chemical interactions of the various generated ions and radicals with wafer 519 etch features in wafer 519 and selectively deposit layers on wafer 519.

[0086] When a plasma grid 550 is used such that both an upper subchamber 502 and a lower subchamber 503 are present, induced currents act on the gas present in the upper subchamber 502 to generate an electron-ion plasma in the upper subchamber 502. The optional internal plasma grid 550 limits the number of thermal electrons in the lower subchamber 503. In some embodiments, the apparatus 500 is designed and operated such that the plasma present in the lower subchamber 503 is an ion-ion plasma.

[0087] Both the upper electron-ion plasma and the lower ion-ion plasma can contain positive and negative ions, but the ion-ion plasma has a greater ratio of negative ions to positive ions. Volatile etch and / or deposition byproducts can be removed from the lower subchamber 503 through port 522. The chuck 517 disclosed herein can operate at high temperatures ranging from about 10° C. to about 250° C. or higher. The temperature depends on the process operation and the particular recipe.

[0088] The apparatus 500 may be coupled to equipment (not shown) when installed in a clean room or fabrication facility. The equipment includes plumbing to provide process gases, vacuum, temperature control, and environmental particle control. These equipment will be coupled to the apparatus 500 when installed in the intended fabrication facility. Additionally, the apparatus 500 may be coupled to a transfer chamber that allows a robot to move semiconductor wafers in and out of the apparatus 500 using typical automated operations.

[0089] In some embodiments, a system controller 530 (which may include one or more physical or logical controllers) controls some or all of the operation of the process chamber 524. The system controller 530 may include one or more memory devices and one or more processors. In some embodiments, the apparatus 500 includes a switching system for controlling flow rates and durations when the disclosed embodiments are implemented. In some embodiments, the apparatus 500 may have a switching time of up to about 500 ms, or up to about 750 ms. The switching time may depend on the flowing chemistry, the selected recipe, the reactor architecture, and other factors.

[0090] In some implementations, the system controller 530 is part of a system, such a system may be part of the examples described above. Such a system may include semiconductor processing equipment, including one or more processing tools, one or more chambers, one or more processing platforms, and / or specific processing components (wafer pedestals, gas flow systems, etc.). These systems may be integrated with electronics for controlling system operations before, during, and after processing of a semiconductor wafer or substrate. Such electronics may be integrated into the system controller 530 and control various components or subparts of the system or systems. The system controller 530 may be programmed to control any of the processes disclosed herein depending on the processing parameters and / or type of system. Such processes may include delivery of process gases, temperature settings (e.g., heating and / or cooling), pressure settings, vacuum settings, power settings, radio frequency (RF) generator settings, RF matching circuit settings, frequency settings, flow rate settings, fluid delivery settings, position and motion settings, wafer loading and unloading from tools and other transfer tools connected or interlocked with the particular system, and / or wafer loading and unloading from load locks.

[0091] Broadly, the system controller 530 may be defined as electronic equipment having various integrated circuits, logic, memory, and / or software that receive instructions, issue instructions, control operations, enable cleaning operations, enable endpoint measurements, etc. The integrated circuits may include chips in the form of firmware that store program instructions, digital signal processors (DSPs), chips defined as application specific integrated circuits (ASICs), and / or one or more microprocessors, i.e., microcontrollers that execute program instructions (e.g., software). The program instructions may be instructions communicated to the controller in the form of various individual settings (or program files) that define operational parameters for performing a particular process on or for a semiconductor wafer or for a system. The operational parameters may, in some embodiments, be part of a recipe defined by a process engineer to accomplish one or more processing steps in the fabrication or removal of one or more layers, materials, metals, oxides, silicon, silicon dioxide, surfaces, circuits, and / or wafer dies.

[0092] The system controller 530 may, in some embodiments, be part of, or coupled to, a computer that is integrated or coupled with the system or otherwise networked to the system, or a combination thereof. For example, the controller may be in the "cloud" or all or part of a fab host computer system. This allows for remote access of wafer processing. The computer may allow remote access to the system to monitor the current progress of a fabrication operation, review the history of past fabrication operations, review trends or performance criteria from multiple fabrication operations, modify parameters of a current process, set processing steps following a current process, or start a new process. In some examples, a remote computer (e.g., a server) may provide process recipes to the system over a network. Such a network may include a local network or the Internet. The remote computer may include a user interface that allows entry or programming of parameters and / or settings, which are then communicated from the remote computer to the system. In some examples, the system controller 530 receives instructions in the form of data. Such data identifies parameters for each processing step performed during one or more operations. It should be understood that the parameters may be specific to the type of process being performed and the type of tool that the controller is configured to interface with or control. Thus, as described above, the system controller 530 may be distributed, for example, by including one or more individual controllers that are networked together and cooperate toward a common purpose (such as the processes and controls described herein).An example of a distributed controller for such purposes would include one or more integrated circuits on the chamber that communicate with one or more integrated circuits located remotely (e.g., at the platform level or as part of a remote computer) and coupled to control the process in the chamber.

[0093] Exemplary systems may include, but are not limited to, a plasma etch chamber or module, a deposition chamber or module, a spin rinse chamber or module, a metal plating chamber or module, a cleaning chamber or module, a bevel edge etch chamber or module, a physical vapor deposition (PVD) chamber or module, a chemical vapor deposition (e.g., PECVD) chamber or module, an ALD chamber or module, an ALE chamber or module, an ion implantation chamber or module, a tracking chamber or module, an EUV lithography chamber (scanner) or module, a dry development chamber or module, and any other semiconductor processing system that may be associated with or used in the fabrication and / or manufacturing of semiconductor wafers.

[0094] As described above, depending on the process step or steps being performed by the tool, the controller may communicate with one or more other tool circuits or modules, other tool components, cluster tools, other tool interfaces, adjacent tools, nearby tools, tools located throughout the factory, a main computer, another controller, or tools used for material transport to and from tool locations and / or load ports within a semiconductor manufacturing factory.

[0095] EUVL patterning can be performed using any suitable tool, often referred to as a scanner, such as the TWINSCAN NXE:3300B® platform supplied by ASML, Veldhoven, The Netherlands). The EUVL patterning tool may be a standalone device from which substrates are loaded and unloaded for deposition and etching as described herein. Or, as described below, the EUVL patterning tool may be a module on a larger multi-component tool. FIG. 6 illustrates a semiconductor process cluster tool architecture having a vacuum integrated deposition, EUV patterning, and dry develop / etch module in conjunction with a vacuum transfer module suitable for carrying out the processes described herein. The processes can be performed without such vacuum integrated equipment, although such equipment may be advantageous in some embodiments.

[0096] 6 illustrates a semiconductor process cluster tool architecture having a vacuum integrated deposition and patterning module suitable for implementing embodiments described herein. Such a cluster process tool architecture may include a PR and underlayer deposition module, a resist exposure (EUV scanner) module, and / or a resist dry develop and etch module, as described herein. In some embodiments, one or more hardware parameters of the process stations (including those described in detail herein) may be programmatically adjusted by one or more computer controllers.

[0097] In some embodiments, some of the processing functions, such as vapor deposition, treatment, exposure, and / or dry development and etching of a resist film, can be performed sequentially in the same module. Thus, embodiments of the present disclosure are directed to an apparatus for processing a substrate, such as an apparatus for processing a metal-containing photoresist. The apparatus has a process chamber with a substrate support configured to support a semiconductor substrate having a substrate layer and a metal-containing photoresist positioned on the substrate layer. The apparatus can further include a process gas source connected to the process chamber and associated flow control hardware, thermal control hardware, substrate handling hardware connected to the process chamber, and a controller having a processor and a memory. In some implementations, the processor and memory are communicatively connected to each other, the processor is at least operatively connected to the flow control hardware and the substrate handling hardware, and the memory stores computer-executable instructions for performing operations in the method of fabricating a patterned structure described herein.

[0098] In some embodiments, a controller having a processor and a memory can be configured with computer-executable instructions to perform the following operations: exposing the metal-containing EUV photoresist to a first elevated temperature in an oxygen-containing environment in a process chamber, and exposing the metal-containing EUV photoresist to a second elevated temperature in an inert gas environment, the second elevated temperature being higher than the first elevated temperature. In some embodiments, the first elevated temperature is between about 150° C. and about 220° C., and the second elevated temperature is between about 220° C. and about 250° C.

[0099] As mentioned above, FIG. 6 illustrates a semiconductor process cluster tool architecture having a vacuum integrated deposition and patterning module in conjunction with a vacuum transfer module suitable for carrying out the processes described herein. The arrangement of transfer modules to "transfer" wafers between multiple storage facilities and processing modules is sometimes referred to as a "cluster tool architecture" system. The deposition and patterning modules are vacuum integrated according to the requirements of a particular process. Other modules, such as for etching, can also be included in the cluster. The processing steps described herein may be carried out in any one or more of these modules, or in separate modules dedicated to such processing.

[0100] A vacuum transport module (VTM) 638 interfaces with four processing modules 620a-620d, which can be individually optimized to perform various fabrication processes. By way of example, processing modules 620a-620d can be implemented to perform deposition, evaporation, thermal and / or plasma treatment, electroless deposition, dry development, etching, strip, and / or other semiconductor processes. For example, module 620a can be an ALD reactor that can operate to perform non-plasma thermal atomic layer deposition and form metal-containing photoresist or other materials described herein. In one example, module 620a is a Vector® tool available from Lam Research, Inc. of Fremont, Calif. In these or other embodiments, module 620b can be a plasma enhanced chemical vapor deposition (PECVD) tool, such as a Lam Vector®. It should be understood that the figures are not necessarily drawn to scale.

[0101] Airlocks 642 and 646, also known as loadlocks or transfer modules, interface with the VTM 638 and the patterning module 640. For example, as mentioned above, a suitable patterning module could be a TWINSCAN NXE:3300B® platform supplied by ASML, Veldhoven, The Netherlands). This tool architecture allows workpieces such as semiconductor substrates or wafers to be transferred under vacuum so that they do not react before exposure. The integration of the deposition module with the lithography tool is facilitated by the fact that EUV lithography also requires significantly reduced pressures, given the strong optical absorption of incident photons by atmospheric gases such as H2O, O2, etc.

[0102] As mentioned above, this integrated architecture is only one possible embodiment of a tool for carrying out the described process. The process can also be carried out with more conventional standalone EUV lithography scanners and as a module, a deposition reactor such as the Lam Vector tool described with reference to FIG. 6 but without an integrated patterning module, either standalone or integrated in a cluster architecture with other tools such as etch, strip, etc. (e.g., Lam Kiyo or Gamma tools).

[0103] Airlock 642 may be an "out" load lock, referring to the transfer of substrates from the VTM 638 servicing deposition module 620a to the patterning module 640, and airlock 646 may be an "in" load lock, referring to the transfer of substrates from the patterning module 640 back to the VTM 638. The in load lock 646 may also provide interlocking to the outside of the tool for access and egress of substrates. Each process module has a facet that interlocks the module to the VTM 638. For example, deposition process module 620a has facet 636. Within each facet, sensors, such as sensors 1-18 shown, are used to detect the passage of wafer 626 as it moves between the respective stations. Patterning module 640 and airlocks 642 and 646 may similarly include additional facets and sensors not shown.

[0104] The main VTM robot 622 transfers wafers 626 between modules including airlocks 642 and 646. In one embodiment, the robot 622 has one arm, and in another embodiment, the robot 622 has two arms, each arm having an end effector 624 that lifts a wafer such as wafer 626 for transfer. A front-end robot 644 is used internally to transfer wafers 626 from the exit airlock 642 to the patterning module 640 and from the patterning module 640 to the entry airlock 646. The front-end robot 644 can also transfer wafers 626 between the entry loadlock and the exterior of the tool for substrate access and egress. Because the entry airlock module 646 has the ability to adapt the environment between atmospheric pressure and vacuum, the wafers 626 can move between the two pressure environments without being damaged.

[0105] It should be noted that EUV lithography tools typically operate at a higher vacuum (e.g., lower pressure) than deposition tools. In this case, it is desirable to increase the vacuum environment of the substrate during transfer between the deposition tool and the EUV lithography tool (e.g., apply a larger vacuum so that the substrate is exposed to a lower pressure) to allow for outgassing of the substrate before entering the EUV lithography tool. The unloading airlock 642 can provide this function by holding the transferred wafer at a low pressure, no higher than the pressure in the patterning module 640 for a period of time, and venting the off-gassing, so that the optics of the patterning module 640 are not contaminated by off-gassing from the substrate. A suitable pressure for the venting off-gas airlock is 1E-8 Torr or less.

[0106] In some embodiments, a system controller 650 (which may include one or more physical or logical controllers) controls some or all of the operations of the cluster tool and / or its separate modules. An exemplary system controller is further described above in connection with FIG. 4B. It should be noted that the controller may be local to the cluster architecture, or may be located outside the cluster architecture on the manufacturing floor, or may be located at a remote location and connected to the cluster architecture via a network. The system controller 650 may include one or more memory devices and one or more processors. The processor may include a central processing unit (CPU) or computer, analog and / or digital input / output connections, stepper motor controller boards, and other similar components. Instructions are executed on the processor to perform the appropriate control operations. These instructions may be stored in a memory device associated with the controller or provided over a network. In certain embodiments, the system controller executes system control software.

[0107] The system control software may include instructions for controlling the timing of application and / or magnitude of any aspect of tool or module operation. The system control software may be configured in any suitable manner. For example, various process tool component subroutines or control objects may be written to control the operation of process tool components necessary to perform various process tool processes. The system control software may be coded in any suitable computer readable programming language. In some embodiments, the system control software includes input / output control (IOC) sequence instructions for controlling the various parameters described above. For example, each stage of a semiconductor fabrication process may include one or more instructions executed by the system controller. For example, instructions for setting process conditions for condensation, deposition, evaporation, patterning, and / or etching stages may be included in the corresponding recipe stages.

[0108] In various embodiments, an apparatus for forming a negative pattern mask is provided. The apparatus can include one or more process chambers for patterning, deposition, and / or etching, and a controller including instructions for forming a negative pattern mask. One or more of the process chambers can be configured to perform one or more of the process steps described herein. The instructions can include code for dry depositing, processing as described herein, patterning features in a metal oxide resist on a semiconductor substrate by EUV exposure to expose a surface of the substrate, dry developing the photopatterned resist, and / or etching an underlying layer or layer stack using the patterned resist as a mask in the associated one or more process chambers.

[0109] It should be noted that the computer controlling the movement of the wafers may be local to the cluster architecture, or may be located outside the cluster architecture on the manufacturing floor, or may be located at a remote location and connected to the cluster architecture via a network. The controller described above with respect to FIG. 5B may be implemented using the tool of FIG.

[0110] conclusion Processing strategies (eg, post apply bake, post exposure bake, post apply remote plasma treatment, and post exposure remote plasma treatment) are disclosed that improve the EUV lithography dry developability performance of metal-containing EUV resists.

[0111] In the foregoing description, numerous specific details are set forth to provide a thorough understanding of the presented embodiments. The disclosed embodiments may be practiced without some or all of these specific details. In other instances, well-known process operations have not been described in detail so as not to unnecessarily obscure the disclosed embodiments. It will be understood that while the disclosed embodiments are described in conjunction with specific embodiments, they are not intended to limit the disclosed embodiments.

[0112] Although the foregoing embodiments have been described in some detail for clarity of understanding, it will be apparent that certain changes and modifications can be practiced within the scope of the appended claims. It should be noted that there are many alternative ways of implementing the processes, systems, and devices of the present embodiments. Thus, the present embodiments should be considered as illustrative rather than restrictive, and the embodiments should not be limited to the details set forth herein.

[0113] The following claims are provided to further describe certain embodiments of the present disclosure, but the present disclosure is not necessarily limited to these embodiments.

Claims

1. A method for processing a metal-containing extreme ultraviolet (EUV) photoresist, comprising: placing a substrate in a process chamber, wherein the substrate is a semiconductor substrate comprising a substrate layer and a metal-containing EUV photoresist positioned on the substrate layer; exposing the metal-containing EUV photoresist to a first high temperature in an oxygen-containing environment in the process chamber; exposing the metal-containing EUV photoresist to a second high temperature in an inert gas environment, wherein the second high temperature is higher than the first high temperature. A method as described above.

2. The method according to claim 1, wherein the metal-containing EUV photoresist comprises an EUV-exposed portion and an EUV-unexposed portion, and the exposure of the metal-containing EUV photoresist to the first high temperature in the oxygen-containing environment and the exposure of the metal-containing EUV photoresist to the second high temperature in the inert gas environment increase the etching selectivity between the EUV-exposed portion and the EUV-unexposed portion in a subsequent dry development process.

3. The method according to claim 2, wherein the exposure of the metal-containing EUV photoresist to the first high temperature in the oxygen-containing environment and the exposure of the metal-containing EUV photoresist to the second high temperature in the inert gas environment reduce line edge roughness (LER) and dose to size (DtS) in the subsequent dry development process.

4. The method according to claim 2, further comprising exposing the metal-containing EUV photoresist to EUV radiation before placing the substrate in the process chamber to form the EUV-exposed portion and the EUV-unexposed portion. A method as described above.

5. The method according to claim 4, wherein a first waiting time between the exposure to EUV radiation and the exposure to the first high temperature is less than about 20 minutes, and a second waiting time between the exposure to the first high temperature and the exposure to the second high temperature is less than about 1 hour.

6. The method according to claim 1, wherein the first high temperature is about 150°C to about 220°C, and the second high temperature is about 220°C to about 250°C.

7. The method according to claim 1, wherein the oxygen-containing environment contains oxygen-containing species, and the partial pressure of the oxygen-containing species is at least about 100 Torr in the oxygen-containing environment.

8. The method according to claim 1, wherein The oxygen-containing environment is oxygen (O 2 ), ozone (O 3 ), water (H 2 O), hydrogen peroxide (H 2 O 2 ), carbon monoxide (CO), carbon dioxide (CO 2 ), or a combination thereof, method.

9. The method according to claim 1, wherein The inert gas environment is nitrogen (N 2 ), helium (He), neon (Ne), argon (Ar), xenon (Xe), or a combination thereof, method.

10. The method according to claim 1, wherein each of the oxygen-containing environment and the inert gas environment contains no water or substantially no water. **Claim 11** The method according to claim 1, wherein the metal-containing EUV photoresist is a metal oxide-containing EUV photoresist. **Claim 12** The method according to claim 1, wherein the oxygen-containing environment contains oxygen radicals and ions generated from a remote plasma source, and the metal-containing EUV photoresist is exposed to the oxygen radicals and the ions. **Claim 13** The method according to claim 1, wherein exposing the metal-containing EUV photoresist to the second high temperature in the inert gas environment is performed in the same process chamber as exposing the metal-containing EUV photoresist to the first high temperature in the oxygen-containing environment. **Claim 14** The method according to claim 1, further comprising repeating one or more times the step of exposing the metal-containing EUV photoresist to the oxygen-containing environment and the step of exposing the metal-containing EUV photoresist to the inert gas environment. **Claim 15** The method according to claim 1, wherein the metal-containing EUV photoresist is dry-developed, and a part of the metal-containing EUV photoresist is selectively removed, and the exposure to the first high temperature in the oxygen-containing environment and the exposure to the second high temperature in the inert gas environment are post-exposure bake (PEB) operations performed before the dry development. **Claim 16** An apparatus for processing a metal-containing EUV photoresist, comprising a process chamber including a substrate support configured to support a semiconductor substrate having a substrate layer and a metal-containing EUV photoresist positioned thereon, a process gas source connected to the process chamber and associated gas flow control hardware, substrate thermal control hardware, and a controller for performing the following operations: exposing the metal-containing EUV photoresist to a first high temperature in an oxygen-containing environment in the process chamber, and exposing the metal-containing EUV photoresist to a second high temperature in an inert gas environment, wherein the second high temperature is higher than the first high temperature. a controller configured to include instructions for implementing and an apparatus comprising the same. **Claim 17** The apparatus according to claim 16, wherein the first high temperature is from about 150°C to about 220°C, and the second high temperature is from about 220°C to about 250°C. **Claim 18** The apparatus according to claim 16, wherein each of the oxygen-containing environment and the inert gas environment does not contain moisture or substantially does not contain moisture. **Claim 19** The apparatus according to claim 16, wherein the partial pressure of the oxygen-containing species is at least about 100 Torr in the oxygen-containing environment. **Claim 20** The apparatus according to claim 16, The oxygen-containing environment contains oxygen-containing species, the concentration of the oxygen-containing species is at least 20% by volume in the oxygen-containing environment, and the oxygen-containing species are oxygen (O 2 ), ozone (O 3 ), water (H 2 O), hydrogen peroxide (H 2 O 2 ), carbon monoxide (CO), carbon dioxide (CO 2 ), or a combination thereof.

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