Germanium and Silicon Stacks for 3D NAND

Abstract

An exemplary semiconductor processing method may include providing a silicon-containing precursor to a processing region of a semiconductor processing chamber. A substrate may be disposed within the processing region of the semiconductor processing chamber. The method may include forming a plasma of the silicon-containing precursor in the processing region and forming a layer of a first material on the substrate. The layer of the first material may include silicon oxide. The method may include providing a germanium-containing precursor to a processing region of the semiconductor processing chamber and forming a plasma of the germanium-containing precursor in the processing region. The forming the plasma of the germanium-containing precursor may be performed at a plasma power of about 500 W or greater. The method may include forming a layer of a second material on the substrate. The layer of the second material may include germanium oxide.

Description

[Technical field]

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS This application claims the benefit of U.S. Patent Application No. 63 / 246,006, filed September 20, 2021, the entire disclosure of which is incorporated herein by reference for all purposes.

[0002] The present technology relates to semiconductor processing and materials, and more particularly to the formation and processing of layered memory structures. [Background technology]

[0003] Integrated circuits are made possible by processes that create intricately patterned layers of material on a substrate surface. Creating patterned materials on a substrate requires controlled methods of forming materials and removing exposed materials. Stacked memories, such as vertical or 3D NAND, may involve the formation of a series of alternating layers of dielectric materials through which many memory holes or apertures may be etched. The nature of the materials in the layers of material, as well as the process conditions and materials for etching, may affect the uniformity of the structures formed. Material defects may lead to inconsistent patterning, which may further affect the uniformity of the structures formed.

[0004] Thus, there is a need for improved systems and methods that can be used to fabricate high quality devices and structures. These and other needs are addressed by the present technology. Summary of the Invention

[0005] An exemplary method of forming a semiconductor structure may include providing a silicon-containing precursor to a processing region of a semiconductor processing chamber. A substrate may be disposed within the processing region of the semiconductor processing chamber. The method may include forming a plasma of the silicon-containing precursor in the processing region and forming a layer of a first material on the substrate. The layer of the first material may include silicon oxide. The method may include providing a germanium-containing precursor to the processing region of the semiconductor processing chamber and forming a plasma of the germanium-containing precursor in the processing region. The forming the plasma of the germanium-containing precursor may be performed at a plasma power of about 500 W or greater. The method may include forming a layer of a second material on the substrate. The layer of the second material may include germanium oxide.

[0006] In some embodiments, the temperature in the semiconductor processing chamber may be maintained at about 550° C. or less while forming the layer of the first material and the layer of the second material on the substrate. The pressure in the semiconductor processing chamber may be maintained at about 6 Torr or less while forming the layer of the first material and the layer of the second material on the substrate. Forming the plasma of the silicon-containing precursor may be performed at a plasma power of about 500 W or less. Forming the plasma of the germanium-containing precursor may be performed at a plasma power of about 900 W or more. The atomic ratio of germanium to oxygen in the layer of the second material may be about 1:2 or less. Each layer of material may have a thickness between about 10 nm and about 30 nm. The method may include forming an alternating set of layers of the first material and layers of the second material on the substrate. The method may further include annealing the substrate subsequent to forming the alternating set of layers of the first material and layers of the second material.

[0007] Some embodiments of the present technology may include a semiconductor processing method. The method may include forming a layer of a first material on a substrate in a processing region of a semiconductor processing chamber. The layer of the first material may include silicon oxide. The method may include forming a layer of a second material on the substrate. The layer of the second material may include germanium oxide. An atomic ratio of germanium to oxygen in the layer of the second material may be about 3:2 or less. The method may include annealing the substrate subsequent to forming the first layer and the second layer on the substrate.

[0008] In some embodiments, the temperature in the semiconductor processing chamber may be maintained at about 550° C. or less while forming the layer of the first material and the layer of the second material on the substrate. The pressure in the semiconductor processing chamber may be maintained at about 6 Torr or less while forming the layer of the first material and the layer of the second material on the substrate. The atomic ratio of germanium to oxygen in the layer of the second material may be about 2:3 or less. The method may include forming a plasma of a germanium-containing precursor in the processing region prior to forming the layer of the second material on the substrate. The forming of the plasma of the germanium-containing precursor may be performed at a plasma power of about 900 W or more. The method may include forming an alternating set of layers of the first material and layers of the second material on the substrate. The alternating set of layers of the first material and layers of the second material may include at least 50 alternating layers of silicon oxide and germanium oxide.

[0009] Some embodiments of the present technology may include a semiconductor processing method. The method may include providing a silicon-containing precursor and an oxygen-containing precursor to a processing region of a semiconductor processing chamber. A substrate may be disposed in the processing region of the semiconductor processing chamber. The method may include forming a plasma of the silicon-containing precursor and the oxygen-containing precursor in the processing region. The method may include forming a layer of a first material on the substrate. The layer of the first material may include silicon oxide. The method may include providing a germanium-containing precursor and an oxygen-containing precursor to the processing region of the semiconductor processing chamber. The method may include forming a plasma of the germanium-containing precursor and the oxygen-containing precursor in the processing region. The method may include forming a layer of a second material on the substrate. The layer of the second material may include germanium oxide. A ratio of germanium to oxygen in the layer of the second material may be about 1:2 or less.

[0010] In some embodiments, the oxygen-containing precursor with the silicon-containing precursor may be the same precursor as the oxygen-containing precursor with the germanium-containing precursor. The flow rate of the oxygen-containing precursor may be increased from a first flow rate provided while providing the silicon-containing precursor to a second flow rate while providing the germanium-containing precursor. The forming of the plasma of the germanium-containing precursor may be performed at a plasma power of about 800 W or more. The temperature in the semiconductor processing chamber may be maintained at about 550° C. or less while forming the layer of the first material and the layer of the second material on the substrate. The pressure in the semiconductor processing chamber may be maintained at about 6 Torr or less while forming the layer of the first material and the layer of the second material on the substrate.

[0011] Such techniques can provide numerous benefits over conventional systems and techniques. For example, processes and structures may protect against defect formation during etching operations. In addition, operation of embodiments of the present techniques may improve the formation of memory holes through the stack. These and other embodiments, along with many of their advantages and features, are described in further detail in conjunction with the following description and accompanying drawings.

[0012] A further understanding of the nature and advantages of the disclosed technology may be realized by reference to the remaining portions of the specification and the drawings. [Brief description of the drawings]

[0013] [Figure 1] 1 is a schematic cross-sectional view illustrating an exemplary processing chamber in accordance with some embodiments of the present technique. [Diagram 2] 1A-1D illustrate selected operations of a forming method in accordance with some embodiments of the present technique. [Figure 3A] 3A-3B are diagrams illustrating exemplary schematic cross-sectional structures that may include layers of material and may be fabricated in accordance with some embodiments of the present technology. [Figure 3B] 3A-3B are diagrams illustrating exemplary schematic cross-sectional structures that may include layers of material and may be fabricated in accordance with some embodiments of the present technology. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0014] Some of the drawings are included as schematics. It should be understood that the drawings are for illustrative purposes and should not be considered to scale unless specifically indicated as such. Furthermore, as schematics, the drawings are provided to aid in understanding and may not include all aspects or information compared to actual representations and may include redundant or exaggerated material for illustrative purposes.

[0015] In the accompanying drawings, similar components and / or features may have the same reference symbol. Furthermore, various components of the same type may be distinguished by following the reference symbol with a letter that distinguishes between the similar components. If only the first reference symbol is used in the specification, the description is applicable to any of the similar components having the same first reference symbol regardless of the letter.

[0016] As the number of cells formed in a 3D NAND structure increases, the aspect ratios of the individual layers and other structures increase, sometimes dramatically. During 3D NAND processing, a stack of placeholder layers and dielectric materials may form the inter-electrode dielectric or inter-poly dielectric layers. These placeholder layers may have various operations performed to completely remove the material and place the structures before replacing it with metal. The inter-poly dielectric layers are often formed overlying a conductive layer, such as polysilicon. Etching operations may be performed to remove the material of the placeholder layers before replacing it with metal.

[0017] A wet etch may be used to remove the material of the placeholder layer, such as silicon nitride. The wet etch may involve immersing the structure having the placeholder layer and a stack of dielectric material in an etchant, such as phosphoric acid. The etchant may be intended to remove the placeholder layer without substantially removing the dielectric material, so that a metal may be deposited to replace the removed placeholder material.

[0018] Conventional techniques may struggle with uniformity and control during the etch removal process due to the material differences between the two layer types, as well as the etch process and materials. For example, conventional techniques may not be able to uniformly remove the placeholder layer during the etch process. The present technique overcomes these issues by adjusting the material used for the placeholder layer while forming a structure having a stack of placeholder layers and dielectric materials that can accommodate or limit one or more challenges that may otherwise occur. For example, the present technique may employ a germanium oxide placeholder layer instead of a conventional silicon nitride placeholder layer. By utilizing a germanium oxide material, the present technique may allow the etch process to be performed by a dry etch process that may be more selective than conventional wet processes. In addition, the present technique may overcome conventional problems with germanium films. Conventionally formed germanium oxide may be temperature sensitive, and downstream processing may include annealing, which may cause the germanium to diffuse into the silicon material and, in some circumstances, completely dissolve the separate layers and destroy the layered structure. The structure of the present invention can form germanium oxide to improve temperature sensitivity, ensuring that the layers can remain discrete during subsequent processing. The remaining disclosure routinely identifies specific materials and semiconductor structures that utilize the techniques of the present disclosure, but it will be readily understood that the systems, methods, and materials are equally applicable to many other structures that can benefit from aspects of the present technology. Thus, the technology should not be considered limited to use with only 3D NAND processing or materials. Additionally, while an exemplary chamber is described that provides a basis for the present technology, it should be understood that the present technology can be applied to virtually any semiconductor processing chamber that can enable the operations described.

[0019] FIG. 1 illustrates a cross-sectional view of an exemplary semiconductor processing chamber system 100 according to some embodiments of the present technique. The semiconductor processing chamber 100 may be utilized to form a film layer according to some embodiments of the present technique, but it should be understood that the method may be similarly implemented in any chamber in which film formation may occur. The semiconductor processing chamber 100 may include a chamber body 102, a substrate support 104 disposed within the chamber body 102, and a lid assembly 106 coupled to the chamber body 102 and enclosing the substrate support 104 within a processing volume 120. The substrate 103 may be provided to the processing volume 120 through an opening 126, which may be conventionally sealed for processing using a slit valve or door. The substrate 103 may rest on a surface 105 of the substrate support during processing. The substrate support 104 may be rotatable, as indicated by arrow 145, along an axis 147 along which an axis 144 of the substrate support 104 may lie. Alternatively, the substrate support 104 may be elevated and rotated as needed during the deposition process.

[0020] The plasma profile converter 111 may be disposed in the semiconductor processing chamber 100 to control plasma distribution across the substrate 103 disposed on the substrate support 104. The plasma profile converter 111 may include a first electrode 108 that may be disposed adjacent to the chamber body 102 and may separate the chamber body 102 from other components of the lid assembly 106. The first electrode 108 may be part of the lid assembly 106 or may be a separate sidewall electrode. The first electrode 108 may be an annular or ring-shaped member or may be a ring electrode. The first electrode 108 may be a continuous loop around the circumference of the semiconductor processing chamber 100 surrounding the processing volume 120 or may be discontinuous at selected locations as desired. The first electrode 108 may also be a perforated electrode, such as a perforated ring or mesh electrode, or may be a plate electrode, such as an auxiliary gas distributor.

[0021] The one or more isolators 110a, 110b may be a dielectric material such as ceramic or a metal oxide, e.g., aluminum oxide and / or aluminum nitride, and may contact the first electrode 108 and electrically and thermally isolate the first electrode 108 from the gas distributor 112 and from the chamber body 102. The gas distributor 112 may define an aperture 118 for distributing the process precursors into the processing volume 120. The gas distributor 112 may be coupled to a first power source 142, such as an RF generator, an RF power source, a DC power source, a pulsed DC power source, a pulsed RF power source, or any other power source that may be coupled to a processing chamber. In some embodiments, the first power source 142 may be an RF power source.

[0022] The gas distributor 112 may be a conductive gas distributor or a non-conductive gas distributor. The gas distributor 112 may also be formed of conductive and non-conductive components. For example, the body of the gas distributor 112 may be conductive and the faceplate of the gas distributor 112 may be non-conductive. The gas distributor 112 may be powered, such as by a first power source 142 as shown in FIG. 1, or the gas distributor 112 may be coupled to ground in some embodiments.

[0023] The first electrode 108 may be coupled to a first tuned circuit 128, which may control the ground path of the semiconductor processing chamber 100. The first tuned circuit 128 may include a first electronic sensor 130 and a first electronic controller 134. The first electronic controller 134 may be or include a variable capacitor or other circuit element. The first tuned circuit 128 may be or include one or more inductors 132. The first tuned circuit 128 may be any circuit that allows for a variable or controllable impedance under the plasma conditions present in the processing volume 120 during processing. In some embodiments as illustrated, the first tuned circuit 128 may include a first circuit leg and a second circuit leg coupled in parallel between ground and the first electronic sensor 130. The first circuit leg may include a first inductor 132A. The second circuit leg may include a second inductor 132B coupled in series with the first electronic controller 134. The second inductor 132B may be disposed between the first electronic controller 134 and a node connecting both the first and second circuit legs to the first electronic sensor 130. The first electronic sensor 130 may be a voltage or current sensor and may be coupled to the first electronic controller 134, which may be responsible for some closed-loop control of the plasma conditions within the process volume 120.

[0024] The second electrode 122 may be coupled to the substrate support 104. The second electrode 122 may be embedded in the substrate support 104 or coupled to the surface 105 of the substrate support 104. The second electrode 122 may be a plate, a perforated plate, a mesh, a wire screen, or any other distributed arrangement of conductive elements. The second electrode 122 may be a tuning electrode and may be coupled to a second tuning circuit 136 by a conduit 146, a cable having a selected resistance, such as 50 Ω, disposed, for example, in the axis 144 of the substrate support 104. The second tuning circuit 136 may have a second electronic sensor 138 and a second electronic controller 140, which may be a second variable capacitor. The second electronic sensor 138 may be a voltage or current sensor and may be coupled to the second electronic controller 140 to provide further control over the plasma conditions in the process volume 120.

[0025] The third electrode 124 may be a bias electrode and / or an electrostatic chuck electrode and may be coupled to the substrate support 104. The third electrode may be coupled to a second power source 150 through a filter 148, which may be an impedance matching circuit. The second power source 150 may be DC power, pulsed DC power, RF bias power, pulsed RF source or bias power, or a combination of these or other power sources. In some embodiments, the second power source 150 may be RF bias power.

[0026] The lid assembly 106 and substrate support 104 of FIG. 1 may be used with any processing chamber for plasma or thermal processing. In operation, the semiconductor processing chamber 100 may bear real-time control of plasma conditions within the processing volume 120. The substrate 103 may be disposed on the substrate support 104, and processing gases may be flowed through the lid assembly 106 using the inlet 114 according to any desired flow scheme. The gases may exit the semiconductor processing chamber 100 through the outlet 152. Power may be coupled with the gas distributor 112 to establish a plasma within the processing volume 120. The substrate may receive an electrical bias using the third electrode 124 in some embodiments.

[0027] When a current is applied to the plasma in the process volume 120, a potential difference can be established between the plasma and the first electrode 108. A potential difference can also be established between the plasma and the second electrode 122. The electronic controllers 134, 140 can then be used to adjust the flow characteristics of the ground path represented by the two tuned circuits 128 and 136. Set points can be communicated to the first tuned circuit 128 and the second tuned circuit 136 to provide independent control of deposition rate and center-to-edge plasma density uniformity. In an embodiment where the electronic controllers are both variable capacitors, an electronic sensor can adjust the variable capacitor to independently maximize deposition rate and minimize thickness non-uniformity.

[0028] Each tuning circuit 128, 136 may have a variable impedance that may be adjusted using the respective electronic controller 134, 140. If the electronic controller 134, 140 is a variable capacitor, the capacitance range of each of the variable capacitors and the inductance of the first inductor 132A and the second inductor 132B may be selected to provide an impedance range. This range may depend on the frequency and voltage characteristics of the plasma and may have a minimum value for the capacitance range of each variable capacitor. Thus, when the capacitance of the first electronic controller 134 is at a minimum or maximum value, the impedance of the first tuning circuit 128 may be high, resulting in a plasma shape with minimal aerial or lateral coverage above the substrate support. When the capacitance of the first electronic controller 134 approaches a value that minimizes the impedance of the first tuning circuit 128, the aerial coverage of the plasma may grow to a maximum value to effectively cover the entire working area of ​​the substrate support 104. As the capacitance of the first electronic controller 134 deviates from the minimum impedance setting, the plasma shape may shrink from the chamber walls and the aerial coverage of the substrate support may decrease. The second electronic controller 140 may have a similar effect, and as the capacitance of the second electronic controller 140 can be changed, the aerial coverage of the plasma above the substrate support may increase or decrease.

[0029] The electronic sensors 130, 138 can be used to tune the respective circuits 128, 136 in a closed loop. A current or voltage set point may be installed in each sensor depending on the type of sensor used, and the sensors may be equipped with control software that determines adjustments to the respective electronic controllers 134, 140 to minimize deviations from the set point. As a result, the plasma shape may be selected and dynamically controlled during processing. Although the above discussion is based on the electronic controllers 134, 140 being variable capacitors, it should be understood that any electronic component having adjustable characteristics may be used to provide the tuning circuits 128 and 136 with adjustable impedance.

[0030] FIG. 2 illustrates the operation of an exemplary method 200 of semiconductor processing according to some embodiments of the present technique. The method may be performed in a variety of processing chambers, including the semiconductor processing chamber 100 described above, as well as any other chamber in which plasma deposition may be performed. The method 200 may include a number of optional operations that may or may not be specifically associated with some embodiments of the method according to the present technique. It should be understood that the method 200 may be performed on any number of semiconductor structures or substrates 315, including the exemplary structure 300 as shown in FIG. 3A, on which alternating layers of materials may be formed. It should be understood that FIGS. 3A and 3B show only a partial schematic diagram, and that the substrate may include any number of structural sections having the aspects as shown in the figures, as well as alternative structural aspects that may also benefit from the operation of the present technique.

[0031] Prior to the first operation of method 200, the substrate 315 may be processed in one or more techniques before being placed in a processing region of the semiconductor processing chamber 100 in which method 200 may be performed. Some or all of the operations may be performed in a chamber or system tool such as those described above, or may be performed in different chambers on the same system tool, which may include the semiconductor processing chamber in which the operations of method 200 may be performed.

[0032] The substrate 315 may have a substantially planar surface or an uneven surface in embodiments. The substrate may be a material such as crystalline silicon, silicon oxide, strained silicon (developed by IBM), silicon germanium, doped or undoped polysilicon, doped or undoped silicon wafers, patterned or unpatterned wafers, silicon on insulators, carbon doped silicon oxide, silicon nitride, doped silicon, germanium, gallium arsenide, or sapphire. The substrate 315 may have a variety of dimensions, such as 200 mm or 300 mm diameter wafers, as well as rectangular or square panels.

[0033] Method 200 may include a number of optional operations as illustrated that may or may not be specifically associated with some embodiments of methods according to the present technology. For example, many of the operations are described to provide a broader scope of structural formations, but are not critical to the present technology or may be performed by alternative methods as described further below. As mentioned above, method 200 may describe operations shown generally in FIG. 3A that are described in conjunction with the operations of method 200.

[0034] Structure 300 may, in some embodiments, show a partial view of a stack of alternating layers of materials that may be used in 3D NAND memory formation. The alternating layers of materials may be fabricated by any number of methods, including plasma enhanced chemical vapor deposition, physical vapor deposition, atomic layer deposition, thermally enhanced chemical vapor deposition, or any other formation technique. In some embodiments, plasma enhanced chemical vapor deposition may be performed in a processing chamber, such as semiconductor processing chamber 100 described above. Although method 200 discusses the formation of silicon oxide followed by the formation of germanium oxide, in embodiments also encompassed by the present technology, the order of formation may be reversed. Additionally, any number of layers of materials may be fabricated in a stack, or any portion of any stack, and different portions of the stack may include a greater, lesser, or similar number of layers than any other portion of the stack according to embodiments of the present technology.

[0035] The method 200 may include providing a silicon-containing precursor to a processing region of the semiconductor processing chamber 100 in operation 205. Silicon-containing precursors that may be used may include, but are not limited to, silane (SiH4), disilane (Si2H6), silicon tetrafluoride (SiF4), silicon tetrachloride (SiCl4), dichlorosilane (SiH2Cl2), tetraethyl orthosilicate (TEOS), as well as any other silicon-containing precursor that may be used for silicon oxide film formation. The method 200 may also include forming a plasma of the silicon-containing precursor in the processing region in operation 210. In an embodiment, the plasma of the silicon-containing precursor may be formed by providing RF power to a faceplate to generate a plasma in the processing region, although any other processing chamber capable of generating a plasma may be used as well. Forming the plasma of the silicon-containing precursor may be performed at a plasma power of about 500 W or less, and may be performed at a plasma power of about 475 W or less, about 450 W or less, about 425 W or less, about 400 W or less, about 375 W or less, about 350 W or less, or less, which may facilitate the formation of longer chains of silicon and oxygen in the produced film.

[0036] After forming the plasma of the silicon-containing precursor, the method 200 may include forming a layer of a first material on the substrate in operation 215. The layer of first material may include a silicon-containing material, such as silicon oxide. After deposition to a sufficient thickness, the flow of the silicon-containing precursor may be reduced or eliminated before proceeding to subsequent operations.

[0037] The method 200 may include, in operation 220, providing a germanium-containing precursor to a processing region of the semiconductor processing chamber 100. Germanium-containing precursors that may be used may include, but are not limited to, germane (GeH4), digermane (Ge2H6), germanium difluoride (GeF2), germanium tetrafluoride (GeF4), germanium dichloride (GeCl2), germanium tetrabromide (GeBr4), as well as any other germanium-containing precursor that may be used to form germanium-containing (such as germanium oxide) films.

[0038] In either operation 205 or operation 220, an oxygen-containing precursor may further be provided to the processing region of the semiconductor processing chamber 100. The oxygen-containing precursors that may be used may include, but are not limited to, O2, N2O, NO2, O3, H2O, and any other oxygen-containing precursor that may be used for silicon-containing (such as silicon oxide) or germanium-containing (such as germanium oxide) film formation. When an oxygen-containing precursor is provided in both operation 205 and operation 220, the oxygen-containing precursor provided with the silicon-containing precursor in operation 205 may be a similar precursor to the oxygen-containing precursor provided with the germanium-containing precursor in operation 220. Since they contain similar constituents, O2 and O3 may be similar precursors, and N2O and NO3 may be similar precursors. It is also contemplated that dissimilar oxygen-containing precursors may be used during operation 205 and operation 220. In some embodiments, the flow rate of the oxygen-containing precursor may be increased from a first flow rate provided while providing the silicon-containing precursor in operation 205 to a second flow rate while providing the germanium-containing precursor in operation 220. It is also contemplated that the flow rate of the oxygen-containing precursor may be substantially similar during operation 205 and operation 220. Similarly, a nitrogen-containing precursor may also be provided to the processing region of the semiconductor processing chamber 100. The nitrogen-containing precursor used during operation 205 or operation 220 may include N2, N2O, NO2, NH3, N2H2, as well as any other nitrogen-containing precursor that may be used for silicon-containing (including silicon oxide) or germanium-containing (including germanium oxide) film formation. In either operation 205 or operation 220, one or more additional precursors may be included, such as an inert precursor, which may include Ar, He, Xe, Kr, nitrogen, or other precursors.

[0039] The oxygen-containing precursor may be flowed at a higher flow rate than either the silicon-containing precursor or the germanium-containing precursor during the formation of the silicon oxide layer and / or the germanium oxide layer. For example, in some embodiments, the oxygen-containing precursor may be flowed at a flow rate of at least 10:1 compared to the flow rate of the silicon-containing precursor or the germanium-containing precursor, and may be about 20:1 or more, about 30:1 or more, about 40:1 or more, about 50:1 or more, about 60:1 or more, about 70:1 or more, about 80:1 or more, about 90:1 or more, about 100:1 or more, or more. Similarly, in some embodiments, the flow rate of the oxygen-containing precursor may be increased from a first flow rate provided during the provision of the silicon-containing precursor in operation 205 to a second flow rate during the provision of the germanium-containing precursor in operation 220. By increasing the flow rate of the oxygen-containing precursor during the germanium film formation, a more oxygen-rich film may be formed. Thus, in some embodiments, the oxygen-containing precursor may be flowed at a flow rate of about 100:1 or more compared to the germanium-containing precursor, and may be about 200:1 or more, about 300:1 or more, about 400:1 or more, about 500:1 or more, about 600:1 or more, about 700:1 or more, about 800:1 or more, about 900:1 or more, about 1000:1 or more, or more.

[0040] In operation 225 of method 200, a plasma of the germanium-containing precursor may be formed in the processing region. In an embodiment, the plasma of the germanium-containing precursor may be formed by providing RF power to a faceplate to generate a plasma in the processing region, although any other processing chamber capable of generating a plasma may be used as well. Forming the plasma of the germanium-containing precursor may be performed with a plasma power of about 500 W or more, and may be performed with a plasma power of about 550 W or more, about 600 W or more, about 650 W or more, about 700 W or more, about 750 W or more, about 800 W or more, about 800 W or more, about 850 W or more, about 900 W or more, about 950 W or more, about 1000 W or more, or more. The plasma power during the formation of the germanium-containing plasma may be necessary to create an environment rich in oxygen radicals. As described further below, it may be desirable for the atomic ratio of germanium to oxygen in the layer of the second material deposited on the layer of the first material to be about 3:2 or less. Thus, to achieve this atomic ratio, a plasma power of about 500 W or more may be required to create an oxygen radical-rich environment and deposit sufficient oxygen in the layer of the second material. If the plasma power is less than 500 W, the germanium atoms may begin to bond with each other and form regions of germanium-rich germanium oxide, thereby undesirably increasing the germanium to oxygen atomic ratio and increasing the temperature sensitivity of the resulting film. Furthermore, maintaining a plasma power of about 500 W or more may help separate the germanium atoms until they begin to oxidize.

[0041] After forming the plasma of the germanium-containing precursor, the method 200 may include forming a layer of a second material on the substrate in operation 230. The layer of the second material may include a germanium-containing material, such as germanium oxide. The atomic ratio of germanium to oxygen in the layer of the second material may be about 3:2 or less, about 1:1 or less, about 1:2 or less, about 2:5 or less, about 1:3 or less, about 1:4 or less, about 1:5 or less, or less. A layer of a second material having an atomic ratio of germanium to oxygen of about 3:2 or less may have increased thermal stability compared to a layer of a material having an atomic ratio of germanium to oxygen of more than 3:2. A layer of a material having an atomic ratio of germanium to oxygen of more than 3:2 may not have desirable thermal stability because germanium atoms may diffuse to adjacent layers during an annealing operation, as described further below. As described above, an oxygen-containing precursor may be provided in addition to the germanium-containing precursor in operation 220. This additional oxygen-containing precursor may contribute to an increase in the oxygen concentration, thus decreasing the atomic ratio of germanium to oxygen in the layer of the second material.

[0042] The deposition in operation 205 and operation 220 may be performed at a substrate or pedestal temperature of about 550° C. or less. As a result, in some embodiments, the deposition may be performed at a temperature of about 525° C. or less, about 500° C. or less, about 475° C. or less, about 450° C. or less, about 425° C. or less, about 300° C. or less, about 375° C. or less, about 350° C. or less, about 325° C. or less, about 300° C. or less, about 275° C. or less, about 250° C. or less, about 225° C. or less, about 200° C. or less, or less. In addition, the deposition may be performed at a pressure of about 6 Torr or less, such as about 5 Torr or less, about 4 Torr or less, about 3 Torr or less, about 2 Torr or less, about 1 Torr or less, or less. Operations 205 and 220 may be formed at the same or similar process conditions. For example, the temperature and / or pressure may be maintained for both the formation of the layer of the first material and the layer of the second material. Conversely, the temperature and / or pressure may be modified or adjusted between the formation of the layers of the first material and the layers of the second material. Additionally, the temperature and / or pressure may be modified or adjusted between the formation of various layers in alternating layers of structure 300.

[0043] The layer of the first material and the layer of the second material may each have a substantially similar thickness. For example, the layer of the first material and the layer of the second material may each have a thickness within about 5 nm of each other, within about 4 nm of each other, within about 3 nm of each other, within about 2 nm of each other, within about 1 nm of each other, or less. In embodiments, the layer of the first material and the layer of the second material may each have a thickness of about 10 nm or more, such as about 12 nm or more, about 14 nm or more, about 16 nm or more, about 18 nm or more, about 20 nm or more, or more. Additionally, the layer of the first material and the layer of the second material may each have a thickness of about 30 nm or less, such as about 28 nm or less, about 26 nm or less, about 24 nm or less, about 22 nm or less, about 20 nm or less, or less. In some embodiments, the layers of materials may each have a thickness of about 10 nm to 30 nm.

[0044] The method 200 may include repeating operations 205 through 230 at operation 235 to form an alternating set of layers of a first material and layers of a second material. These operations may be repeated any number of times until a predetermined number of pairs of layers may be formed, which may comprise a stack of layers. As discussed above, FIG. 3A illustrates a structure 300 including a substrate 305 having a stack 310 of alternating layers of silicon oxide and germanium oxide. The illustrated stack 310 may include multiple portions 315, which may each include at least one layer 317 of a silicon oxide material and at least one layer 319 of a germanium oxide material. Each portion may also include multiple pairs of layers, including about 2 pairs or more, about 10 pairs or more, about 50 pairs or more, about 100 pairs or more, or more pairs of layers. In total, the structure 300 may include at least 10 alternating layers of a first material and a second material, and may include at least 30 layers, at least 50 layers, at least 100 layers, at least 150 layers, or more. Any particular number of pairs falling within any of these defined ranges should be understood as specifically defined herein. Although three portions 315a, 315b, and 315c are illustrated, more or fewer portions may be included in accordance with some embodiments of the present technology.

[0045] In operation 240, an optional anneal may be performed, which may increase the temperature of the formed film with or without increasing the oxygen concentration in the material. The anneal may include a process that increases the temperature of the structure to about 500° C. or higher, and may increase the temperature of the first portion of the stack to about 550° C. or higher, about 600° C. or higher, about 650° C. or higher, about 700° C. or higher, about 750° C. or higher, about 800° C. or higher, about 850° C. or higher, about 900° C. or higher, or higher. Operation 240 may be performed multiple times during method 200. For example, a first anneal may be performed after the formation of first portion 315a and before the formation of second portion 315b. By performing an anneal between the formation of first portion 315a and second portion 315b, outgassing may be performed to limit deformation of the structure during any subsequent processing.

[0046] As discussed above, the germanium to oxygen atomic ratio in the layer of the second material may be about 3:2 or less. If the germanium to oxygen atomic ratio is too high, such as greater than 3:2, the germanium oxide layer may lack the desired stability during the annealing operation. For example, germanium may diffuse into the adjacent silicon oxide layer during the annealing operation when the germanium to oxygen atomic ratio is greater than 3:2. For example, when the germanium to oxygen atomic ratio is greater than 3:2, the silicon oxide layer and the germanium oxide layer may completely dissolve and combine into one homogenous layer during the annealing.

[0047] After forming the structure 300, the structure may be further processed to prepare it for use, such as 3D NAND. In subsequent processing, and as shown in FIG. 3B, a plurality of memory holes or apertures may be etched into the structure 301. A hard mask may be applied to the structure 300, and high aspect ratio memory holes may be etched into the structure 301. The memory holes may be trenches or channels that are etched from the top of the structure 301 into the substrate 315. After the memory holes are etched, further deposition and etching processes may be performed before removing any remaining geranium oxide material.

[0048] In conventional structures with alternating layers of silicon oxide and silicon nitride, the process of etching the memory holes can be difficult. The etching process performed may not have sufficient selectivity between the two materials, which may result in insufficient removal of the silicon nitride, as well as over-etching of the silicon oxide, which may damage the cell structure. Conversely, germanium oxide may be more easily etched by a dry etching process with increased selectivity to silicon oxide, which may both increase the removal of germanium oxide throughout the structure, as well as control the loss of silicon oxide. Germanium oxide may be characterized by a reduced hardness relative to silicon nitride, which may facilitate the formation of memory holes, making it possible to use thinner hard masks, as well as limiting the interface residence time of the etching process, which may damage the silicon oxide in conventional processing of silicon nitride.

[0049] After etching of the memory holes and any additional deposition and / or etching processes associated with memory cell formation, as will be appreciated by those skilled in the art, the remaining germanium oxide material may be removed. The removed germanium oxide may be replaced with a metal-continuous material such as tungsten. During the etch to remove silicon nitride of conventional structures, insufficient removal capability of silicon nitride may be realized. When a silicon nitride layer is used, as opposed to a germanium oxide layer as in the present disclosure, a wet etch using phosphoric acid (H3PO4) is mandatory. During this wet etch removal of silicon nitride, silicon oxide by-products may be formed. A portion of this silicon oxide by-product may deposit on the existing silicon oxide layer in the structure. This unintentional deposition of silicon oxide during silicon nitride removal may create a mismatched shape of the existing silicon oxide layer, which may be undesirable.

[0050] In embodiments of the present disclosure, if a germanium oxide layer is used instead of a silicon nitride layer, wet etching may not be required. Instead, dry etching may be performed using a hydrogen-containing gas and / or an argon-containing gas. In such embodiments, a plasma may be formed from a hydrogen-containing gas to etch the germanium oxide material, and one or more carrier gases, such as argon, may be included for plasma stability. This dry etch using a hydrogen-containing gas may etch the germanium oxide material without substantially etching the silicon oxide material. Furthermore, this dry etch may be performed in the same semiconductor processing chamber 100 used to form the structure. Wet etching of germanium oxide using water is possible, but such wet etching may result in bending of the silicon oxide layer, surface tension effects, etc.

[0051] Utilizing one or more of the described processes may result in improved material removal and therefore more uniform formation of memory holes, thereby limiting the difficulties of stack processing and eventual removal of the material to be replaced with the metal-containing material, as well as improving profile uniformity through the memory holes. As a result, the present technology may result in improved manufacturing, which may produce more uniform stack structures than conventional techniques.

[0052] In the above description, for purposes of explanation, numerous details have been set forth in order to provide an understanding of various embodiments of the present technology. However, it will be apparent to one skilled in the art that particular embodiments may be practiced without some of these details, or with additional details.

[0053] Although several embodiments have been disclosed, those skilled in the art will recognize that various modifications, alternative configurations, and equivalents may be used without departing from the spirit of the embodiments. In addition, many well-known processes and elements have not been described to avoid unnecessarily obscuring the technology. Thus, the above description should not be considered as limiting the scope of the technology. In addition, although a method or process may be described in a sequence or steps, it should be understood that the operations may be performed simultaneously or in a different order than listed.

[0054] Where a range of values ​​is provided, unless the context clearly indicates otherwise, each intermediate value between the upper and lower limits of that range is also understood to be specifically disclosed, to the smallest fraction of the unit of the lower limit. Any stated or unstated intermediate value in the stated range, and any smaller range between any other stated or intermediate value in that stated range, are also included. The upper and lower limits of those smaller ranges may be independently included or excluded from the range, and each range in which either, neither, or both of the limits are included in the smaller range is also encompassed in the art, subject to any specifically excluded limits in the stated range. If the stated range includes one or both of the limits, then ranges excluding either or both of those included limits are also included.

[0055] As used herein and in the appended claims, the singular forms "a," "an," and "the" include the plural unless the context clearly dictates otherwise. Thus, for example, a reference to a "silicon-containing precursor" includes a plurality of such precursors, a reference to a "layer of a first material" includes a reference to one or more layers, and equivalents thereof known to those skilled in the art, and so forth.

[0056] Additionally, the words "comprise," "comprising," "containing," "containing," "including," and "including," when used in this specification and the claims that follow, are intended to specify the presence of stated features, integers, components, or operations, but do not exclude the presence or addition of one or more other features, integers, components, operations, acts, or groups.

Claims

1. providing a silicon-containing precursor to a processing region of a semiconductor processing chamber having a substrate disposed therein; forming a plasma of the silicon-containing precursor in the processing region; forming a layer of a first material comprising silicon oxide on the substrate; providing a germanium-containing precursor to the processing region of the semiconductor processing chamber; forming a plasma of the germanium-containing precursor in the processing region; forming a layer of a second material on the substrate, the second layer comprising germanium oxide; A semiconductor processing method comprising:

2. 10. The semiconductor processing method of claim 1, wherein a temperature within the semiconductor processing chamber is maintained at or below about 550°C while forming the layer of first material and the layer of second material on the substrate.

3. 10. The semiconductor processing method of claim 1, wherein a pressure within the semiconductor processing chamber is maintained at about 6 Torr or less while forming the layer of first material and the layer of second material on the substrate.

4. 10. The semiconductor processing method of claim 1, wherein forming the plasma of the silicon-containing precursor is carried out at a plasma power of about 500 W or less.

5. 10. The semiconductor processing method of claim 1, wherein forming the plasma of the germanium-containing precursor is carried out at a plasma power of about 900 W or greater.

6. 10. The semiconductor processing method of claim 1, wherein the atomic ratio of germanium to oxygen in the layer of second material is about 1:2 or less.

7. 10. The semiconductor processing method of claim 1, wherein each layer of material has a thickness between about 10 nm and about 30 nm.

8. 10. The semiconductor processing method of claim 1, further comprising forming alternating sets of layers of said first material and layers of said second material on said substrate.

9. 10. The semiconductor processing method of claim 8, further comprising annealing the substrate subsequent to forming the alternating sets of layers of the first material and the layers of the second material.

10. forming a layer of a first material comprising silicon oxide on a substrate in a processing region of a semiconductor processing chamber; forming a layer of a second material on the substrate, the layer of second material comprising germanium oxide, wherein an atomic ratio of germanium to oxygen in the layer of second material is less than or equal to about 3:2; forming the layer of the first material and the layer of the second material on the substrate, followed by annealing the substrate; A semiconductor processing method comprising:

11. 11. The semiconductor processing method of claim 10, wherein a temperature within the semiconductor processing chamber is maintained at or below about 550°C while forming the layer of first material and the layer of second material on the substrate.

12. 11. The semiconductor processing method of claim 10, wherein a pressure within the semiconductor processing chamber is maintained at about 6 Torr or less while forming the layer of first material and the layer of second material on the substrate.

13. 11. The semiconductor processing method of claim 10, wherein the atomic ratio of germanium to oxygen in the layer of second material is less than or equal to about 2:

3.

14. forming a plasma of a germanium-containing precursor in the processing region before forming the layer of the second material on the substrate, wherein forming the plasma of the germanium-containing precursor is performed at a plasma power of about 900 W or greater.

11. The semiconductor processing method of claim 10, further comprising:

15. forming an alternating set of layers of the first material and layers of the second material on the substrate, the alternating set of layers of the first material and layers of the second material comprising at least 50 alternating layers of silicon oxide and germanium oxide.

11. The semiconductor processing method of claim 10, further comprising:

16. providing a silicon-containing precursor and an oxygen-containing precursor to a processing region of a semiconductor processing chamber having a substrate disposed therein; forming a plasma of the silicon-containing precursor and the oxygen-containing precursor in the processing region; forming a layer of a first material comprising silicon oxide on the substrate; providing a germanium-containing precursor and an oxygen-containing precursor to the processing region of the semiconductor processing chamber; forming a plasma of the germanium-containing precursor and the oxygen-containing precursor in the processing region; forming a layer of a second material on the substrate, the layer of second material including germanium oxide, wherein a ratio of germanium to oxygen in the layer of second material is about 1:2 or less; A semiconductor processing method comprising:

17. 17. The semiconductor processing method of claim 16, wherein the oxygen-containing precursor provided with the silicon-containing precursor is the same precursor as the oxygen-containing precursor provided with the germanium-containing precursor.

18. 20. The semiconductor processing method of claim 17, wherein the flow rate of the oxygen-containing precursor is increased from a first flow rate provided while providing the silicon-containing precursor to a second flow rate while providing the germanium-containing precursor.

19. 17. The semiconductor processing method of claim 16, wherein forming the plasma of the germanium-containing precursor is carried out at a plasma power of about 800 W or greater.

20. a temperature within the semiconductor processing chamber is maintained at or below about 550° C. while forming the layer of the first material and the layer of the second material on the substrate; a pressure within the semiconductor processing chamber is maintained at about 6 Torr or less while forming the layer of the first material and the layer of the second material on the substrate; 17. The semiconductor processing method of claim 16.

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