Modification of metal-containing surfaces in high aspect ratio plasma etching.

Abstract

Provided herein are methods and apparatus for etching high aspect ratio features in a substrate having a mixed material stack. The methods involve using low plasma power, high chamber pressure, and / or low temperature while exposing the substrate to a metal-containing additive gas during etching with a fluorocarbon gas.

Description

[Technical field]

[0001] Related Applications The PCT Application Form is being filed contemporaneously herewith as a part of this application. Each application to which this application claims benefit or priority as identified in the contemporaneously filed PCT Application Form is hereby incorporated by reference in its entirety and for all purposes. [Background technology]

[0002] Semiconductor fabrication processes involve etching certain structures, including structures having exposed surfaces that include two or more materials or compositions. In addition, etching can be performed to form small feature sizes for some structures, and the reliability of the features to maintain their size, and in some cases their shape, in subsequent processes can be used to form desired structures.

[0003] The background discussion set forth herein is intended to be generally in the context of this disclosure, and the work of the inventors named herein, to the extent set forth in this "Background" section, and aspects of this description that may not otherwise be classified as prior art at the time of filing, are not admitted, explicitly or implicitly, as prior art to this disclosure. Summary of the Invention

[0004] One embodiment involves a method of processing a substrate, the method including providing a substrate having a mixed material stack; igniting a first plasma at a first plasma power to expose the mixed material stack to one or more etching gases and partially etch features in the mixed material stack to form a partially etched mixed material stack; and exposing the partially etched mixed material stack to a second plasma generated from igniting a metal-containing additive gas at a second plasma power, where the second plasma power is less than the first plasma power.

[0005] In various embodiments, the metal-containing additive gas includes a halogen.

[0006] In various embodiments, the metal-containing additive gas includes a metal such as any of tungsten, tin, molybdenum, and titanium.

[0007] In various embodiments, the second plasma power is between about 1% and about 10% less than the first plasma power.

[0008] In various embodiments, exposing the partially etched mixed material stack to the second plasma is performed at a first chamber pressure that is greater than a second chamber pressure used during exposure of the mixed material stack to the one or more etching gases, hi some embodiments, the first chamber pressure is about 1.5 times to about 4 times greater than the second chamber pressure.

[0009] In various embodiments, exposing the partially etched mixed material stack to the second plasma is performed using a first substrate temperature that is less than a second substrate temperature used during exposure of the mixed material stack to the one or more etching gases. In some embodiments, the first substrate temperature is between about 20° C. and about 60° C.

[0010] In various embodiments, exposing the partially etched mixed material stack to the second plasma is for a duration of less than about 20 seconds.

[0011] In various embodiments, the one or more etching gases include at least one gas containing fluorine and carbon atoms.

[0012] In various embodiments, the metal-containing additive gas is diluted in an inert gas. In some embodiments, the metal-containing additive gas and the inert gas are flowed in parallel with a ratio of the flow rate of the metal-containing additive gas to the flow rate of the inert gas of about 1:40 to about 1:100. In some embodiments, the inert gas is argon or krypton.

[0013] In any of the above embodiments, the mixed material stack includes two or more layers, each layer having a composition selected from the group consisting of oxide, nitride, carbide, and polysilicon.

[0014] In any of the above embodiments, the mixed material stack includes an ONON stack and an oxide.

[0015] In any of the above embodiments, the sidewalls of the feature comprise two or more materials, including any one or more of an oxide, a nitride, a carbide, and polysilicon.

[0016] In any of the above embodiments, exposing the mixed material stack to one or more etching gases includes exposing the mixed material stack to one or more cycles of successive alternating pulses of a fluorocarbon gas and a hydrogen-containing fluorocarbon gas.

[0017] In some embodiments, exposing the partially etched mixed material stack to the second plasma occurs every n cycles of successive alternating pulses, where n is an integer equal to or greater than 1.

[0018] Another aspect involves an apparatus for processing a substrate, the apparatus comprising one or more process chambers, each process chamber comprising a chuck, a plasma generator, a first gas source for containing one or more etching gases, a second gas source for containing a metal-containing additive gas, one or more gas inlets to the process chambers, associated flow control hardware for delivering gases from the first gas source and the second gas source to the one or more process chambers, and a controller having at least one processor and a memory, the at least one processor and the memory being communicatively coupled to each other. The at least one processor is at least operatively connected to the flow control hardware, and the memory stores computer-executable instructions for controlling the at least one processor to at least control the flow control hardware to: cause a substrate to be brought into a first of the one or more process chambers; cause a first plasma to be generated using one or more etching gases at a first plasma power; and cause a second plasma to be generated using a metal-containing additive gas at a second plasma power, the second plasma power being less than the first plasma power. For example, in some embodiments, the second plasma power is less than about 1% to about 10% of the first plasma power.

[0019] In various embodiments, the memory further stores computer-executable instructions for shuttling the substrate through a second of the one or more process chambers before causing a second plasma to be generated in the second of the one or more process chambers.

[0020] In some embodiments, the first chamber pressure of a second of the one or more process chambers is greater than the second chamber pressure of a first of the one or more process chambers, for example, in some embodiments, the first chamber pressure is about 1.5 to about 4 times greater than the second chamber pressure.

[0021] In some embodiments, the chuck holding the substrate is cooled between generating the first plasma and generating the second plasma, for example, in some embodiments, the substrate is cooled to a temperature of about 20° C. to about 60° C.

[0022] In some embodiments, the memory further stores computer-executable instructions for causing a diluent gas to be flowed in parallel with the metal-containing additive gas. For example, in some embodiments, the ratio of the flow rate of the metal-containing additive gas to the flow rate of the diluent gas is about 1:40 to about 1:100.

[0023] These and other aspects are described further below with reference to the drawings. [Brief description of the drawings]

[0024] [Figure 1A] FIG. 2 is a side view of a feature having various materials on its sidewalls. [Figure 1B] FIG. 2 is a side view of a feature having different materials on its sidewalls.

[0025] [Figure 1C] 1A-1D are top views of a substrate having features of different shapes.

[0026] [Diagram 2] FIG. 1 is a process flow diagram illustrating steps in a method performed in accordance with certain disclosed embodiments.

[0027] [Figure 3A] FIG. 1 illustrates an apparatus for plasma etching according to one embodiment. [Figure 3B] FIG. 1 illustrates an apparatus for plasma etching according to one embodiment. [Figure 3C] FIG. 1 illustrates an apparatus for plasma etching according to one embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0028] In the following description, numerous specific details are set forth in order to provide a thorough understanding of the presented embodiments. The disclosed embodiments may be practiced without some or all of these specific details. In other instances, well-known process steps have not been described in detail so as not to unnecessarily obscure the disclosed embodiments. Although the disclosed embodiments will be described in connection with specific embodiments, it will be understood that they are not intended to limit the disclosed embodiments.

[0029] Semiconductor fabrication processes can involve the fabrication of a variety of structures. In some cases, some structures can be formed whereby multiple alternating layers of material in a stack are formed on a substrate, followed by etching vertical features into the layers of material. In some embodiments, the alternating layers can be alternating oxide and nitride layers, such as those used in the fabrication of 3D-NAND devices. In some embodiments, some structures can involve multiple alternating layers that change composition depending on the depth of the layer of material, and the sidewalls of features formed in the alternating layers include first two alternating materials and then second two alternating materials, such that the point where the alternating materials change is different depending on the depth of the alternating layers in the overall stack. In some embodiments, a portion of some features can include one material, while a portion of some features includes multiple materials, and another portion includes multiple alternating materials. In addition, some structures can include features having sidewalls that include a first set of alternating layers, followed by a second set of alternating layers, followed by a third or more sets of alternating layers, and where the materials, or compositions, within the alternating layers vary within one sidewall of the feature and may differ from those of a second sidewall within the same feature. Such features can be referred to as "mixed features," i.e., the feature has multiple alternating material compositions within its sidewalls.

[0030] FIG. 1A shows an example cross-section of a side view of a stack having a negative feature 101 with all oxide 103 on the right sidewall and some oxide 103, but then alternating oxide 103 and nitride 105 sidewalls on the left. FIG. 1B shows an example cross-section of a side view of a stack having a negative feature 101 with sidewalls that have some oxide 103, and some nitride 105, as well as a third material 107, such as carbide. Although one feature is shown, it will be understood that multiple features, with sidewall variations at each feature, can be present on a single substrate. Such substrates can be difficult to etch consistently and uniformly across features, both across the wafer and within the depth of the feature, especially in very deep features, such as features having a depth of at least about 8000 nm.

[0031] The features may also have different sizes or shapes across the substrate, making it difficult to maintain the profile of the features and shapes. An example is shown in FIG. 1C, which shows a top view of a substrate with various features 109, 111, and 113 with different diameters, shapes, and x:y ratios. In addition, such features may have a particular feature size, which may be measured by its aspect ratio, or its depth, and its width. Such features may also have a particular shape, such as having vertical sidewalls, or having a circular shape from a top view, or a trench shape from a top view. Existing techniques for etching such features face various challenges, including undercutting, non-uniform etching along the sidewalls of the features, feature size variation during etching and in subsequent steps, pattern loading effects, non-uniform chipping on the sidewalls, charging effects between the oxide and oxide / nitride regions, feature shape variation during etching, feature profile distortion, feature bending, and others. In addition, it is difficult to uniformly etch different materials, different feature sizes, different feature shapes, and different feature depths using a single etching step.

[0032] Provided herein are methods and apparatus for etching mixed features while maintaining feature shape and size, thereby reducing pattern loading effects. The methods involve including a metal-containing gas exposure step during, after, or both etching, using low plasma power, low temperature, and high pressure. In various embodiments, the metal-containing gas includes tungsten. In some embodiments, the metal-containing gas includes a halogen. In various embodiments, the metal-containing gas is tungsten hexafluoride. The plasma power is adjusted at high plasma power, for example, with the metal-containing gas to prevent chipping into the sidewall of the feature, and the gas can act as a harsh etchant. Tungsten can cause the formation of tungsten by-products on the surface of the sidewall, causing deformation or striations from the crystallized tungsten by-product. Where high plasma power is used during the introduction of the metal-containing gas, sidewall surfaces that include nitrogen or nitride in the feature can etch more quickly compared to oxide surfaces. As a result, adjusting the plasma power can substantially affect the feature profile. Low temperature and high pressure may be used to reduce the formation of crystallized metal by-products. In various embodiments, the metal-containing gas is diluted with an inert gas such as argon or krypton. The metal-containing gas may be added during the main etch (e.g., when the main etch gas is introduced) or may be performed as a separate flash step inserted in short periodic exposures during the etch step. In some embodiments, the flash step is performed only occasionally during the main etch step, which is performed at high plasma. Without being bound to a particular theory, it is believed that the short exposure and the adjusted process conditions of the metal-containing gas cause some surface modification that uniforms the etching of the sidewalls during the formation of negative features in complex mixed material stacks.

[0033] Although the following description focuses on etching one particular mixed material stack with a metal-containing additive gas, aspects of the disclosure may also be implemented to etch other materials, including one or other structures to maintain feature profile.

[0034] FIG. 2 shows an example process flow diagram illustrating steps that may be performed by certain disclosed embodiments. In step 201, a substrate is provided having a mixed material stack formed thereon. The implementations disclosed below describe the deposition of materials onto a substrate, such as a wafer, substrate, or other workpiece. The workpieces may be of various shapes, sizes, and materials. In this application, the terms "semiconductor wafer," "wafer," "substrate," "wafer substrate," and "partially fabricated integrated circuit" are used interchangeably. Those skilled in the art will appreciate that the term "partially fabricated integrated circuit" may refer to a silicon wafer during the various stages of integrated circuit fabrication thereon. Wafers or substrates used in the semiconductor device industry typically have diameters of 200 mm, or 300 mm, or 450 mm. Unless otherwise stated, the process details (e.g., flow rates, power levels, etc.) described herein are applicable for processing of 300 mm diameter substrates and for processing chambers configured to process 300 mm diameter substrates, and may be scaled as appropriate for other sized substrates or chambers. In addition to semiconductor wafers, other workpieces that may be used in the implementations disclosed herein include a variety of items such as printed circuit boards and the like. The processes and apparatus may be used in the fabrication of semiconductor devices, displays, LEDs, solar panels, and the like. The substrate may be a silicon wafer, e.g., a 200 mm wafer, a 300 mm wafer, or a 450 mm wafer, including wafers having one or more layers of material deposited thereon, such as dielectric, conductive, or semiconductive materials.

[0035] The substrate has a mixed material stack formed thereon. The mixed material stack has two or more layers, each layer having one, two, or more materials in a single layer. Each layer can be about 100 Å to about 500 Å, or up to about 50 nm thick. Each layer can have a different thickness. In some embodiments, the mixed material stack includes one or more of an oxide, a carbide, and / or a nitride. In some embodiments, the mixed material stack includes one or more of an oxide material, a nitride material, alternating layers of oxide and nitride, alternating layers of polysilicon and oxide, three alternating layers of oxide, nitride, and polysilicon, and silicon oxynitride. For example, mixed material stacks can include ONON (oxide-nitride-oxide-nitride) stacks, OPOP (silicon oxide on polysilicon) stacks, or OMOM stacks (silicon oxide on metals such as tungsten, cobalt, or molybdenum), and features can be formed in such multilayer substrates, with sidewalls of the features including more than one composition. Stacks of multiple thin layers can range from bilayers (such as ON) to 5000 composite layers (such as {ON} 150 )

[0036] Oxides include, but are not limited to, metal oxides, semiconductor oxides, and dielectric oxides. Oxides include undoped oxides and doped oxides. An example oxide is silicon oxide. An example oxide is undoped silicon dioxide. "Silicon oxide" is used herein to refer to Si x O y The term "silicon oxide" refers to compounds containing silicon and oxygen atoms, including any and all stoichiometric possibilities for x and y, including integer values ​​of x and y, and non-integer values ​​of x and y. For example, "silicon oxide" refers to compounds having the chemical formula SiO n where 1≦n≦2, and n can be an integer or a non-integer. "Silicon oxide" includes compounds having the formula SiO 1.8"Silicon oxide" includes silicon dioxide (SiO2) and silicon monoxide (SiO). "Silicon oxide" also includes both natural and synthetic variants, and also includes any and all crystalline and molecular structures that include tetrahedral coordination of oxygen atoms surrounding a central silicon atom. "Silicon oxide" also includes amorphous silicon oxides and silicates.

[0037] Carbides include, but are not limited to, metallic carbides, semiconducting carbides, and dielectric carbides. Carbides include undoped and doped carbides. One example carbide is silicon carbide.

[0038] Nitrides include, but are not limited to, metal nitrides, semiconductor nitrides, and dielectric nitrides. Nitrides include undoped and doped nitrides. One exemplary nitride is undoped silicon nitride. "Silicon nitride" is defined herein as Si x N y The term "silicon nitride" refers to any or all stoichiometric possibilities for x, y, x=3, y=4, and x=y=1, y=2, y=3, y=4, and includes integer values ​​of x and y, as well as non-integer values ​​of x and y. For example, "silicon nitride" has the chemical formula SiN n where 1≦n≦2, and n can be an integer or a non-integer. "Silicon nitride" includes compounds having the formula: SiN 1.8 "Silicon nitride" can include substoichiometric compounds such as Si3N4, and silicon nitride with traces and / or interstitial hydrogen (SiNH), and silicon nitride with traces and / or interstitial oxygen (SiON). "Silicon nitride" also includes both natural and synthetic variants, and also includes any and all lattice, crystal, and molecular structures, including trigonal alpha silicon nitride, hexagonal beta silicon nitride, and cubic gamma silicon nitride. "Silicon nitride" also includes amorphous silicon nitride, and can include silicon nitride with trace amounts of impurities.

[0039] In some embodiments, the mixed material stack includes some regions having silicon oxide and some regions having alternating silicon oxide and silicon nitride layers, each layer having a thickness of about 10 Å to about 50 Å. The mixed material stack may have a total thickness of about 8000 nm to about 20000 nm. The mixed material stack may be formed over a semiconductor substrate. The mixed material stack may not have features etched thereon. In some embodiments, some features may be etched thereon. In some embodiments, the mixed material stack may have one or more etch masks thereon.

[0040] In step 203, the mixed material stack is exposed to an etching gas to partially form a negative feature in the mixed material stack. Any etching process used to etch mixed material stacks can be used in step 203. The etching gas can include a halogen-containing gas, such as a fluorocarbon gas or a hydrofluorocarbon gas. Exemplary etchants for etching silicon oxide include nitrogen trifluoride, fluoroform (CHF3), octafluorocyclobutane (C4F8), tetrafluoromethane (CF4), and combinations thereof. Exemplary etchants for etching silicon carbide, silicon nitride, silicon, tungsten, ruthenium, copper, cobalt, and molybdenum for feature filling with these materials include hydrobromic acid (HBr), fluoromethane (CH3F), chlorine (Cl2), silicon tetrafluoride (SiF4), tetrafluoromethane (CF4), boron trichloride (BCl), fluoroform (CHF3), and combinations thereof. In various embodiments, the etchant may be flowed with one or more inert gases, such as argon.

[0041] In various embodiments, step 203 is a continuous etching process by sequentially flowing one or more etching gases. In various embodiments, step 203 involves a cyclic etching process by exposing the mixed material stack to time-separated pulses of etching gases. In some embodiments, the etching in step 203 is performed by igniting a plasma. In some embodiments, the plasma is ignited using a radio frequency plasma. In various embodiments, the plasma is generated in situ. In some embodiments, the plasma may be remotely generated in a remote plasma chamber prior to delivery to the process chamber housing the substrate. In various embodiments, the plasma is ignited while flowing the etching gas using a plasma power between about 10,000 W and about 50,000 W for a single station chamber.

[0042] In various embodiments, step 203 involves a high plasma power etching process using at least one halogen-containing gas. In one example, step 203 involves at least one cycle of etching performed by (1) introducing a fluorocarbon gas in a pulse and (2) introducing a hydrofluorocarbon gas in a pulse, both pulses performed while igniting a plasma using high plasma power, such as at least about 30,000 W or more, for a single station chamber. The single station chamber can be on a platform that can hold up to about 10 chambers. Introducing a hydrofluorocarbon gas can be referred to as a hydrogen-rich etching step. In some embodiments, step 203 is performed by alternating between a fluorocarbon gas exposure and a hydrogen-rich fluorocarbon gas exposure. The flow rate of the etching gas depends on the etching gas mixture and composition, the chamber size, and other factors. In some embodiments, the flow rate of the etching gas is about 4 sccm for a 20 second exposure.

[0043] In various embodiments, step 203 may be performed at a chamber pressure between about 10 mTorr and about 50 mTorr. In various embodiments, step 203 may be performed using a substrate temperature between about −20° C. and about 100° C. It will be understood that the substrate temperature is the temperature set for the pedestal that holds the substrate.

[0044] At step 205, a metal-containing additive gas is introduced at controlled, mild process conditions to bring metal to the exposed surfaces of the mixed material stack. The brought metal prevents line bending, maintains the structural integrity and profile of the feature structures, and minimizes the formation of metal by-products on the mixed material stack. The metal-containing additive gas can be a tungsten-containing gas. In some embodiments, the metal-containing additive gas is a halogen-containing gas. In various embodiments, the metal-containing additive gas is a volatile metal compound. In some embodiments, the metal-containing additive gas is tungsten hexafluoride (WF6). Further non-limiting examples include molybdenum hexafluoride (MoF6), titanium tetrachloride (TiCl4), tin tetrachloride (SnCl4), tungsten hexacarbonyl (W(CO)6), molybdenum hexacarbonyl (Mo(CO)6), tetrakis(diethylamino)titanium(IV) ([(C2H5)2N]4Ti), (C5H5)WH2, and combinations thereof. In some embodiments, the metal-containing additive gas is diluted in an inert gas, such as argon, krypton, helium, or combinations thereof.

[0045] The controlled mild process conditions include one or more of low plasma power, high chamber pressure, and low temperature. In various embodiments, the plasma power used in step 205 is less than the plasma power used in step 203. In some embodiments, the plasma power used in step 205 is less than about 20% of the plasma power used in step 203. In some embodiments, the plasma power used in step 205 is less than about 10% of the plasma power used in step 203. In some embodiments, the plasma power used in step 205 is about 1% to about 2% of the plasma power used in step 203. In some embodiments, the plasma power used in step 205 is about 200 W for a four station station.

[0046] In various embodiments, the chamber pressure used in step 205 is higher than the chamber pressure used in step 203. In some embodiments, the chamber pressure used in step 205 is 1.5 times higher than the chamber pressure used in step 203. In some embodiments, the chamber pressure used in step 205 is 4 times higher than the chamber pressure used in step 203. In some embodiments, the chamber pressure is between about 20 mTorr and about 100 mTorr.

[0047] In various embodiments, the substrate temperature used in step 205 is less than the substrate temperature used in step 203. In some embodiments, the substrate temperature used in step 205 is less than about 20° C. In some embodiments, the substrate temperature used in step 205 is less than about 60° C. In some embodiments, the substrate temperature used in step 205 is between about 20° C. and about 100° C.

[0048] The selection of which process conditions to use under milder conditions in step 205 depends on the material being etched and the structure of the mixed material stack. In some embodiments, at least one process condition is adjusted. In some embodiments, two or more process conditions are adjusted. In some embodiments, only the plasma power is adjusted. In some embodiments, only the pressure is adjusted. In some embodiments, only the substrate temperature is adjusted. In some embodiments, only the plasma power and the pressure are adjusted. In some embodiments, only the plasma power and the substrate temperature are adjusted. In some embodiments, only the pressure and the substrate temperature are adjusted. In some embodiments, the plasma power, the pressure, and the temperature are all adjusted. In some embodiments, other process conditions are adjusted, such conditions being adjusted alone or in combination with one or more other process conditions. For example, the duration of exposure to the metal-containing additive gas may be adjusted. To achieve the effect of using a metal-containing additive gas, a very small amount of metal may be used in step 205. In another example, the amount and selection of a diluent gas flowed with the metal-containing additive gas is adjusted. Exemplary diluent gases include argon or krypton. The diluent gas is an inert gas and may be flowed in parallel with the metal-containing additive gas.

[0049] The flow rate of the metal-containing additive gas may depend on the chamber size and other factors. In some embodiments, the flow rate of the metal-containing additive gas is less than about 25% of the flow rate of the gas used during step 203. In some embodiments, the flow rate of the metal-containing additive gas is between about 0.5 sccm and about 5 sccm. The flow rate of the diluent or inert gas flowed with the metal-containing additive gas depends on the flow rate of the metal-containing additive gas. For lower flow rates of the metal-containing additive gas, the diluent or inert gas may be flowed at a higher flow rate, or composition percentage of the total flow rate, to enable effective delivery of the gas to the process chamber housing the substrate. In some embodiments, the ratio of the flow rate of the metal-containing additive gas to the flow rate of the inert gas is between about 1:40 and about 1:100.

[0050] In some embodiments, step 205 is performed for a particular duration. For example, step 205 may be performed as a "flash" step after any etching has been performed in step 203, prior to completing the etching of features into the mixed material stack. The "flash" step may last for a duration of about 1 second to about 30 seconds, or about 10 seconds to about 20 seconds. The duration of step 205 may be increased as the etch is performed deeper into the mixed material stack.

[0051] In some embodiments, steps 203 and 205 are performed in different chambers. In some embodiments, steps 203 and 205 are performed in the same chamber. In some embodiments, steps 203 and 205 are performed without breaking vacuum. For example, in some embodiments, steps 203 and 205 are performed in separate stations in a multi-station chamber without breaking vacuum. The disclosed embodiments promote efficiency since deposition and etching can be performed in the same chamber or in the same tool. In some embodiments, the process chamber is purged between steps 203 and 205. Purging the chamber can involve flowing a purge or sweep gas, which can be the carrier gas used in the other steps or can be a different gas. Exemplary purge gases include argon, nitrogen, hydrogen, and helium. In various embodiments, the purge gas is an inert gas. Exemplary inert gases include argon, nitrogen, and helium. In some embodiments, purging can involve evacuating the chamber. In some embodiments, purging may include one or more evacuation sub-phases to evacuate the process chamber. Alternatively, it will be appreciated that in some embodiments, purging may be omitted. Purging may be performed for any suitable duration, such as between about 0.1 seconds and about 2 seconds.

[0052] At step 207, step 203 is optionally repeated. At step 209, step 205 is optionally repeated. In some embodiments, step 205 is performed before step 203. In some embodiments, step 205 is performed after step 203. In some embodiments, steps 203 and 205 are performed multiple times. The repeated steps of steps 203 and 205 can be performed sequentially or variably. In some embodiments, step 205 is performed periodically during step 203. In some embodiments where step 205 involves cyclic exposure to an etching gas, step 205 is inserted after every n cycles, where n is any integer equal to or greater than 1. In some embodiments, step 205 is sometimes performed every n cycles, or sometimes after all cycles have been performed in step 203, or sometimes depending on the condition of the mixed material stack, the composition of the sidewalls in the features formed from the etching in step 203, and other factors.

[0053] Step 205 is performed to achieve reduced feature twist, reduced feature distortion, improved or maintained feature ovality (such as maintaining a feature ovality of about 1 for a particular feature, or having a feature ovality difference of about 0 between the incoming and resulting features), reduced sidewall roughness, and reduced or eliminated chipping effects.

[0054] Device The methods described herein may be performed by any suitable apparatus. In various embodiments, a suitable apparatus includes a process chamber configured for plasma processing and a controller configured to perform any of the methods described herein. As mentioned above, example apparatus that may be used to perform the etching processes described herein include the FLEX™ and VANTEX™ families of reactive ion etching reactors available from Lam Research Corporation, Fremont, Calif.

[0055] 3A-3C diagrammatically illustrate an embodiment of an adjustable gap capacitively coupled confined radio frequency (RF) plasma reactor 300 that may be used to perform the etching process described herein. As shown, a vacuum chamber 302 includes a chamber housing 304 that encloses an interior space that houses a lower electrode 306. Within the upper portion of the chamber 302, an upper electrode 308 is vertically spaced apart from a lower electrode 306. The planes of the upper and lower electrodes 308, 306 are substantially parallel and perpendicular to the vertical direction between the electrodes. The upper and lower electrodes 308, 306 are preferably circular and coaxial with respect to a vertical axis. The lower surface of the upper electrode 308 faces the upper surface of the lower electrode 306. The spaced apart opposing electrode surfaces define an adjustable gap 310 therebetween. During the process, the lower electrode 306 is supplied with RF power by an RF power source (matched) 320. RF power is supplied to the lower electrode 306 through an RF supply conduit 322, an RF strap 324, and an RF power member 326. A ground shield 336 may surround the RF power member 326 to provide a more uniform RF field to the lower electrode 306. As described in commonly owned U.S. Pat. No. 7,732,728, which is incorporated herein by reference in its entirety, a wafer is inserted through a wafer port 382 and supported in a gap 310 on the lower electrode 306 for processing, and process gas is supplied to the gap 310 and excited into a plasma state by RF power. The upper electrode 308 may be powered or grounded.

[0056] If one or more chemical species delivered to the plasma reactor 300 are stored as liquids, a modified gas delivery system (not shown) may be used. For example, the modified gas delivery system may include hardware for vaporizing liquid-phase chemical species (e.g., bubblers, evaporators, etc.), as well as appropriate piping (e.g., hot gas lines and valves) and control equipment (e.g., hot mass flow controllers and / or liquid flow controllers) for implementing reactant delivery.

[0057] 3A-3C, the lower electrode 306 is supported on a lower electrode support plate 316. An insulator ring 314 is placed between the lower electrode 306 and the lower electrode 308. The support plate 316 insulates the lower electrode 306 from the support plate 316.

[0058] RF bias housing 330 supports lower electrode 306 on RF bias housing bowl 332. Bowl 332 is connected to conduit support plate 338 by arm 334 of RF bias housing 330 through an opening in chamber wall plate 318. In a preferred embodiment, RF bias housing bowl 332 and RF bias housing arm 334 are integrally formed as one component, however, arm 334 and bowl 332 could be two separate components bolted or bonded together.

[0059] The RF bias housing arm 334 includes one or more hollow passages for passing RF power and equipment, such as gas coolant, fluid coolant, RF energy, cables for lift pin control, electrical monitoring and actuation signals, from outside the vacuum chamber 302 in the space behind the lower electrode 306 to inside the vacuum chamber 302. The RF supply conduit 322 is insulated from the RF bias housing arm 334, which provides a return path for RF power to the RF power source 320. The equipment conduit 340 provides a passage for the equipment components. Further details of the equipment components are described in U.S. Pat. Nos. 5,948,704 and 7,732,728 and are not shown here for ease of illustration. The gap 310 is preferably surrounded by a confinement ring assembly or shroud (not shown), details of which may be found in commonly owned issued U.S. Pat. No. 7,740,736, which is incorporated herein by reference. The interior of the vacuum chamber 302 is maintained at low pressure by connection to a vacuum pump through a vacuum portal 380 .

[0060] The conduit support plate 338 is attached to an actuating mechanism 342. Details of the actuating mechanism are described in commonly owned U.S. Patent No. 7,732,728, incorporated herein by reference above. The actuating mechanism 342, such as a servomechanical motor, stepper motor, or the like, is attached to a vertical linear bearing 344 by a screw gear 346, such as a ball screw and a motor for rotating the ball screw. During the process for adjusting the size of the gap 310, the actuating mechanism 342 advances along the vertical linear bearing 344. FIG. 3A illustrates the arrangement when the actuating mechanism 342 is in a high position on the linear bearing 344, resulting in a small gap 310a. FIG. 3B illustrates the arrangement when the actuating mechanism 342 is in a center position on the linear bearing 344. As shown, the lower electrode 306, RF bias housing 330, conduit support plate 338, and RF power supply 320 have all been moved lower relative to the chamber housing 304 and upper electrode 308, resulting in a medium sized gap 310b.

[0061] 3C illustrates a larger gap 310c when the actuation mechanism 342 is in a low position on the linear bearing. The upper and lower electrodes 308, 306 preferably remain coaxial during gap adjustment, and the facing surfaces of the upper and lower electrodes across the gap are parallel.

[0062] This embodiment allows the gap 310 between the lower and upper electrodes 306, 308 in the CCP chamber 302 to be adjusted during multi-step process recipes (such as BARC, HARC, and STRIP) to maintain uniform etching across large diameter substrates, such as 300 mm wafers or flat panel displays. In particular, this chamber involves a mechanical arrangement that allows for the linear motion necessary to provide an adjustable gap between the lower and upper electrodes 306, 308.

[0063] 3A illustrates a sealed, laterally biased bellows 350 at its proximal end to the conduit support plate 338 and at its distal end to a stepped flange 328 of the chamber wall plate 318. The inner diameter of the stepped flange defines an opening 312 in the chamber wall plate 318 through which the RF bias housing arm 334 passes. The distal end of the bellows 350 is clamped by a clamp ring 352.

[0064] The laterally biased bellows 350 provides a vacuum seal while allowing vertical movement of the RF bias housing 330, conduit support plate 338, and actuation mechanism 342. The RF bias housing 330, conduit support plate 338, and actuation mechanism 342 may be referred to as a cantilever assembly. The RF power supply 320 preferably moves with the cantilever assembly and may be attached to the conduit support plate 338. Figure 3B shows the bellows 350 in a neutral position when the cantilever assembly is in a center position. Figure 3C shows the laterally biased bellows 350 when the cantilever assembly is in a low position.

[0065] The labyrinth seal 348 provides a particle barrier between the bellows 350 and the interior of the plasma processing chamber housing 304. The fixed shield 356 is fixedly attached to the inner interior wall of the chamber housing 304 at the chamber wall plate 318 to provide a labyrinth groove 360 ​​(slot) within which the movable shield plate 358 moves vertically to accommodate the vertical movement of the cantilever assembly. An outer portion of the movable shield plate 358 remains within the slot at all vertical positions of the lower electrode 306.

[0066] In the embodiment shown, the labyrinth seal 348 includes a fixed shield 356 attached to an inner surface of the chamber wall plate 318 around an opening 312 in the chamber wall plate 318 that defines a labyrinth groove 360. A movable shield plate 358 is attached to and extends radially from an RF bias housing arm 334, where the arm 334 passes through the opening 312 in the chamber wall plate 318. The movable shield plate 358 extends into the labyrinth groove 360, spaced from the fixed shield 356 by a first gap and spaced from the inner surface of the chamber wall plate 318 by a second gap, allowing the cantilever assembly to move vertically. The labyrinth seal 348 prevents migration of broken particles from the bellows 350 into the vacuum chamber interior 305 and prevents radicals from the process gas plasma from migrating to the bellows 350 where they can form deposits that are subsequently broken down.

[0067] FIG. 3A shows the movable shield plate 358 in a higher position in the labyrinth groove 360 ​​above the RF bias housing arm 334 when the cantilever assembly is in a high position (small gap 310a). FIG. 3C shows the movable shield plate 358 in a lower position in the labyrinth groove 360 ​​above the RF bias housing arm 334 when the cantilever assembly is in a low position (large gap 310c). FIG. 3B shows the movable shield plate 358 in a neutral or center position in the labyrinth groove 360 ​​when the cantilever assembly is in a center position (medium gap 310b). Although the labyrinth seal 348 is shown symmetrically about the RF bias housing arm 334, in other embodiments the labyrinth seal 348 can be asymmetric about the RF bias arm 334.

[0068] The apparatus shown in FIGS. 3A-3C includes a controller configured to perform the methods described herein. In some implementations, the controller is part of a system, which may be part of the examples described above. Such a system may include semiconductor processing equipment, including one or more processing tools, one or more chambers, one or more platforms for processing, and / or specific processing components (wafer pedestals, gas flow systems, etc.). These systems may be integrated with electronics for controlling their operation before, during, and after the processing of semiconductor wafers or substrates. The electronics may be referred to as a "controller," which may control various components or subparts of one or more systems. The controller may be programmed to control any of the processes disclosed herein, including delivery of process gases, temperature settings (e.g., heating and / or cooling), pressure settings, vacuum settings, power settings, radio frequency (RF) generator settings, RF matching circuit settings, frequency settings, flow settings, fluid delivery settings, positional and operational settings, wafer transfer into and out of tools and other transfer tools and / or load locks connected or interfaced to a particular system, depending on the processing conditions and / or type of system.

[0069] Generally speaking, a controller may be defined as an electronic device having various integrated circuits, logic, memory, and / or software that receive instructions, issue instructions, control operations, enable cleaning operations, enable end-point measurements, etc. Integrated circuits may include chips in the form of firmware that store program instructions, digital signal processors (DSPs), chips defined as application specific integrated circuits (ASICs), and / or one or more microprocessors or microcontrollers that execute program instructions (e.g., software). Program instructions may be instructions communicated to the controller in the form of various individual settings (or program files) that define operating parameters for performing a particular process on or for a semiconductor wafer or for a system. The operating parameters may, in some embodiments, be part of a recipe defined by a process engineer to accomplish one or more processing steps during the fabrication of one or more layers, materials, metals, oxides, silicon, silicon dioxide, surfaces, circuits, and / or dies of a wafer.

[0070] The controller, in some implementations, may be part of or coupled to a computer that is integrated, coupled, otherwise networked to the system, or a combination thereof. For example, the controller may reside in the "cloud," or all or part of a fab host computer system, which allows remote access of wafer processing. The computer may allow remote access to the system to monitor the current progress of a fabrication process, look at the history of past fabrication processes, look at trends or performance metrics from multiple fabrication processes, change parameters of a current process, set processing steps following a current process, or start a new process. In some examples, a remote computer (e.g., a server) may provide a process recipe to the system over a network, which may include a local network or the Internet. The remote computer may include a user interface, which allows for entry or programming of parameters and / or settings, which are then communicated from the remote computer to the system. In some examples, the controller receives instructions in the form of data that specify parameters for each of the processing steps to be performed during one or more processes. It should be understood that the parameters may be specific to the type of process to be performed and the type of tool with which the controller is configured to interface or control. Thus, as described above, the controller may be distributed, such as by including one or more individual controllers networked together and working toward a common purpose, such as the processes and controls described herein. An example of a controller distributed for such purposes would be one or more integrated circuits on the chamber that communicate with one or more remotely located integrated circuits (such as at the platform level or as part of a remote computer) that together control the process on the chamber.

[0071] Without limitation, example systems may include a plasma etch chamber or module, a deposition chamber or module, a spin rinse chamber or module, a metal plating chamber or module, a cleaning chamber or module, a bevel edge etch chamber or module, a physical vapor deposition (PVD) chamber or module, a chemical vapor deposition (CVD) chamber or module, an atomic layer deposition (ALD) chamber or module, an atomic layer etch (ALE) chamber or module, an ion implantation chamber or module, a track chamber or module, and any other semiconductor processing system that may be associated with or used in the fabrication and / or production of semiconductor wafers.

[0072] As noted above, depending on the process step or steps to be performed by the tool, the controller may communicate with one or more of other tool circuits or modules, other tool components, cluster tools, other tool interfaces, adjacent tools, nearby tools, tools located throughout the factory, a main computer, other controllers, or tools used in material transport carrying containers of wafers to or from the tool's locations and / or load ports within a semiconductor production factory.

[0073] experiment Experiments were performed to etch high aspect ratio features in the ONON stack and in oxide only material using an etching gas without a metal-containing additive gas. At the bottom of the high aspect ratio features in the ONON stack, the etch did not reach the etch stop layer at the bottom of the stack in some areas but reached other areas resulting in depth loading issues. Hole profiles showed some partially etched features. Similar substrates were exposed to the etching gas while using a tungsten hexafluoride additive gas at low plasma power and high pressure during etching. The resulting substrates showed improved profile shape retention, reduced bowing on the oxide substrate, and improved depth loading.

[0074] conclusion Although the above embodiments have been described in some detail for purposes of clarity of understanding, it will be apparent that certain changes and modifications may be implemented within the scope of the appended claims. It should be noted that there are many alternative ways of implementing the process, system, and apparatus of the present embodiments. Thus, the present embodiments should be considered as illustrative and not restrictive, and the embodiments are not limited to the details shown herein.

Claims

1. 1. A method for processing a substrate, comprising: Providing a substrate having a mixed material stack; igniting a first plasma at a first plasma power to expose the mixed material stack to one or more etching gases and partially etch features into the mixed material stack to form a partially etched mixed material stack; exposing the partially etched mixed material stack to a second plasma generated from igniting a metal-containing additive gas at a second plasma power, the second plasma power being less than the first plasma power; A method comprising:

2. 2. The method of claim 1, wherein the metal-containing additive gas is a halogen.

3. 10. The method of claim 1, wherein the metal-containing additive gas comprises a metal selected from the group consisting of tungsten, tin, molybdenum, and titanium.

4. The method of claim 1 , wherein the second plasma power is about 1% to about 10% less than the first plasma power.

5. 10. The method of claim 1, wherein exposing the partially etched mixed material stack to the second plasma is performed at a first chamber pressure that is higher than a second chamber pressure used during the exposing the mixed material stack to the one or more etching gases.

6. 10. The method of claim 1, wherein the exposing the partially etched mixed material stack to the second plasma is performed using a first substrate temperature that is less than a second substrate temperature used during the exposing the mixed material stack to the one or more etching gases.

7. 10. The method of claim 1, wherein the exposing the partially etched mixed material stack to the second plasma occurs for a duration of less than about 20 seconds.

8. 2. The method of claim 1, wherein the one or more etching gases include at least one gas comprising fluorine and carbon atoms.

9. 10. The method of claim 1, wherein the metal-containing additive gas is diluted in an inert gas.

10. 1. An apparatus for processing a substrate, comprising: one or more process chambers, each process chamber comprising a chuck; A plasma generator; a first gas source for containing one or more etching gases; a second gas source for containing a metal-containing additive gas; one or more gas inlets to the process chamber and associated flow control hardware for delivering gas from the first gas source and the second gas source to the one or more process chambers; A controller having at least one processor and a memory, the at least one processor and the memory are communicatively coupled to each other; the at least one processor is at least operatively connected to the flow control hardware; The memory includes: causing a substrate to be brought into a first of the one or more process chambers; causing a first plasma to be generated using one or more etching gases at a first plasma power; causing a second plasma to be generated using a metal-containing additive gas at a second plasma power; storing computer-executable instructions for controlling the at least one processor to at least control the flow control hardware to perform: the second plasma power is less than the first plasma power. An apparatus comprising:

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