How to Etch Molybdenum

Abstract

A substrate processing method comprising: providing a substrate including an etch mask on a metallic molybdenum layer in a recessed feature; exposing the substrate to a plasma excited deposition gas that forms an etching protection layer on a sidewall of the recessed feature; and exposing the substrate to a plasma excited etching gas that etches the metallic molybdenum layer according to the etch mask, the exposing steps being performed alternately multiple times.

Description

[Technical field]

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS This application claims the benefit of U.S. Provisional Patent Application No. 63 / 287,371, filed December 8, 2021, which is incorporated herein by reference.

[0002] The present invention relates generally to methods for fabricating semiconductor devices, and in a particular embodiment, to a method for dry etching molybdenum. [Background technology]

[0003] A semiconductor integrated circuit (IC) is a network of electronic components built by sequentially depositing and patterning layers of various materials to form monolithic structures on a substrate. Each new technology node roughly doubles the component density and reduces the unit cost of ICs. Enabled by advances in patterning, hundreds of transistors can be fabricated on chips as small as 1 μm. 2 1000m2, and can be packed into an area of ​​100m2 and connected to signals and power by metal lines with half pitches of less than 15nm. The resistance of such fine lines is mainly dependent on conduction near the edges. Liners used as metal diffusion barriers and random electron scattering along metal edges result in the narrow width effect (NWE), where resistance rises sharply with decreasing width. Therefore, for nodes below 5nm, molybdenum metal is an interesting metal for wires at the highest density interconnect levels due to its low diffusivity in silicon oxide (eliminating the need for diffusion barriers), low bulk mean free path (less edge scattering), high melting point, and low thermal expansion coefficient. While molybdenum has promising properties, integrating it into high volume IC manufacturing requires dry etching methods with good control of etch profile, etch rate, and etch selectivity to masking materials and underlying layers. Therefore, further innovations in the process of dry etching of molybdenum metal are desirable. Summary of the Invention [Means for solving the problem]

[0004] A substrate processing method comprising: providing a substrate including an etch mask on a metallic molybdenum layer in a recessed feature; exposing the substrate to a plasma excited deposition gas that forms an etching protection layer on a sidewall of the recessed feature; and exposing the substrate to a plasma excited etching gas that etches the metallic molybdenum layer according to the etch mask, the exposing steps being performed alternately multiple times.

[0005] A method of processing a substrate, the method comprising: providing a substrate including an etch mask over a metallic molybdenum layer in a recessed feature; depositing an etch protection layer in the recessed feature, the etch protection layer including an oxide layer; performing a breakthrough etch step to etch through the etch protection layer at a bottom of the recessed feature; and exposing the substrate to a plasma excited etch gas that etches the metallic molybdenum layer according to the etch mask.

[0006] 1. A method of processing a substrate, comprising: providing a substrate including an etch mask on a metal molybdenum layer in a recessed feature; depositing an etch protection layer on sidewalls of the etch mask, the etch protection layer including an oxide layer; and exposing the substrate to a plasma-excited etching gas that etches the metal molybdenum layer in accordance with the etch mask, the deposition and exposure being performed alternately multiple times.

[0007] For a more complete understanding of the present invention, and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which: [Brief description of the drawings]

[0008] [Figure 1A] 1 illustrates a flow chart summarizing a process flow for patterning a molybdenum layer, according to an embodiment. [Figure 1B]1A-1C illustrate cross-sectional views of a semiconductor device at various intermediate steps of the process flow summarized in the flowchart illustrated in FIG. [Figure 1C] 1A-1C illustrate cross-sectional views of a semiconductor device at various intermediate steps of the process flow summarized in the flowchart illustrated in FIG. [Figure 1D] 1A-1C illustrate cross-sectional views of a semiconductor device at various intermediate steps of the process flow summarized in the flowchart illustrated in FIG. [Figure 2A] 1 illustrates a cross-sectional view of a semiconductor device showing undesirable etching characteristics and defects resulting from patterning a metal molybdenum layer using an anisotropic dry etch process having a poor process window. [Figure 2B] 1 illustrates a cross-sectional view of a semiconductor device showing undesirable etching characteristics and defects resulting from patterning a metal molybdenum layer using an anisotropic dry etch process having a poor process window. [Figure 3A] 1 illustrates a flow chart summarizing a gas pulse cyclic etch technique for patterning a molybdenum metal layer, according to an embodiment. [Figure 3B] 3B illustrates various cross-sectional views of a semiconductor device at various intermediate stages in patterning a molybdenum metal layer using the gas pulse cyclic etch technique summarized in the flow chart illustrated in FIG. 3A. [Figure 3C] 3B illustrates various cross-sectional views of a semiconductor device at various intermediate stages in patterning a molybdenum metal layer using the gas pulse cyclic etch technique summarized in the flow chart illustrated in FIG. 3A. [Figure 3D] 3B illustrates various cross-sectional views of a semiconductor device at various intermediate stages in patterning a molybdenum metal layer using the gas pulse cyclic etch technique summarized in the flow chart illustrated in FIG. 3A. [Figure 3E]3B illustrates various cross-sectional views of a semiconductor device at various intermediate stages in patterning a molybdenum metal layer using the gas pulse cyclic etch technique summarized in the flow chart illustrated in FIG. 3A. [Figure 3F] 3B illustrates various cross-sectional views of a semiconductor device at various intermediate stages in patterning a molybdenum metal layer using the gas pulse cyclic etch technique summarized in the flow chart illustrated in FIG. 3A. [Figure 4] 1 illustrates a flow chart summarizing an ALD-based cyclic etch technique for patterning a molybdenum metal layer, according to an embodiment. [Diagram 5] 1 illustrates a flow chart of a single cycle of a cyclic etch technique, according to an embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] An embodiment of a dry etching method for subtractive etching of molybdenum metal is described in this disclosure. In this disclosure, molybdenum metal refers to elemental molybdenum and its alloys, including molybdenum with small amounts of impurities and dopants. In subtractive etching of metal, a patterned etch mask is formed on a metal layer, and this pattern is transferred to the metal layer by directly etching recessed features that extend through the metal to form a pattern of metal lines. Typically, a dry etch process such as reactive ion etching (RIE) is used. Before forming the etch mask, the metal layer is uniformly formed on a planar surface of an interlayer dielectric (ILD) layer. After patterning the metal by subtractive etching, another ILD layer can be formed to fill the recessed features and cover the metal lines for isolation. For conventional copper interconnects, a more complex damascene process flow is used in which a patterned etch mask is used to etch trenches for metal lines into the ILD layer and overfilled with metal. The overfill material, including any metal deposited on top of the dielectric surfaces between the trenches, is then removed using, for example, chemical mechanical planarization (CMP) to form metal lines inlaid into the ILD. As known to those skilled in the art, depositing metal on top of a flat surface is simpler than filling 10-20 nm wide trenches with void-free metal. Furthermore, the CMP step is expensive, thus increasing the fabrication costs.

[0010] Patterning metals by subtractive etching is preferred over damascene etching because it is simpler and less expensive, as long as the etch process meets appropriate manufacturing criteria. For example, the etch process must meet specifications for etch rate, etch selectivity, sidewall profile, line edge roughness (LER) and defect density (e.g., for bridging and line breaking defects) with good control to achieve stable manufacturing. Described in this disclosure is a dry etch process for patterning metal layers including molybdenum that offers several advantages, such as suppression of lateral etching to reduce undercutting, low LER and more vertical edge profiles, in addition to improved control of etch rate and etch selectivity.

[0011] The ILD layer is typically a silicon oxide-based dielectric. Copper is a contaminant that easily diffuses into silicon oxide, so a continuous diffusion barrier lining the trench is required before filling the trench with copper. Typically, a liner is formed that is thick enough (e.g., 1.5 nm to 3 nm) to ensure that there are no holes or discontinuities at the edges and corners where copper can leak into the ILD and degrade the time-dependent dielectric breakdown (TDDB) lifetime of the interconnect structure. The liner can increase the resistance of the metal line in two main ways. The low resistivity core metal can be replaced by a liner material that includes a more resistive metal or insulator. In addition, a higher diffuse electron scattering rate at the core metal and liner interface can further increase the line resistance. Diffuse scattering along edges is more dominant in metals where the bulk mean free path (λ) of the electrons is longer than the cross-sectional dimensions of the line. The metal line resistance with decreasing W rises more rapidly than 1 / W due to edge effects, geometric effects (reduced cross-sectional area) and scattering effects (higher scattering rate at interfaces). Here, W refers to the line width including the liner. For example, in a damascene process, W would be the trench width. This means that the effective resistivity ρ(W) increases with decreasing W, an undesirable phenomenon referred to in this disclosure as the narrow width effect (NWE). The effective resistivity ρ(W) is the line resistance normalized to L / (Wt), where L is the length of the line and t is the thickness of the metal. Undesirable consequences of increasing ρ(W) due to NWE include more joule heating leading to larger ohmic drop (reduced circuit speed) and accelerated electromigration (EM) at higher temperatures. Copper exhibits strong NWE because it requires a diffusion barrier liner. For example, ρ(W) decreases to 10 nm when W is reduced to 10 nm, which is lower than its bulk resistivity (ρ o = 16.8 Ω-nm).

[0012] The strong NWE of copper lines is a concern when scaling copper interconnects, a concern that has driven research into replacing copper with suitable metals, at least at the lower metal levels where the most densely packed metal lines are located. As mentioned in the background paragraph, molybdenum does not require a diffusion barrier due to its low diffusivity in silicon oxide. Furthermore, at a short λ=11.2 nm, the diffuse scattering along the edges of the molybdenum lines is not as dominant as that along the edges of copper lines at λ=39.9 nm. Geometric effects (reduced cross-sectional area) become significant when W is below nearly ten times the liner thickness, while scattering effects (higher scattering rate at interfaces) severely impact ρ(W) when W is reduced below λ. Indeed, when comparing different metals, we use ρ as an indicator of the magnitude of the scattering effect component of the NWE. o × λ is often used as the metric ρ o ×λ is 670Ω-nm for copper 2 In comparison, molybdenum has a higher ρ o = 53.4 Ω-nm, ρ o ×λ is 600Ω-nm 2 Therefore, NWE is less severe in molybdenum than in copper. o and a low thermal expansion coefficient (5×10 -6 Molybdenum metal is being considered as an alternative to copper because of its other attractive properties, such as its high melting point (an indicator of good EM reliability) and stable interface with silicon oxide.

[0013] For the finest pitch wiring levels in IC designs, replacing damascene copper with barrier-free metal lines patterned using subtractive etching is one of several architectural changes that may be imminently required to meet the performance, power, area, and cost (PPAC) goals of technology scaling. As discussed above, molybdenum metal shows promise for this purpose. Integrating molybdenum wiring into an IC fabrication flow requires a process of forming a metal layer containing molybdenum metal on a substrate, forming a patterned etch mask on the metal layer, and transferring the pattern to the metal layer by etching a pattern of recessed features that extend through the metal layer. This disclosure describes an embodiment of a method for etching a pattern of recessed features that extend through the molybdenum metal layer to expose a portion of a major surface of an underlying layer. The method employs a cyclic process to separate control of the vertically progressing etch front from control of the sidewall profile, providing improved process optimization. For example, each cycle of the cyclic process may include a first portion using a set of process parameters and gases optimized to deposit a passivating solid by-product for sidewall protection, and a second portion using a different set of process parameters and gases optimized to selectively remove metallic molybdenum to vertically expand the recessed features. Temporal separation of the deposition and etch steps of the cyclic etch process allows for improved optimization that provides a wider process window, resulting in smooth vertical sidewalls with negligible undercut and footing defects during fabrication.

[0014] 1A illustrates a flow chart summarizing a process flow 100 for patterning a molybdenum metal layer using subtractive etching. Process flow 100 may be part of a fabrication flow for a semiconductor device 110 incorporating a layer of metal lines comprising molybdenum metal using embodiments described in this disclosure. The basic process steps of process flow 100 will be described with reference to cross-sectional views of semiconductor device 110 illustrated generally in FIGS. 1B-1D.

[0015] As indicated in box 102 of the flowchart of FIG. 1A, process flow 100 includes providing a substrate having a molybdenum metal layer formed on an underlayer and an etch mask patterned on the molybdenum metal layer. In box 104, a subtractive etch process is performed through the patterned etch mask to form a pattern of metal lines comprising molybdenum metal. The subtractive etch process includes a cyclic etch process. Each cycle of the cyclic etch process includes depositing an etch protection layer in the recessed features of the molybdenum metal layer and anisotropically etching the molybdenum metal. After the metal lines are formed, remaining portions of the etch mask may be removed, as indicated in box 106.

[0016] FIG. 1B illustrates a cross-sectional view of the semiconductor device 110 after a molybdenum metal layer 116 has been formed on the underlayer 114 and an etch mask 122 has been patterned on the molybdenum metal layer 116 as indicated in box 104 of the flow chart of FIG. 1A. The underlayer 114 may include a dielectric layer, such as an ILD layer including a low-k silicon oxide or an insulating etch stop layer in the ILD layer. The molybdenum metal layer 116 may be formed using a suitable film growth technique, such as plasma-enhanced chemical vapor deposition (PECVD). A thin adhesion layer (not shown) (e.g., TiN or TaN) may be optionally deposited on the underlayer 114 prior to forming the molybdenum metal layer 116. In addition to promoting adhesion, the adhesion layer may help improve the morphology of the molybdenum metal layer 116 during film growth. Various other layers below the underlayer 114 are collectively referred to as a substrate layer 112.

[0017] The etch mask 122 is a first pattern of recessed features, each recessed feature 124 having vertical sidewalls and a bottom that exposes a portion of the major surface of the molybdenum metal layer 116. In the exemplary embodiment of FIG. 1B, the etch mask 122 includes a patterned hard mask layer 118 and a patterned photoresist layer 120. The patterned hard mask layer 118 can be formed by depositing a hard mask material on the molybdenum metal layer 116 and then etching the hard mask material using the patterned photoresist layer 120 as an etch mask. The patterned photoresist layer 120 can be formed using a suitable lithography technique, such as extreme ultraviolet (EUV) lithography. The minimum half pitch (critical dimension) of the patterned photoresist layer can be about 5 nm to about 15 nm. Examples of hard mask materials include silicon oxide, silicon nitride, titanium nitride, and the like, or a combination of multiple layers. In some other embodiments, the patterned hard mask layer 118 can be omitted from the etch mask 122.

[0018] In FIG. 1C, a subtractive etch process is performed through a patterned etch mask 122 to anisotropically remove the metallic molybdenum layer 116 to further extend the recessed features 124 of FIG. 1B to form a second pattern of recessed features, each having vertical sidewalls and a bottom that exposes a portion of the major surface of the underlying layer 114. Depending on the selectivity of the etch chemistry, certain portions of the etch mask 122 are eroded away, as illustrated in FIG. 1C. As noted above, embodiments of the etch process described in this disclosure employ a cyclical process to achieve the vertical sidewalls illustrated generally in FIG. 1C. In each cycle of the cyclical etch process, the process switches between a sidewall passivation step and an etching step that vertically removes the metallic molybdenum. Different embodiments of this method for etching metallic molybdenum are described in further detail below. The metal thickness is from about 50 nm to about 200 nm and the minimum half pitch of the pattern is from about 5 nm to about 15 nm, so the aspect ratio of the recessed features 126 is in a range where the sidewall profile must be well controlled to make the process manufacturable.

[0019] 1D, after completing the subtractive etch process, the remaining portions of the etch mask 122 may be removed. Typically, a cover layer 128, such as another ILD layer, is formed over the patterned metal molybdenum layer 116 to cover the metal lines and fill the spaces between the lines.

[0020] 2A and 2B illustrate undesirable etching characteristics and defects that result from an insufficient process window of the anisotropic dry etch process (e.g., a conventional RIE process) used to etch the recessed features 126 in the metallic molybdenum layer 116 during the etch step described with reference to FIG. 1C.

[0021] Typically, the substrate is exposed to a plasma in a processing chamber and a halogen (e.g., chlorine or fluorine) based chemistry is utilized to etch the molybdenum. Halogen radicals excited by the plasma react with the molybdenum to form volatile by-products that can be pumped out of the chamber. In a conventional RIE process, anisotropy is achieved by applying a bias signal (e.g., DC bias or radio frequency (RF) bias) to the substrate and using a plasma-excited gaseous mixture containing elements such as carbon, hydrogen and oxygen in addition to halogens to cause chemical reactions that form solid by-products (e.g., oxides and polymers). The solid by-products are selectively deposited on vertical surfaces to protect the sidewalls of the recessed features, a technique called sidewall passivation. The passivation layer is selectively formed on the sidewalls by sputtering the solid by-products away from the floor of the recessed features with high energy ions (e.g., argon ions) excited by the plasma and directed vertically by the bias signal. In addition, bombarding the surface with ions enhances the reaction rate there by breaking bonds between the molybdenum atoms and thus promoting their bonding with the halogen radicals. Thus, the vertical etch rate is enhanced by ion bombardment at the bottom surface, while the lateral etch rate is retarded by sidewall passivation.

[0022] A delicate balance must be struck between passivation rate and removal rate to provide a wide enough process window for stable manufacturing. Aggressive scaling of lateral dimensions results in smaller top openings of the recessed features 126 and higher aspect ratios of the recessed features 126. Thus, it becomes more difficult to open a wide enough process window with conventional RIE methods. FIG. 2A illustrates an example of undercutting or lateral etching formed in a metal molybdenum layer when using lean halogen chemistry. Lean halogen chemistry refers to a gaseous mixture that increases the relative halogen content, resulting in more removal and less passivation. As illustrated diagrammatically in FIG. 2A, there is excessive lateral etching due to insufficient sidewall passivation. The combination of lateral etching and narrow line width t can even result in line break defects. FIG. 2B illustrates a different example of tapered sidewall profile and bottom footing defects formed when the etch chemistry is adjusted to promote sidewall passivation by depositing a protective layer of solid by-products on the sidewalls. In the example illustrated in FIG. 2B, the footing is severe enough to cause a bridging defect.

[0023] Additionally, note that poor sidewall profile control increases the surface roughness along the sidewall. This worsens the LER of the etched pattern metal lines beyond that of the patterned etch mask 122 lines introduced by the lithography process. Since line resistance depends on the line width (W), increasing LER increases the variance and average value of the resistance of short metal lines even for a fixed resistivity ρ. At NME, i.e., ρ=ρ(W), the effect of LER on line resistance worsens. In addition, the high frequency component of LER (i.e., roughness over a wire length of about 1 nm or less) increases diffuse edge scattering by reflecting electrons at random angles independent of the angle of incidence, as opposed to specular edge scattering, where the angle of reflection is equal to the angle of incidence. Specular scattering conserves the momentum of electrons in the direction of current flow, whereas diffuse scattering randomizes the momentum, which increases ρ(W), thereby unnecessarily increasing NWE. The embodiments of the present invention described below provide greater flexibility in adjusting sidewall passivation and material removal, resulting in improved sidewall profile and sidewall profile control.

[0024] One embodiment of implementing process flow 100 using gas pulse cyclic etch technique 300 is described with reference to Figures 3A-3F. Figure 3A illustrates a flow chart summarizing gas pulse cyclic etch technique 300, and Figures 3B-3F illustrate various cross-sectional views of a semiconductor device 320 at various intermediate stages of patterning a metal molybdenum layer using gas pulse cyclic etch technique 300.

[0025] As indicated in box 302 of the illustrated flow chart in FIG. 3A and shown in the cross-sectional view of a semiconductor device 320 in FIG. 3B, the gas pulse cyclic etch technique 300 receives an incoming substrate similar to that described above with reference to FIG. 1B. The substrate includes an underlayer 324 on which a molybdenum metal layer 326 is formed. A patterned etch mask 322 is formed on the molybdenum metal layer 326. The pattern includes recessed features 334 having exposed surfaces of the molybdenum metal layer 326 as floors of each recessed feature. In one embodiment, the patterned etch mask 322 includes a patterned photoresist layer 330 and a hardmask layer 328, e.g., a tetraethyl orthosilicate (TEOS) hardmask layer 328. The hardmask layer 328 is patterned using the photoresist layer 330 as a masking layer. In some other embodiments, the patterned photoresist layer 330 may not be present on the incoming substrate because it was removed during the process of patterning the hardmask layer 328.

[0026] In some embodiments, the gas pulse cyclic etch technique 300 includes an initial etch step (box 304 in FIG. 3A ) that anisotropically etches a portion of the metallic molybdenum layer 326 to expand the recessed feature 334 to form an extended recessed feature 336, as seen in the cross-sectional view of the semiconductor device 320 illustrated in FIG. 3C . After the initial etch step (box 304) completes the formation of the extended recessed feature 336, a gas pulse cycle in the gas pulse cyclic etch technique 300 can be performed.

[0027] As illustrated in the flowchart of Figure 3A, each gas pulse cycle 312 includes two parts. The first part is a deposition step (box 306 and Figure 3D) and the second part is an etch step (box 310 and Figure 3F). In one embodiment, the gas pulse cyclic etch technique 300 has an optional breakthrough etch step (box 308 and Figure 3E) inserted between the deposition step of box 306 and the etch step of box 310 to expose a molybdenum surface vertically below the material deposited on the floor of the extended recessed feature 336.

[0028] During the deposition step of the gas pulse cyclic etch technique 300 (FIG. 3A-box 306 and FIG. 3D), the substrate is exposed to a plasma-enhanced deposition gas. As illustrated in the cross-sectional view of the semiconductor device 320 in FIG. 3D, exposure to the plasma-enhanced deposition gas forms an etch protection layer 340 along the sidewalls and floor of the recessed feature 336. The set of plasma process parameters and gases used for the deposition step of box 306 of the gas pulse cyclic etch technique 300 can be optimized to deposit a passivating solid by-product for sidewall protection.

[0029] In some embodiments, the deposition gas is a fluorocarbon (C x F y ) or hydrofluorocarbons (C x H y F z). Non-limiting examples of fluorocarbons that may be deposition gases include C2F4, C2F6, C4F8, and C4F6. Non-limiting examples of hydrofluorocarbons that may be deposition gases include CHF3, CH2F2, and CH3F. Additional gases that may be included in the deposition gas are H2, O2, and diluting inert gases (e.g., argon, helium, or nitrogen). Plasma process parameters include a chamber pressure of about 30 mTorr to about 300 mTorr, an RF source power of about 50 W to about 800 W at a frequency of about 25 MHz to about 60 MHz, and a pulsed RF bias power of about 0 W (no RF bias) to about 100 W at a frequency of about 0.1 kHz to about 100 kHz. The substrate temperature is controlled to about 0°C to about 60°C. In these embodiments, the formed etch protection layer 340 (shown in FIG. 3D) is an organic film containing C and H atoms, for example an organic film resulting from the deposition of species generated from CH3F plasma dissociation.

[0030] In other certain embodiments, the deposition gas includes a sulfur-containing gas, such as sulfur dioxide (SO2), carbonyl sulfide (COS), and the like. In various embodiments, the deposition gas includes SO2 or COS, i.e., either only SO2 or COS, or both SO2 and COS. Additional gases that may be included in the deposition gas are H2, O2, and a diluting inert gas (e.g., argon, helium, or nitrogen). Plasma process parameters include a chamber pressure of about 30 mTorr to about 300 mTorr, an RF source power of about 50 W to about 800 W at a frequency of about 25 MHz to about 60 MHz, and a pulsed RF bias power of about 0 W (no RF bias) to about 100 W at a frequency of about 0.1 kHz to about 100 kHz. The substrate temperature is controlled to about 0°C to about 60°C. In this embodiment, the formed etch protection layer 340 (shown in FIG. 3D) may be sulfide or highly oxidized sulfur-containing groups, such as sulfonic acid groups and sulfates, resulting from deposition of chemical species generated from SO2 / O2 or SO2 / H2 plasma dissociation.

[0031] In various embodiments, the deposition thickness of the etch protection layer 340 can be between about one monolayer and about several monolayers of material, in other words, the thickness range can be between about 0.3 nm and about 2 nm.

[0032] During the etch step (FIG. 3A-box 310 and FIG. 3F), the substrate is exposed to a plasma-excited etching gas. Typically, either lean halogen chemistries, chlorine-based or fluorine-based chemistries are used to selectively remove metallic molybdenum and vertically expand the recessed feature. For example, as illustrated in FIG. 3F, recessed feature 336 is further expanded to form recessed feature 342. Non-limiting examples of fluorine-containing gases that can be etching gases include F2, CF4, NF3 and SF6. Non-limiting examples of chlorine-containing gases that can be etching gases include Cl2, CCl4 and BCl3. In some embodiments, the gaseous mixture can also include oxygen. In some embodiments, the gaseous mixture can further include an inert gas such as argon. Metallic molybdenum is removed anisotropically, with removal occurring preferentially from above horizontal surfaces. The anisotropy is achieved by applying a vertical bias signal to the substrate and depositing a passivating etch protection layer on the vertical sidewalls. As discussed above, the bias accelerates ions (e.g., argon ions) vertically to collide with molybdenum atoms. This collision increases the etch rate at the bottom of the recessed feature, e.g., recessed feature 342. The RF bias signal can be a DC, or RF, or pulsed RF signal. In some embodiments, a pulsed RF bias power of about 300 W to about 1200 W at a frequency of about 0.1 kHz to about 100 kHz can be used. Other plasma process parameters include a chamber pressure of about 5 mTorr to about 100 mTorr and an RF source power of about 100 W to about 800 W at a frequency of about 25 MHz to about 60 MHz. The substrate temperature is controlled to about 0° C. to about 60° C.

[0033] The initial etch step (box 304 and FIG. 3C) may be performed using a process similar to that of the etch step (box 310) used during gas pulse cycle 312. The initial etch step is a non-deposition step that uses a carbon-free plasma excited etch gas such as, for example, Cl2.

[0034] As illustrated in the cross-sectional view of Figure 3D, the floor of the extended recessed feature 336 is covered by the deposited solid by-products to form an etch protection layer 340. In the exemplary embodiment of the gas pulse cyclic etch technique 300 described with reference to Figures 3A-3F, an optional breakthrough etch step (box 308 and Figure 3E) is inserted between the deposition step of box 306 and the etch step of box 310 (see flowchart in Figure 3A) to expose a molybdenum surface vertically below the recessed feature 336.

[0035] In FIG. 3E, an optional breakthrough etch step (box 308) is performed to again expose a portion of the surface of the metallic molybdenum layer 326 to the environment. In this exemplary embodiment, the breakthrough etch in box 308 is a sputter etch process using, for example, high energy argon ions. Generally, ions are accelerated by a vertical electric field in the plasma sheath, which may be enhanced by applying a bias signal, such as a pulsed RF bias signal. In one embodiment, a pulsed RF bias power of about 50 W to about 1200 W at a frequency of about 0.1 kHz to about 100 kHz may be applied to the substrate.

[0036] While the exemplary embodiment uses an optional breakthrough etch step (box 308) to remove the portion of the etch protection layer 340 formed over the horizontal surfaces at the bottom of the recessed feature 336, in certain other embodiments, the plasma parameters of the etch step of box 310 of each gas pulse cycle 312 may be adjusted to break through the etch protection layer 340. For example, the oxygen content may be increased along with the RF bias power to aid in removing the etch protection layer 340 from the horizontal surfaces. Note that some of the organic polymers in the etch protection layer 340 may be oxidized by oxygen radicals. Thus, care must be taken to prevent oxygen from ashing the etch protection layer 340 from some of the surfaces along the sidewalls, resulting in a loss of control of the sidewall profile. Once the etch protection layer 340 covering the bottom of the recessed feature 336 has been removed, the etch step of box 310 may continue to extend the recessed feature 336 further downward to form the recessed feature 342 of FIG. 3F.

[0037] In the above description of the gas pulse cyclic etch technique 300, the various steps of each gas pulse cycle 312, namely the deposition step of box 306 and the etch step of box 310, are distinguishable in time. Separating the two steps in time not only provides the advantage of independently optimizing the process parameters for the passivation and material removal portions of the process, but also the advantage of having a new etch protection layer that passivates the newly formed sidewall portions of the etched molybdenum metal layer, thereby providing an improved vertical etch profile during each cycle.

[0038] In some embodiments, the number of gas pulse cycles 312 may be a predetermined fixed number in a process recipe. In other embodiments, the process may be terminated by a process controller after an endpoint signal is received indicating that the underlayer 324 has been exposed. In some embodiments, an overetch step may be performed after the gas pulse cyclic etch technique 300 is performed.

[0039] In another embodiment of implementing the process flow 100, a deposition-etch cyclic etch technique forms an etch protection layer using an atomic layer deposition (ALD) process. The ALD-based cyclic etch technique 400 is summarized in the flowchart illustrated in FIG. 4. The ALD-based cyclic etch technique 400 is similar to the gas pulse cyclic etch technique 300, but differs in the manner in which the etch protection layer is formed. In addition, the optional breakthrough etch step is not optional in the ALD-based cyclic etch technique 400. These changes are indicated in bold in the flowchart of FIG. 4.

[0040] The etch protection layer is formed using an ALD technique in the deposition step (box 406) of each deposition-etch cycle 412 of the ALD-based cyclic etch technique 400. The etch protection layer is a thin oxide layer comprising an oxide that has high etch resistance to plasmas containing halogen radicals (e.g., chlorine and fluorine radicals). In one example, the oxide layer comprises silicon oxide (SiO2). As known to those skilled in the art, in ALD techniques, the deposition reaction occurs as two self-limiting half-reactions. In one example, a silicon oxide layer can be deposited by exposing the substrate to a silicon precursor (e.g., SiCl4 or SiF4) with or without plasma excitation, followed by exposure to an oxidizer (e.g., plasma excited oxygen gas).

[0041] The etch protection layer can be conformally formed over the entire exposed surface of the substrate, including the horizontal surfaces of the molybdenum metal layer. Thus, the breakthrough etch step (box 408) can be an optional step. The other steps of the ALD-based cyclic etch technique 400 are described above in connection with the gas pulse cyclic etch technique 300 with reference to Figures 3A-3F.

[0042] Although the deposition and etch steps in the above-described cyclic etch techniques can be performed in separate processing chambers, such processes are time consuming and expensive. In embodiments of the present disclosure, the cyclic etch techniques, i.e., the gas pulse cyclic etch technique 300 and the ALD-based cyclic etch technique 400, can be performed in a single processing chamber with appropriate chamber conditioning steps integrated into the process flow.

[0043] FIG. 5 illustrates a flow chart of one cycle 500 of a cyclic etch process, such as the gas pulse cycle 312 (of the gas pulse cyclic etch technique 300) and the deposition-etch cycle 412 (of the ALD-based cyclic etch technique 400). Each cycle 500 has a deposition step 502 and an etch step 508 separated in time. To reduce process variations, the deposition step 502 and the etch step 508 include power stabilization periods and gas flow stabilization periods determined by a process controller. As illustrated in the flow chart of FIG. 5, several other measures can be taken to further reduce process-induced variations. A gas purge step 504 can be performed after each deposition step 502 to thoroughly remove contaminants and gaseous reaction by-products. Similarly, another gas purge step 510 can be performed after each etch step 508. In some embodiments, a chamber precoat step 506 can be performed before the etch step 508 to ensure that the initial conditions of the process chamber are the same each time the etch step 508 is performed. The chamber precoat step deposits a coating on the walls of the process chamber. The coatings may include silicon, oxides (e.g., silicon oxide), or carbon deposited using a plasma process. The chamber precoat step 506 is performed with a wafer covering the chuck (substrate holder) to avoid deposition on the chuck. For example, a blank wafer may be placed on the chuck prior to the chamber precoat step 506. These additional precautions help meet the stringent process control specifications necessary to incorporate molybdenum metal into high volume IC manufacturing.

[0044] As noted above, several advantages can be obtained by using the described embodiment of the cyclic etch process for patterning molybdenum metal by separating the passivation portion from the material removal portion, including reduced undercutting, low LER, vertical edge profiles, and good control of etch rate and etch selectivity. Nonetheless, it is understood that the methods described in this disclosure allow for a partial time overlap between deposition and etching (in embodiments where the gas pulse cycle 312 includes the optional breakthrough etch step of box 308, etching refers to the breakthrough etch step of box 308).

[0045]

[0023] Illustrative embodiments of the present invention are summarized herein. Other embodiments can be seen throughout the specification and claims appended hereto.

[0046] Example 1. A method of processing a substrate, comprising: providing a substrate including an etch mask over a metallic molybdenum layer in a recessed feature; exposing the substrate to a plasma-enhanced deposition gas that forms an etching protection layer on sidewalls of the recessed feature; and exposing the substrate to a plasma-enhanced etching gas that etches the metallic molybdenum layer according to the etch mask, wherein these exposing steps are performed alternately multiple times.

[0047] Example 2. Plasma-excited deposition gas is fluorocarbon (C x F y ) or hydrofluorocarbons (C x H y F z ) and the ratio of carbon atoms to fluorine atoms is greater than 1 / 4 and less than or equal to 1.

[0048] Example 3. The method of any one of Examples 1 or 2, wherein the plasma-enhanced deposition gas comprises a sulfur-containing gas.

[0049] Example 4. The method of any one of Examples 1-3, wherein the sulfur-containing gas comprises SO2 or COS gas.

[0050] Example 5. The method of any one of Examples 1-4, wherein the plasma excited etching gas comprises a halogen-containing gas.

[0051] Example 6. The method of any one of Examples 1-5, wherein the halogen-containing gas comprises F2, CF4, NF3, SF6, Cl2, CCl4 or BCl3 gas.

[0052] Example 7. The method of any one of Examples 1-6, wherein the plasma enhanced etching gas further comprises an oxygen-containing gas.

[0053] Example 8. The method of any one of Examples 1-7, wherein the plasma enhanced etching gas further comprises argon gas.

[0054] Example 9. The method of any one of Examples 1-8, further comprising performing a breakthrough etch step of etching through the etch protection layer at the bottom of the recessed feature.

[0055] Example 10. The method of any one of Examples 1-9, wherein exposing the substrate to a plasma-excited etching gas further comprises applying a bias signal to the substrate.

[0056] Example 11. A method of processing a substrate comprising: providing a substrate including an etch mask over a metallic molybdenum layer in a recessed feature; depositing an etch protection layer in the recessed feature, the etch protection layer including an oxide layer; performing a breakthrough etch step to etch through the etch protection layer at a bottom of the recessed feature; and exposing the substrate to a plasma-enhanced etch gas that etches the metallic molybdenum layer in accordance with the etch mask.

[0057] Example 12. The method of Example 11, wherein depositing an etch protection layer includes exposing the substrate to a silicon-containing precursor and an oxidizing agent to form a silicon oxide layer.

[0058] Example 13. The method of any one of Examples 11 or 12, wherein depositing the etch protection layer comprises alternately exposing the substrate to a silicon-containing precursor and an oxidizing agent to form a silicon oxide layer.

[0059] Example 14. The method of any one of Examples 11-13, wherein the plasma-enhanced etching gas comprises a halogen-containing gas.

[0060] Example 15. The method of any one of Examples 11-14, wherein the halogen-containing gas comprises F2, CF4, NF3, SF6, Cl2, CCl4 or BCl3 gas.

[0061] Example 16. The method of any one of Examples 11-15, wherein the plasma enhanced etching gas further comprises an oxygen-containing gas.

[0062] Example 17. A method of processing a substrate, comprising: providing a substrate including an etch mask on a metal molybdenum layer in a recessed feature; depositing an etch protection layer on a sidewall of the etch mask, the etch protection layer including an oxide layer; and exposing the substrate to a plasma excited etching gas that etches the metal molybdenum layer in accordance with the etch mask, the deposition and exposure being performed alternately multiple times.

[0063] Example 18. The method of example 17, wherein exposing the substrate to a plasma-excited etching gas further comprises applying a bias signal to the substrate.

[0064] Example 19. The method of any one of Examples 17 or 18, wherein depositing the etch protection layer comprises exposing the substrate to a silicon-containing precursor and an oxidizing agent to form a silicon oxide layer.

[0065] Example 20. The method of any one of Examples 17-19, wherein depositing the etch protection layer comprises alternately exposing the substrate to a silicon-containing precursor and an oxidizing agent to form a silicon oxide layer.

[0066] Example 21. The method of any one of Examples 17-20, wherein the plasma-enhanced etching gas comprises a halogen-containing gas.

[0067] Example 22. The method of any one of Examples 17-21, wherein the halogen-containing gas comprises F2, CF4, NF3, SF6, Cl2, CCl4 or BCl3 gas.

[0068] Example 23. The method of any one of Examples 17-22, wherein the plasma enhanced etching gas further comprises an oxygen-containing gas.

[0069] Example 24. The method of any one of Examples 17-23, further comprising performing a breakthrough etching step of etching through the etch protection layer at the bottom of the recessed feature.

[0070] Example 25. The method of any one of Examples 17-24, wherein the deposition and the exposure are both performed in a processing chamber, and the method further includes performing a chamber precoat step after the deposition and before the exposure, the chamber precoat step depositing a coating on the walls of the processing chamber.

[0071] While the present invention has been described with reference to exemplary embodiments, this specification is not intended to be construed in a limiting sense. Various modifications and combinations of the exemplary embodiments, as well as other embodiments of the present invention, will become apparent to those skilled in the art upon reference to this specification. It is therefore intended that the appended claims cover any such modifications or embodiments.

Claims

1. 1. A method of substrate processing, comprising: providing a substrate including an etch mask over the molybdenum metal layer in the recessed feature; exposing the substrate to a plasma-enhanced deposition gas, the plasma-enhanced deposition gas forming an etch-protective layer on sidewalls of the recessed feature; exposing the substrate to a plasma-enhanced etching gas, wherein the plasma-enhanced etching gas etches the molybdenum metal layer according to the etch mask; and wherein both of the exposing steps are alternated multiple times by stopping the exposing step to the plasma excited deposition gas and exposing to the plasma excited etching gas, and stopping the plasma excited etching gas and exposing to the plasma excited deposition gas, such that the exposure to the plasma excited deposition gas is separated in time from the exposure to the plasma excited etching gas.

2. The plasma-excited film-forming gas is a fluorocarbon (C ｘ F ｙ ) or hydrofluorocarbon (C ｘ H ｙ F ｚ ), 2. The method of claim 1, wherein the ratio of carbon atoms to fluorine atoms is greater than 1 / 4 and less than or equal to 1.

3. The method of claim 1 , wherein the plasma-enhanced deposition gas comprises a sulfur-containing gas.

4. The sulfur-containing gas is SO ２ or COS gas.

5. The method of claim 1 , wherein the plasma-enhanced etching gas comprises a halogen-containing gas.

6. The halogen-containing gas is F ２ , C.F. ４ , N.F. ３ , S.F. ６ , Cl ２ , CCl ４ or BCl ３ The method of claim 5 , comprising a gas.

7. The method of claim 5 , wherein the plasma enhanced etching gas further comprises an oxygen-containing gas.

8. The method of claim 5 , wherein the plasma enhanced etching gas further comprises argon gas.

9. 1. A method of substrate processing, comprising: providing a substrate including an etch mask over the molybdenum metal layer in the recessed feature; depositing an etch protection layer in the recessed feature, the etch protection layer comprising an oxide layer; performing a breakthrough etching step after the depositing step, wherein the breakthrough etching step etches through the etch protection layer at the bottom of the recessed feature; after the performing step, exposing the substrate to a plasma-enhanced etching gas, wherein the plasma-enhanced etching gas etches the molybdenum metal layer according to the etch mask; A method comprising:

10. 10. The method of claim 9, wherein depositing the etch protection layer comprises exposing the substrate to a silicon-containing precursor and an oxidizing agent to form a silicon oxide layer.

11. 10. The method of claim 9, wherein depositing the etch protection layer comprises alternately exposing the substrate to a silicon-containing precursor and an oxidizing agent to form a silicon oxide layer.

12. The method of claim 9 , wherein the plasma-enhanced etching gas comprises a halogen-containing gas.

13. The halogen-containing gas is F ２ , C.F. ４ , N.F. ３ , S.F. ６ , Cl ２ , CCl ４ or BCl ３ The method of claim 12 comprising a gas.

14. 1. A method of substrate processing, comprising: providing a substrate including an etch mask over the molybdenum metal layer in the recessed feature; Pulsing the deposition gas and the etching gas to perform a gas pulse cycle process, Each cycle is depositing an etching protection layer on sidewalls of the etch mask, the etching protection layer comprising an oxide layer; and exposing the substrate to a plasma-enhanced etching gas formed from the etching gas, the plasma-enhanced etching gas etching the molybdenum metal layer according to the etch mask; and during each cycle, the depositing step and the exposing step are alternately performed, and during the depositing step, the exposure to the deposition gas is separated in time from the exposure to the plasma-enhanced etching gas; and A method comprising:

15. 15. The method of claim 14, wherein exposing the substrate to the plasma-enhanced etching gas further comprises applying a bias signal to the substrate.

16. 15. The method of claim 14, wherein depositing the etch protection layer comprises exposing the substrate to a silicon-containing precursor and an oxidizing agent to form a silicon oxide layer.

17. 15. The method of claim 14, wherein depositing the etch protection layer comprises alternately exposing the substrate to a silicon-containing precursor and an oxidizing agent to form a silicon oxide layer.

18. The method of claim 14 , wherein the plasma-enhanced etching gas comprises a halogen-containing gas.

19. 15. The method of claim 14, further comprising performing a breakthrough etching step, wherein said breakthrough etching step etches through said etch protection layer at the bottom of said recessed feature.

20. the depositing step and the exposing step are both performed in a processing chamber; The method further comprises performing a chamber precoat step after the depositing step and before the exposing step; 15. The method of claim 14, wherein the chamber precoat step deposits a coating on the walls of the processing chamber.

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