III-nitride semiconductor structures on silicon-on-insulator and methods for growing same - Patents.com

Abstract

1. A semiconductor structure (1) comprising: a silicon-on-insulator substrate (101) comprising a silicon base layer (10), an intermediate layer (11) on the base layer (10) comprising a trap rich layer (111) and a buried insulator (121) on the trap rich layer (111), and an n-type doped silicon top layer (12) on the intermediate layer (11); and an epitaxial III-N semiconductor layer stack (202) on the silicon-on-insulator substrate (101) comprising a first active III-N layer (21) on the top layer (12), a second active III-N layer (22) on the first active III-N layer (21), and a two-dimensional electron gas (200) between the first active III-N layer (21) and the second active III-N layer (22).

Description

[Technical field]

[0001]

[0001] The present invention relates generally to, among other things, semiconductor structures and methods for growing same, and more particularly to semiconductor structures including III-nitrides grown on silicon-on-insulator that achieve superior performance for high power and high frequency applications, and methods for growing same. [Background technology]

[0002] (background) III-nitride based heterostructures are highly suitable for high power and high frequency applications due to their high electron velocity and high critical electric field. For example, AlGaN / GaN heterostructures are conventionally used to fabricate field effect transistors, also called FETs. In this heterostructure, a two-dimensional electron gas, also called 2DEG, is generated by spontaneous and piezoelectric polarization between the two active layers, i.e., AlGaN and GaN.

[0003]

[0003] III-nitride based heterostructures are typically fabricated on conventional silicon substrates. As the need for high power and high frequency solutions grows, the telecommunications industry faces the challenge of making such III-nitride based heterostructures compatible with existing technologies. For example, III-nitride based heterostructures should enable the continued miniaturization of microelectronic devices and the continued improvement of their performance.

[0004]

[0004] For high power and high frequency applications, it is essential to maximize the resistivity of the substrate underlying the device. However, measurements performed using spreading resistance profiling on gallium nitride epitaxially grown on silicon substrates show a significant decrease in resistivity with depth in the heterostructure.

[0005]

[0005] More generally, measurements performed using spreading resistance profiling on III-nitride heterostructures epitaxially grown on silicon substrates show a similar drop in resistivity at the interface between the III-nitride heterostructure and the silicon substrate, and a similar presence of p-type dopants at the interface between the III-nitride heterostructure and the silicon substrate. Such presence of p-type dopants at the interface between the III-nitride heterostructure and silicon is due to the diffusion or migration of impurities from the initial growth layer of the III-nitride heterostructure epitaxial layer into the silicon substrate. The impurities act as p-type impurities for the silicon substrate. More specifically, such presence of p-type dopants at the interface between the III-nitride heterostructure and silicon is due to the diffusion or migration of group III elements into the silicon substrate where they act as p-type impurities for the silicon substrate. For example, in the samples investigated in Figures 1A and 1B of the present disclosure, such presence of p-type dopants at the interface between the III-nitride heterostructure and silicon is due to the diffusion or migration of gallium and / or aluminum into the silicon substrate. The gallium and / or aluminum act as p-type impurities for the silicon, thereby changing the resistivity of the silicon substrate.

[0006]

[0006] Several problems arise from such diffusion of group III elements into the silicon substrate. In high power and high frequency applications, the presence of high concentrations of p-type dopants at the interface between gallium nitride and silicon causes capacitive coupling, which results in significant power dissipation and RF losses for components fabricated from this structure. Furthermore, diffusion of group III elements into the silicon substrate creates linearity problems due to the generation of harmonic frequencies in components fabricated from this structure. Summary of the Invention

[0007] (overview)

[0007] It is therefore an object of embodiments of the present invention to propose a semiconductor structure and a manufacturing method that do not exhibit the inherent drawbacks of the prior art. More specifically, it is an object of embodiments of the present invention to propose a semiconductor structure and a manufacturing method thereof that have improved performance at high powers and high frequencies.

[0008]

[0008] The scope of protection sought for various embodiments of the invention is set out in the independent claims.

[0009]

[0009] The embodiments and features described in this specification that do not fall within the scope of the independent claims, if any, should be interpreted as examples useful for understanding various embodiments of the invention.

[0010]

[0010] What is needed is a semiconductor structure that exhibits improved resistivity and reduced power loss and linearity issues. Additionally, what is needed is a semiconductor structure that is compatible with existing technology from a manufacturing standpoint.

[0011]

[0011] This object is achieved, according to a first exemplary aspect of the present disclosure, by A base layer comprising silicone; an intermediate layer formed on the base layer; and The top layer formed on top of the middle layer A silicon-on-insulator substrate comprising: An epitaxial III-N semiconductor layer stack on a silicon-on-insulator substrate, the epitaxial III-N semiconductor layer stack comprising an epitaxial active layer, the epitaxial active layer comprising: a first active III-N layer formed on the top layer; A second active III-N layer formed on top of the diffusion barrier layer an epitaxial III-N semiconductor layer stack, wherein a two-dimensional electron gas is present between the first active III-N layer and the second active III-N layer; Equipped with the top layer comprises n-type doped silicon; The middle class, A trap rich layer; A buried insulator formed on the trap rich layer; This is achieved by a semiconductor structure comprising:

[0012]

[0012] As mentioned above, the presence of p-type dopants at the interface between a III-nitride heterostructure and a silicon substrate on which the III-nitride heterostructure is, for example, epitaxially grown, can be measured, for example, using spreading resistance profiling measurements. Such presence of p-type dopants at the interface between the III-nitride heterostructure and silicon is due to the diffusion or migration of impurities from the initial growth layer of the III-nitride heterostructure epitaxial layer into the silicon substrate. The impurities act as p-type impurities for the silicon substrate. More specifically, such presence of p-type dopants at the interface between the III-nitride heterostructure and silicon is due to the diffusion or migration of group III elements into the silicon substrate where they act as p-type impurities for the silicon substrate.

[0013]

[0013] In the semiconductor structure according to the present disclosure, the diffusion or migration of group III elements from the epitaxial layer of the III-nitride heterostructure to the silicon-on-insulator substrate is confined within a surface region of the silicon-on-insulator substrate close to the epitaxial layer of the III-nitride heterostructure, e.g., within the top layer, and optionally near the interface between the intermediate layer and the top layer. In fact, the intermediate layer of the silicon-on-insulator substrate according to the present disclosure confines the diffusion or migration of group III elements within a surface region of the silicon-on-insulator substrate close to the epitaxial layer of the III-nitride heterostructure, e.g., within the top layer, and optionally near the interface between the intermediate layer and the top layer, thereby shortening the diffusion distance of impurities into the silicon-on-insulator substrate.

[0014]

[0014] In the semiconductor structure according to the present disclosure, the n-type doping of the top layer of the silicon-on-insulator substrate according to the present disclosure compensates for the concentration of group III elements diffusing from the epitaxial layer into the silicon-on-insulator substrate. In other words, the n-type doping of the top layer of the silicon-on-insulator substrate according to the present disclosure balances the concentration of p-type dopants at the interface between the epitaxial layer and the silicon-on-insulator substrate, which concentrations of p-type dopants result from the diffusion of group III atoms from the epitaxial III-N semiconductor layer stack into the top layer of the silicon-on-insulator substrate.

[0015]

[0015] Thus, the semiconductor structures according to the present disclosure exhibit improved performance at high power and high frequency, improved resistivity, and reduced power loss and linearity issues.

[0016]

[0016] The use of a trap rich layer has proven to be one of the most effective techniques to reduce these parasitic effects and enhance the high resistivity properties of silicon while meeting the critical thermal budgets of industrial SOI wafer fabrication and standard CMOS processes. The traps in the trap rich layer capture free carriers at the interface between the silicon and the intermediate layer, thereby allowing the silicon-on-insulator substrate to recover its nominal resistivity, linearity, eliminates DC dependence, and results in a significant reduction in RF losses and crosstalk. In the context of this disclosure, the trap rich layer has a defect density suitable to capture free charges that may be generated in the silicon-on-insulator substrate. The trap rich layer may also provide a trap effect. The trap rich layer has a thickness of tens of nanometers to several microns, for example 50 nm to 3 microns. The trap rich layer includes silicon, or amorphous silicon carbide, or polycrystalline silicon, also called polysilicon.

[0017]

[0017] In the context of this disclosure, a two-dimensional electron gas, also called 2DEG, is a gas of electrons that are free to move in two dimensions, but tightly confined in the first dimension. This tight confinement results in quantized energy levels for motion in that direction. The electrons appear to be a 2D sheet embedded in a 3D world.

[0018]

[0018] In the context of this disclosure, III-nitrides refer to semiconductor compounds formed between elements in group III of the periodic table, such as boron, also called B, aluminum, also called Al, gallium, also called Ga, indium, also called In, and nitrogen, also called N. Examples of binary III-nitride compounds are GaN, AlN, BN, etc. III-nitrides also refer to ternary and quaternary compounds, such as AlGaN and InAlGaN.

[0019] In the context of the present disclosure, the first active III-N layer includes one or more of N, P, As and one or more of B, Al, Ga, In, and Tl. The first active III-N layer includes, for example, GaN. The second active III-N layer includes one or more of N, P, As and one or more of B, Al, Ga, In, and Tl. The second active III-N layer includes, for example, AlGaN. The term AlGaN refers to any stoichiometric ratio (Al x Ga yFor compositions including Al, Ga, and N in (III-N), x is between 0 and 1 and y is between 0 and 1. Alternatively, the second active III-N layer includes, for example, AlN. Alternatively, the second active III-N layer includes InAlGaN. Compositions such as InAlGaN include In in any suitable amount. Alternatively, both the first active III-N layer and the second active III-N layer include InAlGaN, the second active III-N layer includes a bandgap larger than the bandgap of the first active III-N layer, and the second active III-N layer includes a polarization larger than the polarization of the first active III-N layer. Alternatively, both the first active III-N layer and the second active III-N layer include BInAlGaN, the second active III-N layer includes a bandgap larger than the bandgap of the first active III-N layer, and the second active III-N layer includes a polarization larger than the polarization of the first active III-N layer. The composition of the active layers may be selected taking into consideration the properties to be obtained, and the composition may vary accordingly. For example, good results have been obtained with a first active III-N layer comprising GaN about 150 nm thick and a second active III-N layer comprising AlGaN about 20 nm thick.

[0020]

[0020] In the context of the present disclosure, the base layer of the silicon-on-insulator substrate comprises bulk silicon, and the resistivity of the base layer of the silicon-on-insulator substrate is typically comprised between 3 and 5 kOhm-cm, and preferably higher than 1 kOhm-cm. In this way, the resistivity of the substrate underlying the epitaxial III-N semiconductor layer stack is maximized for high power and high frequency applications.

[0021]

[0021] In the context of the present disclosure, the technology of silicon-on-insulator, also called SOI, corresponds to the manufacture of semiconductor devices in layered silicon-insulator silicon substrates. The choice of insulator largely depends on the intended application of the semiconductor device. Within the context of the present disclosure, several types of silicon-on-insulator substrates can be used.

[0022]

[0022] The separation of the base layer of the silicon-on-insulator substrate from the bulk silicon reduces the parasitic capacitance in semiconductor devices fabricated from III-nitride heterostructures, thereby improving their power consumption and their performance. Semiconductor devices fabricated on silicon-on-insulator also exhibit higher latch-up immunity and performance at comparable VDD than semiconductor devices integrated on other types of substrates. The temperature dependence of semiconductor devices fabricated on SOI is reduced compared to semiconductor devices integrated on other types of substrates. Due to the separation, semiconductor devices fabricated on SOI exhibit lower leakage currents and therefore higher power efficiency.

[0023]

[0023] Radio frequency silicon-on-insulator substrates, also known as RF-SOI substrates, enable high RF performance, high linearity RF isolation and power signals, low RF losses, digital processing, and power management integration on a silicon membrane compatible with standard CMOS processes.

[0024]

[0024] For example, an enhanced signal integrity substrate for RF applications comprises a base layer comprising high resistivity silicon, a trap rich layer formed on the base layer, a buried insulator formed on the trap rich layer, and a top layer formed on the buried insulator, the top layer comprising monocrystalline silicon. The resistivity of the base layer is typically greater than 3 kilo-ohm cm. The thickness of the top layer is typically comprised between 50 nm and 200 nm. The addition of the trap rich layer provides superior RF performance. Such substrates are particularly suitable for devices with stringent linearity specifications. Applications are typically targeted, for example, to LTE-Advanced and 5G specifications, addressing different performance requirements. Compared to high resistivity SOI substrates, the enhanced signal integrity substrates exhibit better linearity, lower RF losses, lower crosstalk, improved quality factor for passives, smaller die size, and higher thermal conductivity. The enhanced signal integrity substrates further typically exhibit a harmonic quality factor lower than -80 dBm.

[0025] Another example of RF-SOI includes a base layer including medium resistivity silicon, a trap rich layer formed on the base layer, a buried insulator formed on the trap rich layer, and a top layer including a thin single crystal. Such a substrate is particularly suitable for, for example, cost-sensitive highly integrated devices, and is particularly well suited for, for example, Wi-Fi, IoT, and other consumer application specifications.

[0026] Another example of RF-SOI, called high resistivity SOI, is intended for devices having lower linearity specifications as well as 2G and 3G specifications, for example. Such a substrate comprises a base layer including high resistivity silicon, a buried insulator formed on the base layer, and a top layer including a thin monocrystalline silicon.

[0027]

[0027] Power silicon-on-insulator substrates address the requirements for integrating, for example, high voltage and analog functions into intelligent, energy-efficient and reliable power IC devices for the automotive and industrial markets. Power silicon-on-insulator substrates provide excellent electrical isolation and are ideal for integrating devices operating at different voltages from a few volts to hundreds of volts while reducing die area and improving reliability. These substrates are ideal for applications such as CAN / LIN transceivers, switch mode power supplies, brushless motor drivers, LED drivers, etc. Power SOI comprises a base layer comprising silicon, a buried insulator formed on top comprising oxide, and a top layer comprising silicon. The thickness of the buried insulator is typically comprised between 0.4 μm and 1 μm, and the thickness of the top layer is typically comprised between 0.1 μm and 1.5 μm.

[0028]

[0028] Photonic silicon-on-insulator substrates address the requirements of optical function integration into CMOS chips, for example for low-cost and high-speed optical transceivers. Such substrates comprise a base layer comprising silicon, a buried insulator formed on the base layer and comprising an oxide, and a top layer formed on the buried insulator and comprising monocrystalline silicon. The thickness of the buried insulator is typically comprised between 0.7 μm and 2 μm, and the thickness of the top layer is typically comprised between 0.1 μm and 0.5 μm. The crystalline silicon layer on the insulator can be used to manufacture, for example, optical waveguides and other optical devices, either passive or active, for example by suitable implantation. The buried insulator allows, for example, the propagation of infrared light in the silicon layer based on total internal reflection. The top surface of the waveguide can be left uncovered and exposed to air, for example for sensing applications, or can be covered with a cladding, for example made of silica.

[0029] From a manufacturing perspective, SOI substrates are compatible with most conventional manufacturing processes. In general, SOI-based processes can be implemented without special equipment or significant retooling of existing factories. Among the challenges unique to SOI are new metrology requirements to account for buried insulators, and concerns regarding differential stresses within the top layer, including silicon.

[0030] According to an exemplary embodiment, the n-type doping concentration of the top layer is 1.10 15 cm -3 ~5.10 15 cm -3 is within the range.

[0031] In this manner, the n-type doping of the top layer of the silicon-on-insulator substrate compensates and balances the concentration of group III elements that diffuse from the epitaxial layer into the top layer of the silicon-on-insulator substrate.

[0032] According to an exemplary embodiment, the thickness of the top layer is comprised between 50 and 200 nm. Alternatively, the thickness of the top layer is less than 100 nm.

[0033]

[0033] In this way, the intermediate layer confines the diffusion or migration of group III elements within the thin silicon layer formed by the top layer. In other words, the intermediate layer confines the diffusion or migration of group III elements to the surface region of the silicon-on-insulator substrate close to the epitaxial layer of the group III-nitride heterostructure. The semiconductor structure then exhibits improved performance at high power and frequency, improved resistivity, and reduced power loss and linearity problems.

[0034] According to an exemplary embodiment, the top layer comprises n-type doped silicon, and the n-type doped silicon of the top layer has a (111) orientation.

[0035] According to an exemplary embodiment, the top layer comprises single crystal silicon.

[0036]

[0036] In this way, the top layer of single crystal silicon can be used, for example, to manufacture optical waveguides and other optical devices, either passive or active, for example by suitable implantation. The buried insulator allows, for example, the propagation of infrared light in the top layer of silicon based on total internal reflection. The upper surface of the waveguides manufactured in the top layer can be left uncovered and exposed to air, for example for sensing applications, or can be covered with a cladding, for example made of silica.

[0037] According to an exemplary embodiment, the buried insulator comprises amorphous silicon carbide and the trap rich layer comprises amorphous silicon carbide.

[0038]

[0038] In this way, the amorphous silicon carbide acts as a trap rich and a barrier that confines the diffusion or migration of group III elements from the epitaxial layer of the III-nitride heterostructure into the silicon-on-insulator substrate within a surface region of the silicon-on-insulator substrate close to the epitaxial layer of the III-nitride heterostructure, e.g., within the top layer, and optionally near the interface between the middle layer and the top layer. Alternatively, the trap rich layer comprises silicon or polysilicon.

[0039] According to an exemplary embodiment, the buried insulator comprises silicon dioxide and the trap rich layer comprises silicon.

[0040] According to an exemplary embodiment, the buried insulator comprises silicon dioxide and the trap rich layer comprises amorphous silicon carbide.

[0041] Alternatively, the trap rich layer includes polysilicon.

[0042] According to an exemplary embodiment, the buried insulator comprises a layer comprising silicon nitride confined between two layers comprising silicon oxide, and the trap rich layer comprises amorphous silicon carbide.

[0043]

[0043] In this exemplary embodiment, the buried insulator comprises an ONO dielectric stack, where ONO stands for oxide-nitride-oxide. The buried insulator provides better thermal conduction than silicon dioxide without excessively degrading parasitic capacitive coupling or endangering high speed performance of, for example, active devices fabricated from the semiconductor structure according to the present disclosure. Furthermore, the buried insulator comprising a layer comprising silicon nitride further enhances the technical effect of including the diffusion or migration of group III elements from the epitaxial layer of the III-nitride heterostructure to the silicon-on-insulator substrate in a surface region of the silicon-on-insulator substrate close to the epitaxial layer of the III-nitride heterostructure, for example in the top layer, and optionally near the interface between the middle layer and the top layer. Blocking the diffusion of group III elements from the epitaxial layer of the III-nitride heterostructure to the silicon-on-insulator substrate is more efficient in a semiconductor structure comprising a buried insulator comprising silicon nitride than in a semiconductor structure comprising a buried insulator comprising only silicon dioxide. Alternatively, the trap rich layer comprises silicon or polysilicon.

[0044] According to an exemplary embodiment, the silicon carbide is amorphous.

[0045]

[0045] The amorphous silicon carbide traps in the trap rich layer capture free carriers at the interface between the top silicon layer and the intermediate layer, thereby enabling the silicon-on-insulator substrate to regain its nominal resistivity, linearity, eliminate DC dependence, and result in significant reduction in RF losses and crosstalk.

[0046]

[0046] According to an exemplary embodiment, the thickness of the trap rich layer is comprised between several tens of nanometers and several micrometers. For example, the thickness of a trap rich layer comprising amorphous silicon carbide can reach several tens of nanometers. Alternatively, the thickness of a trap rich layer comprising polysilicon can reach several micrometers.

[0047] According to an exemplary embodiment, the thickness of the buried insulator is comprised between 100 nm and 500 nm.

[0048] According to an exemplary embodiment, the thickness of the intermediate layer, including the buried insulator and the trap rich layer, is comprised between a few hundred nanometers and a few micrometers.

[0049] According to an exemplary embodiment, the epitaxial III-N semiconductor layer stack further comprises a spacer layer formed between the first active III-N layer and the second active III-N layer.

[0050]

[0050] In this manner, the spacer layer epitaxially grown between the first and second active III-N layers enhances electron mobility in the epitaxial III-N semiconductor layer stack.

[0051] According to an exemplary embodiment, the first active III-N layer comprises gallium nitride and the second active III-N layer comprises aluminum gallium nitride.

[0052]

[0052] Preferably, the first active III-N layer is epitaxially grown and comprises pure gallium nitride, preferably a single layer of gallium nitride.

[0053]

[0053] According to an exemplary embodiment, the first active III-N layer comprises InAlGaN, the second active III-V layer comprises InAlGaN, the second active III-N layer comprises a bandgap larger than the bandgap of the first active III-N layer, and the second active III-N layer comprises a polarization larger than the polarization of the first active III-N layer.

[0054]

[0054] In this manner, the use of different materials in adjacent first and second active III-N layers causes polarization to contribute to the conductive 2DEG region near the junction between the first and second active III-N layers, particularly in the first active III-N layer comprising a bandgap narrower than the bandgap of the second active III-N layer.

[0055] The first active III-N layer has a thickness comprised, for example, between 20 and 500 nm, preferably between 30 and 300 nm, more preferably between 50 and 250 nm, for example between 100 and 150 nm. The second active III-N layer has a thickness comprised, for example, between 10 and 100 nm, preferably between 20 and 50 nm. Such a combination of thicknesses leads to good properties for the active layer, for example with regard to the 2DEG obtained.

[0056] According to an exemplary embodiment, the spacer layer comprises aluminum nitride.

[0057] Preferably, the spacer layer is epitaxially grown and comprises pure aluminum nitride.

[0058] According to an exemplary embodiment, the spacer layer has a thickness of less than 2 nm.

[0059]

[0059] In this way, the spacer layer is kept thin enough to minimize the roughness of the spacer layer. Due to the minimized roughness, the spacer layer prevents the diffusion or migration of group III atoms into at least the first active III-N layer. In this way, the thermal stability of the semiconductor structure is further improved. In other words, the thinner the spacer layer, the better the thermal stability of the semiconductor structure. Preferably, the thickness of the spacer layer is comprised between 0.5 nm and 1.5 nm. Even more preferably, the thickness of the spacer layer is comprised between 0.8 nm and 1 nm.

[0060] According to an exemplary embodiment, the epitaxial III-N semiconductor layer stack further comprises an epitaxially grown buffer layer grown between the substrate and the epitaxial active layer.

[0061]

[0061] The buffer layer may be of a different nature from the substrate in that the bandgaps of the substrate and the buffer layer are relatively far apart, for example 1.1 eV and 6.2 eV, respectively, in the sense that the buffer layer has a high bandgap to provide current properties, such as high breakdown voltages, for example greater than 250V, preferably greater than 500V, even more preferably greater than 2000V, greater than 1000V, or even much greater. The buffer layer may be, for example, a III-V buffer layer with a high bandgap, where III refers to group III elements, such as B, Al, Ga, In, Tl, Sc, Y, and the lanthanides and actinides series. Wherein V refers to group V elements, such as N, P, As, Sb, Bi. The buffer layer may comprise a stack of layers, and in one example, typically the first layer is a nucleation layer.

[0062] According to an exemplary embodiment, the semiconductor structure further comprises a passivation stack formed over the epitaxial III-N semiconductor layer.

[0063]

[0063] The passivation stack is formed in situ with the formation of the epitaxial III-N semiconductor layer stack. The passivation stack is formed, for example, on top of the second active III-N layer. In this way, a fully crystalline passivation stack is epitaxially grown on top of the epitaxial III-N semiconductor layer stack. Alternatively, a partially crystalline passivation stack is epitaxially grown on top of the epitaxial III-N semiconductor layer stack. The passivation stack can also be formed by ex situ deposition with the aid of an epitaxy tool, such as atomic layer deposition, also called ALD, chemical vapor deposition, also called CVD, or physical vapor deposition, also called PVD. Alternatively, the passivation stack can be formed by in situ deposition in an MOCVD or MBE chamber. Alternatively, the passivation stack can be formed by depositing an amorphous film of the same material and recrystallizing the amorphous film using thermal annealing. The passivation stack on the second active III-N layer may, for example, comprise gallium nitride. Alternatively, the passivation stack on the second active III-N layer may comprise gallium nitride and silicon nitride.

[0064]

[0064] A passivation stack is formed between the epitaxial III-N semiconductor layer stack and, for example, the gate of a transistor. The passivation stack can be formed only under the gate and can further function as a gate dielectric. Alternatively, the passivation stack can be formed on top of the epitaxial III-N semiconductor layer stack and can completely cover the epitaxial III-N semiconductor layer stack. Alternatively, the passivation stack can be formed on top of the epitaxial III-N semiconductor layer stack and can partially cover the surface of the epitaxial III-N semiconductor layer stack, for example, the passivation stack can be formed in the non-gated area between the source and drain of a high mobility electron transistor, and the passivation stack functions as a passivation and prevents depletion of the underlying 2DEG.

[0065] According to an exemplary embodiment, the passivation stack further comprises an oxide layer and / or silicon nitride.

[0066]

[0066] Thus, the passivation layer of the semiconductor structure according to the first exemplary embodiment of the present disclosure includes a silicon nitride and / or oxide layer serving as a passivation layer, which presents an electrically clean interface to the second active III-N layer and a high dielectric constant to maximize the capacitive coupling between the electrical contacts formed on the semiconductor structure and the 2DEG, which results in an increased transconductance of, for example, a high electron mobility transistor fabricated using the semiconductor structure, and a sufficient thickness to avoid breakdown and leakage due to quantum tunneling.

[0067] According to a second exemplary aspect of the present disclosure, there is provided a method for manufacturing a semiconductor structure, the method comprising: providing a base layer comprising silicon; Providing a trap rich layer; providing a buried insulator formed over the trap rich layer; providing an intermediate layer on the base layer by providing a top layer comprising n-type doped silicon formed over the intermediate layer; providing a silicon-on-insulator substrate, Providing an epitaxial III-N semiconductor layer stack on a silicon-on-insulator substrate, the epitaxial III-N semiconductor layer stack comprising an epitaxial active layer, and providing the epitaxial active layer includes: providing a first active III-N layer on the top layer; Providing a second active III-N layer on the first active III-N layer. providing an epitaxial III-N semiconductor layer stack, whereby a two-dimensional electron gas is formed between the first active III-N layer and the second active III-N layer; Includes.

[0068]

[0068] As mentioned above, the presence of p-type dopants at the interface between a III-nitride heterostructure and a silicon substrate on which the III-nitride heterostructure is, for example, epitaxially grown, can be measured, for example, using spreading resistance profiling measurements. Such presence of p-type dopants at the interface between the III-nitride heterostructure and silicon is due to the diffusion or migration of impurities from the initial growth layer of the III-nitride heterostructure epitaxial layer into the silicon substrate. The impurities act as p-type impurities for the silicon substrate. More specifically, such presence of p-type dopants at the interface between the III-nitride heterostructure and silicon is due to the diffusion or migration of group III elements into the silicon substrate where they act as p-type impurities for the silicon substrate.

[0069]

[0069] In the method for manufacturing a semiconductor structure according to the present disclosure, the diffusion or migration of group III elements from the epitaxial layer of the III-nitride heterostructure to the silicon-on-insulator substrate is confined within a surface region of the silicon-on-insulator substrate close to the epitaxial layer of the III-nitride heterostructure, for example within the top layer, and optionally near the interface between the intermediate layer and the top layer. In fact, in the method according to the present disclosure, the intermediate layer of the silicon-on-insulator substrate confines the diffusion or migration of group III elements within a surface region of the silicon-on-insulator substrate close to the epitaxial layer of the III-nitride heterostructure, for example within the top layer, and optionally near the interface between the intermediate layer and the top layer, thereby shortening the diffusion distance of impurities into the silicon-on-insulator substrate.

[0070]

[0070] In the method for manufacturing a semiconductor structure according to the present disclosure, the n-type doping of the top layer of the silicon-on-insulator substrate compensates for the concentration of group III elements diffusing from the epitaxial layer into the silicon-on-insulator substrate. In other words, the n-type doping of the top layer of the silicon-on-insulator substrate balances the concentration of p-type dopants at the interface between the epitaxial layer and the silicon-on-insulator substrate, which concentrations of p-type dopants result from the diffusion of group III atoms from the epitaxial III-N semiconductor layer stack into the top layer of the silicon-on-insulator substrate.

[0071]

[0071] Thus, semiconductor structures fabricated using methods according to the present disclosure exhibit improved performance at high power and high frequency, improved resistivity, and reduced power loss and linearity issues.

[0072]

[0072] The epitaxial III-N semiconductor layer stack comprises an epitaxial active layer comprising a first active III-N layer, an optional spacer layer, and a second active III-N layer. The epitaxial active layer is formed in situ by epitaxial growth in a metalorganic chemical vapor deposition epitaxial chamber, also called MOCVD, or a metalorganic vapor phase epitaxial chamber, also called MOVPE, or a molecular beam epitaxial chamber, also called MBE, or a chemical beam epitaxial chamber, also called CBE.

[0073]

[0073] The semiconductor structure may be formed by epitaxial growth by metalorganic chemical vapor deposition (MOCVD) or metalorganic vapor phase epitaxy (MOVPE), or it may be molecular beam epitaxy (MBE) or chemical beam epitaxy (CBE). In the MOVPE or MOCVD process, an epitaxial III-N semiconductor layer stack is epitaxially grown on a silicon-on-insulator substrate at a pressure typically comprised between, for example, 5 mBar and 1 Bar, and at a temperature typically comprised between, for example, 600°C and 1200°C. The precursor materials may be, but are not limited to, ammonia (NH3) for nitrogen, trimethylGa (TMGa) or triethylGa (TEGa) for gallium, trimethylAl (TMAl) or triethylAl (TEAl) for aluminum, trimethylindium (TMIn) for indium, and silane (SiH4) or disilane (SiH3)2 for silicon.

[0074]

[0074] The silicon-on-insulator substrate may comprise a buried insulator comprising silicon oxide, in which case it may be produced by several methods, such as separation by implantation of oxygen, known as SIMOX, or wafer bonding, or by a seed method.

[0075] According to an exemplary embodiment, providing a top layer comprising n-type doped silicon includes doping the top layer of silicon by thermal diffusion of an n-type dopant into the top layer of silicon.

[0076]

[0076] Preferably, the n-type doping concentration of the top layer is 1.10 15 cm -3 ~5.10 15 cm -3 is within the range.

[0077] According to an exemplary embodiment, providing a top layer comprising n-type doped silicon includes doping the top layer of silicon by ion implantation of an n-type dopant into the top layer of silicon.

[0078]

[0078] Preferably, the n-type doping concentration of the top layer is 1.10 15 cm -3 ~5.10 15 cm -3 is within the range.

[0079] According to an exemplary embodiment, the n-type dopant is Phosphorescence, Arsenic, Antimony Includes one or more of:

[0080]

[0080] Some exemplary embodiments will now be described with reference to the accompanying drawings. [Brief description of the drawings]

[0081] [Figure 1A] 1 shows a schematic diagram of an exemplary embodiment of measurements performed using spreading resistance profiling on gallium nitride epitaxially grown on a silicon substrate according to the prior art; [Figure 1B] 1 shows a schematic diagram of another exemplary embodiment of measurements performed using spreading resistance profiling on gallium nitride epitaxially grown on a silicon substrate according to the prior art; [Diagram 2] 1 illustrates a schematic diagram of an exemplary embodiment of a semiconductor structure according to the present disclosure; [Diagram 3] 1 illustrates a schematic representation of an exemplary embodiment of a semiconductor structure according to the present disclosure, in which a buried insulator comprises a layer comprising silicon nitride confined between two layers comprising silicon dioxide. [Figure 4] 1 illustrates a schematic representation of an exemplary embodiment of a semiconductor structure according to the present disclosure, in which the epitaxial III-N semiconductor layer stack further comprises a spacer between a first active III-N layer and a second active III-N layer. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0082] Detailed Description of the Embodiments

[0085] FIG. 1A shows a schematic representation of an exemplary embodiment of a measurement performed by means of spreading resistance profiling on gallium nitride epitaxially grown on a silicon substrate according to the prior art. Indeed, FIG. 1A shows a schematic representation of the resistivity 91 on a logarithmic scale of a sample comprising gallium nitride epitaxially grown on silicon as a function of depth 92 in the gallium nitride on silicon heterostructure. In FIG. 1A, section 93 corresponds to the gallium nitride and section 95 corresponds to a portion of the silicon substrate. Section 94 on FIG. 1A corresponds to the interface between the gallium nitride and the silicon substrate. As can be seen on FIG. 1A, the resistivity 96 measured in the gallium nitride is approximately constant throughout the layer, being approximately 1.10 6 The resistivity, which is equal to ohm cm and is measured approximately 1 μm into the silicon substrate, is approximately constant at 1.10 4 However, at the interface 94 between the gallium nitride and the silicon substrate, a significant drop in resistivity 97 is measured by spreading resistance profiling, as seen in FIG. 1A. More precisely, the resistivity 97 at section 94 of the heterostructure is 1.10 6 Ohm cm to 1.10 1 After decreasing to ohm cm, it is 1.10 4 It slowly increases again to ohms cm, going deeper into the silicon substrate. As can be seen in Figure 1A, the drop in resistivity 97 extends from 0.5 μm to nearly 1 μm into the silicon substrate.

[0083]

[0086] The drop in resistivity at the interface between gallium nitride and the silicon substrate is further investigated using spreading resistance profiling measurements. The results of such measurements are shown, for example, in FIG. 1B. FIG. 1B shows a schematic representation of the concentration of species and their type on a logarithmic scale in the same sample containing gallium nitride epitaxially grown on a silicon substrate as characterized on FIG. 1A. In FIG. 1B, section 93 corresponds to the gallium nitride and section 95 corresponds to a portion of the silicon substrate. Section 94 on FIG. 1B corresponds to the interface between gallium nitride and the silicon substrate. As can be seen on FIG. 1B, the gallium nitride in this sample is almost undoped, with a doping rate of 2.10 10 atom.cm -3 The silicon substrate shows a lower concentration of 81 than the sample, and the silicon substrate is 2.10 μm from approximately 1 μm into the silicon substrate. 11 atom.cm -3 From 6.10 11 atom.cm -3 However, at the interface 94 between the gallium nitride and the silicon substrate, a significant concentration 82 of p-type dopant is measured by spreading resistance profiling, as seen in FIG. 1B. More precisely, this concentration 82 is close to 2.10 in the gallium nitride. 10 atom.cm -3 2.10 in Section 94, up from 15 atom.cm -3 Then the concentration 82 slowly decreases again into the silicon substrate, reaching 2.10 11 atom.cm -3 The conclusion can be drawn from such spreading resistance profiling measurements that a high concentration of p-type dopants is present at the interface between gallium nitride and silicon, extending over 0.5 μm to almost 1 μm, and into the silicon substrate.

[0084]

[0087] FIG. 2 shows a schematic cross-section of an exemplary embodiment of a semiconductor structure 1 according to the present disclosure, the cross-section being performed along a plane containing a growth direction 2, with a transverse direction 3 transverse to the growth direction 2. A third direction 4 is transverse to the growth direction 2 and the transverse direction 3. The semiconductor structure 1 comprises a silicon-on-insulator substrate 101 and an epitaxial III-N semiconductor layer stack 202 on the silicon-on-insulator substrate 101. The silicon-on-insulator substrate 101 comprises a base layer 10, an intermediate layer 11 formed on the base layer 10, and a top layer 12 formed on the intermediate layer 11. The base layer 10 comprises silicon. The resistivity of the base layer 10 is typically comprised between 3 and 5 kilo-ohm-cm, greater than 1 kilo-ohm-cm. The epitaxial III-N semiconductor layer stack 202 comprises an epitaxial active layer 20. The epitaxial active layer 20 comprises a first active III-N layer 21 formed on the top layer 12 and a second active III-N layer formed on the first active III-N layer 21. The first active III-N layer 21 includes, for example, gallium nitride, and the second active III-N layer 22 includes, for example, aluminum gallium nitride. A two-dimensional electron gas 200 is formed between the first active III-N layer 21 and the second active III-N layer 22. The top layer 12 includes n-type doped silicon. The orientation of the silicon in the top layer 12 is (111). The n-type doping concentration of the top layer 12 is 1.10 15 cm -3 ~5.10 15 cm -3The thickness of the top layer 12 is comprised between 50 and 200 nm. According to an alternative embodiment, the thickness of the top layer 12 is less than 100 nm. The intermediate layer 11 comprises a trap rich layer 111 and a buried insulator 121 formed on the trap rich layer 111. The buried insulator 121 comprises silicon dioxide and the trap rich layer 111 comprises silicon. The thickness of the buried insulator 121 is comprised between 100 nm and 500 nm. The thickness of the trap rich layer 111 may be, for example, several micrometers. According to an alternative embodiment, the buried insulator 121 comprises silicon dioxide and the trap rich layer 111 comprises silicon carbide, for example amorphous silicon carbide. The thickness of the trap rich layer 111 may be, for example, several tens of nanometers.

[0085]

[0088] FIG. 3 shows a schematic cross-section of an exemplary embodiment of a semiconductor structure 1 according to the present disclosure, the cross-section being performed along a plane containing the growth direction 2, with a transverse direction 3 transverse to the growth direction 2. A third direction 4 is transverse to the growth direction 2 and the transverse direction 3. Components with the same reference numbers as on FIG. 2 perform the same functions. The semiconductor structure 1 comprises a silicon-on-insulator substrate 101 and an epitaxial III-N semiconductor layer stack 202 on the silicon-on-insulator substrate 101. The silicon-on-insulator substrate 101 comprises a base layer 10, an intermediate layer 11 formed on the base layer 10, and a top layer 12 formed on the intermediate layer 11. The base layer 10 comprises silicon. The resistivity of the base layer 10 is typically comprised between 3 and 5 kilo-ohm-cm, greater than 1 kilo-ohm-cm. The epitaxial III-N semiconductor layer stack 202 comprises an epitaxial active layer 20. The epitaxial active layer 20 comprises a first active III-N layer 21 formed on the top layer 12 and a second active III-N layer formed on the first active III-N layer 21. The first active III-N layer 21 includes, for example, gallium nitride, and the second active III-N layer 22 includes, for example, aluminum gallium nitride. A two-dimensional electron gas 200 is formed between the first active III-N layer 21 and the second active III-N layer 22. The top layer 12 includes n-type doped silicon. The orientation of the silicon in the top layer 12 is (111). The n-type doping concentration of the top layer 12 is 1.10 15 cm -3 ~5.10 15 cm -3The thickness of the top layer 12 is in the range of 100 nm. The thickness of the top layer 12 is comprised between 50 and 200 nm. According to an alternative embodiment, the thickness of the top layer 12 is less than 100 nm. The intermediate layer 11 comprises a trap rich layer 111 and a buried insulator 121 formed on the trap rich layer 111. The buried insulator 121 comprises a layer 131 comprising silicon nitride limited between two layers 132, 133 comprising silicon oxide, the trap rich layer 111 comprising silicon carbide, for example amorphous silicon carbide. According to an alternative embodiment, the buried insulator 121 comprises silicon dioxide and the trap rich layer 111 comprises silicon carbide, for example amorphous silicon carbide. The thickness of the buried insulator 121 is comprised between 100 nm and 500 nm. The thickness of the trap rich layer 111 may be, for example, several tens of nanometers. According to a further alternative embodiment, the buried insulator 121 comprises silicon dioxide and the trap rich layer 111 comprises silicon. The thickness of the trap rich layer 111 may be, for example, a few micrometers.

[0086]

[0089] FIG. 4 shows a schematic cross-section of an exemplary embodiment of a semiconductor structure 1 according to the present disclosure, the cross-section being performed along a plane containing the growth direction 2, with a transverse direction 3 transverse to the growth direction 2. A third direction 4 is transverse to the growth direction 2 and the transverse direction 3. Components with the same reference numbers as on FIG. 2 or FIG. 3 perform the same functions. The semiconductor structure 1 comprises a silicon-on-insulator substrate 101 and an epitaxial III-N semiconductor layer stack 202 on the silicon-on-insulator substrate 101. The silicon-on-insulator substrate 101 comprises a base layer 10, an intermediate layer 11 formed on the base layer 10, and a top layer 12 formed on the intermediate layer 11. The base layer 10 comprises silicon. The resistivity of the base layer 10 is typically comprised between 3 and 5 kilo-ohm-cm, greater than 1 kilo-ohm-cm. The epitaxial III-N semiconductor layer stack 202 comprises an epitaxial active layer 20. The epitaxial active layer 20 comprises a first active III-N layer 21 formed on the top layer 12, a spacer layer 23 formed on the first active III-N layer 21, and a second active III-N layer formed on the spacer layer 23. The first active III-N layer 21 comprises, for example, gallium nitride, and the second active III-N layer 22 comprises, for example, aluminum gallium nitride. The spacer layer 23 preferably comprises aluminum nitride. A two-dimensional electron gas 200 is formed between the first active III-N layer 21 and the second active III-N layer 22. The top layer 12 comprises n-type doped silicon. The orientation of the silicon in the top layer 12 is (111). The n-type doping concentration of the top layer 12 is 1.10 15 cm -3 ~5.10 15 cm -3The thickness of the top layer 12 is comprised between 50 and 200 nm. According to an alternative embodiment, the thickness of the top layer 12 is less than 100 nm. The intermediate layer 11 comprises a trap rich layer 111 and a buried insulator 121 formed on the trap rich layer 111. The buried insulator 121 comprises silicon dioxide and the trap rich layer 111 comprises silicon. The thickness of the buried insulator 121 is comprised between 100 nm and 500 nm. The thickness of the trap rich layer 111 may be, for example, a few micrometers. According to an alternative embodiment, the buried insulator 121 comprises silicon dioxide and the trap rich layer 111 comprises silicon carbide, for example amorphous silicon carbide. The thickness of the trap rich layer 111 may be, for example, a few micrometers.

[0087]

[0090] Although the present invention has been illustrated by reference to specific embodiments, it will be apparent to those skilled in the art that the present invention is not limited to the details of the above exemplary embodiments, and the present invention can be practiced with various changes and modifications without departing from the scope of the present invention. The present embodiments are therefore to be considered in all respects as illustrative and not restrictive, the scope of the invention being indicated by the appended claims rather than by the foregoing description, and all modifications that fall within the scope of the claims are therefore intended to be embraced.

[0088]

[0091] Furthermore, readers of this patent application will understand that the words "comprising" or "comprise" do not exclude other elements or steps, and the words "a" or "an" do not exclude a plurality, and that a single element, such as a computer system, processor, or another integrated unit, may perform the functions of several means recited in the claims. Any reference signs in the claims should not be construed as limiting the respective claims concerned. Terms such as "first", "second", "third", "a", "b", "c", etc., used in the specification or claims, are introduced to distinguish similar elements or steps and do not necessarily describe a sequential or chronological order. Similarly, terms such as "upper", "lower", "upper", "lower", etc., are introduced for explanatory purposes and do not necessarily indicate a relative position. It will be understood that the terms so used are interchangeable under appropriate circumstances, and that embodiments of the invention can operate in other orders according to the invention or in orientations different from those described or illustrated above.

Claims

1. a base layer (10) comprising silicon; an intermediate layer (11) formed on the base layer (10); and A top layer (12) formed on the intermediate layer (11) a silicon-on-insulator substrate (101) comprising: an epitaxial III-N semiconductor layer stack (202) on the silicon-on-insulator substrate (101), the epitaxial III-N semiconductor layer stack (202) comprising an epitaxial active layer (20), the epitaxial active layer (20) comprising: a first active III-N layer (21) formed on said top layer (12); A second active III-N layer (22) formed on the first active III-N layer (21). an epitaxial III-N semiconductor layer stack (202) comprising a two-dimensional electron gas (200) between the first active III-N layer (21) and the second active III-N layer (22); Equipped with the top layer (12) comprises n-type doped silicon; The intermediate layer (11) a trap rich layer (111); a buried insulator (121) formed on the trap rich layer (111); A semiconductor structure (1) comprising:

2. The n-type doping concentration of the top layer (12) is 1.10 １５ cm －３ ~5.10 １５ cm －３ The semiconductor structure (1) according to claim 1, wherein

3. The semiconductor structure (1) according to claim 1 or 2, wherein the thickness of said top layer (12) is comprised between 50 and 200 nm.

4. 3. The semiconductor structure (1) of claim 1 or 2, wherein the n-type doped silicon of the top layer (12) has a (111) orientation.

5. The semiconductor structure (1) of claim 1 or 2, wherein the buried insulator (121) comprises silicon dioxide and the trap rich layer (111) comprises silicon.

6. The semiconductor structure (1) of claim 1 or 2, wherein the buried insulator (121) comprises silicon dioxide and the trap rich layer (111) comprises amorphous silicon carbide.

7. 3. The semiconductor structure (1) of claim 1 or 2, wherein the buried insulator (121) comprises a layer (131) comprising silicon nitride confined between two layers (132, 133) comprising silicon oxide, and the trap rich layer (111) comprises amorphous silicon carbide.

8. The semiconductor structure (1) according to claim 1 or 2, wherein the thickness of the buried insulator (121) is comprised between 100 nm and 500 nm.

9. 3. The semiconductor structure (1) of claim 1, wherein the epitaxial III-N semiconductor layer stack (202) further comprises a spacer layer (23) formed between the first active III-N layer (21) and the second active III-N layer (22).

10. The semiconductor structure (1) of claim 1 or 2, wherein the first active III-N layer (21) comprises gallium nitride and the second active III-N layer (22) comprises aluminum gallium nitride.

11. The semiconductor structure (1) of claim 9, wherein the spacer layer (23) comprises aluminum nitride.

12. A method for manufacturing a semiconductor structure (1), comprising: providing a base layer (10) comprising silicon; providing a trap rich layer (111); providing a buried insulator (121) formed on the trap rich layer (111); providing an intermediate layer (11) on the base layer (10) by Providing a top layer (12) comprising n-type doped silicon formed on said intermediate layer (11). providing a silicon-on-insulator substrate (101), providing an epitaxial III-N semiconductor layer stack (202) on the silicon-on-insulator substrate (101), the epitaxial III-N semiconductor layer stack (202) comprising an epitaxial active layer (20); providing a first active III-N layer (21) on said top layer (12); providing a second active III-N layer (22) on the first active III-N layer (21); providing an epitaxial III-N semiconductor layer stack (202), whereby a two-dimensional electron gas (200) is formed between the first active III-N layer (21) and the second active III-N layer (22); A method comprising:

13. 13. The method of claim 12, wherein the step of providing a top layer (12) comprising n-type doped silicon comprises doping the silicon of the top layer (12) by thermal diffusion of n-type dopants into the silicon of the top layer (12).

14. 13. The method of claim 12, wherein the step of providing a top layer (12) comprising n-type doped silicon comprises doping the silicon of the top layer (12) by ion implantation of an n-type dopant into the silicon of the top layer (12).

15. The n-type dopant is Phosphorus, arsenic, Antimony The method of any one of claims 12 to 14, comprising one or more of:

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