Short gates on the active for nanosheets and longer gates on STI

Abstract

Short gates on the active for nanosheets and longer gates on STI A method for forming a nanosheet device is presented, the method including forming a nanosheet stack on a substrate, the nanosheet stack being separated by shallow trench isolation (STI) regions, forming a first hardmask material on the nanosheet stack, depositing a sacrificial gate, recessing the sacrificial gate such that a recess is defined adjacent the first hardmask material, where a top surface of the sacrificial gate is below a top surface of the first hardmask material, forming a second hardmask material in the recess, defining a uniform gate length in both the first and second hardmask materials, and selectively trimming the first hardmask material such that the gate length over the nanosheet stack is less than the gate length over the STI regions.

Description

[Background technology]

[0001] The present invention relates generally to semiconductor devices, and more particularly to a self-aligned method and structure for forming short gates over active areas and longer gates over shallow trench isolation (STI) regions for nanosheet (NS) multi-threshold integration.

[0002] As semiconductor integrated circuits (ICs) or chips get smaller, stacked nanosheets, which are two-dimensional nanostructures with thicknesses ranging from approximately 1 to 100 nanometers, are increasingly used. Nanosheets and nanowires are seen as viable device options at 5 nanometers and beyond the scaling of semiconductor devices. The general process flow for nanosheet formation involves removing a sacrificial layer of silicon germanium (SiGe) between silicon (Si) sheets. Summary of the Invention

[0003] According to an embodiment of the present invention, a method for forming a nanosheet device is provided. The method includes forming a nanosheet stack(s) on a substrate, the nanosheet stack(s) being separated by shallow trench isolation (STI) regions(s), forming a first hardmask material over the nanosheet stack(s), depositing a sacrificial gate, recessing the sacrificial gate such that recess(s) are defined adjacent the first hardmask material, where an upper surface of the sacrificial gate is below an upper surface of the first hardmask material, forming a second hardmask material in the recess(s), defining a uniform gate length in both the first and second hardmask materials, and selectively trimming the first hardmask material such that the gate length over the nanosheet stack(s) is less than the gate length over the STI regions(s).

[0004] According to another embodiment of the present invention, a method for forming a nanosheet device is provided. The method includes forming a nanosheet stack over a substrate, the nanosheet stack separated by shallow trench isolation (STI) regions; forming a first hardmask material over the nanosheet stack; depositing a first sacrificial material; removing the first hardmask material such that a first recess is defined over the nanosheet stack; depositing a second sacrificial material in the first recess defined over the nanosheet stack; forming a second hardmask material over the second sacrificial material; recessing the first sacrificial material such that a second recess is defined adjacent the second hardmask material; forming a third hardmask material in the second recess; defining a uniform gate length in both the second and third hardmask materials; and selectively trimming the second hardmask material such that the gate length over the nanosheet stack is less than the gate length over the STI regions.

[0005] According to yet another embodiment, a nanosheet device is provided, the nanosheet device including: a nanosheet stack disposed over a substrate, the nanosheet stack separated by a shallow trench isolation (STI) region to define a non-uniform gate length across the nanosheet transistor, such that the gate length above the nanosheet stack is smaller than the gate length above the STI region, and a work function metal (WFM) disposed over the nanosheet stack and the STI region, the WFM pinches off in a region defined by the gate length above the nanosheet stack, and the WFM cannot pinch off in a region defined by the gate length above the STI region.

[0006] It should be noted that exemplary embodiments of the present invention are described with reference to different subject matter. In particular, some embodiments are described with reference to method type claims, while other embodiments are described with reference to apparatus type claims. However, a person skilled in the art shall infer from the above and following description that, unless otherwise stated, any combination of features belonging to one type of subject matter, as well as any combination of features relating to different subject matter, in particular any combination of features of method type claims and features of apparatus type claims, shall also be considered as described herein.

[0007] These and other features and advantages will become apparent from the following detailed description of illustrative embodiments thereof, which should be read in connection with the accompanying drawings.

[0008] The present invention provides details in the following description of preferred embodiments with reference to the following figures. [Brief description of the drawings]

[0009] [Figure 1] 1 is a cross-sectional view of a semiconductor structure including a nanosheet stack formed on a substrate according to an embodiment of the present invention. [Diagram 2] 2 is a cross-sectional view of the semiconductor structure of FIG. 1 in which an oxide is deposited on the nanosheet stack, according to an embodiment of the present invention. [Diagram 3] 3 is a cross-sectional view of the semiconductor structure of FIG. 2 in which a dummy gate is deposited over an oxide and planarization is performed in accordance with an embodiment of the present invention. [Figure 4] FIG. 4 is a cross-sectional view of the semiconductor structure of FIG. 3 in which the dummy gate is recessed to expose a first hard mask formed on the nanosheet stack, according to an embodiment of the present invention. [Diagram 5]FIG. 5 is a cross-sectional view of the semiconductor structure of FIG. 4 in which a second hardmask is formed adjacent to the first hardmask, an organic planarization layer (OPL) is deposited over the first and second hardmasks, and the first and second hardmasks are etched to form openings exposing an amorphous silicon (a-Si) layer formed over the nanosheet stack, in accordance with an embodiment of the invention. [Figure 6] FIG. 6 is a cross-sectional view of the semiconductor structure of FIG. 5 in which an isotropic etch occurs to selectively etch portions of the first hard mask to define rounded edges for the first hard mask, in accordance with an embodiment of the present invention. [Figure 7] 7 is a cross-sectional view of the semiconductor structure of FIG. 6 with the OPL removed in accordance with an embodiment of the present invention. [Figure 8] FIG. 8 is a cross-sectional view of the semiconductor structure of FIG. 7 in which a first hard mask shape is transferred to an a-Si layer formed on top of the nanosheet stack, according to an embodiment of the invention. [Figure 9] 9 is a cross-sectional view of the semiconductor structure of FIG. 8 on which a gate spacer is deposited, in accordance with an embodiment of the present invention. [Figure 10] 10 is a cross-sectional view of the semiconductor structure of FIG. 9, in which source / drain epitaxial regions and inner spacers are formed within the nanosheet stack, according to an embodiment of the invention. [Figure 11] FIG. 11 is a cross-sectional view of the semiconductor structure of FIG. 10 after the first and second hard masks have been removed and an interlayer dielectric (ILD) is formed over the source / drain epitaxial regions in accordance with an embodiment of the present invention. [Figure 12] FIG. 12 is a cross-sectional view of the semiconductor structure of FIG. 11 in which the dummy gate regions and every other sacrificial layer of the nanosheet stack are removed in accordance with an embodiment of the present invention. [Figure 13] 13 is a cross-sectional view of the semiconductor structure of FIG. 12, where work function metal (WFM) deposition occurs, in accordance with an embodiment of the present invention. [Figure 14]14 is a cross-sectional view of the semiconductor structure of FIG. 13 in which a mask is deposited to pattern the WFM, the WFM is exposed to an isotropic etch, and a WFM seal is formed under the mask, in accordance with an embodiment of the present invention. [Figure 15] 15 is a cross-sectional view of the semiconductor structure of FIG. 14 in which the remaining WFM is etched away, the mask is removed, and then another WFM is deposited in accordance with an embodiment of the present invention. [Figure 16] FIG. 2 is a cross-sectional view of a semiconductor structure including a nanosheet stack formed on a substrate, where, in contrast to FIG. 1, a-Si is not formed on the nanosheet stack, according to an embodiment of the present invention. [Figure 17] FIG. 17 is a cross-sectional view of the semiconductor structure of FIG. 16 in which an oxide is deposited, a dummy material is deposited over the oxide, planarization is performed, the nanosheet stack hard mask is recessed, and the exposed oxide areas are removed in accordance with an embodiment of the present invention. [Figure 18] FIG. 18 is a cross-sectional view of the semiconductor structure of FIG. 17 in which directional fill occurs to deposit an a-Si portion on top of the nanosheet stack, according to an embodiment of the present invention. [Figure 19] FIG. 19 is a cross-sectional view of the semiconductor structure of FIG. 18 in which a first hardmask is deposited over the a-Si portion and the exposed a-Si dummy material is recessed to expose sidewalls of the first hardmask in accordance with an embodiment of the present invention. [Figure 20] FIG. 20 is a cross-sectional view of the semiconductor structure of FIG. 19, where a second hardmask is deposited adjacent to the first hardmask, in accordance with an embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] Throughout the drawings, the same or similar reference numbers represent the same or similar elements.

[0011] Embodiments according to the invention provide methods and devices for forming short gates on active areas and longer gates on shallow trench isolation (STI) regions for nanosheet (NS) multi-threshold integration. Exemplary embodiments of the invention relate to non-uniform gate lengths for single lateral transistors. As a result, exemplary embodiments of the invention present methods and structures for forming non-uniform gate lengths where the gate length (Lg) variation is self-aligned to the active area, thereby providing more room for the gate on the STI region for work function metal (WFM) patterning.

[0012] Examples of semiconductor materials that can be used to form such nanosheet structures include silicon (Si), germanium (Ge), silicon-germanium alloy (SiGe), silicon carbide (SiC), silicon-germanium carbide (SiGeC), III-V compound semiconductors, or II-VI compound semiconductors, or combinations thereof. III-V compound semiconductors are materials that contain at least one element from group III of the periodic table of elements and at least one element from group V of the periodic table of elements. II-VI compound semiconductors are materials that contain at least one element from group II of the periodic table of elements and at least one element from group VI of the periodic table of elements.

[0013] Although the present invention is described with respect to a given exemplary architecture, it is to be understood that other architectures, structures, substrate materials, and process features and steps / blocks may be varied within the scope of the present invention. It is noted that certain features may not be shown in every figure for purposes of clarity. This is not intended to be construed as a limitation of any particular embodiment or of the scope of the illustrations or claims.

[0014] FIG. 1 is a cross-sectional view of a semiconductor structure including a nanosheet stack formed on a substrate according to an embodiment of the present invention.

[0015] In various exemplary embodiments, the semiconductor structure 5 includes shallow trench isolation (STI) regions 12 formed in a substrate 10. In one example, a plurality of field effect transistor (FET) devices may be formed on the substrate 10. The FET devices may be formed by building nanosheet stacks.

[0016] The nanosheet stack 20 of the structure 5 can include alternating layers of a first semiconductor layer 22 and a second semiconductor layer 24. The first semiconductor layer 22 can be, for example, silicon germanium (SiGe) and the second semiconductor layer 24 can be, for example, silicon (Si).

[0017] An oxide 30 may be formed on the nanosheet stack 20. A sacrificial layer 32 may be formed on the oxide 30. A first hard mask 34 may be formed on the sacrificial layer 32.

[0018] The sacrificial layer 32 may be, for example, an amorphous silicon (a-Si) layer.

[0019] The first hardmask 34 may be, for example, a nitride-containing hardmask.

[0020] The structure 5' is a cross-sectional view taken along line Y-Y'. The structure 5' illustrates the nanosheet stack 20 formed on the substrate 10, as well as the oxide 30, the sacrificial layer 32, and the first hard mask 34.

[0021] Structure 5'' is a top view of structure 5. Structure 5'' illustrates the STI regions 12, as well as the first hard mask 34.

[0022] In one or more embodiments, the substrate 10 can be a semiconductor or an insulator with an active surface semiconductor layer. The substrate 10 can be crystalline, semi-crystalline, microcrystalline, or amorphous. The substrate 10 can be essentially (e.g., except for contaminants) a single element (e.g., silicon), predominantly (e.g., with doping) a single element, e.g., silicon (Si) or germanium (Ge), or the substrate 10 can include a compound, e.g., Al2O3, SiO2, GaAs, SiC, or SiGe. The substrate 10 can also have multiple layers of materials, e.g., a semiconductor-on-insulator substrate (SeOI), a silicon-on-insulator substrate (SOI), a germanium-on-insulator substrate (GeOI), or a silicon-germanium-on-insulator substrate (SGOI). The substrate 10 can also have other layers forming the substrate 10, including high-k oxides and / or nitrides. In one or more embodiments, the substrate 10 can be a silicon wafer. In an embodiment, the substrate 10 is a single crystal silicon wafer.

[0023] The shallow trench isolation (STI) region 12 may be formed by etching a trench in a doped lower source / drain (S / D) region (not shown) using a conventional dry etching process such as reactive ion etching (RIE) or plasma etching. The trench may optionally be lined with a conventional lining material, such as silicon nitride or silicon oxynitride, and then chemical vapor deposition (CVD) or another similar deposition process is used to fill the trench with silicon oxide or another such as an STI dielectric material. The STI dielectric may optionally be densified after deposition. A conventional planarization process, such as chemical mechanical polishing (CMP), may optionally be used to provide a planar structure.

[0024] For example, referring to nanosheet stack 20, first semiconductor layer 22 may be the first layer in a stack of sheets of alternating materials. Nanosheet stacks 20 each include a first semiconductor layer 22 and a second semiconductor layer 24. Although it is specifically contemplated that first semiconductor layer 22 may be formed from silicon germanium and second semiconductor layer 24 may be formed from silicon, it should be understood that any suitable material may be used instead, so long as the two semiconductor materials have etch selectivity with respect to one another. As used herein, the term "selectivity" in relation to a material removal process refers to a rate of material removal for a first material being greater than a rate of removal for at least another material of the structure to which the material removal process is applied. Alternating semiconductor layers 22 / 24 may be deposited by any suitable mechanism. It is specifically contemplated that semiconductor layers 22 / 24 may be epitaxially grown from one another, although alternative deposition processes such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or gas cluster ion beam (GCIB) deposition are also contemplated.

[0025] FIG. 2 is a cross-sectional view of the semiconductor structure of FIG. 1 in which an oxide is deposited on the nanosheet stack, according to an embodiment of the present invention.

[0026] In various exemplary embodiments, an oxide 40 is deposited over the nanosheet stack 20 encapsulating the oxide 30 , the sacrificial layer 32 , and the first hardmask 34 .

[0027] FIG. 3 is a cross-sectional view of the semiconductor structure of FIG. 2 in which a dummy gate is deposited over an oxide and planarization is performed in accordance with an embodiment of the present invention.

[0028] In various exemplary embodiments, a dummy gate 42 is deposited on the oxide 40 and planarization is performed. The planarization can be, for example, chemical mechanical polishing (CMP). The planarization results in the exposure of the top surface 35 of the first hard mask 34. The dummy gate 42 is thus formed between the nanosheet stacks 20. The dummy gate 42 can be, for example, a-Si. The dummy gate can also be referred to as a sacrificial gate.

[0029] FIG. 4 is a cross-sectional view of the semiconductor structure of FIG. 3 in which the dummy gate is recessed to expose a first hard mask formed over the nanosheet stack, according to an embodiment of the invention.

[0030] In various exemplary embodiments, the dummy gate 42 is recessed to expose the first hard mask 34 formed on the nanosheet stack 20. The recessing results in that the dummy gate region 42' remains between the nanosheet stack 20. The recessing further results in that the sidewall "SW" of the first hard mask 34 is exposed. The recessing may extend a distance D1 from the top surface 35 of the first hard mask 34 to the top surface of the dummy gate region 42'.

[0031] Any etching technique known in the art may be used for the recessing.

[0032] FIG. 5 is a cross-sectional view of the semiconductor structure of FIG. 4 in which a second hardmask is formed adjacent to the first hardmask, an organic planarization layer (OPL) is deposited over the first and second hardmasks, and the first and second hardmasks are etched to form openings exposing an amorphous silicon (a-Si) layer formed over the nanosheet stack, in accordance with an embodiment of the present invention.

[0033] In various exemplary embodiments, a second hard mask 44 is formed adjacent to the first hard mask 34. The second hard mask 44 is planarized to be approximately flush with the top surface 35 of the first hard mask 34. An OPL layer 46 is then deposited over the first and second hard masks 34, 44. An opening 48 is then created.

[0034] The second hard mask 44 may be, for example, a silicon monoxide (SiO) layer.

[0035] The first and second hard masks 34 , 44 are etched to form an opening 48 that exposes a dummy gate region 42 ′ to be formed above the nanosheet stack 20 .

[0036] In the Y-Y' view, an opening 48 extends through OPL 46 and first hard mask 34 to expose a top surface of dummy gate region 42'.

[0037] In the A-A' view, an opening 48 extends through OPL 46 and second hard mask 44 to expose a top surface of dummy gate region 42'.

[0038] Top view FIG. 7 illustrates the exposure of dummy gate region 42'.

[0039] FIG. 6 is a cross-sectional view of the semiconductor structure of FIG. 5 in which an isotropic etch occurs to selectively etch portions of the first hard mask to define rounded edges for the first hard mask in accordance with an embodiment of the present invention.

[0040] In various exemplary embodiments, an isotropic etch 50 occurs to selectively etch portions of the first hard mask 34 to define rounded edges (top view 52) for the first hard mask 34. The isotropic etch 50 extends a distance D2 below the OPL 46 (viewpoint Y-Y'). As noted in top view 52, ​​the corners of the first hard mask 34 are slightly rounded as a result of the isotropic etch 50. Any etching technique known in the art may be used.

[0041] Therefore, selectively trimming the first hard mask 34 results in a gate length above the nanosheet stacks 20 that is smaller than the gate length above the STI regions 12. This is further illustrated in the top view of FIG. 8 below. As a result, selective trimming results in a non-uniform gate length with a shorter Lg above the active region (nanosheet stacks 20) and a longer Lg above the STI regions 12.

[0042] FIG. 7 is a cross-sectional view of the semiconductor structure of FIG. 6 with the OPL removed in accordance with an embodiment of the present invention.

[0043] In various exemplary embodiments, OPL 46 is removed. OPL 46 may be removed, for example, by ashing.

[0044] Removal of OPL 46 results in exposure of first hardmask 34 and second hardmask 44 .

[0045] The top view illustrates the first hard mask 34, the second hard mask 44, and the dummy gate region 42' with rounded edges.

[0046] FIG. 8 is a cross-sectional view of the semiconductor structure of FIG. 7 in which a first hard mask feature is transferred to an a-Si layer formed on top of the nanosheet stack, according to an embodiment of the invention.

[0047] In various exemplary embodiments, the first hard mask shape is transferred to a dummy gate region 42' formed on top of the nanosheet stack 20. The patterning results in an opening 58.

[0048] In the YY' view, the upper surface 31 of the oxide 30 is exposed.

[0049] In the A-A' view, the top surface of the STI region 12 is exposed. In the A-A' view, the opening 58 extends entirely through the dummy gate region 42'.

[0050] In the top view, the length of the first hard mask is designated as L1 and the length of the second hard mask 44 is designated as L2. In this case, L2>L1. In other words, selectively trimming the first hard mask 34 results in a gate length above the nanosheet stacks 20 that is smaller than the gate length above the STI regions 12. As a result, selective trimming results in a non-uniform gate length with a shorter Lg above the active region (nanosheet stacks 20) and a longer Lg above the STI regions 12.

[0051] FIG. 9 is a cross-sectional view of the semiconductor structure of FIG. 8 upon which a gate spacer is deposited, in accordance with an embodiment of the present invention.

[0052] In various exemplary embodiments, a gate spacer 60 is formed.

[0053] In the Y-Y′ view, a gate spacer 60 is formed adjacent to the first hard mask 34 up to the top surface of the nanosheet stack 20 .

[0054] In the A-A' view, gate spacers 60 are formed adjacent the second hard mask 44 up to the top surface of the STI regions 12. In the STI regions 12, deposition of the gate spacers 60 may result in pinch-off between adjacent dummy gate regions 42'.

[0055] In the top view, the gate spacer 60 is shown in direct contact with both the first and second hard masks 34,44.

[0056] FIG. 10 is a cross-sectional view of the semiconductor structure of FIG. 9 in which source / drain epitaxial regions and inner spacers are formed within the nanosheet stack according to an embodiment of the invention.

[0057] In various exemplary embodiments, the source / drain epitaxial region 64 and the inner spacer 62 are formed in the nanosheet stack 20. The bottom portion of the gate spacer 60 directly contacts the sidewall of the upper portion of the source / drain epitaxial region 64. The source / drain epitaxial region 64 extends above the upper surface of the nanosheet stack 20. The source / drain epitaxial region 64 is coplanar with the upper surface 31 of the oxide 30.

[0058] The inner spacer 62 is vertically aligned with the gate spacer 60 (Y-Y' perspective).

[0059] In a top view, the source / drain epitaxial regions 64 are horizontally aligned with the first hard mask 34 and the source / drain epitaxial regions 64 are not horizontally aligned with or offset from the second hard mask 44. The gate spacers 60 prevent the source / drain epitaxial regions 64 from directly contacting the first and second hard masks 34, 44.

[0060] Etching may include a dry etching process, such as, for example, reactive ion etching, plasma etching, ion etching, or laser ablation. Etching may further include a wet chemical etching process in which one or more chemical etchants are used to remove portions of the blanket layer not protected by the patterned photoresist.

[0061] In some examples, the selective wet etch or selective dry etch may selectively remove portions of the first semiconductor layer 22 (e.g., a SiGe layer) and leave all or part of the second semiconductor layer 24. Such removal creates gaps or openings or recesses in the second semiconductor layer 24 of the FET device.

[0062] Dry and wet etching processes may have etching parameters that may be adjusted, such as the etchant used, etching temperature, etching solution concentration, etching pressure, source power, RF bias voltage, RF bias power, etchant flow rate, and other suitable parameters. Dry etching processes may include polarized plasma etching processes using chlorine-based chemistries. Other dry etching gases may include tetrafluoromethane (CF4), nitrogen trifluoride (NF3), sulfur hexafluoride (SF6), and helium (He), and chlorine trifluoride (ClF3). Dry etching may also be performed anisotropically using mechanisms such as DRIE (deep reactive ion etching). Chemical vapor etching may be used as a selective etching method, and the etching gas may include a gas mixture with hydrogen chloride (HCl), tetrafluoromethane (CF4), and hydrogen (H2). Chemical vapor etching may be performed by CVD at suitable pressures and temperatures.

[0063] FIG. 11 is a cross-sectional view of the semiconductor structure of FIG. 10 after the first and second hard masks have been removed and an interlayer dielectric (ILD) is formed over the source / drain epitaxial regions in accordance with an embodiment of the present invention.

[0064] In various exemplary embodiments, the first and second hard masks 34, 44 are removed and an interlayer dielectric (ILD) 66 is formed over and in direct contact with the source / drain epitaxial regions 64.

[0065] In the top view, a distance L1 is shown between the active areas and a distance L2 is shown between the STI areas, with L2>L1, meaning that the gate length is longer over the STI areas and the gate length is shorter over the active areas (nanosheet stacks 20). Thus, the gate length is not uniform throughout. Rather, the gate length varies across the length of the nanosheet transistor. For example, in the A-A' view, the length is larger or longer between adjacent gate spacers 60, but in the Y-Y' view, the length is shorter or smaller between adjacent gate spacers 60.

[0066] The ILD 66 may be any suitable material, such as, for example, porous silica, carbon-doped oxide, silicon dioxide, silicon nitride, silicon oxynitride, or other dielectric material. Any known manner of forming the ILD 66 may be utilized. The ILD 66 may be formed using, for example, CVD, PECVD, ALD, flowable CVD, spin-on dielectric, or PVD.

[0067] FIG. 12 is a cross-sectional view of the semiconductor structure of FIG. 11 in which the dummy gate regions and every other sacrificial layer of the nanosheet stack are removed in accordance with an embodiment of the present invention.

[0068] In various exemplary embodiments, the dummy gate regions 42′ and every other sacrificial layer 22 of the nanosheet stack 20 are removed. This results in gaps or voids 70 being formed between every other semiconductor layer 24 (e.g., Si layers).

[0069] FIG. 13 is a cross-sectional view of the semiconductor structure of FIG. 12 where work function metal (WFM) deposition occurs in accordance with an embodiment of the present invention.

[0070] In various exemplary embodiments, a work function metal (WFM) deposition occurs. The WFM 72 fills the gap or void 70. The WFM 72 directly contacts the gate spacer 60 such that the WFM 72 encapsulates the gate spacer 60. The WFM 72 directly contacts the inner spacer 62.

[0071] In the Y-Y' view, the WFM 72 pinches off due to the short active gate length.

[0072] In the A-A′ view, the WFM 72 does not cause any pinch-off due to the longer gate length above the STI region 12 .

[0073] In various embodiments, the WFM 72 is a conductive material that can be used to fabricate a semiconductor device that includes a work function metal, such as titanium nitride, titanium carbide, titanium aluminum carbide, tantalum nitride, and tantalum carbide; conductive metals, such as tungsten, aluminum, and copper; and silicon dioxide (SiO2), hafnium oxide (e.g., HfO2), hafnium silicon oxide (e.g., HfSiO4), hafnium silicon oxynitride (Hf w S x O y N z ), lanthanum oxide (e.g., La2O3), lanthanum aluminum oxide (e.g., LaAlO3), zirconium oxide (e.g., ZrO2), zirconium silicon oxide (e.g., ZrSiO4), zirconium silicon oxynitride (Zr w S x O y N z ), tantalum oxide (e.g., TaO2, Ta2O5), titanium oxide (e.g., TiO2), barium-strontium-titanium oxide (e.g., BaTiO3-SrTiO3), barium-titanium oxide (e.g., BaTiO3), strontium-titanium oxide (e.g., SrTiO3), yttrium oxide (e.g., Y2O3), aluminum oxide (e.g., Al2O3), lead-scandium-tantalum oxide (Pb(Sc x Ta 1-x )O3), and lead zinc niobate (e.g., PbZn 1 / 3 Nb 2 / 3 O3), but are not limited to these.

[0074] FIG. 14 is a cross-sectional view of the semiconductor structure of FIG. 13 in which a mask is deposited to pattern the WFM, the WFM is exposed to an isotropic etch, and a WFM seal is formed under the mask, in accordance with an embodiment of the present invention.

[0075] In various exemplary embodiments, a mask 74 is deposited to pattern the WFM 72. As shown, for purposes of illustration, one of the nanosheet stacks (on the right) is covered by the mask 74. The WFM 72 is then exposed to an isotropic etch to remove portions of the WFM 72. As a result, the remaining WFM region 72' is illustrated.

[0076] In the XX' view, the distal and proximal ends of every other semiconductor layer 24 are exposed.

[0077] In the Y-Y' view, the top surface of the gate spacer 60 is exposed, and the top surface of the ILD 66 is exposed.

[0078] In the A-A' view, the gate spacer 60 is shown fully exposed.

[0079] The top view illustrates how mask 74 masks the right-hand nanosheet stack.

[0080] Finally, a WFM seal 76 is formed beneath the mask 74 and adjacent to the WFM region 72'.

[0081] The WFM seal 76 can be formed by a divot-fill method because the WFM does not pinch off in the L2 region.

[0082] FIG. 15 is a cross-sectional view of the semiconductor structure of FIG. 14 in which the remaining WFM is etched away, the mask is removed, and then another WFM is deposited in accordance with an embodiment of the present invention.

[0083] In various exemplary embodiments, the remaining WFM 72' is etched away, then the mask 74 is removed, and then another WFM 78 is deposited.

[0084] In the X-X' view, WFM 78 fills gaps or voids 70 and surrounds every other semiconductor layer 24 (left nanosheet stack). In the X-X' view, WFM 78 is in direct contact with WFM 72 and also in direct contact with WFM seal 76 (right nanosheet stack).

[0085] In the Y-Y' view, WFM 78 is in direct contact with gate spacer 60 and in direct contact with inner spacer 62. WFM 78 is also in direct contact with the top surface of ILD 66.

[0086] In the A-A' view, the WFM 78 directly contacts and also surrounds or covers the gate spacer 60.

[0087] FIG. 16 is a cross-sectional view of a semiconductor structure including a nanosheet stack formed on a substrate where, in contrast to FIG. 1, no a-Si is formed on the nanosheet stack according to an embodiment of the present invention.

[0088] In another exemplary embodiment, the nanosheet stack 20 is formed in the structure 100 and the sacrificial layer 32 of FIG. 1 is omitted. As such, an oxide 110 is formed over and in direct contact with the nanosheet stack 20. A hard mask 112 is then formed over the oxide 110.

[0089] FIG. 17 is a cross-sectional view of the semiconductor structure of FIG. 16 in which an oxide is deposited, a dummy material is deposited over the oxide, planarization is performed, the nanosheet stack hard mask is recessed, and the exposed oxide areas are removed in accordance with an embodiment of the present invention.

[0090] In various exemplary embodiments, oxide 114 is deposited, dummy material 116 is deposited on top of oxide 114, planarization is performed, hard mask 112 of nanosheet stack 20 is recessed, and exposed oxide areas adjacent hard mask 112 are removed. As a result, sidewalls "SW" of dummy material 116 are exposed and oxide 110 is recessed down to oxide portion 110'.

[0091] FIG. 18 is a cross-sectional view of the semiconductor structure of FIG. 17 in which directional fill occurs to deposit an a-Si portion on top of the nanosheet stack, according to an embodiment of the invention.

[0092] In various exemplary embodiments, a directional fill occurs to deposit a-Si portion 120 on top of the nanosheet stack 20. The a-Si portion 120 directly contacts the oxide portion 110'. This is in contrast to the configuration described above with respect to Figures 1-5.

[0093] FIG. 19 is a cross-sectional view of the semiconductor structure of FIG. 18 in which a first hardmask is deposited over the a-Si portion and the exposed a-Si dummy material is recessed to expose sidewalls of the first hardmask in accordance with an embodiment of the invention.

[0094] In various exemplary embodiments, a first hard mask 122 is deposited over and in direct contact with a-Si portion 120, and the exposed a-Si dummy material is recessed to expose the sidewalls of first hard mask 122. The remaining dummy material portion is designated 116'.

[0095] FIG. 20 is a cross-sectional view of the semiconductor structure of FIG. 19 in which a second hardmask is deposited adjacent to the first hardmask in accordance with an embodiment of the present invention.

[0096] In various exemplary embodiments, a second hard mask 124 is deposited adjacent to the first hard mask 122. The remainder of the process is similar to that of Figures 6-15.

[0097] In conclusion, the exemplary embodiments of the present invention present methods and structures for forming a non-uniform gate length (Lg), where a shorter Lg is on the active area and a longer one on the STI area, and the work function may pinch off on the gate in the active area with the smaller Lg, but not in the gate with the longer Lg above the STI area. Thus, the exemplary embodiments of the present invention relate to a non-uniform gate length for a single lateral transistor. As a result, the exemplary embodiments of the present invention present methods and structures for forming a non-uniform gate length where the Lg variation is self-aligned to the active area, thereby providing more room for the gate above the STI area for WFM patterning.

[0098] In one exemplary embodiment, the nanosheet device includes a non-uniform gate length, i.e., shorter Lg over the active region and longer Lg over the STI region, where the Lg variation is substantially matched to the active region, and the work function may pinch off over the gate in the active region with smaller Lg, but not in the gate with larger Lg over the STI region. A method of forming the nanosheet device includes forming at least a first hardmask material over the nanosheet, forming a first dummy gate, recessing the first dummy gate such that a top surface of the first dummy gate is below a top surface of the first hardmask material, forming a second hardmask material in the recess, defining a uniform Lg in both the first and second hardmasks, and selectively trimming the first hardmask such that Lg is smaller over the nanosheet.

[0099] 1-20, deposition is any process by which material is grown, coated, or otherwise transferred onto a wafer. Available techniques include, but are not limited to, thermal oxidation, physical vapor deposition (PVD), chemical vapor deposition (CVD), electrochemical deposition (ECD), molecular beam epitaxy (MBE), and more recently, atomic layer deposition (ALD), among others. As used herein, "depositing" may include any now known or later developed technique appropriate to the material to be deposited, including, for example, but not limited to, chemical vapor deposition (CVD), low pressure CVD (LPCVD), plasma enhanced CVD (PECVD), semi-atmospheric CVD (SACVD) and high density plasma CVD (HDPCVD), rapid thermal CVD (RTCVD), ultra-high vacuum CVD (UHVCVD), limited reaction processing CVD (LRPCVD), metal organic CVD (MOCVD), sputtering deposition, ion beam deposition, electron beam deposition, laser assisted deposition, thermal oxidation, thermal nitridation, spin-on techniques, physical vapor deposition (PVD), atomic layer deposition (ALD), chemical oxidation, molecular beam epitaxy (MBE), plating, and evaporation.

[0100] The term "processing" as used herein includes deposition of material or photoresist, patterning, exposing, developing, etching, cleaning, stripping, embedding, doping, stressing, layering, or removal of material or photoresist, or combinations thereof, as required to form the described structures.

[0101] Although the invention is described with respect to given example architectures, it should be understood that other architectures, structures, substrate materials, and process features and steps / blocks may be varied within the scope of the invention.

[0102] When an element, such as a layer, region, or substrate, is referred to as being "on" or "over" another element, it should be understood that it may be directly on the other element, or intervening elements may also be present. In contrast, when an element is referred to as being "directly on" or "directly over" another element, there are no intervening elements present. When an element is referred to as being "connected" or "coupled" to another element, it should be understood that it may be directly connected or coupled to the other element, or intervening elements may be present. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements present.

[0103] This embodiment may include a design for an integrated circuit chip, which may be created in a graphic computer programming language and stored on a computer storage medium (such as a disk, tape, physical hard drive, or virtual hard drive, such as in a storage access network). If the designer does not manufacture the chip or the photolithography mask used to manufacture the chip, the designer may directly or indirectly communicate the resulting design to such an entity, either by physical mechanism (e.g., by providing a copy of the storage medium storing the design) or electronically (e.g., over the Internet). The stored design is then typically converted into a suitable format (e.g., GDSII) for the manufacture of a photolithography mask that contains multiple copies of the chip design to be formed on a wafer. The photolithography mask is utilized to define areas of the wafer (or layers thereon, or a combination thereof) to be etched or otherwise processed.

[0104] The methods described herein may be used in the manufacture of integrated circuit chips. The resulting integrated circuit chips may be distributed by manufacturers in raw wafer form (i.e., a single wafer having multiple unpackaged chips), as bare die, or in packaged form. In the latter case, the chips are mounted in single-chip packages (such as plastic carriers, with leads attached to a motherboard or other higher level carrier) or multi-chip packages (such as ceramic carriers with either surface or buried wiring, or both). In either case, the chips are then integrated with other chips, discrete circuit elements, or other signal processing devices, or a combination thereof, as part of either (a) an intermediate product, such as a motherboard, or (b) a final product. The final product may be any product that includes the integrated circuit chip, ranging from toys and other low-end applications to advanced computer products with displays, keyboards, or other input devices, and a central processor.

[0105] It should also be understood that material compounds are described in terms of the listed elements, e.g., SiGe. These compounds may contain different percentages of the elements within the compound, e.g., SiGe is SiGe where x is 1 or less. x Ge 1-x etc. Additionally, other elements may be included in the compound and still function in accordance with the present embodiment. Compounds with additional elements are referred to herein as alloys.

[0106] Reference herein to "one embodiment" or "an embodiment" of the invention, as well as other variations thereof, means that the particular feature, structure, characteristic, etc. described in association with that embodiment is included in at least one embodiment of the invention. Thus, the appearances of the phrases "in one embodiment" or "in an embodiment" in various places throughout this specification, as well as any other variations thereof, do not necessarily all refer to the same embodiment.

[0107] It should be understood that the use of any of the following terms " / ", "or ... or combinations thereof", and "at least one of" is intended to encompass the selection of only the first enumerated alternative (A), the selection of only the second enumerated alternative (B), or the selection of both alternatives (A and B), for example, in the case of "A / B", "A or B or combinations thereof", and "at least one of A and B". As a further example, in the case of "A, B, or C or combinations thereof" and "at least one of A, B, and C", such language is intended to encompass the selection of only the first enumerated alternative (A), or the selection of only the second enumerated alternative (B), or the selection of only the third enumerated alternative (C), or the selection of only the first and second enumerated alternatives (A and B), or the selection of only the first and third enumerated alternatives (A and C), or the selection of only the second and third enumerated alternatives (B and C), or the selection of all three alternatives (A and B and C). This can be expanded as many times as there are items listed, as would be readily apparent to one of ordinary skill in the art.

[0108] The terms used herein are for the purpose of describing particular embodiments only and are not intended to be limitations of example embodiments. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms unless the context clearly indicates otherwise. It is further understood that the terms "comprise", "comprising", "including" or "comprising" or combinations thereof, as used herein, describe the presence of stated features, integers, steps, operations, elements or components or combinations thereof, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components or groups or combinations thereof.

[0109] Spatial terms such as "beneath," "below," "lower," "upper," "above," and the like may be used herein for ease of description to describe the relationship of one element or feature to another element or feature as illustrated in the figures. It should be understood that the spatial terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device is flipped over in the figures, an element described as "below" or "beneath" the other element or feature would be oriented "above" the other element or feature. Thus, the term "below" may encompass both an above and below orientation. The device may be otherwise oriented (rotated 90 degrees or to other orientations) and the spatial descriptions used herein may be interpreted accordingly. In addition, it should also be understood that when a layer is referred to as being "between" two layers, it may be the only layer between the two layers, or there may also be one or more intervening layers.

[0110] Terms such as first, second, etc. may be used herein to describe various elements, but it should be understood that these elements should not be limited by these terms. These terms are only used to distinguish one element from another. Thus, a first element discussed below may be named a second element without departing from the scope of the present concept.

[0111] Having described preferred embodiments of the method for forming short gates on active regions and longer gates on shallow trench isolation (STI) regions for nanosheet (NS) multi-threshold integration (intended to be illustrative and not limiting), it is noted that modifications and variations may be made by those skilled in the art in light of the above teachings. It is therefore to be understood that changes may be made in the particular embodiments described that are within the scope of the invention as outlined by the appended claims. Having thus described aspects of the invention with particularity and as specifically required by the patent laws, what is claimed and what is desired to be protected by letters patent is set forth in the appended claims.

[0112] In a preferred embodiment of the present invention as described hereinbefore, there is provided a method for forming a nanosheet device, the method comprising forming a nanosheet stack on a substrate, the nanosheet stack being separated by a shallow trench isolation (STI) region; forming a first hardmask material on the nanosheet stack; depositing a first sacrificial material; removing the first hardmask material such that a first recess is defined on the nanosheet stack; and removing the first hardmask material from the nanosheet stack. The method includes depositing a second sacrificial material in a first recess defined on the nanosheet stack, forming a second hardmask material on the second sacrificial material, recessing the first sacrificial material such that a second recess is defined adjacent to the second hardmask material, forming a third hardmask material in the second recess, defining a uniform gate length in both the second and third hardmask materials, and selectively trimming the second hardmask material such that the gate length above the nanosheet stack is less than the gate length above the STI region. The method may further include forming a gate spacer on the nanosheet stack. The method may further include forming a source / drain epitaxial region and an inner spacer in the nanosheet stack. The inner spacer may be vertically aligned with the gate spacer. The source / drain epitaxial region may directly contact a lower inner wall of the gate spacer.

Claims

1. 1. A method for forming a nanosheet device, comprising: forming a nanosheet stack on a substrate, the nanosheet stack being separated by a shallow trench isolation (STI) region; forming a first hardmask material over the nanosheet stack; depositing a sacrificial gate; recessing the sacrificial gate such that a recess is defined adjacent the first hard mask material, wherein a top surface of the sacrificial gate is below a top surface of the first hard mask material; forming a second hard mask material in the recess; Defining a uniform gate length in both the first and second hard mask materials; selectively trimming the first hardmask material such that a gate length over the nanosheet stack is smaller than a gate length over the STI region.

2. 2. The method of claim 1, further comprising etching the sacrificial gate to define an opening exposing a top surface of the STI region.

3. 3. The method of claim 2, further comprising forming a gate spacer in the opening defined over the nanosheet stack and over the STI region.

4. The method of claim 3 , further comprising forming source / drain epitaxial regions and inner spacers in the nanosheet stack.

5. The method of claim 4 , wherein the inner spacer is vertically aligned with the gate spacer.

6. 5. The method of claim 4, wherein the source / drain epitaxial regions directly contact a lower inner sidewall of the gate spacer.

7. 5. The method of claim 4, further comprising depositing an interlayer dielectric (ILD) over and in direct contact with said source / drain epitaxial regions.

8. 8. The method of claim 7, further comprising removing the sacrificial gate and every other semiconductor layer of the nanosheet stack.

9. 10. The method of claim 8, further comprising depositing a first work function metal (WFM) in direct contact with the STI regions and in direct contact with the gate spacer.

10. 10. The method of claim 9, wherein the first WFM pinches off in a region defined by the gate length above the nanosheet stack, and the first WFM cannot pinch off in a region defined by the gate length above the STI region.

11. The method of claim 10 , further comprising forming a mask on one of the nanosheet stacks for etching the first WFM.

12. The method of claim 11 , further comprising forming a WFM seal under the mask.

13. The method of claim 12 further comprising removing any remaining first WFM and removing the mask to deposit a second WFM.

14. A nanosheet transistor, comprising: a nanosheet stack disposed over a substrate, the nanosheet stack separated by shallow trench isolation (STI) regions to define a non-uniform gate length across the nanosheet transistor, such that the gate length above the nanosheet stack is smaller than the gate length above the STI regions; a work function metal (WFM) disposed on the nanosheet stack and the STI region, the WFM pinching off within a region defined by the gate length above the nanosheet stack, and the WFM cannot pinch off within a region defined by the gate length above the STI region.

15. The nanosheet transistor of claim 14 , wherein a gate spacer is disposed on the nanosheet stack.

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