Semiconductor memory device

Abstract

To provide a semiconductor memory device capable of high integration.SOLUTION: A semiconductor memory device includes: a plurality of memory layers (ML) arranged in a first direction (Z); first via-wiring (104) extending in the first direction; second via-wiring (104) in a position different from a position of the first via-wiring in a second direction (X) and extending in the first direction. Each of the plurality of memory layers includes: first wiring (120) disposed between the first via-wiring and the second via-wiring and extending in a third direction; a first semiconductor layer electrically connected to the first via-wiring; a first gate electrode opposed to the first semiconductor layer and electrically connected to the first wiring; a first memory portion (130) electrically connected to the first semiconductor layer; a second semiconductor layer electrically connected to the second via-wiring; a second gate electrode opposed to the second semiconductor layer and electrically connected to the first wiring; and a second memory portion (130) electrically connected to the second semiconductor layer.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] The present embodiment relates to a semiconductor memory device. [Background technology]

[0002] 2. Description of the Related Art With the increasing integration density of semiconductor memory devices, studies on three-dimensional semiconductor memory devices are underway. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] US Patent Application Publication No. 2022 / 0399340 [Patent Document 2] US Patent Application Publication No. 2022 / 0399340 [Patent Document 3] US Patent Application Publication No. 2022 / 0352169 [Patent Document 4] Patent No. 10707210 Specification [Patent Document 5] JP 2022-147872 A Summary of the Invention [Problem to be solved by the invention]

[0004] A semiconductor memory device capable of being highly integrated is provided. [Means for solving the problem]

[0005] A semiconductor memory device according to one embodiment includes a substrate, a plurality of memory layers arranged in a first direction intersecting a surface of the substrate, a first via wiring extending in the first direction, and a second via wiring that is at a different position in a second direction intersecting the first direction from the first via wiring and extends in the first direction. Each of the plurality of memory layers includes a first wiring provided between the first via wiring and the second via wiring and extending in a third direction intersecting the first and second directions. Each of the plurality of memory layers includes a first semiconductor layer electrically connected to the first via wiring, a first gate electrode facing the first semiconductor layer and electrically connected to the first wiring, and a first memory unit provided on the opposite side of the first wiring in the second direction with respect to the first semiconductor layer and electrically connected to the first semiconductor layer. In addition, each of the multiple memory layers includes a second semiconductor layer electrically connected to the second via wiring, a second gate electrode facing the second semiconductor layer and electrically connected to the first wiring, and a second memory unit provided on the opposite side of the second semiconductor layer to the first wiring in the second direction and electrically connected to the second semiconductor layer. [Brief description of the drawings]

[0006] [Figure 1] 1 is a schematic circuit diagram showing a configuration of a portion of a semiconductor memory device according to a first embodiment. [Diagram 2] FIG. 2 is a schematic perspective view showing a configuration of a portion of the semiconductor memory device. [Diagram 3] FIG. 2 is a schematic perspective view showing a configuration of a portion of the semiconductor memory device. [Figure 4] FIG. 2 is a schematic perspective view showing a configuration of a portion of the semiconductor memory device. [Diagram 5] 2 is a schematic XY cross-sectional view showing a configuration of a portion of the semiconductor memory device. FIG. [Figure 6] FIG. 2 is a schematic plan view showing a configuration of a portion of the semiconductor memory device. [Figure 7] 2 is a schematic XY cross-sectional view showing a configuration of a portion of the semiconductor memory device. FIG. [Figure 8] FIG. 2 is a schematic cross-sectional view showing a configuration of a portion of the semiconductor memory device. [Figure 9]5A to 5C are schematic cross-sectional views for explaining a manufacturing method of the semiconductor memory device. [Figure 10] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Figure 11] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Figure 12] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Figure 13] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Figure 14] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Figure 15] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Figure 16] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Figure 17] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Figure 18] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Figure 19] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Figure 20] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Figure 21] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Figure 22] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Figure 23] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Figure 24] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Diagram 25] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Figure 26] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Figure 27] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Figure 28] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Figure 29] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Diagram 30] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Diagram 31] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Diagram 32] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Diagram 33] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Diagram 34] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Diagram 35] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Diagram 36] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Figure 37] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Figure 38] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Figure 39] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Diagram 40] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Diagram 41] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Diagram 42] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Diagram 43] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Diagram 44] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Diagram 45] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Figure 46] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Figure 47] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Figure 48] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Figure 49] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Figure 50] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Figure 51] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Figure 52] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Figure 53] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Figure 54] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Figure 55] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Figure 56] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Figure 57] 5A to 5C are schematic cross-sectional views for explaining the same manufacturing method. [Figure 58] 3 is a schematic XY cross-sectional view for explaining the effect of the semiconductor memory device according to the first embodiment. FIG. [Figure 59] 3 is a schematic XY cross-sectional view for explaining the effect of the semiconductor memory device according to the first embodiment. FIG. [Figure 60] 10 is a schematic XY cross-sectional view showing a configuration of a portion of a semiconductor memory device according to a second embodiment. FIG. [Figure 61] 11 is a schematic XY cross-sectional view showing a configuration of a portion of a semiconductor memory device according to a third embodiment. FIG. [Figure 62] 11 is a schematic XY cross-sectional view showing a configuration of a portion of a semiconductor memory device according to a fourth embodiment. FIG. [Figure 63] FIG. 13 is a schematic plan view showing a configuration of a portion of a semiconductor memory device according to a fifth embodiment. [Figure 64]13 is a schematic XY cross-sectional view showing a configuration of a portion of a semiconductor memory device according to a sixth embodiment. FIG. [Figure 65] FIG. 2 is a schematic plan view showing a configuration of a portion of the semiconductor memory device. [Figure 66] 13 is a schematic XY cross-sectional view showing a configuration of a portion of a semiconductor memory device according to a seventh embodiment. FIG. [Figure 67] 13 is a schematic XY cross-sectional view showing a configuration of a portion of a semiconductor memory device according to an eighth embodiment. FIG. [Figure 68] FIG. 2 is a schematic plan view showing a configuration of a portion of the semiconductor memory device. [Figure 69] FIG. 13 is a schematic plan view showing a configuration of a portion of a semiconductor memory device according to a ninth embodiment. [Figure 70] 23 is a schematic XY cross-sectional view showing a configuration of a portion of a semiconductor memory device according to a tenth embodiment. FIG. [Figure 71] FIG. 2 is a schematic plan view showing a configuration of a portion of the semiconductor memory device. [Figure 72] FIG. 23 is a schematic circuit diagram showing a configuration of a portion of a semiconductor memory device according to an eleventh embodiment. [Figure 73] FIG. 2 is a schematic perspective view showing a configuration of a portion of the semiconductor memory device. [Figure 74] FIG. 2 is a schematic plan view showing a configuration of a portion of the semiconductor memory device. [Figure 75] FIG. 23 is a schematic plan view showing a configuration of a portion of a semiconductor memory device according to a twelfth embodiment. [Figure 76] FIG. 23 is a schematic plan view showing a configuration of a portion of a semiconductor memory device according to a thirteenth embodiment. [Figure 77] FIG. 23 is a schematic plan view showing a configuration of a portion of a semiconductor memory device according to a fourteenth embodiment. [Figure 78] FIG. 23 is a schematic plan view showing a configuration of a portion of a semiconductor memory device according to a fifteenth embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0007] Next, a semiconductor memory device according to an embodiment will be described in detail with reference to the drawings. Note that the following embodiment is merely an example, and is not intended to limit the present invention. Also, the following drawings are schematic, and for the sake of explanation, some configurations may be omitted. Also, parts common to multiple embodiments may be given the same reference numerals, and explanations may be omitted.

[0008] In addition, in this specification, the term "semiconductor memory device" may refer to a memory die, or may refer to a memory system including a controller die, such as a memory chip, a memory card, or an SSD (Solid State Drive). Furthermore, it may refer to a configuration including a host computer, such as a smartphone, a tablet terminal, or a personal computer.

[0009] In addition, in this specification, when it is said that a first configuration is "electrically connected" to a second configuration, the first configuration may be directly connected to the second configuration, or the first configuration may be connected to the second configuration via wiring, a semiconductor member, a transistor, etc. For example, when three transistors are connected in series, the first transistor is "electrically connected" to the third transistor even if the second transistor is in an OFF state.

[0010] Furthermore, in this specification, when it is said that a first configuration is "electrically connected between" a second configuration and a third configuration, it may mean that the first configuration, the second configuration, and the third configuration are connected in series, and that the second configuration is electrically connected to the third configuration via the first configuration.

[0011] In addition, in this specification, when it is said that a circuit or the like "conducts" two wirings or the like, it may mean, for example, that the circuit or the like includes a transistor or the like, that the transistor or the like is provided in a current path between the two wirings, and that the transistor or the like is in an ON state.

[0012] In this specification, a predetermined direction parallel to the upper surface of the substrate is called the X direction, a direction parallel to the upper surface of the substrate and perpendicular to the X direction is called the Y direction, and a direction perpendicular to the upper surface of the substrate is called the Z direction.

[0013] In this specification, a direction along a predetermined plane may be referred to as a first direction, a direction along this predetermined plane that intersects with the first direction may be referred to as a second direction, and a direction that intersects with this predetermined plane may be referred to as a third direction. These first, second, and third directions may or may not correspond to any of the X, Y, and Z directions.

[0014] In this specification, expressions such as "upper" and "lower" are based on the substrate. For example, the direction away from the substrate along the Z direction is called "up," and the direction toward the substrate along the Z direction is called "down." Furthermore, when referring to a certain configuration, the lower surface or lower end refers to the surface or end of the configuration facing the substrate, and when referring to the upper surface or upper end, refers to the surface or end of the configuration facing away from the substrate. Furthermore, surfaces that intersect with the X or Y direction are called side surfaces, etc.

[0015] Furthermore, in this specification, when we say the "center position" of a certain feature, it may mean, for example, the position of the center of the circumscribing circle of this feature, or it may mean the center of gravity of an image of this feature on a specified plane.

[0016] [First embodiment] [Circuit configuration] Fig. 1 is a schematic circuit diagram showing a configuration of a portion of a semiconductor memory device according to the first embodiment. As shown in Fig. 1, the semiconductor memory device according to this embodiment includes a memory cell array MCA. The memory cell array MCA includes a plurality of memory layers ML0 to ML3, a plurality of bit lines BL connected to the plurality of memory layers ML0 to ML3, a plurality of global bit lines GBL electrically connected to the plurality of bit lines BL, and a plate line PL connected to the plurality of memory layers ML0 to ML3.

[0017] Each of the memory layers ML0 to ML3 includes a plurality of word lines WL0 to WL2 (hereinafter sometimes referred to as "word lines WL") and a plurality of memory cells MC connected to the plurality of word lines WL0 to WL2. Each of the memory cells MC includes a transistor TrC and a capacitor CpC. A source electrode of the transistor TrC is connected to a bit line BL. A drain electrode of the transistor TrC is connected to the capacitor CpC. A gate electrode of the transistor TrC is connected to one of the word lines WL0 to WL2. One electrode of the capacitor CpC is connected to the drain electrode of the transistor TrC. The other electrode of the capacitor CpC is connected to a plate line PL.

[0018] Each bit line BL is connected to a plurality of memory cells MC corresponding to the plurality of memory layers ML0 to ML3, and each bit line BL is connected to a global bit line GBL.

[0019] Moreover, the memory layers ML0 to ML3 each include a plurality of transistors TrL0a, TrL0b, TrL1a, TrL1b, TrL2a, TrL2b, TrL3a, and TrL3b (hereinafter, sometimes referred to as "transistors TrL") provided corresponding to a plurality of word lines WL0 to WL2. The drain electrodes of the transistors TrL are connected to one of the word lines WL0 to WL2. The source electrodes of the transistors TrL are connected to word line selection lines LW0a, LW0b, LW1a, LW1b, LW2a, and LW2b (hereinafter, sometimes referred to as "word line selection lines LW"). The gate electrodes of the transistors TrL are connected to layer selection lines LL0a, LL0b, LL1a, LL1b, LL2a, LL2b, LL3a, and LL3b (hereinafter, sometimes referred to as "layer selection lines LL").

[0020] The word line selection line LW is connected to a plurality of transistors TrL corresponding to a plurality of memory layers ML0 to ML3. The layer selection lines LL0a, LL1a, LL2a, and LL3a are connected in common to all the transistors TrL0a, TrL1a, TrL2a, and TrL3a corresponding to the memory layers ML0 to ML3, respectively. Similarly, the layer selection lines LL0b, LL1b, LL2b, and LL3b are connected in common to all the transistors TrL0b, TrL1b, TrL2b, and TrL3b corresponding to the memory layers ML0 to ML3, respectively.

[0021] [structure] 2 and 3 are schematic perspective views showing a partial configuration of the semiconductor memory device according to the first embodiment. FIG. 3 shows a partial configuration omitted in FIG. 2. FIG. 4 is a schematic perspective view showing a partial configuration of the semiconductor memory device, and shows an enlarged portion of FIG. 2. FIG. 5 is a schematic XY cross-sectional view showing a partial configuration of the semiconductor memory device. FIG. 6 is a schematic plan view showing a partial configuration of the semiconductor memory device. FIG. 7 is a schematic XY cross-sectional view showing a partial configuration of the semiconductor memory device, and shows an enlarged portion of FIG. 5. FIG. 8 is a schematic cross-sectional view showing a partial configuration of the semiconductor memory device, showing a configuration in which the structure shown in FIG. 7 is cut along line AA' and viewed along the direction of the arrow.

[0022] 2 and 3 show a part of a semiconductor substrate Sub and a memory cell array MCA provided above the semiconductor substrate Sub.

[0023] The semiconductor substrate Sub is, for example, a semiconductor substrate such as silicon (Si) containing a P-type impurity such as boron (B). An insulating layer and an electrode layer (not shown) are provided on the upper surface of the semiconductor substrate Sub. The upper surface of the semiconductor substrate Sub and the insulating layer and electrode layer (not shown) constitute a control circuit for controlling the semiconductor memory device according to the first embodiment. For example, a sense amplifier circuit is provided in a region directly below the memory cell array MCA. The sense amplifier circuit is electrically connected to the bit line BL. In a read operation, the sense amplifier circuit is capable of reading data stored in the selected memory cell MC by detecting a change in voltage or a current of the bit line BL.

[0024] The memory cell array MCA includes a plurality of memory layers ML arranged in the Z direction. In addition, insulating layers 103 such as silicon oxide (SiO2) are provided between the plurality of memory layers ML.

[0025] The memory cell array MCA also includes a plurality of structures extending in the Z direction penetrating the plurality of memory layers ML, and wiring layers M0 and M1 (FIG. 3) provided above the plurality of memory layers ML.

[0026] Hereinafter, the multiple configurations extending in the Z direction penetrating the multiple memory layers ML, the multiple memory layers ML, and the wiring layers M0 and M1 will be described in order.

[0027] [Multiple structures extending in the Z direction through multiple memory layers ML] The memory cell array MCA is provided with a plurality of conductive members 102 aligned in the X direction. These conductive members 102 each extend in the Y direction and the Z direction, and divide the memory layer ML in the X direction.

[0028] The conductive member 102 includes, for example, a laminated structure of titanium nitride (TiN) and tungsten (W), etc. The conductive member 102 functions as, for example, a plate line PL (FIG. 1).

[0029] Furthermore, in the memory cell array MCA, a region between the conductive member 102 and a conductive layer 120 (described later) is provided with a plurality of via wirings 104 aligned in the Y direction. Each of the plurality of via wirings 104 extends in the Z direction, penetrating a plurality of memory layers ML.

[0030] 4, the via wiring 104 includes, for example, a conductive oxide film 104a including a conductive oxide, a barrier conductive film 104b such as titanium nitride (TiN), and a conductive member 104c such as tungsten (W). The via wiring 104 may include ruthenium (Ru), iridium (Ir), or other metals instead of the conductive oxide film 104a. The via wiring 104 may also include only a conductive oxide, or may include only ruthenium (Ru), iridium (Ir), or other metals.

[0031] As used herein, "conductive oxide" includes, for example, indium tin oxide (ITO), indium zinc oxide (IZO), ruthenium oxide (RuO2), iridium oxide (IrO2), or other conductive materials that contain oxygen.

[0032] The conductive member 104c has a substantially cylindrical shape extending in the Z direction. The barrier conductive film 104b has a substantially cylindrical shape extending in the Z direction along the outer circumferential surface of the conductive member 104c. The conductive oxide film 104a has a substantially cylindrical shape extending in the Z direction along the outer circumferential surface of the barrier conductive film 104b. The via wiring 104 functions as, for example, a bit line BL (FIG. 1).

[0033] 5, in the first embodiment, a plurality of via wirings 104 are arranged between two conductive members 102 adjacent to each other in the X direction to form two rows having different positions in the X direction. When focusing on these via wirings 104, the Y direction positions of the plurality of via wirings 104 included in the row provided on one side in the X direction with respect to a conductive layer 120 described later approximately coincide with the Y direction positions of any of the plurality of via wirings 104 included in the row provided on the other side in the X direction with respect to the conductive layer 120.

[0034] In the first embodiment, the via wirings 104 are arranged between two conductive layers 120 adjacent to each other in the X direction to form two rows having different positions in the X direction. When focusing on the via wirings 104, the Y direction positions of the via wirings 104 included in the row provided on one side in the X direction with respect to the conductive member 102 are approximately equal to the Y direction positions of the via wirings 104 included in the row provided on the other side in the X direction with respect to the conductive member 102.

[0035] In addition, in a region of the memory cell array MCA corresponding to a conductive layer 120 described later, a plurality of insulating members 105 are provided aligned in the Y direction along the conductive layer 120. Each of the insulating members 105 extends in the Z direction penetrating the memory layers ML. The insulating members 105 include, for example, silicon oxide (SiO2) or the like. In the illustrated example, the central positions of the insulating members 105 in the X direction are approximately aligned with the central position of the conductive layer 120 in the X direction. In the illustrated example, the positions of the insulating members 105 in the Y direction correspond to any of a plurality of insulating members 115 described later.

[0036] [Memory layer ML structure] As shown in FIG. 5, the memory layer ML includes a conductive layer 120 provided between two conductive members 102 adjacent to each other in the X direction and extending in the Y direction, a plurality of transistor structures 110 provided between the conductive members 102 and the conductive layer 120 and aligned in the Y direction corresponding to the plurality of via wirings 104, and a plurality of capacitor structures 130 provided between the conductive members 102 and the plurality of transistor structures 110 and aligned in the Y direction corresponding to the plurality of via wirings 104.

[0037] As shown in FIG. 4, for example, the transistor structure 110 includes a semiconductor layer 111 connected to the outer peripheral surface of the via wiring 104 and extending in the X direction, an insulating layer 112 provided on an upper surface, a lower surface, both side surfaces in the Y direction, and one side surface in the X direction (the conductive layer 120 side) of the semiconductor layer 111, and a conductive layer 113 provided on an upper surface, a lower surface, both side surfaces in the Y direction, and one side surface in the X direction (the conductive layer 120 side) of the insulating layer 112.

[0038] 7, both side surfaces in the X direction of the semiconductor layer 111 may be formed along a circle centered on the central position of the via wiring 104. Similarly, the side surfaces on one side (conductive layer 120 side) of the insulating layer 112 and the conductive layer 113 in the X direction may be formed along a circle centered on the central position of the via wiring 104. Both side surfaces in the Y direction of the semiconductor layer 111, the insulating layer 112, and the conductive layer 113 may be formed linearly along the side surfaces of the insulating member 115.

[0039] Note that both side surfaces of the semiconductor layer 111 in the X direction do not have to be formed along a circle. Even in such a case, for example, both side surfaces of the semiconductor layer 111 in the X direction may be curved when viewed from the Z direction. For example, the length of the semiconductor layer 111 in the X direction may differ depending on the position in the Y direction. For example, the length of the semiconductor layer 111 in the X direction at a position close to the insulating member 115 may be shorter than the length of the semiconductor layer 111 in the X direction at a position far from the insulating member 115.

[0040] The semiconductor layer 111 functions as, for example, a channel region of the transistor TrC (FIG. 1). The semiconductor layer 111 may be, for example, a semiconductor containing at least one element of gallium (Ga) and aluminum (Al), indium (In), zinc (Zn), and oxygen (O), or may be another oxide semiconductor. The multiple semiconductor layers 111 aligned in the Z direction are commonly connected to a via wiring 104 extending in the Z direction.

[0041] The insulating layer 112 functions as, for example, a gate insulating film of the transistor TrC (FIG. 1). The insulating layer 112 includes, for example, silicon oxide (SiO2).

[0042] The conductive layer 113 functions as, for example, a gate electrode of the transistor TrC (FIG. 1). The conductive layer 113 includes, for example, a conductive oxide such as titanium nitride (TiN) or indium tin oxide (ITO). As shown in FIG. 5, the multiple conductive layers 113 aligned in the Y direction are commonly connected to a conductive layer 120 extending in the Y direction. As shown in FIG. 7 and FIG. 8, the conductive layer 113 faces the upper surface, the lower surface, both side surfaces in the Y direction, and one side surface in the X direction (the conductive layer 120 side) of the semiconductor layer 111 via the insulating layer 112.

[0043] 5, an insulating member 115 such as silicon oxide (SiO2) is provided between two semiconductor layers 111 adjacent to each other in the Y direction. The insulating member 115 extends in the Z direction, penetrating the multiple memory layers ML.

[0044] The conductive layer 120 functions as, for example, a word line WL (FIG. 1). As described above, the conductive layer 120 extends in the Y direction. Both side surfaces in the X direction of the conductive layer 120 are connected to a plurality of conductive layers 113 arranged in the Y direction. As shown in FIGS. 7 and 8, the conductive layer 120 includes, for example, a barrier conductive film 121 made of titanium nitride (TiN) or the like, and a conductive film 122 made of tungsten (W).

[0045] 5, the conductive layer 120 includes a plurality of through holes 123 aligned in the Y direction along the above-mentioned plurality of insulating members 105. The inner circumferential surfaces of the plurality of through holes 123 surround the insulating member 105 and are connected to the outer circumferential surface of the insulating member 105.

[0046] 7 and 8, the capacitor structure 130 includes a conductive layer 131, a conductive layer 132 provided on an upper surface, a lower surface, both side surfaces in the Y direction, and one side surface in the X direction (the transistor structure 110 side) of the conductive layer 131, an insulating layer 133 provided on an upper surface, a lower surface, both side surfaces in the Y direction, and one side surface in the X direction (the transistor structure 110 side) of the conductive layer 132, a conductive layer 134 provided on an upper surface, a lower surface, both side surfaces in the Y direction, and one side surface in the X direction (the transistor structure 110 side) of the insulating layer 133, an insulating layer 135 provided on an upper surface, a lower surface, and both side surfaces in the Y direction of the conductive layer 134, a conductive layer 136 provided on an upper surface, a lower surface, and both side surfaces in the Y direction of the insulating layer 135, and a conductive layer 137 provided on an upper surface, a lower surface, and both side surfaces in the Y direction of the conductive layer 136.

[0047] The conductive layers 131, 132, 136, and 137 function as one electrode of the capacitor CpC (FIG. 1). The conductive layers 131 and 137 include, for example, tungsten (W) or the like. The conductive layers 132 and 136 include, for example, titanium nitride (TiN) or the like. The conductive layers 131, 132, 136, and 137 are connected to the conductive member 102.

[0048] The insulating layers 133 and 135 function as insulating layers of the capacitor CpC (FIG. 1). The insulating layers 133 and 135 may be, for example, zirconia (ZrO2), alumina (Al2O3), or other insulating metal oxides. The insulating layers 133 and 135 may also be, for example, a laminated film of multiple insulating metal oxides (for example, a laminated film of zirconia and alumina).

[0049] The conductive layer 134 functions as, for example, the other electrode of the capacitor CpC (FIG. 1). The conductive layer 134 includes, for example, a conductive oxide such as indium tin oxide (ITO). The conductive layer 134 is insulated from the conductive layers 131, 132, 136, and 137 via the insulating layers 133 and 135. The conductive layer 134 is connected to a side surface of the semiconductor layer 111 in the X direction.

[0050] [Structure of wiring layers M0 and M1] As shown in FIG. 3, the memory cell array MCA is provided with a wiring layer M0 provided above a plurality of memory layers ML, and a wiring layer M1 provided above the wiring layer M0.

[0051] The wiring layer M1 includes a plurality of wirings m1. The plurality of wirings m1 may include, for example, a laminated film of a barrier conductive film such as titanium nitride (TiN) and a metal film such as tungsten (W) or copper (Cu). At least a part of the plurality of wirings m1 functions as a global bit line GBL (FIG. 1). The global bit line GBL is aligned in the Y direction and extends in the X direction.

[0052] The wiring layer M0 includes a plurality of wirings m0. The plurality of wirings m0 may include, for example, a laminated film of a barrier conductive film such as titanium nitride (TiN) and a metal film such as tungsten (W) or copper (Cu). At least a part of the plurality of wirings m0 electrically connects the via wiring 104 functioning as the bit line BL and the wiring m1 functioning as the global bit line GBL.

[0053] 5, both side surfaces in the X direction of the conductive layer 120 are connected to a plurality of conductive layers 113 arranged in the Y direction. In this embodiment, in order to realize a 1T1C type memory cell MC in such a configuration, the transistor structure 110 connected to one side surface of the conductive layer 120 in the X direction and the transistor structure 110 connected to the other side surface of the conductive layer 120 in the X direction are electrically connected to different global bit lines GBL.

[0054] 6, among the global bit lines GBL arranged in the Y direction, the even-numbered global bit lines GBLe counting from the positive side of the Y direction are provided at positions overlapping the corresponding bit lines BL when viewed from the Z direction. Among the multiple wirings m0, multiple wirings m0e connected to such global bit lines GBLo are provided at positions overlapping the global bit lines GBLe and the bit lines BL when viewed from the Z direction. Also, each wiring m0e is electrically connected to the bit line BL through a via contact electrode c0e (FIG. 3) extending in the Z direction, and is electrically connected to the global bit line GBLe through a via contact electrode c1e extending in the Z direction.

[0055] On the other hand, among the multiple global bit lines GBL arranged in the Y direction, the odd-numbered global bit lines GBLo counting from the positive side in the Y direction are provided at positions that do not overlap the corresponding multiple bit lines BL when viewed from the Z direction. Among the multiple wirings m0, multiple wirings m0o connected to such global bit lines GBLo each extend in the Y direction from a position overlapping with the global bit line GBLo when viewed from the Z direction to a position overlapping with the bit line BL. Also, a via contact electrode c0o (FIG. 3) extending in the Z direction is provided at a position overlapping with both the bit line BL and the wiring m0o when viewed from the Z direction. Also, a via contact electrode c1o extending in the Z direction is provided at a position overlapping with both the global bit line GBLo and the wiring m0o when viewed from the Z direction. The wiring m0o is electrically connected to the bit line BL through the via contact electrode c0o, and is electrically connected to the global bit line GBLo through the via contact electrode c1o.

[0056] In the illustrated example, the width of the wire m0o in the Y direction is greater than the width of the wire m0e in the Y direction.

[0057] [Manufacturing method] 9 to 57 are schematic cross-sectional views for explaining the manufacturing method of the semiconductor memory device according to the first embodiment. FIG. 9, FIG. 11, FIG. 13, FIG. 15, FIG. 17, FIG. 19, FIG. 21, FIG. 23, FIG. 25, FIG. 27, FIG. 29, FIG. 31, FIG. 33, FIG. 35, FIG. 37, FIG. 39, FIG. 41, FIG. 43, FIG. 45, FIG. 47, FIG. 49, FIG. 51, and FIG. 56 show cross sections corresponding to FIG. 7. FIG. 10, FIG. 12, FIG. 14, FIG. 16, FIG. 18, FIG. 20, FIG. 22, FIG. 24, FIG. 26, FIG. 28, FIG. 30, FIG. 32, FIG. 34, FIG. 36, FIG. 38, FIG. 40, FIG. 42, FIG. 44, FIG. 46, FIG. 48, FIG. 50, FIG. 52, FIG. 54, and FIG. 57 show cross sections corresponding to FIG. 8. FIG. 55 shows a cross section corresponding to FIG. 5.

[0058] In this manufacturing method, for example, as shown in Fig. 10, a plurality of insulating layers 103 and a plurality of sacrificial layers MLA are alternately formed. The sacrificial layers MLA include, for example, silicon nitride (Si3N4) etc. This process is performed, for example, by CVD (Chemical Vapor Deposition) etc.

[0059] Next, as shown in FIG. 9, an insulating member 115 is formed. In this step, for example, an opening is formed at a position corresponding to the insulating member 115. This opening extends in the Z direction and penetrates the multiple insulating layers 103 and the multiple sacrificial layers MLA aligned in the Z direction. This step is performed by, for example, RIE. After the opening is formed, the insulating member 115 is formed. This step is performed by, for example, CVD.

[0060] 11 and 12, an opening 104A is formed at a position corresponding to the via wiring 104. The opening 104A extends in the Z direction as shown in Fig. 12, and penetrates the multiple insulating layers 103 and the multiple sacrificial layers MLA aligned in the Z direction. This step is performed by, for example, RIE or the like.

[0061] Next, as shown in, for example, FIG. 13 and FIG. 14, an opening 111A is formed at a position corresponding to the semiconductor layer 111. In the opening 111A, a part of the upper surface and a part of the lower surface of the insulating layer 103, a part of the side surface in the X direction of the sacrificial layer MLA, and a part of the side surface in the Y direction of the insulating member 115 are exposed. In this process, for example, a part of the sacrificial layer MLA is selectively removed through the opening 104A. This process is performed by, for example, wet etching or the like. For example, as shown in FIG. 13, the side surface in the X direction of the opening 111A may be curved when viewed from the Z direction. For example, the length in the X direction of the opening 111A may differ depending on the position in the Y direction. For example, the length in the X direction of the opening 111A at a position close to the insulating member 115 may be shorter than the length in the X direction of the opening 111A at a position far from the insulating member 115.

[0062] Next, as shown in, for example, FIG. 15 and FIG. 16, a conductive layer 113A and a sacrificial layer 111B such as silicon (Si) are formed inside the opening 111A and the opening 104A. The conductive layer 113A is formed on a part of the upper surface, a part of the lower surface, and the surface exposed to the opening 104A of the insulating layer 103, a part of the side surface in the X direction of the sacrificial layer MLA, and a part of the side surface in the Y direction of the insulating member 115. The opening 111A is filled with the sacrificial layer 111B, and the opening 104A is not filled with the sacrificial layer 111B. This process is performed, for example, by CVD or the like. Although not shown, after the conductive layer 113A and the sacrificial layer 111B are formed, the upper part of the opening 104A is blocked by an insulating layer or the like.

[0063] 17 and 18, an opening 102A is formed at a position corresponding to the conductive member 102. The opening 102A extends in the Y and Z directions, and penetrates the insulating layers 103 and the sacrificial layers MLA arranged in the Z direction, as well as the insulating member 115, to divide these components in the X direction. This process is performed by, for example, RIE or the like.

[0064] Next, as shown in, for example, FIGS. 19 and 20, an opening 130A is formed at a position corresponding to the capacitor structure 130. In this step, the sacrificial layer MLA is removed through the opening 102A. Also, a portion of the conductive layer 113A that covers one side surface of the sacrificial layer 111B in the X direction (the side surface on the opening 102A side) is removed. In this step, the side surface of the sacrificial layer 111B in the X direction is exposed inside the opening 102A. This step is performed by, for example, wet etching or the like.

[0065] 21 and 22, the sacrificial layer 111B is oxidized through the openings 102A and 130A to form an insulating layer 111C. The sacrificial layer 130B made of silicon (Si) or the like is embedded in the openings 102A and 130A. This process is performed by, for example, CVD or the like.

[0066] Next, the conductive layer 113 is formed, for example, as shown in Figures 23 and 24. In this step, for example, the portion of the sacrificial layer 111B provided on the inner circumferential surface of the opening 104A is removed. Next, the portion of the conductive layer 113A provided on the inner circumferential surface of the opening 104A is removed, and the conductive layer 113A is divided in the Z direction. This step is performed, for example, by wet etching or the like.

[0067] Next, the sacrificial layer 111B is removed, for example, as shown in Figures 25 and 26. This step is performed by, for example, wet etching or the like.

[0068] 27 and 28, the insulating layer 111C and a part of the sacrificial layer 130B are removed. This step is performed by, for example, wet etching.

[0069] Next, as shown in FIG. 29 and FIG. 30, for example, an insulating layer 112A and a sacrificial layer 111B are formed inside the opening 111A and the opening 104A. The insulating layer 112A is formed on the upper surface, the lower surface, and the surface exposed to the opening 111A of the conductive layer 113, a part of the upper surface, a part of the lower surface, and the surface exposed to the opening 104A of the insulating layer 103, a part of the side surface in the X direction of the sacrificial layer 130B, and a part of the side surface in the Y direction of the insulating member 115. The opening 111A is filled with the sacrificial layer 111B, and the opening 104A is not filled with the sacrificial layer 111B. This process is performed by, for example, CVD or the like. Although not shown, after the insulating layer 112A and the sacrificial layer 111B are formed, the upper part of the opening 104A is blocked by an insulating layer or the like.

[0070] Next, the sacrificial layer 130B is removed, for example, as shown in Figures 31 and 32. This step is performed by, for example, wet etching or the like.

[0071] Next, as shown in Fig. 33 and Fig. 34, for example, the insulating layer 112 is formed. In this step, a portion of the insulating layer 112A that covers one side surface in the X direction of the sacrificial layer 111B (the side surface on the opening 102A side) is removed through the opening 102A and the opening 130A. In this step, the side surface in the X direction of the sacrificial layer 111B is exposed inside the opening 102A. This step is performed by, for example, wet etching or the like.

[0072] 35 and 36, for example, a conductive layer 134A is formed through the openings 102A and 130A on one side surface in the X direction of the sacrificial layer 111B (the side surface on the opening 102A side), one side surface in the X direction (the opening 102A side) and both side surfaces in the Y direction of the insulating member 115, and the upper surface, lower surface, and one side surface in the X direction (the opening 102A side) of the insulating layer 103. This process is performed by, for example, ALD (Atomic Layer Deposition) or the like.

[0073] 37 and 38, a sacrificial layer 130C of silicon (Si) or the like is formed inside the opening 102A. The opening 130A is filled with the sacrificial layer 130C, and the opening 102A is not filled with the sacrificial layer 130C. This process is performed by, for example, CVD or the like.

[0074] 39 and 40, a part of the sacrificial layer 130C is removed through the opening 102A. In this step, for example, a part of the conductive layer 134A provided on the side surface in the X direction of the insulating member 115 and the insulating layer 103 is exposed. This step is performed by, for example, wet etching or the like.

[0075] 41 and 42, the conductive layer 134 is formed. In this step, for example, the portions of the conductive layer 134A provided on the side surfaces of the insulating member 115 and the insulating layer 103 in the X direction are removed, and the conductive layer 134A is divided in the Y direction and the Z direction. This step is performed by, for example, wet etching or the like.

[0076] Next, the sacrificial layer 130C is removed, for example, as shown in Figures 43 and 44. This step is performed by, for example, wet etching or the like.

[0077] 45 and 46, a part of the insulating member 115 and a part of the insulating layer 103 are removed through the opening 102A to form an opening 130D. In the illustrated example, the region inside the conductive layer 134 is shown as opening 130A, and the region outside the conductive layer 134 is shown as opening 130D. In this step, the insulating member 115 and the insulating layer 103 are removed to an extent that the conductive layer 113 is not exposed in the opening 130D. This step is performed by, for example, wet etching or the like.

[0078] 47 and 48, insulating layers 133 and 135, conductive layers 132 and 136, conductive layers 131 and 137, and conductive member 102 are formed on the upper surface, lower surface, one side surface in the X direction (the side surface on the opening 102A side), and both side surfaces in the Y direction of conductive layer 134 through openings 130A, 130D, and opening 102A. This process is performed by, for example, CVD or the like.

[0079] Next, the sacrificial layer 111B is removed, for example, as shown in Figures 49 and 50. This step is performed by, for example, wet etching or the like.

[0080] 51 and 52, the semiconductor layer 111 is formed inside the opening 111A and the opening 104A. The opening 111A is filled with the semiconductor layer 111. The opening 104A is not filled with the semiconductor layer 111. This process is performed by, for example, ALD or the like.

[0081] Next, as shown in Figures 53 and 54, for example, the via wiring 104 is formed inside the opening 104A. This process is performed by, for example, ALD and CVD.

[0082] 55, an opening 105A is formed at a position corresponding to the insulating member 105. The opening 105A extends in the Z direction and penetrates the multiple insulating layers 103 and the multiple sacrificial layers MLA aligned in the Z direction. This step is performed by, for example, RIE or the like.

[0083] Next, as shown in Fig. 56 and Fig. 57, for example, an opening 120A is formed at a position corresponding to the conductive layer 120. A part of the upper surface and a part of the lower surface of the insulating layer 103, the side surface in the X direction of the conductive layer 113, and the side surface in the X direction of the insulating member 115 are exposed inside the opening 120A. In this step, for example, the sacrificial layer MLA is selectively removed through the opening 105A. This step is performed by, for example, wet etching or the like.

[0084] 7 and 8, the conductive layer 120 is formed inside the opening 120A. This process is performed by, for example, CVD or the like.

[0085] [effect] Next, the effects of the semiconductor memory device according to the first embodiment will be described with reference to Fig. 58 and Fig. 59. Fig. 58 and Fig. 59 are schematic XY cross-sectional views for explaining the effects of the semiconductor memory device according to the first embodiment. Fig. 58 shows a partial configuration of the semiconductor memory device according to the first embodiment. Fig. 59 shows a partial configuration of a semiconductor memory device according to a comparative example.

[0086] As described above, in the memory layer ML (FIG. 58) according to the first embodiment, one conductive layer 120 is provided between two conductive members 102 adjacent to each other in the X direction. Both side surfaces in the X direction of the conductive layer 120 are respectively connected to a plurality of transistor structures 110 aligned in the Y direction.

[0087] On the other hand, as shown in FIG. 59, in the memory layer ML0 according to the comparative example, two conductive layers 126 spaced apart in the X direction are provided between two conductive members 102 adjacent in the X direction. These two conductive layers 126 are electrically independent of each other and function as separate word lines WL. The side surfaces on one side in the X direction (the conductive member 102 side) of these two conductive layers 126 are each connected to a plurality of transistor structures 116 aligned in the Y direction. On the other hand, the side surfaces on the other side in the X direction (the side opposite to the conductive member 102) of the two conductive layers 126 are not connected to any of the transistor structures 116.

[0088] The transistor structure 116 includes a semiconductor layer that is electrically connected to the via wiring 104 and functions as a channel region of the transistor, and a gate electrode of the transistor that faces the semiconductor layer and is electrically connected to the conductive layer 126.

[0089] Here, in the first embodiment, one conductive layer 120 (FIG. 58) is provided between two conductive members 102 adjacent in the X direction, instead of two conductive layers 126 (FIG. 59). Therefore, it is possible to reduce the wiring width in the X direction by approximately the width of one conductive layer 126. In addition, it is also possible to reduce the width of the insulating layer between the two conductive layers 126. This makes it possible to achieve high integration of the memory cell array MCA.

[0090] In the transistor structure 110 according to this embodiment, the conductive layer 113 faces the upper surface, the lower surface, and both side surfaces in the Y direction of the semiconductor layer 111.

[0091] In such a configuration, it is possible to suppress interference of electric fields between the multiple semiconductor layers 111 arranged in the Z direction. Therefore, even when the memory cell array MCA is highly integrated in the Z direction, it is possible to provide a semiconductor memory device that can appropriately control the semiconductor layers 111 to be in the ON state or OFF state and operates appropriately.

[0092] Furthermore, when the transistor TrC is turned on, channels are formed on the upper surface, the lower surface, and both side surfaces in the Y direction of the semiconductor layer 111. This allows the ON current of the transistor TrC to be relatively large, thereby enabling faster and more stable operation.

[0093] In this embodiment, the conductive layer 120 functioning as the word line WL is provided on the opposite side of the plate line PL with respect to the transistor structure 110, and is provided at a position not overlapping with the transistor structure 110 when viewed from the Z direction. Therefore, the conductive layer 120 and the transistor structure 110 can be formed independently, and can be manufactured relatively easily. In addition, it is possible to make the wiring resistance of the conductive layer 120 a relatively small value while suppressing the width of the memory layer ML in the Z direction.

[0094] [Second embodiment] 55 to 57, in manufacturing the semiconductor memory device according to the first embodiment, an opening 105A is formed penetrating a plurality of insulating layers 103 and a plurality of sacrificial layers MLA arranged in the Z direction, and the sacrificial layers MLA are removed and a conductive layer 120 is formed through this opening 105A. After the conductive layer 120 is formed, an insulating member 105 is formed inside the opening 105A.

[0095] Here, the position, shape, size, etc. of the opening 105A can be adjusted as appropriate. Therefore, the position, shape, size, etc. of the structure corresponding to the insulating member 105 can also be adjusted as appropriate. Other structural examples of the insulating member 105 will be described below as second to fourth embodiments.

[0096] First, a semiconductor memory device according to a second embodiment will be described with reference to Fig. 60. Fig. 60 is a schematic XY cross-sectional view showing a configuration of a portion of the semiconductor memory device. In the following description, the same components as those in the first embodiment are denoted by the same reference numerals, and description thereof will be omitted.

[0097] The semiconductor memory device according to the second embodiment is basically configured in the same manner as the semiconductor memory device according to the first embodiment.

[0098] However, the semiconductor memory device according to the second embodiment includes a plurality of insulating members 205 instead of the plurality of insulating members 105. The insulating members 205 are basically configured similarly to the insulating members 105. However, the central positions in the X direction of the insulating members 205 are provided on one side in the X direction (the negative side in the X direction in the illustrated example) with respect to the central position in the X direction of the conductive layer 120.

[0099] 5, the outer circumferential surface of the insulating member 105 according to the first embodiment is surrounded by the conductive layer 120 over the entire periphery and is connected to the conductive layer 120. On the other hand, in the example of FIG. 60, the outer circumferential surface of the insulating member 205 is surrounded by the conductive layer 120 and the insulating member 115 and is connected to the conductive layer 120 and the insulating member 115.

[0100] [Third embodiment] Next, a semiconductor memory device according to a third embodiment will be described with reference to Fig. 61. Fig. 61 is a schematic XY cross-sectional view showing a configuration of a portion of the semiconductor memory device. In the following description, the same components as those in the first embodiment are denoted by the same reference numerals, and description thereof will be omitted.

[0101] The semiconductor memory device according to the third embodiment is basically configured in the same manner as the semiconductor memory device according to the first embodiment.

[0102] However, the semiconductor memory device according to the third embodiment includes a plurality of insulating members 305 instead of the plurality of insulating members 105. The insulating members 305 are basically configured in the same manner as the insulating members 105. However, the central positions in the X direction of some of the insulating members 305 (in the illustrated example, the odd-numbered insulating members 305 counting from the positive side in the Y direction) are provided on one side in the X direction (e.g., the positive side in the X direction) with respect to the central position in the X direction of the conductive layer 120. Also, the central positions in the X direction of other parts of the insulating members 305 (in the illustrated example, the even-numbered insulating members 305 counting from the positive side in the Y direction) are provided on the other side in the X direction (e.g., the negative side in the X direction) with respect to the central position in the X direction of the conductive layer 120.

[0103] In the example of FIG. 61, the outer circumferential surface of the insulating member 305 is surrounded by the conductive layer 120 and the insulating member 115 and is connected to the conductive layer 120 and the insulating member 115 .

[0104] [Fourth embodiment] Next, a semiconductor memory device according to a fourth embodiment will be described with reference to Fig. 62. Fig. 62 is a schematic XY cross-sectional view showing a configuration of a portion of the semiconductor memory device. In the following description, the same components as those in the first embodiment are denoted by the same reference numerals, and the description thereof will be omitted.

[0105] The semiconductor memory device according to the fourth embodiment is basically configured similarly to the semiconductor memory device according to the first embodiment.

[0106] However, the semiconductor memory device according to the fourth embodiment includes a plurality of insulating members 405 instead of the plurality of insulating members 105. The insulating members 405 are basically configured in the same manner as the insulating members 105. However, the number of the insulating members 105 aligned in the Y direction is the same as the number of the insulating members 115 aligned in the Y direction. On the other hand, the number of the insulating members 405 aligned in the Y direction is smaller than the number of the insulating members 115 aligned in the Y direction.

[0107] Moreover, the semiconductor memory device according to the fourth embodiment includes a conductive layer 420 instead of the conductive layer 120. The conductive layer 420 includes a plurality of portions 421 and portions 422 arranged alternately in the Y direction. The portion 421 is configured similarly to the conductive layer 120. The portion 422 is provided at a position corresponding to the insulating member 405. Unlike the portion 421, the portion 422 is not connected to any of the conductive layers 113. The width in the X direction of the portion 422 is larger than the width in the X direction of the portion 421. The width in the Y direction of the portion 422 is smaller than the width in the Y direction of the portion 421. The widths in the X direction and the Y direction of the portion 422 are larger than the widths in the X direction and the Y direction of the insulating member 405, respectively.

[0108] Here, the conductive layer 420 according to the fourth embodiment includes a portion 421 connected to the transistor structure 110, and a portion 422 in which the insulating member 405 is provided. With such a configuration, since no configuration corresponding to the insulating member 105 is formed in the portion 421, it may be possible to further increase the integration density of the memory cell array MCA by reducing the width of the portion 421 in the X direction.

[0109] In the example of FIG. 62, the entire outer circumferential surface of the insulating member 405 is surrounded by the conductive layer 420 and connected to the conductive layer 420.

[0110] [Fifth embodiment] Next, a semiconductor memory device according to a fifth embodiment will be described with reference to Fig. 63. Fig. 63 is a schematic plan view showing a configuration of a portion of the semiconductor memory device. In the following description, the same reference numerals are used to designate the same configuration as in the first embodiment, and description thereof will be omitted.

[0111] The semiconductor memory device according to the fifth embodiment is basically configured in the same manner as the semiconductor memory device according to the first embodiment.

[0112] However, the semiconductor memory device according to the fifth embodiment includes a wiring layer M5 instead of the wiring layers M0 and M1.

[0113] The wiring layer M5 includes a plurality of wirings m5. The plurality of wirings m5 may include, for example, a laminated film of a barrier conductive film such as titanium nitride (TiN) and a metal film such as tungsten (W) or copper (Cu). At least a part of the plurality of wirings m5 functions as a global bit line GBL (FIG. 1).

[0114] As described with reference to FIG. 6, the multiple global bit lines GBL according to the first embodiment each extend in the X direction and are electrically connected to multiple via wirings 104 whose positions in the Y direction are approximately the same.

[0115] On the other hand, as shown in FIG. 63, the multiple global bit lines GBL according to the fifth embodiment each extend in a diagonal direction (a direction that does not coincide with either the Y direction or the X direction in the XY plane and in the XY cross section) and are electrically connected to multiple via wirings 104 at different positions in the Y direction.

[0116] In the fifth embodiment, both global bit lines GBLo and GBLe are provided at positions overlapping the corresponding bit lines BL when viewed from the Z direction. The lower surfaces of the global bit lines GBLo and GBLe are in direct contact with the via contact electrodes c0o and c0e.

[0117] According to this configuration, the configuration corresponding to the wiring layer M0 and the via contact electrodes c1o and c1e can be omitted, and therefore the manufacturing cost can be reduced compared to the first embodiment.

[0118] The semiconductor memory device according to the fifth embodiment may include a plurality of insulating members 205 (FIG. 60), a plurality of insulating members 305 (FIG. 61), or a plurality of insulating members 405 (FIG. 62) instead of the plurality of insulating members 105. When the semiconductor memory device according to the fifth embodiment includes a plurality of insulating members 405, the semiconductor memory device according to the fifth embodiment may include a conductive layer 420 (FIG. 62) instead of the conductive layer 120.

[0119] [Sixth embodiment] Next, a semiconductor memory device according to a sixth embodiment will be described with reference to Fig. 64 and Fig. 65. Fig. 64 is a schematic XY cross-sectional view showing a partial configuration of the semiconductor memory device. Fig. 65 is a schematic plan view showing a partial configuration of the semiconductor memory device. In the following description, the same reference numerals are used for configurations similar to those of the third embodiment, and description thereof will be omitted.

[0120] The semiconductor memory device according to the sixth embodiment is basically configured similarly to the semiconductor memory device according to the third embodiment.

[0121] 5, in the semiconductor memory device according to the first embodiment, a plurality of via wirings 104 are arranged between two conductive members 102 adjacent in the X direction to form two rows with different positions in the X direction. When focusing on these via wirings 104, the Y direction positions of the plurality of via wirings 104 included in a row provided on one side in the X direction with respect to the conductive layer 120 approximately coincide with the Y direction positions of any of the plurality of via wirings 104 included in a row provided on the other side in the X direction with respect to the conductive layer 120.

[0122] 64, in the semiconductor memory device according to the sixth embodiment, a plurality of via wirings 104 are arranged between two conductive members 102 adjacent in the X direction to form two rows having different positions in the X direction. However, when focusing on these via wirings 104, the Y direction positions of the plurality of via wirings 104 included in the row provided on one side in the X direction with respect to the conductive layer 120 do not match any of the Y direction positions of the plurality of via wirings 104 included in the row provided on the other side in the X direction with respect to the conductive layer 120.

[0123] 64, the Y-direction positions of the via wirings 104 included in a row provided on one side in the X-direction with respect to the conductive layer 120 approximately coincide with the middle positions of any two adjacent via wirings 104 in the Y-direction among the via wirings 104 included in a row provided on the other side in the X-direction with respect to the conductive layer 120. The Y-direction positions of the via wirings 104 included in a row provided on one side in the X-direction with respect to the conductive layer 120 are between the Y-direction positions of any two adjacent via wirings 104 in the Y-direction among the via wirings 104 included in a row provided on the other side in the X-direction with respect to the conductive layer 120.

[0124] Moreover, the semiconductor memory device according to the sixth embodiment does not include the wiring layer M0.

[0125] 65, in the sixth embodiment, both global bit lines GBLo, GBLe in the wiring layer M1 are provided at positions overlapping the corresponding bit lines BL when viewed from the Z direction. The lower surfaces of the global bit lines GBLo, GBLe are in direct contact with the via contact electrodes c0o, c0e.

[0126] According to this configuration, the configuration corresponding to the wiring layer M0 and the via contact electrodes c1o and c1e can be omitted, and therefore the manufacturing cost can be reduced compared to the first embodiment.

[0127] [Seventh embodiment] Next, a semiconductor memory device according to a seventh embodiment will be described with reference to Fig. 66. Fig. 66 is a schematic XY cross-sectional view showing a configuration of a portion of the semiconductor memory device. In the following description, the same components as those in the sixth embodiment are denoted by the same reference numerals, and description thereof will be omitted.

[0128] The semiconductor memory device according to the seventh embodiment is basically configured similarly to the semiconductor memory device according to the sixth embodiment.

[0129] However, the semiconductor memory device according to the seventh embodiment includes a plurality of insulating members 405 described with reference to Fig. 62 instead of the plurality of insulating members 305. The number of the plurality of insulating members 405 aligned in the Y direction is smaller than the number of the plurality of insulating members 115 aligned in the Y direction.

[0130] Moreover, the semiconductor memory device according to the seventh embodiment includes the conductive layer 420 described with reference to FIG.

[0131] In the example of FIG. 66, the entire outer circumferential surface of the insulating member 405 is surrounded by the conductive layer 420 and is connected to the conductive layer 420.

[0132] [Eighth embodiment] Next, a semiconductor memory device according to an eighth embodiment will be described with reference to Fig. 67 and Fig. 68. Fig. 67 is a schematic XY cross-sectional view showing a partial configuration of the semiconductor memory device. Fig. 68 is a schematic plan view showing a partial configuration of the semiconductor memory device. In the following description, the same reference numerals are used for configurations similar to those of the third embodiment, and description thereof will be omitted.

[0133] The semiconductor memory device according to the eighth embodiment is basically configured similarly to the semiconductor memory device according to the first embodiment.

[0134] 5, in the semiconductor memory device according to the first embodiment, a plurality of via wirings 104 are arranged between two conductive layers 120 adjacent to each other in the X direction to form two rows having different positions in the X direction. When focusing on the plurality of via wirings 104, the Y direction positions of the plurality of via wirings 104 included in the row provided on one side in the X direction with respect to the conductive member 102 are approximately equal to the Y direction positions of any of the plurality of via wirings 104 included in the row provided on the other side in the X direction with respect to the conductive member 102.

[0135] 67, in the semiconductor memory device according to the eighth embodiment, a plurality of via wirings 104 are arranged between two conductive layers 120 adjacent in the X direction to form two rows having different positions in the X direction. However, when focusing on these via wirings 104, the Y direction positions of the plurality of via wirings 104 included in the row provided on one side in the X direction with respect to the conductive member 102 do not match any of the Y direction positions of the plurality of via wirings 104 included in the row provided on the other side in the X direction with respect to the conductive member 102.

[0136] 67, the Y-direction positions of the via wirings 104 included in a row provided on one side in the X-direction with respect to the conductive member 102 approximately coincide with the middle positions of any two adjacent via wirings 104 in the Y-direction among the via wirings 104 included in a row provided on the other side in the X-direction with respect to the conductive member 102. The Y-direction positions of the via wirings 104 included in a row provided on one side in the X-direction with respect to the conductive member 102 are between the Y-direction positions of any two adjacent via wirings 104 in the Y-direction among the via wirings 104 included in a row provided on the other side in the X-direction with respect to the conductive member 102.

[0137] 68, in the eighth embodiment, both of the global bit lines GBLo and GBLe are provided at positions that do not overlap with the corresponding bit lines BL when viewed from the Z direction. In the example of FIG. 68, the width of the wiring m0e in the Y direction is approximately the same as the width of the wiring m0o in the Y direction.

[0138] The semiconductor memory device according to the eighth embodiment may include a plurality of insulating members 205 (FIG. 60), a plurality of insulating members 305 (FIG. 61), or a plurality of insulating members 405 (FIG. 62) instead of the plurality of insulating members 105. When the semiconductor memory device according to the eighth embodiment includes a plurality of insulating members 405, the semiconductor memory device according to the eighth embodiment may include a conductive layer 420 (FIG. 62) instead of the conductive layer 120.

[0139] [Ninth embodiment] Next, a semiconductor memory device according to a ninth embodiment will be described with reference to Fig. 69. Fig. 69 is a schematic plan view showing a configuration of a portion of the semiconductor memory device. In the following description, the same reference numerals are used to designate the same configuration as in the first embodiment, and description thereof will be omitted.

[0140] The semiconductor memory device according to the ninth embodiment is basically configured similarly to the semiconductor memory device according to the eighth embodiment.

[0141] However, the semiconductor memory device according to the ninth embodiment includes the wiring layer M5 described with reference to FIG. 63, instead of the wiring layers M0 and M1.

[0142] In the ninth embodiment, both global bit lines GBLo and GBLe are provided at positions overlapping the corresponding bit lines BL when viewed from the Z direction. The lower surfaces of the global bit lines GBLo and GBLe are in direct contact with the via contact electrodes c0o and c0e.

[0143] According to this configuration, the configuration corresponding to the wiring layer M0 and the via contact electrodes c1o and c1e can be omitted, and therefore the manufacturing cost can be reduced compared to the first embodiment.

[0144] The semiconductor memory device according to the ninth embodiment may include a plurality of insulating members 205 (FIG. 60), a plurality of insulating members 305 (FIG. 61), or a plurality of insulating members 405 (FIG. 62) instead of the plurality of insulating members 105. When the semiconductor memory device according to the ninth embodiment includes a plurality of insulating members 405, the semiconductor memory device according to the ninth embodiment may include a conductive layer 420 (FIG. 62) instead of the conductive layer 120.

[0145] [Tenth embodiment] Next, a semiconductor memory device according to a tenth embodiment will be described with reference to Fig. 70 and Fig. 71. Fig. 70 is a schematic XY cross-sectional view showing a partial configuration of the semiconductor memory device. Fig. 71 is a schematic plan view showing a partial configuration of the semiconductor memory device. In the following description, the same reference numerals are used for configurations similar to those of the sixth embodiment, and description thereof will be omitted.

[0146] The semiconductor memory device according to the tenth embodiment is basically configured similarly to the semiconductor memory device according to the sixth embodiment.

[0147] 64, in the semiconductor memory device according to the sixth embodiment, a plurality of via wirings 104 are arranged between two conductive layers 120 adjacent to each other in the X direction to form two rows having different positions in the X direction. When focusing on these via wirings 104, the Y direction positions of the plurality of via wirings 104 included in a row provided on one side in the X direction with respect to the conductive member 102 are approximately equal to the Y direction positions of any of the plurality of via wirings 104 included in a row provided on the other side in the X direction with respect to the conductive member 102.

[0148] 70, also in the semiconductor memory device according to the tenth embodiment, a plurality of via wirings 104 are arranged between two conductive layers 120 adjacent in the X direction to form two rows having different positions in the X direction. However, when focusing on these via wirings 104, the Y direction positions of the plurality of via wirings 104 included in the row provided on one side in the X direction with respect to the conductive member 102 do not match any of the Y direction positions of the plurality of via wirings 104 included in the row provided on the other side in the X direction with respect to the conductive member 102.

[0149] 70, the Y-direction positions of the via wirings 104 included in a row provided on one side in the X-direction with respect to the conductive member 102 approximately coincide with the middle positions of any two adjacent via wirings 104 in the Y-direction among the via wirings 104 included in a row provided on the other side in the X-direction with respect to the conductive member 102. The Y-direction positions of the via wirings 104 included in a row provided on one side in the X-direction with respect to the conductive member 102 are between the Y-direction positions of any two adjacent via wirings 104 in the Y-direction among the via wirings 104 included in a row provided on the other side in the X-direction with respect to the conductive member 102.

[0150] Moreover, the semiconductor memory device according to the tenth embodiment does not include the wiring layer M0.

[0151] 71, in the tenth embodiment, both global bit lines GBLo, GBLe in the wiring layer M1 are provided at positions overlapping the corresponding bit lines BL when viewed from the Z direction. The lower surfaces of the global bit lines GBLo, GBLe are in direct contact with the via contact electrodes c0o, c0e.

[0152] According to this configuration, the configuration corresponding to the wiring layer M0 and the via contact electrodes c1o and c1e can be omitted, and therefore the manufacturing cost can be reduced compared to the first embodiment.

[0153] [Eleventh embodiment] Next, a semiconductor memory device according to an eleventh embodiment will be described with reference to Figures 72 to 74. In the following description, the same components as those in the first embodiment are denoted by the same reference numerals, and description thereof will be omitted.

[0154] [Circuit configuration] FIG. 72 is a schematic circuit diagram showing a configuration of a portion of the semiconductor memory device.

[0155] The semiconductor memory device according to the eleventh embodiment is basically configured similarly to the semiconductor memory device according to the first embodiment.

[0156] However, as shown in FIG. 72, the memory cell array MCA11 according to the eleventh embodiment includes a transistor layer TL in addition to the components included in the memory cell array MCA according to the first embodiment.

[0157] The transistor layer TL includes a plurality of bit line selection lines LB0 to LB2 and a plurality of transistors TrB connected to the plurality of bit line selection lines LB0 to LB2. A source electrode of the transistor TrB is connected to the global bit line GBL. A drain electrode of the transistor TrB is connected to the bit line BL. That is, in this embodiment, the plurality of bit lines BL are each electrically connected to the global bit line GBL via the transistor TrB. A gate electrode of the transistor TrB is connected to any one of the bit line selection lines LB0 to LB2.

[0158] The transistor layer TL includes a plurality of transistors TrTa, TrTb (hereinafter, sometimes referred to as "transistors TrT") provided corresponding to the plurality of bit line selection lines LB0 to LB2. The drain electrodes of the transistors TrT are connected to any of the bit line selection lines LB0 to LB2. The source electrodes of the transistors TrT are connected to the word line selection lines LW. The gate electrodes of the transistors TrT are connected to the wirings LTa, LTb (hereinafter, sometimes referred to as "wirings LT").

[0159] The wiring LTa is commonly connected to all the transistors TrTa, and similarly, the wiring LTb is commonly connected to all the transistors TrTb.

[0160] [structure] Fig. 73 is a schematic perspective view showing a configuration of a portion of the semiconductor memory device, and Fig. 74 is a schematic plan view showing a configuration of a portion of the semiconductor memory device.

[0161] As shown in FIG. 73, the memory cell array MCA11 includes a transistor layer TL provided between a plurality of memory layers ML and a wiring layer M0.

[0162] The transistor layer TL is basically configured in the same manner as the memory layer ML.

[0163] However, the semiconductor layer 111, the insulating layer 112, and the conductive layer 113 in the transistor layer TL function as the channel region, the gate insulating film, and the gate electrode of the transistor TrB, respectively. The conductive layer 120 in the transistor layer TL functions as the bit line selection lines LB0 to LB2. The conductive layer 134 in the transistor layer TL functions as the source electrode of the transistor TrB.

[0164] In the eleventh embodiment, the via contact electrodes c0o and c0e are connected to the conductive layer 134 in the transistor layer TL.

[0165] The semiconductor memory device according to the eleventh embodiment may include a plurality of insulating members 205 (FIG. 60), a plurality of insulating members 305 (FIG. 61), or a plurality of insulating members 405 (FIG. 62) instead of the plurality of insulating members 105. When the semiconductor memory device according to the eleventh embodiment includes a plurality of insulating members 405, the semiconductor memory device according to the eleventh embodiment may include a conductive layer 420 (FIG. 62) instead of the conductive layer 120.

[0166] [Twelfth embodiment] Next, a semiconductor memory device according to a twelfth embodiment will be described with reference to Fig. 75. Fig. 75 is a schematic plan view showing a configuration of a portion of the semiconductor memory device. In the following description, the same reference numerals are used to designate the same configuration as in the sixth embodiment, and the description thereof will be omitted.

[0167] The semiconductor memory device according to the twelfth embodiment is basically configured similarly to the semiconductor memory device according to the sixth embodiment.

[0168] However, the memory cell array MCA12 according to the twelfth embodiment includes a transistor layer TL in addition to the components included in the memory cell array MCA according to the sixth embodiment.

[0169] In the twelfth embodiment, similarly to the eleventh embodiment, the via contact electrodes c0o and c0e are connected to the conductive layer 134 in the transistor layer TL.

[0170] [Thirteenth embodiment] Next, a semiconductor memory device according to a thirteenth embodiment will be described with reference to Fig. 76. Fig. 76 is a schematic plan view showing a configuration of a portion of the semiconductor memory device. In the following description, the same reference numerals are used to designate the same configuration as in the eighth embodiment, and description thereof will be omitted.

[0171] The semiconductor memory device according to the thirteenth embodiment is basically configured similarly to the semiconductor memory device according to the eighth embodiment.

[0172] However, the memory cell array MCA13 according to the thirteenth embodiment includes a transistor layer TL in addition to the components included in the memory cell array MCA according to the eighth embodiment.

[0173] In the thirteenth embodiment, similarly to the eleventh embodiment, the via contact electrodes c0o and c0e are connected to the conductive layer 134 in the transistor layer TL.

[0174] The semiconductor memory device according to the thirteenth embodiment may include a plurality of insulating members 205 (FIG. 60), a plurality of insulating members 305 (FIG. 61), or a plurality of insulating members 405 (FIG. 62) instead of the plurality of insulating members 105. When the semiconductor memory device according to the thirteenth embodiment includes a plurality of insulating members 405, the semiconductor memory device according to the thirteenth embodiment may include a conductive layer 420 (FIG. 62) instead of the conductive layer 120.

[0175] [Fourteenth embodiment] Next, a semiconductor memory device according to a fourteenth embodiment will be described with reference to Fig. 77. Fig. 77 is a schematic plan view showing a configuration of a portion of the semiconductor memory device. In the following description, the same reference numerals are used to designate the same configuration as in the tenth embodiment, and the description thereof will be omitted.

[0176] The semiconductor memory device according to the fourteenth embodiment is basically configured similarly to the semiconductor memory device according to the tenth embodiment.

[0177] However, the memory cell array MCA14 according to the fourteenth embodiment includes a transistor layer TL in addition to the components included in the memory cell array MCA according to the tenth embodiment.

[0178] In the fourteenth embodiment, similarly to the eleventh embodiment, the via contact electrodes c0o and c0e are connected to the conductive layer 134 in the transistor layer TL.

[0179] [Fifteenth embodiment] Next, a semiconductor memory device according to a fifteenth embodiment will be described with reference to Fig. 78. Fig. 78 is a schematic plan view showing a configuration of a portion of the semiconductor memory device. In the following description, the same reference numerals are used to designate the same configuration as in the first embodiment, and description thereof will be omitted.

[0180] The semiconductor memory device according to the fifteenth embodiment is basically configured similarly to the semiconductor memory device according to the first embodiment.

[0181] However, as shown in FIG. 78, in the fifteenth embodiment, a gap G is provided between two conductive layers 120 adjacent to each other in the Z direction.

[0182] The gap G can be formed, for example, after the step of forming the conductive layer 120 and before the step of forming the insulating member 105 by a method such as wet etching.

[0183] With such a configuration, it is possible to reduce the capacitance between two conductive layers 120 adjacent to each other in the Z direction and to increase the operating speed.

[0184] In the semiconductor memory devices according to the second to fourteenth embodiments, a gap G may be provided between two conductive layers 120 adjacent to each other in the Z direction, similar to the semiconductor memory device according to the fifteenth embodiment.

[0185] [Other embodiments] The semiconductor memory devices according to the first to fifteenth embodiments have been described above. However, the semiconductor memory devices according to these embodiments are merely examples, and the specific configurations and the like can be appropriately adjusted.

[0186] For example, in the first to fifteenth embodiments, the wiring layers M0 and M1 are provided above the memory cell arrays MCA, MCA11, MCA12, MCA13, and MCA14 (hereinafter referred to as "memory cell arrays MCA, etc.") (the opposite side of the semiconductor substrate Sub with respect to the memory cell arrays MCA, etc.). However, the wiring layers M0 and M1 may be provided below the memory cell arrays MCA, etc. (the side of the semiconductor substrate Sub with respect to the memory cell arrays MCA, etc.).

[0187] In the eleventh to fourteenth embodiments, when the wiring layers M0 and M1 are provided below the memory cell array MCA, the transistor layer TL may be provided below the multiple memory layers ML (between the multiple memory layers ML and the wiring layer M0).

[0188] In the semiconductor memory devices according to the first to fifteenth embodiments, the via wiring 104 functioning as a bit line contains a conductive oxide such as indium tin oxide (ITO). However, such a conductive oxide may be included in the transistor structure 110, not in the via wiring 104 extending in the Z direction. The via wiring 104 and the transistor structure 110 may contain other materials.

[0189] Furthermore, in the semiconductor memory devices according to the first to fifteenth embodiments, the conductive layer 113 functioning as the gate electrode of the transistor TrC may face only one of the upper surface and the lower surface of the semiconductor layer 111 functioning as the channel region of the transistor TrC.

[0190] In the semiconductor memory devices according to the first to fifteenth embodiments, the semiconductor layer functioning as the channel region of the transistor TrC may face the upper and lower surfaces of the conductive layer functioning as the gate electrode of the transistor TrC.

[0191] In the above description, an example has been described in which a capacitor CpC is adopted as the memory unit connected to the transistor structure 110. However, the memory unit does not have to be the capacitor CpC. For example, the memory unit may include a ferroelectric material, a ferromagnetic material, a chalcogen material such as GeSbTe, or other material, and may record data by utilizing the properties of these materials. For example, in any of the structures described above, the insulating layer between the electrodes that forms the capacitor CpC may include any of these materials.

[0192] Moreover, the methods for manufacturing the semiconductor memory devices according to the first to fifteenth embodiments can also be adjusted as appropriate. For example, the order of any two of the above-described steps may be reversed, or any two of the above-described steps may be performed simultaneously.

[0193] [others] Although some embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included in the scope and spirit of the invention, and are included in the scope of the invention and its equivalents described in the claims. [Explanation of symbols]

[0194] Sub...semiconductor substrate, ML...memory layer, BL...bit line, WL...word line, PL...plate line, TrC...transistor, CpC...capacitor, 102...conductive layer, 104...via wiring, 110...transistor structure, 111...semiconductor layer, 112...insulating layer, 113...conductive layer, 120...conductive layer, 130...capacitor structure.

Claims

1. A substrate; A plurality of memory layers aligned in a first direction intersecting a surface of the substrate; A first via wiring extending in the first direction; a second via wiring that is different in position from the first via wiring in a second direction intersecting the first direction and extends in the first direction; Equipped with Each of the plurality of memory layers includes: a first wiring provided between the first via wiring and the second via wiring and extending in a third direction intersecting the first direction and the second direction; a first semiconductor layer electrically connected to the first via wiring; a first gate electrode facing the first semiconductor layer and electrically connected to the first wiring; a first memory unit provided on an opposite side of the first wiring in the second direction with respect to the first semiconductor layer and electrically connected to the first semiconductor layer; a second semiconductor layer electrically connected to the second via wiring; a second gate electrode facing the second semiconductor layer and electrically connected to the first wiring; a second memory unit provided on an opposite side of the second semiconductor layer from the first wiring in the second direction and electrically connected to the second semiconductor layer; A semiconductor memory device comprising:

2. The first gate electrode faces one and the other surfaces of the first semiconductor layer in the first direction and one and the other surfaces in the third direction.

2. The semiconductor memory device according to claim 1.

3. A gap is provided between the first wirings arranged in the first direction corresponding to the memory layers.

2. The semiconductor memory device according to claim 1.

4. The first memory unit is A first electrode electrically connected to the first semiconductor layer; a second electrode facing the first electrode; an insulating layer provided between the first electrode and the second electrode; 2. The semiconductor memory device according to claim 1, comprising:

5. The first semiconductor layer includes at least one element of gallium (Ga) and aluminum (Al), indium (In), zinc (Zn), and oxygen (O).

2. The semiconductor memory device according to claim 1.

6. A substrate; A plurality of memory layers aligned in a first direction intersecting a surface of the substrate; a plurality of via wirings arranged to form a first row and a second row having different positions in a second direction intersecting the first direction; Equipped with the first row includes a plurality of first via wirings arranged in a third direction intersecting the first direction and the second direction and extending in the first direction; the second row includes a plurality of second via wirings aligned in the third direction and extending in the first direction; Each of the plurality of memory layers includes: a first wiring provided between the plurality of first via wirings and the plurality of second via wirings and extending in the third direction; a plurality of first semiconductor layers electrically connected to the plurality of first via wirings; a plurality of first gate electrodes facing the plurality of first semiconductor layers and electrically connected to the first wiring; a plurality of first memory units provided on an opposite side of the first wiring to the plurality of first semiconductor layers in the second direction and electrically connected to the plurality of first semiconductor layers; a plurality of second semiconductor layers electrically connected to the plurality of second via wirings; a plurality of second gate electrodes facing the plurality of second semiconductor layers and electrically connected to the first wiring; a plurality of second memory units provided on an opposite side of the plurality of second semiconductor layers from the first wiring in the second direction and electrically connected to the plurality of second semiconductor layers; A semiconductor memory device comprising:

7. In a first cross section extending in the second direction and the third direction and including the first wiring, the semiconductor memory device further includes a plurality of first insulating members aligned in the third direction along the first wiring.

7. The semiconductor memory device according to claim 6.

8. a plurality of second insulating members arranged alternately with the plurality of first semiconductor layers in the third direction; The positions of the first insulating members in the third direction correspond to the positions of the second insulating members in the third direction.

8. The semiconductor memory device according to claim 7.

9. The central positions of the plurality of first insulating members in the second direction substantially coincide with the central positions of the first wirings in the second direction.

8. The semiconductor memory device according to claim 7.

10. The plurality of first insulating members are provided on one side in the second direction with respect to a center position of the first wiring in the second direction.

8. The semiconductor memory device according to claim 7.

11. some of the plurality of first insulating members are provided on one side in the second direction with respect to a center position of the first wiring in the second direction; Another part of the plurality of first insulating members is provided on the other side in the second direction with respect to a central position of the first wiring in the second direction.

8. The semiconductor memory device according to claim 7.

12. a plurality of second insulating members arranged alternately with the plurality of first semiconductor layers in the third direction; The number of the first insulating members arranged in the third direction is smaller than the number of the second insulating members arranged in the third direction.

8. The semiconductor memory device according to claim 7.

13. a first wiring layer provided on one side of the plurality of memory layers in the first direction; a second wiring layer provided between the plurality of memory layers and the first wiring layer; Equipped with the first wiring layer includes a plurality of second wirings aligned in the third direction and extending in the second direction; The second wiring layer includes a plurality of third wirings extending in the third direction at a position where any one of the plurality of first via wirings or any one of the plurality of second via wirings overlaps any one of the plurality of second wirings when viewed from the first direction.

7. The semiconductor memory device according to claim 6.

14. a first wiring layer provided on one side of the plurality of memory layers in the first direction; the first wiring layer includes a plurality of second wirings; a portion of each of the second wirings is provided at a position overlapping with any of the first via wirings when viewed from the first direction; Another part of the plurality of second wirings is provided at a position overlapping with any one of the plurality of second via wirings when viewed from the first direction.

7. The semiconductor memory device according to claim 6.

15. The plurality of second wirings are aligned in the third direction and extend in the second direction.

15. The semiconductor memory device according to claim 14.

16. In a second cross section including the second wirings, the second wirings extend in the second direction and the third direction, and the second wirings extend in a direction intersecting the second direction and the third direction.

15. The semiconductor memory device according to claim 14.

17. The positions of the first via wirings in the third direction are approximately the same as the positions of any of the second via wirings in the third direction.

7. The semiconductor memory device according to claim 6.

18. The positions of the first via wirings in the third direction do not coincide with any of the positions of the second via wirings in the third direction.

7. The semiconductor memory device according to claim 6.

19. a fourth wiring extending in the first direction and the third direction and connected to the first memory units; a plurality of third via wirings provided on an opposite side of the fourth wiring from the plurality of first via wirings in the second direction, arranged in the third direction, and extending in the first direction; Further comprising: Each of the plurality of memory layers includes: a fifth wiring provided on an opposite side of the first wiring in the second direction with respect to the third via wirings and extending in the third direction; a plurality of third semiconductor layers electrically connected to the plurality of third via wirings; a plurality of third gate electrodes facing the plurality of third semiconductor layers and electrically connected to the fifth wiring; a plurality of third memory units provided between the plurality of third semiconductor layers and the fourth wiring and electrically connected to the plurality of third semiconductor layers and the fourth wiring; 7. The semiconductor memory device according to claim 6, further comprising:

20. The positions of the first via wirings in the third direction are approximately the same as the positions of any of the third via wirings in the third direction.

20. The semiconductor memory device according to claim 19.

21. The positions of the first via wirings in the third direction do not coincide with any of the positions of the third via wirings in the third direction.

20. The semiconductor memory device according to claim 19.

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