Designed substrate structure for power and RF application

Abstract

To provide an improved method and system related to epitaxial growth processes and substrate structures.SOLUTION: A substrate structure includes: a polycrystalline ceramic core 110 with a front surface featuring a plurality of voids and containing polycrystalline material; a barrier layer 118 that encapsulates the polycrystalline ceramic core and defines valleys corresponding to a plurality of voids; an adhesive layer 116 that is bonded to a barrier layer above the front surface of the polycrystalline ceramic core and defines a filled region with the valley filled with bonding layer material corresponding to a plurality of voids; a bonding layer 120 bonded to the adhesive layer; and a single crystal silicon layer 125 bonded to the bonding layer.SELECTED DRAWING: Figure 1A

Description

[Technical field]

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application claims priority to U.S. Provisional Patent Application No. 62 / 354,623, entitled "POLYCRYSTALLINE CERAMIC SUBSTRATE AND METHOD OF MANUFACTURE," filed June 24, 2016, the disclosure of which is incorporated herein by reference in its entirety for all purposes.

[0002] The following US patent applications are being filed concurrently herewith, the disclosures of which are incorporated herein by reference in their entireties for all purposes:

[0003]

[0003] Application No. 15 / 621,235, entitled “POLYCRYSTALLINE CERAMIC SUBSTRATE AND METHOD OF MANUFACTURE,” filed on June 13, 2017 (Attorney Docket No. 098825-1049531 (003210US)). [Background technology]

[0004]

[0004] Light emitting diode (LED) structures are typically epitaxially grown on sapphire substrates. Many products now use LED devices, including lighting, computer monitors, and other display devices.

[0005]

[0005] The growth of gallium nitride based LED structures on sapphire substrates is a heteroepitaxial growth process since the substrate and epitaxial layers are composed of different materials. Due to the heteroepitaxial growth process, the epitaxially grown materials can exhibit various adverse effects including reduced uniformity and reduced metrics related to the electronic / optical properties of the epitaxial layers. Therefore, there is a need in the art for improved methods and systems related to epitaxial growth processes and substrate structures. Summary of the Invention

[0006]

[0006] The present invention relates generally to engineered substrate structures. More specifically, the present invention relates to methods and systems suitable for use in epitaxial growth processes. By way of example only, the present invention is applied to methods and systems for providing a substrate structure suitable for epitaxial growth, the structure being characterized by a coefficient of thermal expansion (CTE) that is substantially matched to the epitaxial layer grown thereon. The methods and techniques can be applied to a variety of semiconductor processing operations.

[0007] According to one embodiment, a method of manufacturing a ceramic substrate structure includes providing a ceramic substrate, encapsulating the ceramic substrate in a barrier layer, and forming a bonding layer bonded to the barrier layer. The method further includes removing a portion of the bonding layer to expose at least a portion of the barrier layer and define a fill region, and depositing a second bonding layer over the exposed barrier layer and at least a portion of the fill region. In another embodiment, the barrier layer is not exposed during the removal process.

[0008] According to another embodiment, a method of manufacturing a ceramic substrate structure includes providing a ceramic substrate, forming a bonding layer bonded to a front surface of the ceramic substrate, performing a chemical mechanical polishing (CMP) process to remove a portion of the bonding layer to expose at least a portion of the front surface of the ceramic substrate, and encapsulating the ceramic substrate in a barrier layer. In some embodiments, the barrier layer can include silicon nitride. The front surface of the ceramic substrate can be characterized by an RMS roughness in the range of 50-600 nm, and the barrier layer can be characterized by an RMS roughness in the range of 0.5-2 nm. The front surface of the ceramic substrate can be characterized by a plurality of voids, and the bonding layer can fill the plurality of voids.

[0009]

[0009] Many advantages are achieved by the present invention over the prior art. For example, embodiments of the present invention provide a substrate structure suitable for epitaxial growth, characterized by a coefficient of thermal expansion (CTE) that is substantially matched to the epitaxial layer grown thereon. Matching the thermal expansion properties of the growth substrate to the epitaxial layer reduces stress in the epitaxial layer and / or the engineered substrate. Stress can lead to several types of defects. For example, stress can increase dislocation density in the epitaxial layer, which impairs the electrical and optical properties of the epitaxial layer. Stress can also lead to residual strain in the epitaxial layer or substrate, which can lead to further processing concerns in subsequent steps, such as stress cracking, dislocation glide, slip, bending and warping. Bending and warping of the substrate due to thermal expansion can make the material difficult to handle in automated equipment, limiting the ability to perform additional lithography steps required for device fabrication, substrate cracking, and material creep. In addition, stressed materials reduce the performance life of the device. Stress relaxation and stress-induced crack propagation, dislocation glide, and other lattice movements resulting from thermal mismatch can lead to premature failure with modes ranging from degradation of device performance to fracture or delamination of the devices and device layers in which the devices are fabricated.

[0010] These and other embodiments of the present invention, together with many of its advantages and features, include the following: The invention is explained in more detail in the text below and in connection with the attached drawings. [Brief description of the drawings]

[0011] [Figure 1A] FIG. 1 is a simplified schematic diagram illustrating a designed substrate structure according to one embodiment of the present invention. [Figure 1B] 1 is a simplified flowchart illustrating a method for manufacturing a designed substrate according to one embodiment of the present invention. [Figure 1C] FIG. 1 is a simplified schematic diagram illustrating a designed substrate structure including an epitaxial layer according to one embodiment of the present invention. [Diagram 2] FIG. 2 is a simplified schematic diagram illustrating a designed substrate structure after deposition of a bonding layer according to an embodiment of the present invention. [Figure 3A] FIG. 1 is a simplified schematic diagram illustrating a designed substrate structure after thinning the bonding layer according to an embodiment of the present invention. [Figure 3B] FIG. 2 is a simplified schematic diagram illustrating a designed substrate structure after polishing down to an etch stop layer in accordance with an embodiment of the present invention. [Figure 3C] FIG. 1 is a simplified schematic diagram illustrating a designed substrate structure after redeposition of a bonding layer according to an embodiment of the present invention. [Figure 4] FIG. 2 is a simplified schematic diagram illustrating a designed substrate structure after forming one or more designed layers according to one embodiment of the present invention. [Diagram 5] FIG. 1 is a simplified schematic diagram illustrating a designed substrate structure including a release layer according to one embodiment of the present invention. [Figure 6A] FIG. 2 is a simplified schematic diagram illustrating a polycrystalline ceramic core and planarization material according to one embodiment of the present invention. [Figure 6B] FIG. 2 is a simplified schematic diagram illustrating a polycrystalline ceramic core and planarization material after a CMP process according to an embodiment of the present invention. [Figure 6C] FIG. 2 is a simplified schematic diagram showing a planarized polycrystalline ceramic core encapsulated within a barrier shell according to one embodiment of the present invention. [Figure 6D] FIG. 2 is a simplified schematic diagram showing a planarized polycrystalline ceramic core encapsulated in a barrier shell with an exfoliated single crystal Si layer according to one embodiment of the present invention. [Figure 6E] FIG. 1 is a simplified schematic diagram showing a planarized polycrystalline ceramic core encapsulated within a barrier shell covered with a deposited oxide and an exfoliated single crystal Si layer in accordance with one embodiment of the present invention. [Figure 6F] FIG. 2 is a simplified schematic diagram illustrating the formation of engineered layers on an encapsulated and planarized polycrystalline ceramic core according to one embodiment of the present invention. [Figure 6G]FIG. 1 is a simplified schematic diagram showing a delamination Si layer on top of a designed layer on an encapsulated and planarized polycrystalline ceramic core according to one embodiment of the present invention. [Figure 6H] FIG. 1 is a simplified schematic diagram illustrating the formation of a bonding layer on a designed layer on an encapsulated and planarized polycrystalline ceramic core according to one embodiment of the present invention. [Figure 6I] FIG. 1 is a simplified schematic diagram illustrating the formation of a designed layer-on-layer bonding layer on an encapsulated and planarized polycrystalline ceramic core having a delamination Si layer according to one embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0012]

[0029] Embodiments of the present invention relate to engineered substrate structures. More specifically, the present invention relates to methods and systems suitable for use in epitaxial growth processes. By way of example only, the present invention is applied to methods and systems that provide substrate structures suitable for epitaxial growth, characterized by a coefficient of thermal expansion (CTE) that is substantially matched to the epitaxial layers grown thereon. The methods and techniques can be applied to a variety of semiconductor processing operations.

[0013]

[0030] FIG. 1A is a simplified schematic diagram showing a designed substrate structure according to one embodiment of the present invention. As shown in FIG. 1A, the designed substrate structure shown in FIG. , suitable for a variety of electronic and optical applications. The designed substrate structure includes a core 110 (e.g., an AlN substrate) that can have a coefficient of thermal expansion (CTE) that substantially matches the CTE of epitaxial material grown on the designed substrate structure, e.g., on an exfoliated silicon (111) layer. As discussed more fully herein, the epitaxial material can include other basic semiconductor materials, including silicon layers with different crystal orientations other than (111) silicon, and / or compound semiconductor materials, including gallium nitride (GaN)-based materials. These variations include crystal growth planes, etc. One of ordinary skill in the art would recognize many variations, modifications, and alternatives.

[0014]

[0031] For applications involving the growth of gallium nitride (GaN) based materials (epitaxial layers including GaN based layers), the core 110 may be a polycrystalline ceramic material, for example, polycrystalline aluminum nitride (AlN), which may include a binder material such as yttrium oxide. Other materials may be utilized for the core, including polycrystalline gallium nitride (GaN), polycrystalline aluminum gallium nitride (AlGaN), polycrystalline silicon carbide (SiC), polycrystalline zinc oxide (ZnO), polycrystalline gallium trioxide (Ga2O3), and the like.

[0015]

[0032] The thickness of the core may be on the order of 100-1500 μm, for example 725 μm. The core is encapsulated in an adhesive layer 112 (labeled TEOS), which may be referred to as a shell or encapsulation shell. FIG. 1A, which shows only a central portion of the designed substrate structure and not the ends, illustrates this encapsulation by showing the presence of adhesive layer 112 above and below the core 110, and it will be understood that adhesive layer 112 is also present at the ends of the core 110, which are not shown for clarity. Similarly, the conductive layer 114, second adhesive layer 116, and barrier layer 118 are discussed in detail below, but although the presence of these encapsulation layers above and below the core layer is shown, it will be understood that these layers are present at the ends as well. Those skilled in the art will recognize many variations, modifications, and alternatives.

[0016]

[0033] In one embodiment, adhesion layer 112 comprises a tetraethylorthosilicate (TEOS) oxide layer having a thickness on the order of 1,000 Å. In other embodiments, the thickness of the adhesion layer varies, for example, from 100 Å to 2,000 Å. Although TEOS oxide is utilized for the adhesion layer in some embodiments, other materials (e.g., ceramics, particularly polycrystalline ceramics) that provide adhesion between a subsequently deposited layer and the layer or material below it can also be utilized in accordance with embodiments of the present invention. For example, SiO2 or other silicon oxides (Si x O y) adheres well to ceramic materials and provides a suitable surface for subsequent deposition of, for example, conductive materials. Adhesion layer 112 completely surrounds core 110 in some embodiments, forming a completely encapsulated core, and may be formed using an LPCVD process or other suitable deposition process, which may be compatible with semiconductor processing, particularly polycrystalline or composite substrates and layers. The adhesion layer provides a surface onto which subsequent layers are adhered to form elements of a designed substrate structure.

[0017]

[0034] In addition to using LPCVD processes, spin-on glass / dielectric, furnace-based processes, and the like to form the encapsulating adhesion layer, other semiconductor processes including CVD processes or similar deposition processes can be utilized in accordance with embodiments of the present invention. As an example, a deposition process can be utilized to coat a portion of the core, the core can be turned over, and the deposition process can be repeated to coat additional portions of the core. Thus, while in some embodiments LPCVD techniques are utilized to provide a fully encapsulated structure, other deposition techniques can be utilized depending on the particular application.

[0018]

[0035] A conductive layer 114 is formed surrounding the adhesion layer 112. In one embodiment, the conductive layer is a shell of polysilicon (i.e., polycrystalline silicon) formed surrounding the adhesion layer since polysilicon has poor adhesion to ceramic materials. In an embodiment in which the conductive layer is polysilicon, the polysilicon layer has a thickness of about 500-5,000 Å. For example, it may be 2,500 Å. In some embodiments, the polysilicon layer may be formed as a shell to completely surround the adhesion layer (e.g., TEOS oxide layer), thereby forming a fully encapsulated adhesion layer, and may be formed using an LPCVD process. In other embodiments, as described below, the conductive material may be formed on a portion of the adhesion layer, for example, on the bottom half of the substrate structure. In some embodiments, the conductive material may be formed as a fully encapsulating layer and subsequently removed on one side of the substrate structure.

[0019]

[0036] In one embodiment, the conductive layer 114 may be a polysilicon layer that is doped to provide a highly conductive material, such as a polysilicon layer doped with boron to provide a p-type polysilicon layer. In some embodiments, the doping with boron is 1×10 19 cm -3 From 1×10 20 cm -3 The level of other dopants at different dopant concentrations (e.g., 1×10 16 cm -3 From 5×10 18 cm -3 Dopant concentrations ranging from 0.1 to 100% can be used to provide either n-type or p-type semiconductor materials suitable for use in the conductive layer. One of ordinary skill in the art would recognize many variations, modifications, and alternatives.

[0020]

[0037] The presence of the conductive layer 114 is useful in electrostatically chucking the designed substrate to a semiconductor processing tool, such as a tool having an electrostatic chuck (ESC or e-chuck). The conductive layer allows for quick dechucking after processing in the semiconductor processing tool. In embodiments of the invention, the conductive layer allows for electrical contact with the chuck or capacitive coupling to the electrostatic chuck (ESC or e-chuck) during future processing, including bonding. Thus, embodiments of the invention provide a substrate structure that can be processed in a manner utilized with conventional silicon wafers. Those skilled in the art will recognize many variations, modifications, and alternatives. Additionally, having a substrate structure with high thermal conductivity in combination with an ESD chuck can provide better deposition conditions for subsequent designed and epitaxial layer formation, as well as subsequent device fabrication steps. For example, it can provide a desirable thermal profile that can result in lower stress, more uniform deposition thickness, and better stoichiometry control throughout subsequent layer formation.

[0021]

[0038] A second adhesion layer 116 (e.g., a TEOS oxide layer having a thickness on the order of 1000 Å) is formed surrounding the conductive layer 114. In some embodiments, the second adhesion layer 116 completely surrounds the conductive layer to form a complete encapsulation structure, and may be formed using an LPCVD process, a CVD process, or any other suitable deposition process, including the deposition of a spin-on dielectric.

[0022]

[0039] A barrier layer 118, for example a silicon nitride layer, is formed to surround the second adhesive layer 116. In one embodiment, the barrier layer 118 is a silicon nitride layer with a thickness of about 2,000 Å to 5,000 Å. The barrier layer completely surrounds the second adhesive layer 116 to form a complete encapsulation structure in some embodiments and can be formed using an LPCVD process. In addition to silicon nitride layers, amorphous materials including SiCN, SiON, AlN, SiC, etc. can be utilized as the barrier layer. In some embodiments, the barrier layer is comprised of several sub-layers constructed to form the barrier layer. Thus, the term barrier layer is not intended to mean a single layer or material, but rather to encompass one or more materials stacked together in a composite manner. One skilled in the art would recognize many variations, modifications, and alternatives.

[0023]

[0040] In some embodiments, the barrier layer 118, e.g., a silicon nitride layer, is designed to protect the core 110 from elements present in the core 110, e.g., yttrium (elemental), yttrium oxide (i.e., yttria), oxygen, metallic impurities, other trace elements, etc., to the environment of a semiconductor processing chamber in which the designed substrate may reside, e.g., during a high temperature (e.g., 1,000° C.) epitaxial growth process. Utilizing the encapsulation layers described herein, ceramic materials including polycrystalline AlN designed for non-cleanroom environments can be utilized in semiconductor process flows and cleanroom environments.

[0024]

[0041] Typically, the ceramic material utilized to form the core is fired at a temperature in the range of 1,800°C. This process is expected to remove a significant amount of impurities present in the ceramic material. These impurities may include yttrium, calcium, and other elements and compounds resulting from the use of yttria as a sintering agent. Subsequently, during the epitaxial growth process, which is carried out at much lower temperatures in the range of 800°C to 1100°C, the subsequent diffusion of these impurities would be expected to be insignificant. However, contrary to conventional expectations, the inventors have determined that significant diffusion of elements can occur through the layers of the engineered substrate even during the epitaxial growth process at temperatures much lower than the firing temperature of the ceramic material. Thus, embodiments of the present invention integrate a barrier layer into the engineered substrate structure to prevent this undesired diffusion.

[0025]

[0042] Referring again to FIG. 1A, a bonding layer 120 (e.g., a silicon oxide layer) is deposited on a portion of the barrier layer 118, e.g., on top of the barrier layer, and then used during bonding of a substantially single crystalline layer 125 (e.g., a single crystalline silicon layer, such as an exfoliated silicon (111) layer). The bonding layer 120 may be about 1.5 μm thick in some embodiments. In some embodiments, the thickness of the bonding layer is 20 nm or more for bonding induced void relaxation. In some embodiments, the thickness of the bonding layer is in the range of 0.75 to 1.5 μm.

[0026]

[0043] The substantially single crystalline layer 125 (e.g., exfoliated Si(111)) is suitable for use as a growth layer during an epitaxial growth process to form an epitaxial material. In some embodiments, the epitaxial material may include a GaN layer having a thickness of 2 μm to 10 μm, which may be utilized as one of multiple layers utilized in optoelectronic, RF, and power devices. In one embodiment, the substantially single crystalline layer includes a single crystalline silicon layer that is attached to a bonding layer using a layer transfer process.

[0027]

[0044] FIG. 1B is a simplified flow chart illustrating a method for fabricating an engineered substrate according to one embodiment of the present invention. This method can be utilized to fabricate a substrate that is CTE matched to one or more epitaxial layers grown on the substrate. The method 150 includes forming a support structure by providing a polycrystalline ceramic core (160), which can be a cleaned and inspected aluminum nitride (AlN) substrate. Other polycrystalline ceramic cores can be utilized as described above.

[0028]

[0045] The method also includes encapsulating the polycrystalline ceramic core in a first adhesion layer forming a shell (162) (e.g., a tetraethylorthosilicate (TEOS) oxide shell about 80 nm thick), and encapsulating the first adhesion layer in a conductive shell (164) (e.g., a polysilicon shell about 300 nm thick). The first adhesion layer can be formed as a single layer of TEOS oxide. The conductive shell can be formed as a single layer of polysilicon.

[0029]

[0046] The method also includes encapsulating the conductive shell in a second adhesion layer (166) (e.g., a second TEOS oxide shell having a thickness of about 80 nm) and encapsulating the second adhesion layer in a barrier layer shell (168). The second adhesion layer can be formed as a single layer of TEOS oxide. The barrier layer shell can be formed as a single layer of silicon nitride having a thickness of about 400 nm. Further description of the designed substrate structure is provided in U.S. Provisional Patent Application No. 62 / 350,084, filed June 14, 2016 (Attorney Docket No. 098825-1011030-001100US), the disclosure of which is incorporated herein by reference in its entirety. As described herein, embodiments of the present invention include, but are not limited to, a method for manufacturing a semiconductor device, comprising: x O y , Si x N y , Si x O y N zA variety of materials can be utilized for the adhesion layer and diffusion barrier, including various dielectrics such as Ti, TiW, Ta, and TiN encapsulated in a dielectric. One of ordinary skill in the art would recognize many variations, modifications, and alternatives.

[0030]

[0047] Once the support structure including the core, adhesion layer, conductive layer, and diffusion barrier is formed by processes 160-168, the method further includes depositing a bonding layer (e.g., a PECVD silicon oxide layer) on the support structure (170) and bonding a substantially single crystalline layer, e.g., a single crystalline silicon layer, to the bonding layer (172). Other substantially single crystalline layers can be used, including SiC, sapphire, GaN, AlN, SiGe, Ge, diamond, Ga2O3, ZnO, etc., according to embodiments of the invention. Deposition of the bonding layer can include deposition of a bonding material followed by a planarization process as described herein. In embodiments described below, bonding the substantially single crystalline layer (e.g., a single crystalline silicon layer) to the bonding layer utilizes a layer transfer process, where the layer is a single crystalline silicon layer transferred from a silicon wafer.

[0031]

[0048] With reference to FIG. 1A, the bonding layer 120 can be formed by deposition (e.g., PECVD) of a thick (e.g., 4 μm thick) oxide layer followed by a chemical mechanical polishing (CMP) process that thins the oxide to a thickness of about 1.5 μm (as further described below in connection with FIG. 3A). The thick initial oxide serves to fill voids and surface features present on the support structure that may be present after fabrication of the polycrystalline core and that may continue to be present when the encapsulation layer shown in FIG. 1A is formed. The CMP process provides a substantially flat surface free of voids, particles, or other features that can then be used during a wafer transfer process to bond a substantially single crystalline layer, represented by the exfoliated single crystalline silicon (111) layer shown in FIG. 1A, to the bonding layer. The bonding layer need not be characterized by an atomically flat surface, but should provide a substantially flat surface that supports bonding of a substantially single crystalline layer (e.g., a single crystalline silicon layer) with the desired reliability.

[0032]

[0049] One example of a layer transfer process that can be used to bond a substantially single-crystalline layer to a bonding layer is the bonding of a hydrogen-implanted donor wafer (e.g., a silicon wafer containing a substantially single-crystalline layer (e.g., a single-crystalline silicon layer) implanted to form a cleavage plane) to the bonding layer. The bonded pair is then annealed at an annealing temperature (e.g., 200° C.) for an annealing period (e.g., 4 hours) to cluster the implanted species (e.g., hydrogen) into blisters. After annealing, the donor wafer cracks along the cleavage plane, exfoliating a layer of substantially single-crystalline material onto the bonding layer. As shown in FIG. 1A, a layer of Si (111) is exfoliated onto the PECVD bonding layer. Those skilled in the art will recognize many variations, modifications, and alternatives.

[0033]

[0050] The method illustrated in FIG. 1B may also include smoothing the substantially single crystalline layer (174). Referring to FIG. 1A, the substantially single crystalline layer 125 may be a single crystalline silicon (e.g., a Si(111) layer) that is transferred onto the bonding layer 120. The thickness of the substantially single crystalline layer 125 may be varied to meet various application specifications. Additionally, the crystal orientation of the substantially single crystalline layer 125 may be varied to meet application specifications. Additionally, the doping level and profile in the substantially single crystalline layer 125 may be varied to meet particular application specifications. The smoothing illustrated in association with reference numeral 174 may also include thinning the substantially single crystalline layer as a component of the smoothing process.

[0034]

[0051] In some embodiments, the thickness and surface roughness of the substantially single crystalline layer 125 can be further modified for high quality epitaxial growth. Different device applications may have slightly different specifications for the thickness and surface smoothness of the substantially single crystalline layer 125. The cleaving process releases a substantially single crystalline layer 125 from the bulk single crystalline silicon wafer at the peak of the implanted ion profile. After cleaving, the substantially single crystalline layer 125 can be conditioned or modified in some manner before being utilized as a growth surface for epitaxial growth of other materials, such as gallium nitride.

[0035]

[0052] First, the transferred substantially single crystalline layer 125 may contain a small residual hydrogen concentration and may have some crystal damage from the implant. Therefore, it may be beneficial to remove a thin portion of the transferred substantially single crystalline layer 125 where the crystal lattice is damaged. In some embodiments, the depth of the implantation may be adjusted to be greater than the desired final thickness of the substantially single crystalline layer 125. The additional thickness allows for removal of the thin portion of the transferred substantially single crystalline layer that is damaged, leaving an undamaged portion of the desired final thickness.

[0036]

[0053] Second, it may be desirable to adjust the overall thickness of the substantially monocrystalline layer 125. In general, it is desirable for the substantially monocrystalline layer 125 to be thick enough to provide a high quality lattice template for the subsequent growth of one or more epitaxial layers, but thin enough to be highly conformal. The substantially monocrystalline layer 125 is said to be "conformal" when it is relatively thin, such that its physical properties (e.g., CTE) closely resemble those of the material that surrounds it. The conformance of the substantially monocrystalline layer 125 may be inversely proportional to the thickness of the substantially monocrystalline layer 125. The higher the conformance, the lower the defect density of the epitaxial layer grown on the template, allowing for the growth of a thicker epitaxial layer. In some embodiments, the thickness of the substantially monocrystalline layer 125 may be increased by epitaxially growing silicon on an exfoliated silicon layer.

[0037]

[0054] Third, it may be beneficial to improve the smoothness of substantially single crystalline layer 125. The smoothness of the layer may be related to the total hydrogen dose, the presence of any co-implanted species, and the annealing conditions used to form the hydrogen-based cleaved surface. As described below, the initial roughness resulting from the layer transfer (i.e., cleaving process) may be mitigated by thermal oxidation and oxide stripping.

[0038]

[0055] In some embodiments, removal of the damaged layer and adjustment of the final thickness of the substantially single-crystalline layer 125 can be achieved by thermal oxidation of the top of the exfoliated silicon layer, followed by oxide layer stripping with hydrofluoric (HF) acid. For example, an exfoliated silicon layer with an initial thickness of 0.5 μm can be thermally oxidized to form a silicon dioxide layer with a thickness of about 420 nm. After removing the grown thermal oxide, the remaining silicon thickness in the transfer layer can be about 53 nm. During thermal oxidation, the implanted hydrogen can migrate toward the surface. Thus, the subsequent oxide layer stripping can remove some of the damage. Also, thermal oxidation is typically performed at a temperature of 1000° C. or higher. The high temperature can also repair lattice damage.

[0039]

[0056] The silicon oxide layer formed on top of the substantially single crystalline layer during thermal oxidation can be stripped using HF acid etching. The etch selectivity between silicon oxide and silicon (SiO2:Si) by HF acid can be adjusted by adjusting the temperature and concentration of the HF solution as well as the stoichiometry and density of the silicon oxide. Etch selectivity refers to the etch rate of one material over another. The selectivity of the HF solution can range from about 10:1 to about 100:1 for (SiO2:Si). High etch selectivity can reduce the surface roughness by a similar factor from the initial surface roughness. However, the surface roughness of the resulting substantially single crystalline layer 125 can still be greater than desired. For example, a bulk Si(111) surface can have a root mean square (RMS) surface roughness of less than 0.1 nm as determined by a 2 μm×2 μm atomic force microscope (AFM) scan before additional processing. In some embodiments, the desired surface roughness for epitaxial growth of gallium nitride material on Si(111) is, for example, less than 1 nm, less than 0.5 nm, or less than 0.2 nm over a 30 μm×30 μm AFM scan area. could be.

[0040]

[0057] If the surface roughness of the substantially single crystalline layer 125 after thermal oxidation and oxide layer stripping exceeds the desired surface roughness, additional surface smoothing can be performed. There are several methods to smooth the silicon surface. These methods may include hydrogen annealing, laser trimming, plasma smoothing, and touch polishing (e.g., chemical mechanical polishing or CMP). These methods may include preferential attack of high aspect ratio surface peaks. Thus, high aspect ratio features on the surface can be removed more quickly than low aspect ratio features, thus resulting in a smoother surface.

[0041]

[0058] FIG. 1C is a simplified schematic diagram illustrating a designed substrate structure including an epitaxial layer according to an embodiment of the present invention. As shown in FIG. 1C, a planarization layer 705, which may be a planarized version of the substantially single crystalline layer 125, is utilized in the growth process for the formation of the epitaxial layer 710. The planarization layer 705 may be fabricated using one or more planarization techniques described herein. In some embodiments, the epitaxial layer 710 includes a GaN-based layer having a thickness of 2 μm to 10 μm or thicker, which may be utilized as one of multiple layers utilized in an optoelectronic device.

[0042]

[0059] It should be understood that the specific steps illustrated in FIG. 1B provide a particular method of manufacturing a designed substrate according to one embodiment of the present invention. Other sequences of steps may be performed according to different embodiments. For example, alternative embodiments of the present invention may perform the steps outlined above in a different order. Furthermore, each step illustrated in FIG. 1B may include multiple sub-steps that may be performed in various orders as appropriate for the individual step. Furthermore, additional steps may be added or removed depending on the particular application. Those skilled in the art will recognize numerous variations, modifications, and alternatives.

[0043]

[0060] FIG. 2 is a simplified schematic diagram illustrating a designed substrate structure after deposition of a bonding layer according to an embodiment of the present invention. As shown in FIG. 2, the top surface 121 of the bonding layer 120 (e.g., PECVD oxide) is originally rough, and the surface profile is determined to some extent by the surface roughness of the underlying layers and materials. As discussed with respect to FIG. 1B, the initial thickness of the bonding layer may be on the order of a few microns (e.g., 4 μm) in order for the bonding layer to fill the pores present in the polycrystalline ceramic core 110. The bonding layer may be formed in a single step process or a multi-step process, such as repeated cycles of deposition / removal. As an example, deposition of the bonding layer material may be followed by polishing of the bonding layer to reduce its thickness and increase its planarity. This deposition / polishing cycle may then be repeated several times to obtain a bonding layer having a surface roughness that is less than the surface roughness that characterizes the original polycrystalline ceramic core surface. Furthermore, different materials may be utilized in different cycles, providing a layered structure having multiple materials. Those skilled in the art will recognize many variations, modifications, and alternatives.

[0044]

[0061] 3A is a simplified schematic diagram showing a designed substrate structure after thinning the bonding layer according to one embodiment of the present invention. The inventors have found that heat transfer, and capacitive effects that affect switching speed, etc., can be improved or customized for device applications by thinning the bonding layer (e.g., PECVD oxide layer) from an initial value of a few microns to a value in the range of 100 Å to 1.5 μm.

[0045]

[0062] As shown in FIG. 3A, the CMP process can be used to reduce the thickness of the bonding layer 120. However, when the initial thickness of the bonding layer is on the order of a few microns (e.g., 4 μm), which is adequate for the bonding layer to fill the pores present in the polycrystalline ceramic core, the CMP process cannot smooth out all the defects present in the bonding layer. In addition, the CMP pad conformance, slurry management, and pressing force in various areas on the device can be compromised. Controlling the put-down force presents challenges to achieving planarity across the substrate, thereby providing a smooth, flat bond layer. For example, roll-off at the substrate edges can result in edge film thicknesses that are smaller (i.e., thinner) or larger (i.e., thicker) than the average layer thickness.

[0046]

[0063] Although FIG. 3A shows a flat upper surface 310, in a realistic process flow, the thickness variation of bonding layer 120 is in the range of 4,000 Å, resulting in thickness variations that are a significant percentage of the layer thickness as the layer thickness is reduced to 1.5 μm or less.

[0047]

[0064] 3B is a simplified schematic diagram showing a designed substrate structure after polishing down to an etch stop layer according to an embodiment of the present invention. As shown in FIG. 3B, the CMP process is terminated when the barrier layer 118 (e.g., silicon nitride) is exposed. The hardness of the barrier layer material may be much greater than the relatively soft bonding layer, so the barrier layer material can provide a natural CMP stop layer.

[0048]

[0065] Referring to FIG. 3B, the bonding layer 120 (e.g., PECVD oxide) is thinned by a CMP process using the barrier layer 118 (e.g., LPCVD nitride) as a CMP stop layer. A removal rate difference is induced on the CMP tool, and in combination with a thickness feedback system, the CMP process stops on the barrier (e.g., nitride) layer. Note that in FIG. 3B, the amount of pores present in the polycrystalline core is exaggerated for purposes of illustration. In reality, the relative surface area of ​​the exposed barrier layer (i.e., the coplanar nitride area) is much larger than the surface area of ​​the bonding layer represented by the PECVD oxide.

[0049]

[0066] As shown in FIG. 3B, the top surface 320 of the substrate structure includes regions of bonding layer material 120 (e.g., PECVD oxide) and regions of barrier layer material 118 (e.g., LPCVD nitride). This top surface 320, which is electrically insulating, can provide a suitable bonding surface for bonding a donor wafer as described above. In this example, a monocrystalline silicon layer can be bonded to the assemblage of oxide and nitride regions. The valleys or voids present between adjacent peaks of the polycrystalline ceramic core can be referred to as filled regions 305 because they are filled with the bonding layer material. One of ordinary skill in the art would recognize many variations, modifications, and alternatives.

[0050]

[0067] In some embodiments, rather than using the barrier layer 118 as a CMP stop, an additional CMP stop layer is deposited prior to deposition of the bonding layer. With reference to FIG. 2, the additional CMP stop layer is formed between the barrier layer 118 (e.g., a nitride layer) and the PECVD bonding layer 120. Thus, the CMP process ends with an additional CMP stop layer, thereby protecting the barrier layer from removal or excessive thinning that may impair its barrier properties. The ability of the barrier layer to prevent the diffusion of impurities depends on the thickness and diffusion rate of the barrier layer. If the barrier layer is too thin, the barrier layer may not provide sufficient barrier function.

[0051]

[0068] FIG. 3C is a simplified schematic diagram illustrating a designed substrate structure after redeposition of a bonding layer 320 according to an embodiment of the present invention. As an alternative to the bonding surface shown in FIG. 3B, a thin layer of bonding material can be deposited after the CMP process. Referring to FIG. 3B, after stopping at the barrier layer 118 and using a CMP process to remove the bonding layer material, a thin layer (e.g., 200 Å) of a very uniform bonding material (e.g., PECVD oxide) can be redeposited on the polished structure. The bonding layer 320 can be referred to as the redeposition layer. The surface of the bonding layer after the CMP process shown in FIG. 3B can be relatively flat, since the use of a stop layer (either a barrier layer or an additional CMP stop layer) allows for better control of the surface planarity compared to thinning without a stop layer. The bonding layer 320 conforms to the planarized surface of the bonding layer and adheres to it. Since the surface uniformity of the bonding layer 320 is a percentage of the total thickness of the bonding layer 320, the surface of the thin bonding layer 320 can be quite uniform. Thus, the bonding layer 320 provides a continuous bonding surface with superior surface planarity compared to that achievable by applying CMP to a thick bonding layer without the use of a stop layer. Although PECVD oxide is shown as the bonding material in FIG. 3C, this is not required by the present invention and other materials, such as silicon nitride, can be redeposited. Thus, embodiments of the present invention provide a thin, controllable bonding layer with properties independent of the bonding material utilized to enhance the planarity of the polycrystalline ceramic core. Those skilled in the art will recognize many variations, modifications, and alternatives.

[0052]

[0069] In some embodiments, the CMP stop layer may be the polycrystalline ceramic core 110 (e.g., an AlN material within the core). In these embodiments, the barrier layer and the underlying adhesion and conductive layers are removed to expose the top surface of the core material.

[0053]

[0070] Utilizing the processes as described herein, the increase in planarity from the polycrystalline ceramic core to the redeposited layer 320 can be substantial. For example, in one embodiment, the growth surface of the ceramic substrate can be characterized by an RMS roughness in the range of 50-600 nm RMS for an AFM scan of a 50 μm×50 μm area, which is achievable with conventional wafer polishing techniques. Utilizing the processes described herein, the redeposited layer can be characterized by an RMS roughness in the range of 0.5-2 nm RMS for an AFM scan of a 30 μm×30 μm area, which results in an improvement in surface roughness of 2-3 orders of magnitude. The planarity of the layer before CMP can be as much as 30% of the total thickness of the layer. For a 4 μm layer, this can be 1.2 μm. The planarity of the surface after CMP on the stop layer is typically less than 2%, i.e., the planarity is improved by about 10 times.

[0054]

[0071] 4 is a simplified schematic diagram showing a designed substrate structure after forming one or more designed layers according to an embodiment of the present invention. Starting with the designed substrate structure after thinning the bonding layer as shown in FIG. 3A or FIG. 3B, one or more designed layers, which may include one or more dielectric layers, are formed or deposited on the thin designed substrate structure. As shown in FIG. 4, a designed layer 410 that provides good adhesion to the barrier layer 118 and bonding layer 120 materials (e.g., PECVD oxide) can be deposited to cover the exposed barrier layer portions and the fill area.

[0055]

[0072] The engineered layer can be formed using a variety of materials. By way of example, dielectric materials can include silicon nitride, oxynitride, silicon oxynitride, spin-on glass / dielectric, DLC, combinations thereof, and the like. The thickness of the engineered layer can range from very thin layers on the order of 100 Å-200 Å to thick layers on the order of several microns (e.g., 2 μm), depending on the specific device specifications, including heat transfer, capacitance, and breakdown voltage properties. In some embodiments, rather than a dielectric, a conductive layer comprising a refractory metal is deposited as the engineered layer. In other embodiments, a multi-layer structure, which can include both one or more dielectric layers and one or more conductive layers, is fabricated to provide the desired thermal, mechanical, and electrical properties.

[0056]

[0073] The engineered layer 410 shown in Figure 4 allows for enhanced processing capabilities compared to the use of a bonding layer 320 formed using the same material as bonding layer 120. Thus, the embodiment shown in Figure 4 provides enhanced alternative bonding capabilities compared to the embodiment shown in Figure 3C.

[0057]

[0074] 5 is a simplified schematic diagram illustrating an engineered substrate structure including an exfoliation layer 510 according to one embodiment of the present invention. The structure illustrated in FIG. 5 utilizes one or more engineered layers illustrated in FIG. 4 to provide a bonding interface between the engineered layer and the substantially single crystalline layer 510, which is suitable for exfoliation. It may be a single crystal silicon (111) layer.

[0058]

[0075] The thickness of the exfoliation layer 510 can be varied to meet the specifications of various applications. Additionally, the crystal orientation of the exfoliation layer can be varied to meet the specifications of the application. As an example, the crystal orientation can be controlled to impart strain to subsequent epitaxial layers grown after fabrication of the structure shown in FIG. 5. Additionally, the doping levels and profiles in the exfoliation layer can be varied to meet the specifications of a particular application. It is noted that the exfoliation layer can be integrated with other engineered substrate structures described herein, including the engineered substrate structures shown in FIGS. 1A, 3A, 3B, 3C, and 4.

[0059]

[0076] As an alternative to the process flows and structures described above, some embodiments of the present invention enhance the planarity of the polycrystalline ceramic core prior to deposition of the conductive and barrier layers. Thus, some embodiments provide a surface treatment process for the polycrystalline ceramic core prior to forming the engineered laminates described herein to enhance the planarity of the polycrystalline ceramic core surface prior to forming the conductive, barrier and other layers.

[0060]

[0077] FIG. 6A is a simplified schematic diagram illustrating a polycrystalline ceramic core and planarization material according to one embodiment of the present invention. The polycrystalline ceramic core 110 is shown as an AlN substrate. An adhesion-promoting layer 610 is formed on one or more sides of the polycrystalline ceramic core, and a planarization material 620 (e.g., a PECVD oxide fill layer) is deposited on the adhesion-promoting layer 610. The adhesion-promoting layer can be a TEOS oxide, such as 100 Å to 1,000 Å of TEOS oxide, as discussed herein, or other suitable material. The planarization material 620 can be an oxide, nitride, spin-on glass (SOG), or other suitable material. In some embodiments where the planarization material adheres well to the polycrystalline ceramic core, the adhesion-promoting layer is removed. The thickness of the planarization material is selected to fill voids and surface features present in the polycrystalline ceramic core, and the thickness can be on the order of a few microns. One of ordinary skill in the art would recognize many variations, modifications, and alternatives.

[0061]

[0078] FIG. 6B is a simplified schematic diagram showing the polycrystalline ceramic core and planarization material after a CMP process according to an embodiment of the present invention. After deposition of the planarization material 620, a CMP process is used in which the polycrystalline ceramic core 110 (AlN substrate) becomes the CMP stop, thereby polishing away the excess portion of the planarization material. As shown in FIG. 6B, the presence of the polycrystalline ceramic core material as a CMP stop is in negligible amounts (e.g., only 50 Å to 100 Å of planarization material outside of the voids). This reduction in the amount of oxide or other insulating material increases the thermal conductivity of the completed substrate structure and ultimately the devices fabricated thereon. Because the polycrystalline ceramic core has a high thermal conductivity, reducing the thickness of the oxide or other insulating layer can have a large impact on the overall thermal performance. In some embodiments, a thin dielectric layer (e.g., oxide or nitride) is deposited after completion of the CMP process.

[0062]

[0079] 6C is a simplified schematic diagram showing a planarized polycrystalline ceramic core encapsulated in a barrier shell according to one embodiment of the present invention. A barrier layer 630 (e.g., silicon nitride) is deposited, as shown in FIG. 6C, which encapsulates the polycrystalline ceramic core 110 and can be made from one or more materials including Si3N4, oxynitrides, diamond-like carbon (DLC), other suitable materials, combinations thereof, etc. In one embodiment, an LPCVD process or a suitable furnace process is utilized to completely encapsulate the polycrystalline ceramic core.

[0063]

[0080] A barrier layer 630, such as a silicon nitride layer, is formed surrounding the polycrystalline ceramic core. In one embodiment, the barrier layer is a silicon nitride layer having a thickness of about 2,000 Å to 5,000 Å. The barrier layer is a silicon nitride layer. In some embodiments, the barrier layer completely surrounds the polycrystalline ceramic core, forming a fully encapsulated structure. In addition to silicon nitride layers, amorphous materials including SiCN, SiON, AlN, SiC, etc. can be utilized as the barrier layer. In some embodiments, the barrier layer 630 is comprised of several sub-layers constructed to form the barrier layer. Thus, the term barrier layer is not intended to mean a single layer or material, but rather to encompass one or more materials stacked together in a composite fashion. One of ordinary skill in the art would recognize many variations, modifications, and alternatives.

[0064]

[0081] In some embodiments, the barrier layer 630, e.g., a silicon nitride layer, prevents elements present within the polycrystalline ceramic core, e.g., yttrium (elemental), yttrium oxide (i.e., yttria), oxygen, metallic impurities, other trace elements, etc., from diffusing and / or outgassing into the environment of a semiconductor processing chamber in which the engineered substrate may reside, e.g., during a high temperature (e.g., 1,000° C.) epitaxial growth process. Utilizing the encapsulation layers described herein, polycrystalline AlN-containing ceramic materials designed for non-cleanroom environments can be utilized in semiconductor process flows and cleanroom environments.

[0065]

[0082] FIG. 6D is a simplified schematic diagram illustrating a planarized polycrystalline ceramic core encapsulated in a barrier shell with an exfoliated single crystal silicon layer according to an embodiment of the present invention. An exfoliation layer 640, e.g., a single crystal silicon layer, is formed on a barrier layer 630, e.g., a silicon nitride layer. The thickness of the exfoliation layer 640 can be varied to meet various application specifications. Additionally, the crystal orientation of the exfoliation layer 640 can be varied to meet application specifications. Additionally, the doping level and profile in the exfoliation layer can be varied to meet specific application specifications. The exfoliated single crystal silicon layer (e.g., exfoliated Si(111)) is suitable for use as a growth layer during an epitaxial growth process to form an epitaxial material. In some embodiments, the epitaxial material can include a GaN layer having a thickness of 2 μm to 10 μm, which can be utilized as one of multiple layers utilized in optoelectronic, RF, and power devices. Although a single crystal silicon layer is illustrated in FIG. 6D, other substantially single crystal layers can be utilized in accordance with embodiments of the present invention.

[0066]

[0083] FIG. 6E is a simplified schematic diagram showing a planarized polycrystalline ceramic core encapsulated in a barrier shell covered with a deposited oxide and an exfoliated single crystal silicon layer according to one embodiment of the present invention. In this embodiment, an oxide layer 642 (e.g., a silicon oxide layer) is deposited on a barrier layer 630. The oxide layer 642 can function as a bonding interface between the barrier layer 630, which can be a single crystal silicon layer, and the exfoliation layer 640. According to some embodiments, the oxide layer can have a thickness of several hundred angstroms. Although a single crystal silicon layer is shown in FIG. 6E, other substantially single crystal layers can be utilized according to embodiments of the present invention.

[0067]

[0084] Figure 6F is a simplified schematic diagram illustrating the formation of engineered layers on an encapsulated and planarized polycrystalline ceramic core according to one embodiment of the present invention. Figure 6F illustrates the deposition of a conductive layer 650 for the chuck, including a metal layer (e.g., W, Ti, etc.), a polysilicon layer, combinations thereof, etc. In addition to the conductive layer, a thermal management layer 652 (e.g., DLC, SiON, silicon nitride, etc.) can be deposited to provide high thermal conductivity across the substrate.

[0068]

[0085] In FIG. 6F, only the barrier layer 630 is shown encapsulating the polycrystalline ceramic core, but this is not required for the invention. Other layers, including conductive layers and thermal management layers, can be formed as a shell. In some embodiments, a conductive layer 650 is formed on the bottom or back surface 651 of the substrate structure as appropriate for the chuck, and a thermal management layer is formed on the top or front surface of the substrate structure to laterally conduct heat generated by the device. Thus, the layers are encapsulated. Whether formed as an inlaid shell or not, the location of the layers relative to the polycrystalline ceramic core may be varied according to embodiments of the present invention. Additionally, adhesion promoting layers and other suitable layers may be inserted as appropriate for a particular application.

[0069]

[0086] FIG. 6G is a simplified schematic diagram showing an exfoliated Si layer 654 overlying the engineered layers on an encapsulated and planarized polycrystalline ceramic core according to one embodiment of the present invention. The thickness of the exfoliated layer 654 can be varied to meet various application specifications. Additionally, the crystal orientation of the exfoliated layer can be varied to meet application specifications. Additionally, the doping level and profile in the exfoliated layer can be varied to meet specific application specifications. As an example, an exfoliated single crystal silicon layer (e.g., exfoliated Si(111)) is suitable for use as a growth layer during an epitaxial growth process to form an epitaxial material. In some embodiments, the epitaxial material (not shown) can include a GaN layer having a thickness of 2 μm to 10 μm, which can be utilized as one of multiple layers utilized in optoelectronic, RF, and power devices. Although a single crystal silicon layer is illustrated in FIG. 6G, other substantially single crystal layers can be utilized in accordance with embodiments of the present invention.

[0070]

[0087] Figure 6H is a simplified schematic diagram illustrating the formation of a bonding layer 660 on the engineered layers on the encapsulated and planarized polycrystalline ceramic core according to one embodiment of the present invention. To provide a suitable bonding surface when the engineered layers (e.g., conductive layer 650 and thermal management layer 652) shown in Figure 6F are not suitable for bonding, a layer of silicon oxide (e.g., 10 nm to 20 nm of PECVD oxide), other dielectric, or other suitable bonding material can be deposited as bonding layer 660 to facilitate bonding. Alternatively, the oxide can be on a donor wafer.

[0071]

[0088] The layers shown in FIG. 6H can be modified in several ways, including the order of deposition (e.g., conductive / thermal / bonding or thermal / conductive / bonding), a barrier shell can be formed after deposition of one or more conductive and thermal layers, etc. In some embodiments, one or more layers are removed from the substrate structure. Additionally, each layer can include sublayers. Although the conductive and thermal layers are shown on only one side of the substrate, they can be formed on the other side depending on the particular application. One of ordinary skill in the art would recognize many variations, modifications, and alternatives.

[0072]

[0089] FIG. 6I is a simplified schematic diagram illustrating the formation of a bond layer 660 on an engineered layer on an encapsulated and planarized polycrystalline ceramic core with an exfoliation layer 670 (e.g., Si) thereon, according to an embodiment of the present invention. The thickness of the exfoliation layer can be varied to meet various application specifications. Additionally, the crystal orientation of the exfoliation layer 670 can be varied to meet application specifications. Additionally, the doping level and profile in the exfoliation layer can be varied to meet specific application specifications. The exfoliated single crystal silicon layer (e.g., exfoliated Si(111)) is suitable for use as a growth layer during an epitaxial growth process to form an epitaxial material. In some embodiments, the epitaxial material (not shown) can include a GaN layer having a thickness of 2 μm to 10 μm, which can be utilized as one of multiple layers utilized in optoelectronic, RF, and power devices. Although a single crystal silicon layer is illustrated in FIG. 6I, other substantially single crystal layers can be utilized in accordance with embodiments of the present invention.

[0073]

[0090] It is also understood that the examples and embodiments described herein are for illustrative purposes only, and that various modifications or changes in light thereof will be suggested to those skilled in the art and are to be included within the spirit and scope of this application and the appended claims.

Claims

1. 1. A method for manufacturing a substrate structure, the method comprising the steps of: providing a ceramic substrate having a front surface characterized by a plurality of voids and comprising a polycrystalline material; encapsulating the ceramic substrate in a barrier layer defining valleys corresponding to the plurality of voids; forming a bonding layer comprising a bonding layer material and bonded to the barrier layer on the front side of the ceramic substrate; removing a portion of the bonding layer to expose at least a portion of the barrier layer and define a filled region in the valleys corresponding to the plurality of voids, the filled region being filled with the bonding layer material; depositing a second bonding layer over the exposed barrier layer and the at least a portion of the fill region; A method comprising:

2. The method of claim 1 , wherein the ceramic substrate comprises polycrystalline aluminum nitride.

3. The method of claim 1 , wherein removing the portion of the bonding layer comprises a chemical mechanical polishing (CMP) process.

4. The method of claim 1 , wherein the barrier layer comprises silicon nitride.

5. the front surface of the ceramic substrate is characterized by an RMS roughness in the range of 50 to 600 nm; The method of claim 1 , wherein the second bonding layer is characterized by an RMS roughness in the range of 0.5 to 5 nm.

6. The method of claim 1 , wherein the bonding layer comprises silicon oxide and the second bonding layer comprises a silicon oxide layer having a thickness between 100 nm and 1000 nm.

7. The method of claim 1 , further comprising, after removing the portion of the bonding layer, forming a second barrier shell encapsulating the exposed barrier layer and the fill region.

8. bonding a substantially single crystalline layer to the second bonding layer, the substantially single crystalline layer characterized by a first surface roughness; treating the substantially single crystalline layer to form a growth surface characterized by a second surface roughness that is less than the first surface roughness; forming an epitaxial layer bonded to the growth surface; The method of claim 1 further comprising:

9. 1. A method for manufacturing a substrate structure, the method comprising the steps of: providing a ceramic substrate having a front surface characterized by a plurality of ridges and including a polycrystalline material; forming a bonding layer comprising a bonding layer material and bonded to the front surface of the ceramic substrate; performing a chemical mechanical polishing (CMP) process to remove portions of the bonding layer to expose at least a portion of the front surface of the ceramic substrate and define filled regions between adjacent ones of the peaks on the front surface of the ceramic substrate filled with the bonding layer material; encapsulating the ceramic substrate in a barrier layer; A method comprising:

10. The method of claim 9 further comprising depositing an adhesion promoting layer between the front surface of the ceramic substrate and the bonding layer.

11. The method of claim 9 , wherein the ceramic substrate comprises polycrystalline aluminum nitride.

12. The method of claim 9 , further comprising depositing a conductive layer coupled to at least a portion of the barrier layer.

13. The method of claim 9 , further comprising depositing a thermally conductive layer coupled to at least a portion of the barrier layer.

14. 1. A method for manufacturing a substrate structure, the method comprising the steps of: providing a ceramic substrate having a front surface characterized by a plurality of voids and comprising a polycrystalline material; forming a bonding layer comprising a bonding layer material and bonded to the front surface of the ceramic substrate; removing a portion of the bonding layer to expose at least a portion of the front surface of the ceramic substrate and define a filled region in the plurality of voids filled with the bonding layer material; encapsulating the ceramic substrate and the bonding layer in a barrier layer; forming a substantially monocrystalline gallium oxide layer bonded to said barrier layer; A method comprising:

15. forming an adhesive layer bonded to the front surface of the ceramic substrate prior to forming the bonding layer; The method of claim 14 , wherein the bonding layer is bonded to the front surface of the ceramic substrate via the adhesive layer.

16. The method of claim 14 , wherein the ceramic substrate comprises aluminum nitride.

17. The method of claim 14 , wherein the barrier layer comprises silicon nitride.

18. 15. The method of claim 14, wherein the substantially single crystalline gallium oxide layer comprises an exfoliated single crystalline gallium oxide layer.

19. 15. The method of claim 14, further comprising an epitaxial layer coupled to the substantially single crystalline gallium oxide layer.

20. The method of claim 19 , wherein the epitaxial layer comprises an epitaxial III-V layer.

Images