Comparator circuit and counting circuit

Abstract

To classify a difference voltage between a first input voltage and a second input voltage into three levels or more and detect it.SOLUTION: Current generation circuits (113 to 115) generate first current (IA1) passing through a first node according to a difference voltage between two input voltages (VREF, VFB). First and second output circuits (153, 152) generate first and second output signals based on the voltages at the first and second nodes (163 and 162). An insertion transistor (141) is provided between the first and second nodes. In a process of the voltage change at the first node based on the change of the first current resulting from the change of the difference voltage, the logical value of the first output signal is inverted. The first current is changed by the amount of second current, by generating the second current between the first and second nodes based on the change of the first current resulting from the change of the difference voltage. The logical value of the second output signal is inverted in a process in which the voltage of the second node changes based on the change of the second current resulting from the change of the difference voltage.SELECTED DRAWING: Figure 15

Description

[Technical field]

[0001] The present disclosure relates to a comparison circuit and a counting circuit. [Background technology]

[0002] A comparator circuit that detects the relationship between the levels of a first input voltage and a second input voltage is incorporated into various functional circuits. For example, a comparator circuit is used in a switching power supply device (see Patent Document 1 below). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Patent No. 7058326

[0004] [overview] The usefulness of the comparison circuit increases if it is possible to detect the difference between the first input voltage and the second input voltage by classifying it into three or more stages, rather than simply detecting which of the first input voltage and the second input voltage is higher.

[0005] A comparison circuit according to the present disclosure is a comparison circuit configured to generate a plurality of output signals corresponding to a differential voltage between a first input voltage and a second input voltage, each output signal being a binary signal, the plurality of output signals including a first output signal and a second output signal, the comparison circuit including a current generating circuit configured to generate a first current passing through a first node and corresponding to the differential voltage, a first output circuit configured to generate the first output signal based on a voltage of the first node, a second output circuit configured to generate the second output signal based on a voltage of a second node, and an insertion transistor inserted between the first node and the second node, the first output circuit being configured to be biased in a predetermined direction, The logical value of the first output signal is inverted during the process in which the voltage of the first node changes based on the change in the first current associated with the change in the differential voltage, and the current generating circuit changes the first current by the amount of the second current by generating a second current between the first node and the second node via the insertion transistor based on the change in voltage of the first node associated with the change in the differential voltage in the predetermined direction, and when the second current is generated, the second current changes with the change in the differential voltage in the predetermined direction, and the second output circuit inverts the logical value of the second output signal during the process in which the voltage of the second node changes based on the change in the second current associated with the change in the differential voltage in the predetermined direction. [Brief description of the drawings]

[0006] [Figure 1] FIG. 1 is an overall configuration diagram of a power supply device according to an embodiment of the present disclosure. [Diagram 2] FIG. 2 is a timing chart of switching control of the power supply device according to an embodiment of the present disclosure. [Diagram 3] FIG. 3 is a partial configuration diagram of the power supply control device according to an embodiment of the present disclosure. [Figure 4] FIG. 4 is a diagram illustrating the operation of the circuit shown in FIG. 3 according to an embodiment of the present disclosure. [Diagram 5] FIG. 5 is a diagram showing an error correction circuit according to a first reference configuration. [Figure 6]FIG. 6 is a diagram illustrating the operation of the first reference configuration when the load varies. [Figure 7] FIG. 7 is a diagram showing an error correction circuit according to the second reference configuration. [Figure 8] FIG. 8 is a diagram illustrating the operation of the second reference configuration when the load varies. [Figure 9] FIG. 9 is a diagram showing an error correction circuit according to the second reference configuration. [Figure 10] FIG. 10 is a diagram illustrating an error correction circuit according to an embodiment of the present disclosure. [Figure 11] FIG. 11 is a diagram illustrating the operation of a comparison circuit provided in an error correction circuit according to an embodiment of the present disclosure. [Figure 12] FIG. 12 is a configuration diagram of a comparison circuit according to a first example of an embodiment of the present disclosure. [Figure 13] FIG. 13 is a diagram illustrating the operation of a Schmitt inverter according to a first example belonging to an embodiment of the present disclosure. [Figure 14] FIG. 14 is a diagram showing one of four states in a comparator circuit according to a first example of an embodiment of the present disclosure. [Figure 15] FIG. 15 is a diagram showing one of four states in a comparator circuit according to a first example of an embodiment of the present disclosure. [Figure 16] FIG. 16 is a diagram showing one of four states in a comparator circuit according to a first example of an embodiment of the present disclosure. [Figure 17] FIG. 17 is a diagram showing one of four states in a comparator circuit according to a first example of an embodiment of the present disclosure. [Figure 18] FIG. 18 is a configuration diagram of a comparison circuit according to a second embodiment of the present disclosure. [Figure 19] FIG. 19 is a diagram showing one of four states in a comparator circuit according to a second example of the embodiment of the present disclosure. [Figure 20] FIG. 20 is a diagram showing one of four states in a comparator circuit according to a second example of the embodiment of the present disclosure. [Figure 21]FIG. 21 is a diagram showing one of four states in a comparator circuit according to a second example of the embodiment of the present disclosure. [Figure 22] FIG. 22 is a diagram showing one of four states in a comparator circuit according to a second example of the embodiment of the present disclosure. [Diagram 23] FIG. 23 is a configuration diagram of a comparison circuit according to a third example of the embodiment of the present disclosure. [Figure 24] FIG. 24 is a diagram showing one of four states in a comparator circuit according to a third example of an embodiment of the present disclosure. [Diagram 25] FIG. 25 is a diagram showing one of four states in a comparator circuit according to a third example of the embodiment of the present disclosure. [Figure 26] FIG. 26 is a diagram showing one of four states in a comparator circuit according to a third example of an embodiment of the present disclosure. [Figure 27] FIG. 27 is a diagram showing one of four states in a comparator circuit according to a third example of an embodiment of the present disclosure. [Figure 28] FIG. 28 is a waveform diagram showing the operation of a power supply device when the load current increases suddenly according to a fourth example belonging to an embodiment of the present disclosure. [Figure 29] FIG. 29 is a waveform diagram showing the operation of the power supply device relating to the occurrence and elimination of a ground fault according to the first reference configuration. [Diagram 30] FIG. 30 is a waveform diagram showing the operation of the power supply device relating to the occurrence and elimination of a ground fault according to a fifth example belonging to an embodiment of the present disclosure. [Diagram 31] FIG. 31 is a configuration diagram of a comparison circuit according to a sixth embodiment of the present disclosure.

[0007] [Detailed Description] Hereinafter, examples of embodiments of the present disclosure will be specifically described with reference to the drawings. In each of the drawings, the same parts are given the same reference numerals, and duplicated descriptions of the same parts are generally omitted. In this specification, for the sake of simplicity, by writing a symbol or code referring to information, signal, physical quantity, functional part, circuit, element, or part, the name of the information, signal, physical quantity, functional part, circuit, element, or part corresponding to the symbol or code may be omitted or abbreviated.

[0008] First, some terms used in the description of the embodiments of the present disclosure will be explained. Ground refers to a reference conductive part having a reference potential of 0V (zero volts), or refers to the potential of 0V itself. The reference conductive part may be formed using a conductor such as a metal. The potential of 0V may also be called ground potential. In the embodiments of the present disclosure, a voltage shown without a particular reference represents a potential seen from ground.

[0009] A level refers to a level of potential, and for any given signal or voltage, a high level has a higher potential than a low level. For any given signal or voltage, a transition from a low level to a high level is called a rising edge, and a transition from a high level to a low level is called a falling edge.

[0010] For any transistor configured as a FET (field effect transistor) including a MOSFET, the on state refers to a state in which the drain and source of the transistor are conductive, and the off state refers to a state in which the drain and source of the transistor are non-conductive (cut-off state). The same applies to transistors not classified as FETs. Unless otherwise specified, a MOSFET is understood to be an enhancement type MOSFET. MOSFET is an abbreviation for "metal-oxide-semiconductor field-effect transistor". In addition, unless otherwise specified, the backgate of any MOSFET can be considered to be shorted to the source.

[0011] Any switch can be constituted by one or more FETs (field effect transistors). When a certain switch is in the on state, conduction occurs between both ends of the switch, while when a certain switch is in the off state, non-conduction occurs between both ends of the switch.

[0012] For any transistor or switch, the period during which the transistor or switch is in the on state is referred to as the on period, and the period during which the transistor or switch is in the off state is referred to as the off period. Hereinafter, for any transistor or switch, the on state and the off state may also be simply expressed as on and off. For any transistor or switch, the transition from the off state to the on state may be expressed as turn-on, and the transition from the on state to the off state may be expressed as turn-off.

[0013] For any signal having a high-level or low-level signal level, the period during which the level of the signal is high is referred to as the high-level period, and the period during which the level of the signal is low is referred to as the low-level period.

[0014] Regarding the connection between a plurality of parts forming a circuit, such as any circuit element, wiring (line), node, etc., unless otherwise specified, it may be understood to refer to an electrical connection.

[0015] When any two voltages to be compared are voltage v1 and v2, "v1>v2" represents that voltage v1 is higher than voltage v2, and "v1<v2" represents that voltage v1 is lower than voltage v2. The same applies to other expressions including physical quantities other than voltage.

[0016] FIG. 1 shows a schematic configuration diagram of a power supply device 1 according to an embodiment of the present disclosure. The power supply device 1 in FIG. 1 includes a power supply control device 10 and a plurality of discrete components externally connected to the power supply control device 10. The plurality of discrete components include a coil L1 as an output coil, a capacitor C1 as an output capacitor, and resistors R1 and R2 as feedback resistors. The power supply device 1 receives an input voltage V supplied from a voltage source VSIN More desired output voltage V OUT The output terminal TM is a step-down switching power supply device (DC / DC converter) that generates a OUT to the output voltage V OUT That is, the output terminal TM OUT The voltage at is the output voltage V OUT The output voltage V OUT is the output terminal TM OUT The output is supplied to a load (not shown) connected to the output terminal TM OUT The current supplied to the load through the load current I LD The load current I LD is also the output current of the power supply device 1.

[0017] Input voltage V IN and the output voltage V OUT is a positive DC voltage, and the output voltage V OUT is the input voltage V IN For example, the input voltage V IN is 12V, the output voltage V can be set to a desired positive voltage value less than 12V (e.g., 3.3V or 5V) by adjusting the resistance values ​​of resistors R1 and R2. OUT can be stabilized.

[0018] The power supply control device 10 is an electronic component including a semiconductor chip having a semiconductor integrated circuit formed on a semiconductor substrate, a housing (package) that houses the semiconductor chip, and a plurality of external terminals exposed from the housing to the outside of the power supply control device 10. The power supply control device 10 is formed by sealing the semiconductor chip in a housing (package) made of resin. In FIG. 1, only an input terminal TM1, a switch terminal TM2, a ground terminal TM3, and a feedback terminal TM4 are shown as some of the plurality of external terminals provided in the power supply control device 10, but other external terminals (e.g., an enable terminal, a power good terminal, and a boot terminal) are also provided in the power supply control device 10. The output stage MM, the set circuit 11, the reset circuit 12, and the controller 13 shown in FIG. 1 are configured with semiconductor integrated circuits.

[0019] The external configuration of the power supply control device 10 will be described. An input voltage V IN is supplied to the input terminal TM1. The switch terminal TM2 and the output terminal TM OUT That is, one end of the coil L1 is connected to the switch terminal TM2, and the other end of the coil L1 is connected to the output terminal TM OUT Also, the output terminal TM OUT is connected to ground via a capacitor C1. Furthermore, the output terminal TM OUT is connected to one end of resistor R1, and the other end of resistor R1 is connected to ground via resistor R2. A feedback voltage V FB The connection node between resistors R1 and R2 is connected to feedback terminal TM4, which generates a feedback voltage V FB is input to the feedback terminal TM4. The resistors R1 and R2 may be built into the power supply control device 10, in which case the feedback terminal TM4 is a node within the power supply control device 10. The ground terminal TM3 is connected to ground.

[0020] The current flowing through the coil L1 is called the coil current IL. OUT The coil current IL flowing toward the input terminal has a positive polarity, and the coil current IL flowing in the opposite direction has a negative polarity.

[0021] The following describes the internal configuration of the power supply control device 10. The power supply control device 10 includes an output stage MM, a set circuit 11, a reset circuit 12, and a controller 13.

[0022] The output stage MM includes transistors MH and ML configured as N-channel MOSFETs. The transistors MH and ML are a pair of switching elements connected in series between the input terminal TM1 and the ground terminal TM3 (in other words, ground). The transistors MH and ML are switched to drive the input voltage V IN is switched, and a square-wave switch voltage V SWThe transistor MH is provided on the higher potential side than the transistor ML. Specifically, the drain of the transistor MH is connected to the input voltage V IN It is connected to the input terminal TM1, which is the application terminal of the input voltage V IN The source of transistor MH and the drain of transistor ML are commonly connected to switch terminal TM2. The source of transistor ML is connected to ground terminal TM3 (and therefore to ground). However, a resistor for current detection may be inserted between the source of transistor ML and ground terminal TM3.

[0023] The transistor MH functions as an output element (output transistor), and the transistor ML functions as a rectifier element (synchronous rectifier transistor). In the switching drive of the output stage MM, the output element (MH) and the rectifier element (ML) are alternately turned on and off. The coil L1 and the capacitor C1 generate a square-wave-shaped switch voltage V SW is rectified and smoothed to produce the output voltage V OUT The resistors R1 and R2 form a rectifying and smoothing circuit that generates the output voltage V OUT By dividing the output voltage V OUT Feedback voltage V according to FB A feedback voltage generating circuit is formed to generate the feedback voltage V FB is the output voltage V OUT is proportional to the output voltage V OUT As the feedback voltage V FB The output voltage V OUT The feedback voltage V FB In any case, the feedback voltage V FB is the output voltage V OUT The voltage depends on

[0024] Gate signals GH and GL are supplied to the gates of the transistors MH and ML as drive signals, respectively, and the transistors MH and ML are turned on and off in response to the gate signals GH and GL. When the gate signal GH is at a high level, the transistor MH is turned on, and when the gate signal GH is at a low level, the transistor MH is turned off. Similarly, when the gate signal GL is at a high level, the transistor ML is turned on, and when the gate signal GL is at a low level, the transistor ML is turned off. Basically, the transistors MH and ML are turned on and off alternately, but both the transistors MH and ML may be maintained in an off state. The transistors MH and ML are not turned on at the same time. At least one of the output element (MH) and the rectifier element (ML) may be provided outside the power supply control device 10. The entire output stage MM may be provided outside the power supply control device 10.

[0025] When the transistor MH is on, the coil current IL flows through the channel (between the drain and source) of the transistor MH. When the transistor MH is off, the coil current IL flows through the channel of the transistor ML or the parasitic diode of the transistor ML. Figure 2 shows the waveforms of several signals in the power supply control device 10 and the state changes of the transistors MH and ML.

[0026] The set circuit 11 has an oscillation circuit and generates a predetermined frequency f PWM A square wave signal having a frequency f is generated and output as the signal SET. The signal SET and a signal RST described later alternate between a high level and a low level. The duty of the signal SET is arbitrary. Here, the signal SET has a low level in principle, and a square wave signal having a frequency f PWM It is assumed that the signal has a high level for a short period of time at intervals equal to the reciprocal of this (see Figure 2).

[0027] The feedback voltage V FB and the reference voltage V REF is input. Reference voltage V REFhas a predetermined positive DC voltage value. The input voltage V IN Based on the reference voltage V REF The reset circuit 12 generates a feedback voltage V FB and the reference voltage V REF At this time, the reset circuit 12 also references information on the coil current IL to generate the signal RST. The reset circuit 12 sets the level of the signal RST to a low level in principle, and outputs the feedback voltage V FB , reference voltage V REF The level of the signal RST is set to high at a timing based on the coil current IL. In the example of Fig. 2, the signal RST is set to high for only a very short time. At least, the signals SET and RST are not set to high at the same time.

[0028] Signals SET and RST are input to the controller 13. The controller 13 generates gate signals GH and GL in response to the signals SET and RST. The controller 13 supplies the gate signals GH and GL to the gates of the transistors MH and ML to control the on / off states of the transistors MH and ML, respectively, thereby outputting a signal from the output terminal TM OUT to the desired output voltage V OUT Causes the following to occur.

[0029] Specifically, in response to a rising edge of the signal SET, the controller 13 generates a rising edge at the gate GH and a falling edge at the gate signal GL to turn on the transistor MH and turn off the transistor ML. In response to a rising edge of the signal RST, the controller 13 generates a falling edge at the gate GH and a rising edge at the gate signal GL to turn off the transistor MH and turn on the transistor ML. However, when switching the states of the transistors MH and ML, a dead time during which both the transistors MH and ML are turned off may be provided to avoid the transistors MH and ML being turned on simultaneously.

[0030] Although not specifically shown, the power supply control device 10 has an input voltage V IN An internal power supply circuit is provided that generates an internal power supply voltage based on the input voltage V IN Or it is driven based on the internal power supply voltage. Also, the gate signal GL is a signal based on the ground potential, whereas the gate signal GH is a signal based on the potential of the switch terminal TM2. The low level gate signal GH has the potential of the switch terminal TM2, and the high level gate signal GH is a predetermined voltage higher than the potential of the switch terminal TM2. Here, the predetermined voltage is higher than the gate threshold voltage of the transistor MH. A well-known bootstrap circuit (not shown) can be used to generate a boost power supply for generating the gate signal GH. The transistor MH may be configured as a P-channel MOSFET, in which case a boost power supply is not required.

[0031] As a modification, a diode rectification method may be adopted in the power supply device 1. In this case, a synchronous rectification diode having an anode connected to the ground terminal TM3 and a cathode connected to the switch terminal TM2 is provided as a rectification element in place of the transistor ML in the power supply device 1. In this case, only the output element (MH) is turned on and off in the switching drive of the output stage MM.

[0032] Also, while it is assumed here that the power supply device 1 is a step-down switching power supply device, the power supply device 1 may be configured as a step-up, step-up / step-down or inverting switching power supply device.

[0033] The configuration of a circuit for generating the signal RST is shown in Fig. 3. The components of the reset circuit 12 (see also Fig. 1) include an error amplifier 31, a current detection circuit 32, an information synthesis circuit 33, an information retention circuit 34, a ramp circuit 35, an adder 36, and a PWM comparator 37.

[0034] The error amplifier 31 is a current output type transconductance amplifier. The error amplifier 31 has an inverting input terminal and a non-inverting input terminal. A reference voltage VREF is input, and the feedback voltage V FB The error amplifier 31 has a first output terminal connected to the line WP and a second output terminal connected to the line WN. The error amplifier 31 outputs a feedback voltage V FB and the reference voltage V REF The error amplifier 31 generates current signals IP and IN according to the difference between these, and outputs the current signal IP to the wiring WP and the current signal IN to the wiring WN. The positive current signal IP is a current that flows from the error amplifier 31 toward the wiring WP, and the negative current signal IP is a current that flows from the wiring WP into the error amplifier 31. Similarly, the positive current signal IN is a current that flows from the error amplifier 31 toward the wiring WN, and the negative current signal IN is a current that flows from the wiring WN into the error amplifier 31.

[0035] The current signals IP and IN are REF =V FB ", the current signals IP and IN have the same direction and magnitude (i.e., "IN=IP"). At this time, the current signals IP and IN may both be zero, may be positive current signals having the same magnitude, or may be negative current signals having the same magnitude. The current signal IP is "V REF >V FB ", the absolute value of their difference |V REF -V FB The larger the |, the larger the positive direction becomes, and “V REF <V FB ", the absolute value of their difference |V REF -V FB The larger the |, the larger the negative voltage. On the other hand, the current signal IN is REF >V FB ", the absolute value of their difference |V REF -V FB The larger the |, the more negative the V REF <V FB ", the absolute value of their difference |V REF -V FB The larger the |, the larger the positive direction. REF >VFB "When "IP-IN>0", "V REF <V FB ", then "IP-IN<0".

[0036] The current detection circuit 32 has a switch 32a and a resistor 32b, and obtains current information of the coil L1 by detecting the current flowing through the transistor ML during the on-period of the transistor ML. The current information of the coil L1 indicates the value of the coil current IL. The current flowing through the transistor ML during the on-period of the transistor ML passes through the coil L1 and is therefore equal to the coil current IL. A first end of the switch 32a is connected to the drain of the transistor ML. A second end of the switch 32a is connected to the first end of the resistor 32b. A second end of the resistor 32b is connected to the source of the transistor ML. The switch 32a is turned on and off together with the transistor ML in response to a gate signal GL. That is, the switch 32a is on during the on-period of the transistor ML, and the switch 32a is off during the off-period of the transistor ML. Therefore, during the on-period of the transistor ML, a sense signal I is output as current information of the coil L1. SNS is developed across resistor 32b. The sense signal I SNS is expressed as the product of the coil current IL and the on-resistance RonL of the transistor ML. The sense signal I SNS is transmitted to the information synthesis circuit 33. During the off-period of the transistor ML, the switch 32a is turned off, so that the high-level switch voltage V SW is never transmitted to the information synthesis circuit 33.

[0037] In addition, the current detection circuit 32 may obtain current information of the coil L1 by detecting the voltage between both ends of a sense resistor connected in series to the transistor ML, instead of the drain-source voltage of the transistor ML, or by detecting the drain-source voltage of a current detection transistor connected in parallel to the transistor ML.

[0038] The information combining circuit 33 combines the information acquired by the error amplifier 31 and the information acquired by the current detection circuit 32. This combination generates a differential error signal on the wires WP and WN. The differential error signal is made up of an error signal ERRP generated on the wire WP and an error signal ERRN generated on the wire WN.

[0039] The information synthesis circuit 33 has resistors 33a and 33b. A first terminal of the resistor 33a is connected to the wiring WP, and a second terminal of the resistor 33a is connected to a first output terminal of the current detection circuit 32. A first terminal of the resistor 33b is connected to the wiring WN, and a second terminal of the resistor 33b is connected to a second output terminal of the current detection circuit 32. A first output terminal of the current detection circuit 32 is connected to a connection node between the switch 32a and the resistor 32b, and a second output terminal of the current detection circuit 32 is connected to a ground terminal TM3. Therefore, during the on-period of the transistor ML, the sense signal I SNS is applied between the second end of resistor 33a and the second end of resistor 33b. Here, the sense signal I SNS has the potential of the second end of resistor 33a seen from the potential of the second end of resistor 33b.

[0040] The resistors 33a and 33b have the same resistance value, and the resistance value of the resistors 33a and 33b is represented by R. Then, during the ON period of the transistor ML, the error signals ERRP and ERRN are expressed as "ERRP=IP×R+I SNS " and "ERRN = IN × R". If "ΔI = IP-IN", then during the on-period of the transistor ML, "ERRP-ERRN = 2·ΔI × R + I SNS = 2 · ΔI × R - IL · RonL ". The first term on the right-hand side (2 · ΔI × R) is voltage feedback information acquired by the error amplifier 31, and the second term on the right-hand side (IL · RonL) is current feedback information acquired by the current detection circuit 32.

[0041] The data holding circuit 34 includes a sample-and-hold circuit 34a connected to the wiring WP and a sample-and-hold circuit 34b connected to the wiring WN. The controller 13 supplies a signal HOLD, which is a sample / hold control signal, to each of the sample-and-hold circuits 34a and 34b.

[0042] The sample-and-hold circuit 34a samples the error signal ERRP during the on-period of the transistor ML based on the signal HOLD, and holds and outputs the error signal ERRP sampled during the on-period of the transistor ML during the on-period of the transistor MH. The output signal of the sample-and-hold circuit 34a is the signal ERRPa. During the on-period of the transistor ML, "ERRPa=ERRP". The signal ERRPa during the on-period of the transistor MH is equal to the error signal ERRP sampled just before the transistor MH turns on.

[0043] The sample-and-hold circuit 34b samples the error signal ERRN during the on-period of the transistor ML based on the signal HOLD, and holds and outputs the error signal ERRN sampled during the on-period of the transistor ML during the on-period of the transistor MH. The output signal of the sample-and-hold circuit 34b is the signal ERRNa. During the on-period of the transistor ML, "ERRNa=ERRN". The signal ERRNa during the on-period of the transistor MH is equal to the error signal ERRN sampled just before the transistor MH turns on.

[0044] The ramp circuit 35 generates a ramp signal RAMP that monotonically rises at a predetermined rate from a predetermined initial voltage (for example, 0 V) ​​during the on-period of the transistor MH. During the off-period of the transistor MH, the ramp signal RAMP is fixed at the initial voltage.

[0045] The adder 36 adds the ramp signal RAMP to the signal ERRNa from the sample-and-hold circuit 34b, and outputs a signal ERRNb resulting from the addition, where "ERRNb=ERRNa+RAMP."

[0046] A signal ERPa is input to the inverting input terminal of the PWM comparator 37, and a signal ERNb is input to the non-inverting input terminal of the PWM comparator 37. The PWM comparator 37 compares the signals ERPa and ERNb, and generates and outputs a signal RST as a signal indicating the comparison result thereof. The PWM comparator 37 outputs a low-level signal RST when "ERPa > ERNb" holds, and outputs a high-level signal RST when "ERPa < ERNb" holds. When "ERPa = ERNb" holds, the signal RST has a low level or a high level.

[0047] FIG. 4 shows waveforms of signals HOLD, RAMP, ERPa, ERNa, ERNb, and RST. For the sake of illustration, the signals ERNa and ERNb are shown slightly shifted vertically from each other. The controller 13 causes a rising edge to occur in the signal HOLD immediately before the turn-on of the transistor MH and during the on-period of the transistor ML, and causes a falling edge to occur in the signal HOLD promptly after the turn-off of the transistor MH. During the low-level period of the signal HOLD, the sample-and-hold circuit 34a samples so that the current error signal ERRP coincides with the signal ERPa. During the high-level period of the signal HOLD, the sample-and-hold circuit 34a holds the error signal ERRP sampled immediately before the signal HOLD switches from the low level to the high level, and outputs the held error signal ERRP as the signal ERPa.

[0048] Similarly, during the low level period of the signal HOLD, the sample-and-hold circuit 34b samples the current error signal ERRN so that it coincides with the signal ERRNa. During the high level period of the signal HOLD, the sample-and-hold circuit 34b holds the error signal ERRN sampled immediately before the signal HOLD switches from low level to high level, and outputs the held error signal ERRN as the signal ERRNa. After the rising edge of the signal HOLD, during the on period of the transistor MH, the ramp signal RAMP rises monotonically, so the signal ERRNb, which is the sum signal of the signals ERRNa and the ramp signal RAMP, also rises monotonically. When the signal ERRNb rises and reaches the signal ERRPa, a rising edge occurs in the signal RST. The transistor MH is turned off and the transistor ML is turned on at the rising edge of the signal RST, so the voltage of the ramp signal RAMP quickly drops to the initial voltage, which makes "ERRPa>ERRNb" and causes a falling edge in the signal RST.

[0049] The power supply control device 10 outputs an output voltage V OUT is the target voltage V TG The output stage MM is switched so that it is stabilized at "V FB =V REF "When "V OUT =V TG " The load current I LD The increase in the output voltage V OUT This leads to a decrease in the target voltage V TG The output voltage V OUT A decrease in ERRP causes an increase in the differential error signal (an increase in "ERRP-ERRN"). In the power supply control device 10, feedback is added to increase the coil current IL in response to an increase in the differential error signal. Conversely, a decrease in the load current I LD The decrease in the output voltage V OUT This leads to an increase in the target voltage V TG The output voltage V OUT An increase in ERRP causes a decrease in the differential error signal (causing a decrease in "ERRP-ERRN"). In the power supply control device 10, feedback is added that decreases the coil current IL in response to the decrease in the differential error signal.

[0050] Incidentally, a reference error amplifier that has a phase compensation capacitor, which is an integral element, is often used as the error amplifier. The reference error amplifier generates an error signal by charging and discharging the phase compensation capacitor. As a result, it is less likely to oscillate, but the signal bandwidth is limited, making it unsuitable for speeding up the feedback control loop. On the other hand, if an error amplifier without an integral element is used, it is possible to speed up the feedback control loop, but the tradeoff is that it becomes more difficult to cancel the input error of the error amplifier. The error amplifier 31 in Figure 3 is an error amplifier that does not have an integral element, and the input error of the error amplifier 31 is the reference voltage V REF and feedback voltage V FB In addition to the error amplifier 31, the power supply control device 10 is provided with an error correction circuit for canceling the input error of the error amplifier 31.

[0051] 5 shows an error correction circuit 910 according to a first reference configuration. The error correction circuit 910 includes an error correction amplifier 911, an error detection amplifier 912, and a capacitor 913. The error correction amplifier 911 and the error detection amplifier 912 are both transconductance amplifiers. In the first reference configuration, the error amplifier 31 outputs an output voltage V OUT Feedback voltage V FB On the other hand, in order to cancel the input error, the error correction amplifier 911 shifts the differential error signals (ERRP, ERRN) by the amount of change in the calibration signal Vcal1 acquired by the error detection amplifier 912 and the capacitor 913. At this time, the reference voltage V REF The feedback voltage V FB It is necessary to change the calibration signal Vcal1 gradually to compensate for the error of the feedback voltage V FB If the response of the calibration signal Vcal1 to the error in is fast, the output voltage V OUT In the first reference configuration, the error detection amplifier 912 and the capacitor 913 detect the feedback voltage V FB The calibration signal Vcal1 is obtained by integrating the errors.

[0052] For example, in the first reference configuration, as shown in FIG. FB =V REF Starting from the state where the load current I LD The operation when the load current I LD The output voltage V OUT and feedback voltage V FB drops sharply, but the error amplifier 31 responds quickly to keep the output voltage V OUT and feedback voltage V FB The decrease in output voltage V OUT and feedback voltage V FB gradually returns to the original voltage and converges.

[0053] In this way, when the analog circuits (912, 913) are used for correction, the reference voltage V REF and feedback voltage V FB Since the error between them is integrated, the larger the difference voltage between them, the greater the change in the calibration signal Vcal1. When the difference voltage between them becomes zero, the fluctuation of the calibration signal Vcal1 also becomes zero, so convergence in a short time is expected, and the output voltage V after convergence is OUT However, an analog circuit is not suitable for storing the calibration signal Vcal1 for a long time, and it is difficult to reset the calibration signal Vcal1, making it difficult to perform complex control.

[0054] 7 shows an error correction circuit 920 according to a second reference configuration. The error correction circuit 920 uses a digital circuit to correct (calibrate) an error. That is, the error correction circuit 920 uses a comparator 922, an up / down counter 923, and a DAC (digital-to-analog converter) 924 to correct a feedback voltage V FB is the reference voltage V REF If it is lower, the calibration signal Vcal2 is increased by one step by counting up (increasing the count value by 1), and the feedback voltage V FB is the reference voltage V REFIf it is higher, the calibration signal Vcal2 is lowered by one step by counting down (decreasing the count value by 1). The error correction amplifier 921 shifts the differential error signals (ERRP, ERRN) by the amount of change in the calibration signal Vcal2.

[0055] Regarding the second reference configuration, with reference to FIG. FB =V REF Starting from the state where the load current I LD The operation when the load current I LD , feedback voltage V FB The changes in the calibration signal Vcal2 and the output signal out of the comparator 922 are also shown. In the second reference configuration, as in the first reference configuration, the load current I LD The output voltage V OUT and feedback voltage V FB drops sharply, but the error amplifier 31 responds quickly to keep the output voltage V OUT and feedback voltage V FB The decrease in output voltage V OUT and feedback voltage V FB gradually returns to the original voltage and converges.

[0056] In the error correction circuit 920, the counter 923 counts up or down in synchronization with the clock signal. FB is the reference voltage V REF After the feedback voltage V FB is the reference voltage V REF The counter 923 continues counting up until the feedback voltage V FB is the reference voltage V REF When the count value exceeds , the operation of the counter 923 switches to counting down. Digital information including the count value can be stored in a register. In addition, it is easy to stop updating the calibration signal Vcal2 or reset the calibration signal Vcal2 as necessary, making complex control possible.

[0057] In the error correction circuit 920, the feedback voltage V FB Even after the convergence of Vcal2, the calibration signal Vcal2 continues to fluctuate up and down by one step, and the fluctuation is OUT This appears as a ripple in the load current I LD The correction after the fluctuation of the feedback voltage V FB and the output voltage V OUT It takes longer to converge.

[0058] In view of this, it is also considered to change the error correction circuit 920 to an error correction circuit 930 shown in FIG. 9. The error correction circuit 930 is an error correction circuit according to a third reference configuration. The error correction circuit 930 uses three comparators 932_1 to 932_3 to calculate the feedback voltage V FB is the reference voltage V REF Not only is it higher or lower than the feedback voltage V FB is the reference voltage V REF It detects whether the value is significantly below or above the threshold.

[0059] Comparator 932_2 detects the feedback voltage V FB is the reference voltage V REF The comparator 932_3 detects only whether the feedback voltage V FB is the reference voltage V REF The comparator 932_1 detects whether the feedback voltage V FB is the reference voltage V REF Based on these detection results (out1 to out3), the logic circuit 933 sets the input signal to the DAC 934 to output the calibration signal Vcal3 from the DAC 934. FB is the reference voltage V REF If it deviates significantly from the above, the logic circuit 933 expands the amount of change in the calibration signal Vcal3 to 4 steps or 8 steps, etc. The error correction amplifier 931 shifts the differential error signals (ERRP, ERRN) by the amount of change in the calibration signal Vcal3.

[0060] According to the error correction circuit 930, the load current I LD It is possible to increase the correction speed after the fluctuation of the comparators 932_1 to 932_3. However, in reality, an offset caused by manufacturing variations is added to the comparators 932_1 to 932_3. Due to the influence of the offset, it is difficult to stably achieve the expected correction. There is also a possibility that the offset actually added due to the manufacturing variations will be larger than the designed offset.

[0061] As an error correction circuit that takes these circumstances into consideration, the power supply control device 10 is provided with an error correction circuit 50 shown in Fig. 10. The error correction circuit 50 is included as a component of the reset circuit 12 (see Fig. 1). The error correction circuit 50 includes a comparison circuit 51, a logic circuit 52 including a counter 53, a DAC 54 that is a digital-to-analog converter, and an error correction amplifier 55.

[0062] The reference voltage V REF and feedback voltage V FB is input to the comparator circuit 51. REF and feedback voltage V FB Compare with the reference voltage V REF and feedback voltage V FB The comparison circuit 51 generates and outputs a comparison result signal CMPout corresponding to the differential voltage between the inputs. The comparison result signal CMPout is made up of a plurality of output signals. Here, the comparison result signal CMPout includes the output signals OUT1 to OUT3. The internal configuration of the comparison circuit 51 will be described in detail later. Each output signal of the comparison circuit 51 is a binary signal, and therefore the output signals OUT1 to OUT3 each have a logical value of "1" or a logical value of "0". Here, a high level potential is associated with a logical value of "1", and a low level potential is associated with a logical value of "0".

[0063] Figure 11 shows the reference voltage V REF and feedback voltage V FB and the output signals OUT1 to OUT3. L and ΔV H is a given positive voltage. Voltage ΔV Land ΔV H may have the same voltage value or may have different voltage values. FB <V REF -ΔV L When the condition "V REF -ΔV L <V FB <V REF When the condition "V REF <V FB <V REF +ΔV H When the condition "V REF +ΔV H <V FB When the condition "is satisfied," the comparator circuit 51 sets all of the output signals OUT3 to OUT1 to the low level.

[0064] In addition, “V FB =V REF -ΔV L When "V FB =V REF When "V FB =V REF +ΔV H When "is established," the output signals OUT3 and OUT2 are at a low level, and the output signal OUT1 is at a high level or a low level.

[0065] The comparison result signal CMPout from the comparison circuit 51 is input to the logic circuit 52. A clock signal CLK is input to the logic circuit 52, and the clock signal CLK is supplied to the counter 53. The clock signal CLK is a rectangular wave signal having a predetermined clock frequency, and alternately has a high level or a low level. The counter 53 holds a count value VALcnt. The counter 53 counts up or down the count value VALcnt based on the comparison result signal CMPout in synchronization with the clock signal CLK. At this time, the counter 53 adjusts and determines not only the change direction of the count value VALcnt but also the change amount of the count value VALcnt based on the comparison result signal CMPout (a specific example will be described later). Incidentally, a circuit including the comparison circuit 51 and the counter 53, or a circuit including the comparison circuit 51 and the logic circuit 52, can be called a count circuit.

[0066] The logic circuit 52 inputs a digital signal indicating the count value VALcnt to the DAC 54. The DAC 54 converts the digital signal input from the logic circuit 52 into an analog signal, and outputs the analog signal obtained by the conversion as the calibration signal Vcal. The calibration signal Vcal is an analog voltage signal. The calibration signal Vcal is proportional to the count value VALcnt, and the larger the count value VALcnt, the higher the voltage value the calibration signal Vcal has.

[0067] The error correction amplifier 55 is supplied with a calibration signal Vcal and a given bias voltage V BIAS The error correction amplifier 55 is a current output type transconductance amplifier. A calibration signal Vcal is input to a non-inverting input terminal of the error correction amplifier 55, and a bias voltage V BIAS The error correction amplifier 55 has a first output terminal connected to the wiring WP and a second output terminal connected to the wiring WN. The error correction amplifier 55 receives the calibration signal Vcal and the bias voltage V BIAS The correction current signal IcP is output from a first output terminal and the correction current signal IcN is output from a second output terminal.

[0068] The correction current signals IcP and IcN are currents that change in opposite directions. The positive correction current signal IcP is a current that flows from the error correction amplifier 55 toward the wiring WP, and the negative correction current signal IcP is a current that flows from the wiring WP into the error correction amplifier 55. Similarly, the positive correction current signal IcN is a current that flows from the error correction amplifier 55 toward the wiring WN, and the negative correction current signal IcN is a current that flows from the wiring WN into the error correction amplifier 55.

[0069] The correction current signals IcP and IcN are determined by the voltage of the calibration signal Vcal and the bias voltage V BIAS When the voltages of the calibration signal Vcal and the bias voltage Vcal are equal, they flow in the same direction and have the same magnitude. BIAS When it is higher, the absolute value of their difference |Vcal-V BIAS The larger the |, the larger the positive voltage, and the voltage of the calibration signal Vcal becomes the bias voltage V BIAS When it is lower, the absolute value of their difference |Vcal-V BIAS In contrast, the correction current signal IcN increases in the negative direction as the voltage of the calibration signal Vcal increases. BIAS When it is higher, the absolute value of their difference |Vcal-V BIAS The larger the |, the more negative the voltage becomes, and the voltage of the calibration signal Vcal becomes the bias voltage V BIAS When it is lower, the absolute value of their difference |Vcal-V BIAS The larger |, the larger the positive direction.

[0070] By providing the error correction circuit 50, the correction current signal IcP is added to the current signal IP, and the correction current signal IcN is added to the current signal IN. As a result, the reference voltage V REF and feedback voltage V FBThe error signals ERRP and ERRN are corrected so that the error between them is reduced. At this time, the error correction amplifier 55 generates the correction current signals IcP and IcN so that the higher the voltage value of the calibration signal Vcal, the larger the difference signal (ERRP-ERRN) becomes, and the lower the voltage value of the calibration signal Vcal, the smaller the difference signal (ERRP-ERRN) becomes. When the error correction circuit 50 is provided, the error signals ERRP and ERRN are expressed as "ERRP=(IP+IcP)×R+IcP" during the on-period of the transistor ML. SNS " and "ERRN = (IN + IcN) × R". As described above, R represents the resistance value of each of the resistors 33a and 33b. Here, if "ΔI = IP - IN" and "ΔIc = IcP - IcN", then during the on-period of the transistor ML, "ERRP - ERRN = 2 (ΔI + ΔIc) × R + I SNS = 2 (ΔI + ΔIc) × R-IL RonL”.

[0071] In the following, several specific configuration examples, operation examples, application techniques, modified techniques, etc. related to the comparison circuit 51 or other circuits will be described among the multiple embodiments. The matters described above in this embodiment are applied to each of the following embodiments (excluding matters related to the first to third reference configurations) unless otherwise specified and unless there is a contradiction. In the case where there is a matter in each embodiment that contradicts the matters described above, the description in each embodiment may take precedence. Furthermore, unless there is a contradiction, matters described in any of the multiple embodiments shown below can also be applied to any other embodiment (i.e., any two or more of the multiple embodiments can be combined).

[0072] <<First Example>> A first embodiment will now be described. A circuit diagram of a comparison circuit 100 according to the first embodiment is shown in Fig. 12. In the first embodiment, the comparison circuit 100 is used as the comparison circuit 51 in Fig. 10.

[0073] The comparison circuit 100 includes current sources 111-115, a differential pair 120, a current mirror circuit 130, insert transistors 141 and 142, and output circuits 151-153. The differential pair 120 is made up of transistors 121 and 122. The transistors 121 and 122 are P-channel MOSFETs. The current mirror circuit 130 is a cascode current mirror circuit and includes transistors 131-134. The transistors 131-134 and the insert transistors 141 and 142 are N-channel MOSFETs.

[0074] The power supply control device 10 includes a power supply wiring W VDD The power supply voltage VDD is a positive DC voltage. The power supply control device 10 is provided with an internal power supply circuit (not shown), which is connected to an input voltage V IN Based on the input voltage V, it generates the power supply voltage VDD and various bias voltages. IN It may itself be the power supply voltage VDD.

[0075] Current source 111 is the power supply wiring W VDD The current source 111 is provided between the power supply wiring W and the sources of the transistors 121 and 122 and is connected thereto. The sources of the transistors 121 and 122 are connected to each other. VDD A current (bias current) having a constant current value I1 is supplied from the gate of the transistor 121 to a node where the sources of the transistors 121 and 122 are connected to each other. REF The feedback voltage V FB A drain of the transistor 121 is connected to a source of the transistor 131 and a drain of the transistor 132. A drain of the transistor 122 is connected to a source of the transistor 133 and a drain of the transistor 134. The sources of the transistors 132 and 134 are connected to ground. The drain of the transistor 131 is connected to the gates of the transistors 132 and 134. A bias voltage V BIAS1 The bias voltage VBIAS1 has a positive DC voltage value lower than the power supply voltage VDD. The bias voltage V BIAS1 is higher than the gate threshold voltages of the insertion transistors 141 and 142.

[0076] The current source 112 is provided between and connected to the power supply wiring W VDD and the drain of the transistor 131. The current source 112 supplies a current having a constant current value I2 from the power supply wiring W VDD toward the drain of the transistor 131. The drain current of the transistor 121 has a current value I1A. The drain current of the transistor 121 flows through between the drain and the source of the transistor 132. The drain current of the transistor 122 has a current value I1B. The drain current of the transistor 122 flows through between the drain and the source of the transistor 134. The value of the drain current of the transistor 132 is the sum of the current value I1A and the current value I2.

[0077] In the differential pair 120, the transistors 121 and 122 are a transistor pair having the same structure and the same electrical characteristics. Therefore, when “V REF =V FB ”, “I1A = I1B” (ignoring errors). When “V REF >V FB ”, “I1A < I1B”, and as the voltage difference (V REF -V FB ) increases, the current difference (I1B - I1A) also increases. When “V REF <V FB ”, “I1A > I1B”, and as the voltage difference (V FB -V REF ) increases, the current difference (I1A - I1B) also increases. The current mirror circuit 130 operates so that the magnitudes of the drain current of the transistor 132 and the drain current of the transistor 134 become equal to each other (in other words, so as to reduce the difference between the magnitudes of the drain current of the transistor 132 and the drain current of the transistor 134).

[0078] The current source 113 is the power supply wiring W VDDand a node 163. The current source 113 is connected to the power supply line W VDD The current source 113 operates to supply a constant current from the node 163 to the node 163. The constant current from the current source 113 has a current value I3. However, depending on the voltage of the node 163, the output current value from the current source 113 to the node 163 becomes smaller than the current value I3. The current source 113 does not have the ability to increase the voltage of the node 163 above the power supply voltage VDD. When the voltage of the node 163 reaches the power supply voltage VDD, the output current value from the current source 113 to the node 163 fluctuates below the current value I3 as long as the voltage of the node 163 does not exceed the power supply voltage VDD. In the first embodiment, a voltage V3 represents the voltage of the node 163. In the first embodiment, the drain of the transistor 133 is connected to the node 163.

[0079] The current source 114 is the power supply wiring W VDD and a node 162. The current source 114 is connected to the power supply line W VDD The current source 114 operates to supply a constant current from the node 162 to the node 162. The constant current from the current source 114 has a current value I4. However, depending on the voltage of the node 162, the output current value from the current source 114 to the node 162 becomes smaller than the current value I4. The current source 114 does not have the ability to increase the voltage of the node 162 above the power supply voltage VDD. When the voltage of the node 162 has reached the power supply voltage VDD, the output current value from the current source 114 to the node 162 fluctuates below the current value I4 as long as the voltage of the node 162 does not exceed the power supply voltage VDD. In the first embodiment, the voltage V2 represents the voltage of the node 162.

[0080] The current source 115 is the power supply wiring W VDD and a node 161. The current source 115 is connected to the power supply line W VDDCurrent source 115 operates to supply a constant current from current source 115 to node 161. The constant current from current source 115 has a current value I5. However, depending on the voltage of node 161, the output current value from current source 115 to node 161 becomes smaller than the current value I5. Current source 115 does not have the ability to increase the voltage of node 161 above power supply voltage VDD. When the voltage of node 161 has reached power supply voltage VDD, the output current value from current source 115 to node 161 fluctuates below current value I5 as long as the voltage of node 161 does not exceed power supply voltage VDD. In the first embodiment, voltage V1 represents the voltage of node 161.

[0081] The insertion transistor 141 is inserted between the nodes 163 and 162, and the insertion transistor 142 is inserted between the nodes 162 and 161. Specifically, the source of the insertion transistor 141 is connected to the node 163. The drain of the insertion transistor 141 and the source of the insertion transistor 142 are connected to the node 162. The drain of the insertion transistor 142 is connected to the node 161. The gates of the insertion transistors 141 and 142 are supplied with the bias voltage V BIAS1 is supplied.

[0082] Each of the output circuits 151 to 153 is a Schmitt buffer circuit. An arbitrary Schmitt buffer circuit SMT will be described with reference to FIG. 13. The Schmitt buffer circuit SMT receives an input voltage IN SMT The Schmitt buffer circuit SMT has an input terminal and an output terminal that receive an input voltage IN SMT By binarizing the signal OUT SMT and outputs a high or low level signal OUT SMT Outputs the input voltage IN SMT When is low enough, the output signal OUT SMT has a low level. The output signal OUT SMT Starting from the state where is low level, the input voltage IN SMT As the value of “IN SMT <TH U " to "IN SMT >TH UWhen the condition " " is satisfied, the output signal OUT SMT A rising edge occurs at the IN SMT <TH L The output signal OUT SMT is kept at a high level, and “IN SMT <TH L When the condition is met, the output signal OUT SMT A fall edge occurs at TH U is the upper threshold voltage, and TH L is the lower threshold voltage. “VDD>TH U >TH L For example, the upper threshold voltage TH U is 0.7 times the power supply voltage VDD, and the lower threshold voltage TH L is 0.3 times the power supply voltage VDD.

[0083] The input terminals of the output circuits 151, 152, and 153 are connected to nodes 161, 162, and 163, respectively. Therefore, the input voltage IN SMT is the voltage V1 at node 161, and the input voltage IN SMT is the voltage V2 at node 162, and the input voltage IN SMT is the voltage V3 at node 163. The output signal OUT SMT are output signals OUT1, OUT2, and OUT3, respectively. That is, the output circuit 151 generates the output signal OUT1 by binarizing the voltage V1 of the node 161, the output circuit 152 generates the output signal OUT2 by binarizing the voltage V2 of the node 162, and the output circuit 153 generates the output signal OUT3 by binarizing the voltage V3 of the node 163.

[0084] The output circuits 151 to 153 may be configured with Schmitt inverter circuits (this also applies to each output circuit in the embodiments described later). In this case, the logic of the output signals OUT1 to OUT3 is inverted compared to when a Schmitt buffer circuit is used as the output circuits 151 to 153. The output circuits 151 to 153 may be configured with a buffer circuit or inverter circuit that does not have a hysteresis characteristic (this also applies to each output circuit in the embodiments described later).

[0085] When attention is paid to the circuit of the comparison circuit 100 consisting only of the current sources 111 to 113, the differential pair 120, the current mirror circuit 130, and the output circuit 153, the circuit of interest is REF and feedback voltage V FB A single binary signal corresponding to the difference voltage between the inputs can be obtained from the output circuit 153. In the comparison circuit 100, the current sources 114 and 115, the insertion transistors 141 and 142, and the output circuits 151 and 152 are added to the above-mentioned circuit, and the difference voltage (V REF -V FB ) to generate a four-state output (see Figure 11).

[0086] For the sake of concreteness, let us assume a numerical example in which the current values ​​I1, I2, I3, I4, and I5 are 10, 1, 0.5, 0.5, and 0.5 μA (microamperes), respectively. FB is the reference voltage V REF When the voltage V3 at the node 163 is sufficiently lower than the power supply voltage VDD so that the following inequality (1) holds, the voltage V3 at the node 163 rises substantially to the power supply voltage VDD, and the output signal OUT3 of the output circuit 153 goes to a high level. When the following inequality (1) holds, the insert transistor 141 is off, and therefore the insert transistor 142 is off, and therefore the output signals OUT2 and OUT1 are also at a high level. I1B+I3>I1A+I2 (1)

[0087] When applied to the above numerical example, when the sum of the current value I1B and 0.5 μA is greater than the sum of the current value I1A and 1 μA, that is, when “I1B > I1A + 0.5 μA” holds, the voltage V3 of the node 163 rises sufficiently and the output signal OUT3 becomes high level. When the current value I1 is 10 μA, the mutual conductance of the differential pair 120 becomes about 100 μS (micro Siemens). Therefore, the high-level output signal OUT3 indicates that the feedback voltage V FB is 5 mV or more lower than the reference voltage V REF .

[0088] When the feedback voltage V FB rises and switches from the state where “V FB < V REF - 5 mV” holds to the state where “V FB > V REF - 5 mV” holds, the voltage V3 of the node 163 drops from near the power supply voltage VDD. Due to the voltage drop of the node 163, the output signal OUT3 switches to the low level. In addition, when the gate-source voltage of the insertion transistor 141 exceeds the gate threshold voltage of the insertion transistor 141 as the voltage of the node 163 drops, the insertion transistor 141 turns on, and the drain current of the insertion transistor 141 starts to flow through the node 163, the transistors 133 and 134.

[0089] And when the following inequality (2) holds, the voltage V2 of the node 162 drops from near the power supply voltage VDD and the output signal OUT2 switches to the low level. When applied to the above numerical example, since the formula (2) corresponds to the formula “I1B + 1 μA < I1A + 1 μA”, the output signal OUT2 switches to the low level when the feedback voltage V FB just exceeds the reference voltage V FB during the rising process of the feedback voltage V REF . In addition, when the gate-source voltage of the insertion transistor 142 exceeds the gate threshold voltage of the insertion transistor 142 as the voltage of the node 162 drops, the insertion transistor 142 turns on, and the drain current of the insertion transistor 142 starts to flow through the node 162, the insertion transistor 141, the node 163, and the transistors 133 and 134. I1B+I3+I4 <I1A+I2 ···(2)

[0090] Furthermore, the feedback voltage V FB When the following inequality (3) is satisfied due to the rise in the feedback voltage V FB is the reference voltage V REF That is, the low-level output signal OUT1 is 5 mV higher than the feedback voltage V FB is the reference voltage V REF It indicates that the voltage is 5mV higher than the reference voltage. I1B+I3+I4+I5 <I1A+I2 ···(3)

[0091] In the above numerical example, the above voltage ΔV L and ΔV H Both are 5mV (see Figure 11). However, the voltage ΔV L and ΔV H is arbitrary, and the voltage ΔV L and ΔV H may be different from each other.

[0092] As can be understood from the above description, the comparison circuit 100 is in one of four states ST_a1 to ST_a4. FIGS. 14, 15, 16, and 17 show the comparison circuit 100 in states ST_a1, ST_a2, ST_a3, and ST_a4, respectively. A current generating circuit including current sources 113 to 115 generates a feedback voltage V FB and the reference voltage V REF Current I according to the difference voltage between A1 is generated at node 163. A current I A1 flows from node 163 to the current mirror circuit 130 and through transistors 133 and 134 to ground. FB The current I A2 and I A3 may also occur.

[0093] In state ST_a1, the following inequality (a1) holds. The establishment of inequality (a1) means that the reference voltage V REF and the feedback voltage V FB satisfy "V FB <V REF -ΔV L ". Therefore, in state ST_a1, "V FB <V REF -ΔV L " holds. I1A + I2 < I1B + I3 ···(a1)

[0094] In state ST_a1, since "I A1 <I3", the voltage V3 of node 163 rises to the power supply voltage VDD. As a result, the output signal OUT3 is at a high level, and since the insertion transistors 141 and 142 are off, the output signals OUT2 and OUT1 are also at a high level. In state ST_a1, the currents I A2 and I A3 described later do not occur.

[0095] In state ST_a2, the following inequality (a2) holds. The establishment of inequality (a2) means that the reference voltage V REF and the feedback voltage V FB satisfy "V REF -ΔV L <V FB <V REF ". Therefore, in state ST_a2, "V REF -ΔV L <V FB <V REF " holds. I1B + I3 < I1A + I2 < I1B + I3 + I4 ···(a2)

[0096] In state ST_a2, the voltage V3 of node 163 has dropped sufficiently, so the output signal OUT3 is at a low level. In state ST_a2, when the insertion transistor 141 is turned on, the current I A2 which is the drain current of the insertion transistor 141 is generated. The current I A2 flows from node 162 through the insertion transistor 141 to node 163, and the current I A1is added to. In state ST_a2, current I A1 a part of which is current I A2 is understood to be composed of. However, in state ST_a2, since "I A2 <I4", the voltage V2 of node 162 is high enough, so the output signal OUT2 is at a high level, and since the insertion transistor 142 is off, the output signal OUT1 is also at a high level. In state ST_a2, the current I A3 does not occur. As a result, in state ST_a2, the current I A1 is the sum of the current that is one-third of the current value I3 and the current I A2 (<I4).

[0097] In state ST_a3, the following inequality (a3) holds. The establishment of inequality (a3) corresponds to the reference voltage V REF and the feedback voltage V FB satisfying "V REF <V FB <V REF +ΔV H ", so in state ST_a3, "V REF <V FB <V REF +ΔV H " holds. I1B + I3 + I4 < I1A + I2 < I1B + I3 + I4 + I5 ···(a3)

[0098] In state ST_a3, the voltage V3 of node 163 and the voltage V2 of node 162 have decreased sufficiently, so the output signals OUT3 and OUT2 are at a low level. In state ST_a3, the current I A2 is generated and the insertion transistor 142 is turned on, so the drain current of the insertion transistor 142, which is the current I A3 is generated. In state ST_a3, the current that is one-fourth of the current value from the current source 114 is included in the current I A2 . The current I A3 flows from node 161 through the insertion transistor 142, node 162, and the insertion transistor 141 to node 163 and is added to the current I A1 . The current I A3 passes through the channel of the insertion transistor 141, so the current IA3 is the current I A2 As part of the current I A2 In the state included in the current I A1 Is added to the current I (the same applies to the state ST_a4 described later). In the state ST_a3, the current I A1 A part of the current I A3 The current I including A2 Is understood to be composed of the current I A3 However, in the state ST_a3, since "I A3 < I5", the voltage V1 of the node 161 is sufficiently high, so the output signal OUT1 is at a high level. In the state ST_a3, the value of the current I A2 Is greater than the current value I4 and less than the current value (I4 + I5). In the state ST_a3, the current I A1 Is the sum of the current of the current value I3, the current of the current value I4, and the current I A3 (< I5).

[0099] In the state ST_a4, the following inequality (a4) holds. The establishment of the inequality (a4) is based on the reference voltage V REF And the feedback voltage V FB Is "V REF + ΔV H < V FB ", so in the state ST_a4, "V REF + ΔV H < V FB " holds. I1B + I3 + I4 + I5 < I1A + I2 ···(a4)

[0100] In the state ST_a4, the voltages (V3 to V1) of the nodes 163 to 161 have sufficiently decreased, so all the output signals OUT3 to OUT1 are at a low level. In the state ST_a4, similar to the state ST_a3, the currents I A2 And I A3 Are generated. In the state ST_a4, the value of the current I A3 Is the current value I5, and the value of the current I A2 Is the current value (I4 + I5). In the state ST_a4, a part of the current I A1 Is understood to be composed of the current I A3 Including the current I A2 In the state ST_a4, the current IA1 is the sum of a current with a current value of I3, a current with a current value of I4, and a current with a current value of I5.

[0101] In the comparison circuit 100, when the output signal OUT3 is at a high level, the output signals OUT2 and OUT1 are always at a high level, and when the output signal OUT1 is at a low level, the output signals OUT2 and OUT3 are always at a low level. In other words, the high-low relationship of the three thresholds is not inverted due to manufacturing variations. In the above numerical example, the three thresholds are +5 mV, 0 mV, and -5 mV, and the high-low relationship of these three thresholds is invariable against manufacturing variations.

[0102] An additional explanation will be given regarding the operation of the comparison circuit 100. As described above, the current generating circuit including the current sources 113 to 115 generates a feedback voltage V FB and the reference voltage V REF Current I according to the difference voltage between A1 At node 163, the current generating circuit generates a current I A2 can be generated at node 162, and a current I A3 can be generated at node 161. A current I A1 corresponds to the drain current of transistor 134. Current I A2 , I A3 correspond to the drain currents of the insertion transistors 141 and 142, respectively. A1 , I A2 , I A3 are the currents passing through nodes 163, 162, and 161, respectively.

[0103] current I A3 is generated based on the generated current of the current source 115 (the output current to the node 161). A2 is generated based on the generated current of the current source 114 (the output current to the node 162). A3 >0”, the current I A2 includes the current generated by the current source 115 in addition to the current generated by the current source 114 (see FIGS. 16 and 17). A1is generated based on the generated current of the current source 113 (the output current to the node 163). A2 >0”, the current I A1 includes the current generated by the current source 113 as well as the current generated by the current source 114, and "I A3 >0”, the current I A1 includes the current generated by current sources 114 and 115 in addition to the current generated by current source 113 (see FIGS. 15 to 17).

[0104] The current mirror circuit 130 cooperates with the current generating circuits (113 to 115) to generate a current I A1 It operates to reduce the difference between the value of and the current value (I1A+I2).

[0105] For example, the feedback voltage V FB The flow of the change from state ST_a1 to state ST_a4 through states ST_a2 and ST_a3 due to an increase in the feedback voltage V FB During the rise of the voltage difference (V FB -V REF The current mirror circuit 130 and the current generating circuit (113 to 115) change the feedback voltage V FB In response to the rise in A1 In other words, the feedback voltage V FB The increase in current I A1 If we ignore the situation where the voltage V3 at node 163 is sufficiently low, the current I A1 The increase in V causes the voltage V3 at node 163 to decrease.

[0106] Starting from state ST_a1, a transition from state ST_a1 to state ST_a2 occurs as the voltage V3 of node 163 decreases, and during this transition the logical value of the output signal OUT3 of output circuit 153 is inverted from a first logical value ("1" corresponding to a high level) to a second logical value ("0" corresponding to a low level).

[0107] When the insert transistor 141 is turned on based on a voltage drop at the node 163, the current generating circuit generates a current I A2 Generates a current I A2 is the current I A1 In state ST_a2, the feedback voltage V FB The increase in current I A2 This results in an increase in the current I A2 As the voltage V2 at node 162 increases, the voltage V2 at node 162 decreases.

[0108] Starting from state ST_a2, a transition from state ST_a2 to state ST_a3 occurs as the voltage V2 of node 162 decreases, and during this transition the logical value of the output signal OUT2 of output circuit 152 is inverted from the third logical value ("1") corresponding to a high level to a fourth logical value ("0") corresponding to a low level.

[0109] When the insert transistor 142 is turned on based on a voltage drop at the node 162, the current generating circuit generates a current I A3 Generates a current I A3 is the current I A1 In state ST_a3, the feedback voltage V FB The increase in current I A3 This results in an increase in the current I A3 As the voltage V1 at node 161 increases, the voltage V1 at node 161 decreases.

[0110] Starting from state ST_a3, a transition from state ST_a3 to state ST_a4 occurs as the voltage V1 of node 161 decreases, and during this transition the logical value of the output signal OUT1 of output circuit 151 is inverted from the fifth logical value ("1") corresponding to a high level to a sixth logical value ("0") corresponding to a low level.

[0111] In this way, starting from state ST_a1, the feedback voltage V FB During the rise of the voltage difference (V FB -VREF In the process of the feedback voltage V increasing, the logic value of the output signal OUT3 of the output circuit 153 is inverted from the first logic value ("1" corresponding to a high level) to the second logic value ("0" corresponding to a low level) based on the voltage drop of the node 163. FB If increases further, the current I A2 With the occurrence of this, the voltage of the node 162 drops, and the logical value of the output signal OUT2 of the output circuit 152 is inverted from the third logical value ("1" corresponding to a high level) to the fourth logical value ("0" corresponding to a low level) based on the voltage drop of the node 162. FB If increases further, the current I A3 With the occurrence of the feedback voltage V, the voltage of the node 161 drops, and the logic value of the output signal OUT1 of the output circuit 151 is inverted from the fifth logic value ("1" corresponding to a high level) to the sixth logic value ("0" corresponding to a low level) based on the voltage drop of the node 161. FB The order of occurrence of the above three inversions during the rise process of the feedback voltage V FB When the feedback voltage V FB The reverse action occurs when the voltage rises.

[0112] Here, the first, third and fifth logical values ​​are "1" corresponding to a high level, and the second, fourth and sixth logical values ​​are "0" corresponding to a low level. However, as long as one of the first and second logical values ​​is "1" and the other is "0", the relationship between the first and second logical values ​​is arbitrary. The same is true for the set of the third and fourth logical values, and the same is true for the set of the fifth and sixth logical values. The description of the first to sixth logical values ​​shown here also applies to any of the embodiments described below.

[0113] <<Second Example>> A second embodiment will now be described. A circuit diagram of a comparison circuit 200 according to the second embodiment is shown in Fig. 18. In the second embodiment, the comparison circuit 200 is used as the comparison circuit 51 in Fig. 10.

[0114] The comparison circuit 100 includes current sources 111, 112, and 213 to 215, a differential pair 120, a current mirror circuit 130, insert transistors 241 and 242, and output circuits 251 to 253. The insert transistor 241 is an N-channel MOSFET, and the insert transistor 242 is a P-channel MOSFET.

[0115] The current source 111, the current source 112, the differential pair 120, and the current mirror circuit 130 in the comparison circuit 200 are the same as those in the comparison circuit 100 (see FIG. 12). As described above, the power supply control device 10 has a power supply wiring W to which a power supply voltage VDD is applied. VDD A current source 111, a current source 112, a differential pair 120, a current mirror circuit 130, and a power supply line W VDD and ground, and the configurations and operations of the current sources 111, 112, the differential pair 120, and the current mirror circuit 130 are the same as those shown in the first embodiment.

[0116] The current source 213 is the power supply wiring W VDD and a node 262. The current source 213 is connected to the power supply line W VDD Current source 213 operates to supply a constant current from node 262 to node 262. The constant current from current source 213 has a current value I3. However, depending on the voltage of node 262, the output current value from current source 213 to node 262 becomes smaller than current value I3. Current source 213 does not have the ability to increase the voltage of node 262 above power supply voltage VDD. When the voltage of node 262 has reached power supply voltage VDD, the output current value from current source 213 to node 262 fluctuates below current value I3 as long as the voltage of node 262 does not exceed power supply voltage VDD. In the second embodiment, voltage V2 represents the voltage of node 262.

[0117] The current source 214 is the power supply line W VDD and a node 261. The current source 214 is connected to the power supply line W VDDThe current source 214 operates to supply a constant current from the node 261 to the node 262. The constant current from the current source 214 has a current value I4. However, depending on the voltage of the node 261, the output current value from the current source 214 to the node 261 becomes smaller than the current value I4. The current source 214 does not have the ability to increase the voltage of the node 261 above the power supply voltage VDD. When the voltage of the node 261 reaches the power supply voltage VDD, the output current value from the current source 214 to the node 261 fluctuates below the current value I4 as long as the voltage of the node 261 does not exceed the power supply voltage VDD. In the second embodiment, a voltage V1 represents the voltage of the node 261. In the second embodiment, the drain of the transistor 133 is connected to the node 262.

[0118] The current source 215 is provided between the node 263 and ground and is connected thereto. The current source 215 operates to draw a constant current from the node 263 toward the ground. The constant current from the current source 215 has a current value I5. However, depending on the voltage of the node 263, the value of the current drawn from the node 263 to the current source 215 becomes smaller than the current value I5. The current source 215 does not have the ability to reduce the voltage of the node 263 below 0V. When the voltage of the node 263 has been reduced to 0V, the value of the current drawn by the current source 215 from the node 263 fluctuates below the current value I5 as long as the voltage of the node 263 does not fall below 0V. In the second embodiment, a voltage V3 represents the voltage of the node 263.

[0119] The insertion transistor 241 is inserted between the nodes 262 and 261, and the insertion transistor 242 is inserted between the nodes 262 and 263. Specifically, the sources of the insertion transistors 241 and 242 are connected to the node 262. The drain of the insertion transistor 241 is connected to the node 261. The drain of the insertion transistor 242 is connected to the node 263. The gate of the insertion transistor 241 and the gates of the transistors 131 and 133 are supplied with the bias voltage V BIAS1 The bias voltage V BIAS1 is higher than the gate threshold voltage of the insert transistor 241. The gate of the insert transistor 242 is supplied with another bias voltage V BIAS2 The bias voltage V BIAS2has a positive DC voltage value lower than the power supply voltage VDD. BIAS2 >V BIAS1 >0”. The bias voltage V BIAS2 and the absolute value of the gate threshold voltage of the insertion transistor 242.

[0120] Each of the output circuits 251 to 253 is a Schmitt buffer circuit. The input terminals of the output circuits 251, 252, and 253 are connected to nodes 261, 262, and 263, respectively. For this reason (see also FIG. 13), the input voltage IN SMT is the voltage V1 at node 261, and the input voltage IN SMT is the voltage V2 at node 262, and the input voltage IN SMT is the voltage V3 at node 263. The output signal OUT SMT are output signals OUT1, OUT2, and OUT3, respectively. That is, the output circuit 251 generates the output signal OUT1 by binarizing the voltage V1 of the node 261, the output circuit 252 generates the output signal OUT2 by binarizing the voltage V2 of the node 262, and the output circuit 253 generates the output signal OUT3 by binarizing the voltage V3 of the node 263.

[0121] When attention is paid to the circuit of the comparison circuit 200 consisting only of the current sources 111, 112 and 213, the differential pair 120, the current mirror circuit 130 and the output circuit 252, the circuit of interest is REF and feedback voltage V FB A single binary signal corresponding to the difference voltage between the inputs 214 and 215, the insert transistors 241 and 242, and the output circuits 251 and 253 are added to the above-mentioned circuit in the comparison circuit 200, and the difference voltage (V REF -V FB ) to generate a four-state output (see Figure 11).

[0122] When transitioning from the state of “I1B + I3 < I1A + I2” to the state of “I1B + I3 > I1A + I2” (corresponding to the transition from FIG. 21 to FIG. 20), as the voltage V2 of node 262 rises, a rising edge occurs in the output signal OUT2 of the output circuit 252. Further, as the voltage V2 of node 262 rises and the voltage V2 becomes higher than the bias voltage V BIAS2 by a certain voltage or more (when it becomes higher than the absolute value of the gate threshold voltage of the insertion transistor 242), the insertion transistor 242 turns on, and thereby a part of the output current of the current source 213 flows through the insertion transistor 242 to the current source 215 (see FIG. 20). Then, when the current value (I1B + I3 - I5) exceeds the current value (I1A + I2), the voltage V3 of node 263 rises and a rising edge occurs in the output signal OUT3 of the output circuit 253 (see FIG. 19).

[0123] Conversely, when transitioning from the state of “I1B + I3 > I1A + I2” to the state of “I1B + I3 < I1A + I2” (corresponding to the transition from FIG. 20 to FIG. 21), as the voltage V2 of node 262 drops, a falling edge occurs in the output signal OUT2 of the output circuit 252. Further, as the voltage V2 of node 262 drops and the voltage V2 becomes lower than the bias voltage V BIAS1 by a certain voltage or more (when it becomes lower than the gate threshold voltage of the insertion transistor 241), the insertion transistor 241 turns on, and thereby the output current (≦I4) of the current source 214 flows through the insertion transistor 241 to node 262 (see FIG. 21). Then, when the current value (I1B + I3 + I4) is lower than the current value (I1A + I2), the voltage V1 of node 261 drops and a falling edge occurs in the output signal OUT1 of the output circuit 251 (see FIG. 22).

[0124] For example, in the comparison circuit 200, assume a numerical example where the current values I1, I2, I3, I4, I5 are 10, 1, 1, 0.5, 0.5 μA (microampere), respectively. Then, in the comparison circuit 200, the above-mentioned voltage ΔV L and ΔV H both become 5 mV (see FIG. 11). However, the voltages ΔV L and ΔV H are arbitrary, and the voltage ΔV Land ΔV H may be different from each other.

[0125] The comparison circuit 200 is in one of four states ST_b1 to ST_b4. FIGS. 19, 20, 21, and 22 show the comparison circuit 200 in states ST_b1, ST_b2, ST_b3, and ST_b4, respectively. A current generating circuit including current sources 213 to 215 generates a feedback voltage V FB and the reference voltage V REF Current I according to the difference voltage between B1 is generated at node 262. A current I B1 flows from node 262 to the current mirror circuit 130 and through transistors 133 and 134 to ground. FB The current I B2 and I B3 may also occur.

[0126] In the state ST_b1, the following inequality (b1) holds. The hold of inequality (b1) is due to the reference voltage V REF and feedback voltage V FB "V FB <V REF -ΔV L " is satisfied, and therefore in state ST_b1, "V FB <V REF -ΔV L " holds true. I1A+I2 <I1B+I3-I5 ···(b1)

[0127] In the state ST_b1, the voltage V2 of the node 262 is sufficiently high (substantially has the level of the power supply voltage VDD), so that the output signal OUT2 of the output circuit 252 becomes high level and the insertion transistor 242 turns on, causing a current I B3 A current I B3 corresponds to the drain current of the insert transistor 242, and is drawn from the node 262 through the insert transistor 242 and the node 263 to the current source 215. In the state ST_b1, the current I B3The value of I5 is equal to the current value I5 and the voltage V3 at node 263 is equal to the upper threshold voltage TH U In state ST_b1, the voltage V2 of the node 262 is sufficiently high (having substantially the level of the power supply voltage VDD), so the insert transistor 241 is off, and a current I B2 does not occur. In state ST_b1, the current I B1 The value of is smaller than the current value (I3-I5).

[0128] In the state ST_b2, the following inequality (b2) holds. The hold of inequality (b2) is due to the reference voltage V REF and feedback voltage V FB "V REF -ΔV L <V FB <V REF ", so in state ST_b2, "V REF -ΔV L <V FB <V REF " holds true. I1B+I3-I5 <I1A+I2<I1B+I3 ···(b2)

[0129] In the state ST_b2, the voltage V2 of the node 262 is equal to or lower than the upper threshold voltage TH U Since the input voltage Vcc is higher than the reference voltage Vcc, the output signal OUT2 of the output circuit 252 goes to a high level and the insert transistor 242 turns on, causing a current I B3 However, in state ST_b2, the current I B3 The value of I is smaller than the current value I5, and therefore the voltage V3 of the node 263 is sufficiently low, so that the output signal OUT3 of the output circuit 253 is at a low level. In the state ST_b2, similarly to the state ST_b1, the insertion transistor 241 is off, and the current I B2 As a result, in state ST_b2, the current I B1 is a current with a value of I3 minus a current with a value of I5 minus a current B3 (i.e., "I B1 =I3-I B3 ").

[0130] In state ST_b3, the following inequality (b3) holds. The establishment of inequality (b3) means that the reference voltage V REF and the feedback voltage V FB satisfy "V REF < V FB < V REF + ΔV H ". Therefore, in state ST_b3, "V REF < V FB < V REF + ΔV H " holds. I1B + I3 < I1A + I2 < I1B + I3 + I4 ···(b3)

[0131] In state ST_b3, since the voltage V2 of node 262 is lower than the lower threshold voltage TH L of the output circuit 252, the output signal OUT2 of the output circuit 252 is at a low level, the insertion transistor 242 is off, and the insertion transistor 241 is on. When the insertion transistor 242 is off, the current I B3 does not occur, and due to the action of the current source 215, the voltage V3 of node 263 is kept low enough, resulting in the output signal OUT3 of the output circuit 253 being at a low level. When the insertion transistor 241 is on, the current I B2 occurs. The current I B2 flows from node 261 through the insertion transistor 241 to node 262 and is added to the current I B1 . In state ST_b3, a part of the current I B1 is understood to be composed of the current I B2 . However, in state ST_b3, since "I B2 < I4", the voltage V1 of node 261 is high enough, so the output signal OUT1 is at a high level. In state ST_b3, the current I B1 is the sum of the current of I3 and the current I B2 (< I4).

[0132] In state ST_b4, the following inequality (b4) holds. The establishment of inequality (b4) means that the reference voltage V REF and the feedback voltage V FB satisfy "V REF + ΔVH <V FB ", so in state ST_b4, "V REF +ΔV H <V FB " holds true. I1B+I3+I4 <I1A+I2 ···(b4)

[0133] In state ST_b4, the voltage V2 of the node 262 has dropped sufficiently, and therefore, similar to state ST_b3, the output signal OUT2 of the output circuit 252 is at a low level, the insert transistor 242 is off, and the insert transistor 241 is on. Since the insert transistor 242 is off, the output signal OUT3 of the output circuit 253 is also at a low level in state ST_b4. In state ST_b4, the current I B2 The value of the current I increases to a current value I4. In state ST_b4, the current I B1 A part of the current I B2 In addition, in state ST_b4, "I B2 Since the current I = I4", the voltage V1 at the node 261 is low, and the output signal OUT1 is at a low level. B1 is the current with a value of I3 and the current with a value of I4 B2 It becomes the sum of with.

[0134] In the comparison circuit 200, when the output signal OUT3 is at a high level, the output signals OUT2 and OUT1 are always at a high level, and when the output signal OUT1 is at a low level, the output signals OUT2 and OUT3 are always at a low level. In other words, the high-low relationship of the three thresholds is not inverted due to manufacturing variations. In the above numerical example, the three thresholds are +5 mV, 0 mV, and -5 mV, and the high-low relationship of these three thresholds is invariable against manufacturing variations.

[0135] An additional explanation will be given regarding the operation of the comparison circuit 200. As described above, the current generating circuit including the current sources 213 to 215 generates a feedback voltage V FB and the reference voltage V REF Current I according to the difference voltage between B1At node 262, the current generating circuit generates a current I B2 can be generated at node 261, and a current I B3 can be generated at node 263. A current I B1 corresponds to the drain current of transistor 134. Current I B2 , I B3 correspond to the drain currents of the insertion transistors 241 and 242, respectively. B1 , I B2 , I B3 are the currents passing through nodes 262, 261, and 263, respectively.

[0136] current I B2 is generated based on the generated current of the current source 214 (the output current to the node 261). B3 is generated based on the current generated by the current source 215 (the current drawn from the node 263). B1 is generated based on the generated current of the current source 213 (the output current to the node 262). B2 >0”, the current I B1 includes the current generated by the current source 213 as well as the current generated by the current source 214, and "I B3 >0”, the current I B1 is decreased by the amount of the current generated by the current source 215 from the current generated by the current source 213.

[0137] The current mirror circuit 130 cooperates with the current generating circuits (213 to 215) to generate a current I B1 It operates to reduce the difference between the value of and the current value (I1A+I2).

[0138] First, the feedback voltage V FB The flow of the change from state ST_b2 to state ST_b3 to state ST_b4 due to an increase in the feedback voltage V FB During the rise of the voltage difference (V FB -V REF The current mirror circuit 130 and the current generating circuit (213 to 215) change in the feedback voltage V FB In response to the rise inB1 In other words, the feedback voltage V FB The increase in current I B1 Ignoring the situation where the voltage V2 at node 262 is sufficiently low, the current I B1 The increase in V causes the voltage V2 at node 262 to decrease.

[0139] Starting from state ST_b2, a transition from state ST_b2 to state ST_b3 occurs as the voltage V2 of node 262 decreases, and during this transition the logical value of the output signal OUT2 of output circuit 252 is inverted from a first logical value ("1") corresponding to a high level to a second logical value ("0") corresponding to a low level.

[0140] When the insert transistor 241 is turned on based on a voltage drop at the node 262, the current generating circuit generates a current I B2 Generates a current I B2 is the current I B1 In state ST_b3, the feedback voltage V FB The increase in current I B2 This results in an increase in the current I B2 As the voltage V1 at node 261 increases, the voltage V1 at node 261 decreases.

[0141] Starting from state ST_b3, a transition from state ST_b3 to state ST_b4 occurs as the voltage V1 of node 261 decreases, and during this transition the logical value of the output signal OUT1 of output circuit 251 is inverted from a third logical value ("1" corresponding to a high level) to a fourth logical value ("0" corresponding to a low level).

[0142] In this way, starting from state ST_b2, the feedback voltage V FB During the rise of the voltage difference (V FB -V REF In the process of the feedback voltage V increasing, the logic value of the output signal OUT2 of the output circuit 252 is inverted from the first logic value ("1" corresponding to a high level) to the second logic value ("0" corresponding to a low level) based on the voltage drop of the node 262.FB If increases further, the current I B2 With the occurrence of the feedback voltage V, the voltage of the node 261 drops, and the logic value of the output signal OUT1 of the output circuit 251 is inverted from the third logic value ("1" corresponding to a high level) to the fourth logic value ("0" corresponding to a low level) based on the voltage drop of the node 261. FB The order of occurrence of the above two reversals during the rise of the price will never be reversed.

[0143] Next, the feedback voltage V FB The flow of the change from state ST_b3 to state ST_b2 to state ST_b1 due to a decrease in the feedback voltage V FB During the decrease in the voltage difference (V FB -V REF The current mirror circuit 130 and the current generating circuit (213 to 215) change in the feedback voltage V FB In response to the decrease in B1 In other words, the feedback voltage V FB The decrease in current I B1 If we ignore the situation where the voltage V2 at node 262 is sufficiently high, the current I B1 The decrease in V2 causes the voltage V2 at node 262 to increase.

[0144] Starting from state ST_b3, in the process in which the voltage V2 of node 262 rises, a transition occurs from state ST_b3 to state ST_b2, and during this transition, the logical value of the output signal OUT2 of the output circuit 252 is inverted from the second logical value ("0" corresponding to a low level) to the first logical value ("1" corresponding to a high level).

[0145] When the insert transistor 242 is turned on based on a voltage rise at the node 262, the current generating circuit generates a current I B3 Generates a current I B3 When this occurs, the current I B1 is the current I B3 In state ST_b3, the feedback voltage V FB The decrease in current IB3 This results in an increase in the current I B3 As the voltage V3 at node 263 increases, the voltage V3 at node 263 increases.

[0146] Starting from state ST_b2, a transition from state ST_b2 to state ST_b1 occurs as the voltage V3 of node 263 rises, and during this transition the logical value of the output signal OUT3 of output circuit 253 is inverted from the sixth logical value ("0" corresponding to a low level) to the fifth logical value ("1" corresponding to a high level).

[0147] In this way, starting from state ST_b3, the feedback voltage V FB In the process of decreasing (i.e., the differential voltage (V FB -V REF ) in the process of decreasing), the logic value of the output signal OUT2 of the output circuit 252 is inverted from the second logic value ("0" corresponding to a low level) to the first logic value ("1" corresponding to a high level) based on the voltage rise of the node 262. FB If decreases further, the current I B3 With the occurrence of the feedback voltage V, the voltage of the node 263 rises, and the logic value of the output signal OUT3 of the output circuit 253 is inverted from the sixth logic value ("0" corresponding to a low level) to the fifth logic value ("1" corresponding to a high level) based on the voltage rise of the node 263. FB The order of occurrence of the above two reversals during the decline of the

[0148] <<Third Example>> A third embodiment will now be described. A circuit diagram of a comparison circuit 300 according to the third embodiment is shown in Fig. 23. In the third embodiment, the comparison circuit 300 is used as the comparison circuit 51 in Fig. 10.

[0149] The comparison circuit 100 includes current sources 111, 112, and 313 to 315, a differential pair 120, a current mirror circuit 130, insert transistors 341 and 342, and output circuits 351 to 353. The insert transistors 341 and 342 are P-channel MOSFETs.

[0150] The current source 111, the current source 112, the differential pair 120, and the current mirror circuit 130 in the comparison circuit 300 are the same as those in the comparison circuit 100 (see FIG. 12). As described above, the power supply control device 10 has a power supply wiring W to which a power supply voltage VDD is applied. VDD A current source 111, a current source 112, a differential pair 120, a current mirror circuit 130, and a power supply line W VDD and ground, and the configurations and operations of the current sources 111, 112, the differential pair 120, and the current mirror circuit 130 are the same as those shown in the first embodiment.

[0151] The current source 313 is the power supply wiring W VDD and a node 361. The current source 313 is connected to the power supply line W VDD The current source 313 operates to supply a constant current from the node 361 to the node 361. The constant current from the current source 313 has a current value I3. However, depending on the voltage of the node 361, the output current value from the current source 313 to the node 361 becomes smaller than the current value I3. The current source 313 does not have the ability to increase the voltage of the node 361 above the power supply voltage VDD. When the voltage of the node 361 reaches the power supply voltage VDD, the output current value from the current source 313 to the node 361 fluctuates below the current value I3 as long as the voltage of the node 361 does not exceed the power supply voltage VDD. In the third embodiment, a voltage V1 represents the voltage of the node 361. In the third embodiment, the drain of the transistor 133 is connected to the node 361.

[0152] The current source 314 is provided between and connected to the node 362 and ground. The current source 314 operates to draw a constant current from the node 362 toward the ground. The constant current from the current source 314 has a current value I4. However, depending on the voltage of the node 362, the value of the current drawn from the node 362 by the current source 314 becomes smaller than the current value I4. The current source 314 does not have the ability to reduce the voltage of the node 362 below 0V. When the voltage of the node 362 has been reduced to 0V, the value of the current drawn by the current source 314 from the node 362 fluctuates below the current value I4 as long as the voltage of the node 362 does not fall below 0V. In the third embodiment, a voltage V2 represents the voltage of the node 362.

[0153] Current source 315 is provided between node 363 and ground and is connected thereto. Current source 315 operates to draw a constant current from node 363 toward ground. The constant current from current source 315 has a current value I5. However, depending on the voltage of node 363, the value of the current drawn from node 363 to current source 315 becomes smaller than the current value I5. Current source 315 does not have the ability to reduce the voltage of node 363 below 0V. When the voltage of node 363 has been reduced to 0V, the value of the current drawn by current source 315 from node 363 fluctuates below the current value I5 as long as the voltage of node 363 does not fall below 0V. In the third embodiment, voltage V3 represents the voltage at node 363.

[0154] The insertion transistor 341 is inserted between the nodes 361 and 362, and the insertion transistor 342 is inserted between the nodes 362 and 363. Specifically, the source of the insertion transistor 341 is connected to the node 361. The drain of the insertion transistor 341 and the source of the insertion transistor 342 are connected to the node 362. The drain of the insertion transistor 342 is connected to the node 363. The bias voltage V BIAS2 is supplied.

[0155] Each of the output circuits 351 to 353 is a Schmitt buffer circuit. The input terminals of the output circuits 351, 352, and 353 are connected to nodes 361, 362, and 363, respectively. For this reason (see also FIG. 13), the input voltage IN SMT is the voltage V1 at node 361, and the input voltage IN SMT is the voltage V2 at node 362, and the input voltage IN SMT is the voltage V3 at node 363. The output signal OUT SMTThey are output signals OUT1, OUT2, and OUT3, respectively. That is, the output circuit 351 generates the output signal OUT1 by binarizing the voltage V1 at the node 361, the output circuit 352 generates the output signal OUT2 by binarizing the voltage V2 at the node 362, and the output circuit 353 generates the output signal OUT3 by binarizing the voltage V3 at the node 363.

[0156] When focusing on the circuit composed only of the current sources 111, 112, and 313, the differential pair 120, the current mirror circuit 130, and the output circuit 351 among the comparison circuits 300, the circuit of interest is the reference voltage V REF and the feedback voltage V FB A single binary signal corresponding to the voltage difference between them can be obtained from the output circuit 351. In the comparison circuit 300, the current sources 314 and 315, the insertion transistors 341 and 342, and the output circuits 352 and 353 are added to the circuit of interest, and a four-state output corresponding to the voltage difference (V REF -V FB ) is generated (see FIG. 11).

[0157] When the feedback voltage V FB is high enough so that "I1B + I3 < I1A + I2" holds, all of the output signals OUT1 to OUT3 become low level (see FIG. 27). When transitioning from the state of "I1B + I3 < I1A + I2" to the state of "I1B + I3 > I1A + I2", the voltage V1 at the node 361 rises, causing a rising edge in the output signal OUT1 of the output circuit 351. Further, as the voltage V1 at the node 361 rises and the voltage V1 becomes higher than the bias voltage V BIAS2 by a certain voltage or more (when it becomes higher than the absolute value of the gate threshold voltage of the insertion transistor 341), the insertion transistor 341 turns on, and thereby a part of the output current of the current source 313 flows through the insertion transistor 341 to the current source 314 (see FIG. 26).

[0158] Then, when the current value (I1B + I3 - I4) exceeds the current value (I1A + I2), the voltage V2 at the node 362 rises, causing a rising edge in the output signal OUT2 of the output circuit 352. Further, as the voltage V2 at the node 362 rises, the voltage V2 becomes higher than the bias voltage VBIAS2 When the current value (I1B+I3-I4-I5) exceeds the current value (I1A+I2), the voltage V3 at the node 363 rises and a rising edge occurs in the output signal OUT3 of the output circuit 353 (see FIG. 24).

[0159] For example, assume that the current values ​​I1, I2, I3, I4, and I5 in the comparison circuit 300 are 10, 1, 1.5, 0.5, and 0.5 μA (microamperes), respectively. Then, in the comparison circuit 300, the above-mentioned voltage ΔV L and ΔV H Both are 5mV (see Figure 11). However, the voltage ΔV L and ΔV H is arbitrary, and the voltage ΔV L and ΔV H may be different from each other.

[0160] The comparison circuit 300 is in one of four states ST_c1 to ST_c4. FIGS. 24, 25, 26, and 27 show the comparison circuit 300 in states ST_c1, ST_c2, ST_c3, and ST_c4, respectively. A current generating circuit including current sources 313 to 315 generates a feedback voltage V FB and the reference voltage V REF Current I according to the difference voltage between C1 is generated at node 361. A current I C1 flows from node 361 to the current mirror circuit 130 and through transistors 133 and 134 to ground. FB The current I C2 and I C3 For convenience of explanation, among the states ST_c1 to ST_c4, the following will start with the state ST_c4.

[0161] In the state ST_c4, the following inequality (c4) holds. The hold of inequality (c4) is due to the reference voltage VREF and feedback voltage V FB "V REF +ΔV H <V FB ", so in state ST_c4, "V REF +ΔV H <V FB " holds true. I1B+I3 <I1A+I2 ···(c4)

[0162] In state ST_c4, the voltage V1 at the node 361 is sufficiently low (approximately 0 V), so the output signal OUT1 of the output circuit 351 is at a low level and the insert transistor 341 is off. When the insert transistor 341 is off, the voltage V2 at the node 362 is sufficiently low (approximately 0 V), so the output signal OUT2 of the output circuit 352 is at a low level and the insert transistor 342 is off. When the insert transistor 342 is off, the voltage V3 at the node 363 is sufficiently low (approximately 0 V), so the output signal OUT3 of the output circuit 353 is at a low level. In state ST_c4, the current I C2 and I C3 does not occur, and the current I C1 has a current value I3.

[0163] In the state ST_c3, the following inequality (c3) holds. The hold of inequality (c3) is due to the reference voltage V REF and feedback voltage V FB "V REF <V FB <V REF +ΔV H ", so in state ST_c3, "V REF <V FB <V REF +ΔV H " holds true. I1B+I3-I4 <I1A+I2<I1B+I3 ···(c3)

[0164] In state ST_c3, the voltage V1 of the node 361 is lower than the upper threshold voltage TH USince the input voltage Vcc is higher than the reference voltage Vcc, the output signal OUT1 of the output circuit 351 goes high and the insert transistor 341 turns on, causing a current I C2 A current I C2 corresponds to the drain current of the insert transistor 341, and flows from the node 361 through the insert transistor 341 to the node 362. In the state ST_c3, the current I C2 is drawn by the current source 314. In the state ST_c3, the current I C2 The value of I is smaller than the current value I4, so that the voltage V2 of the node 362 is sufficiently low, and the output signal OUT2 of the output circuit 352 is at a low level. In the state ST_c3, similarly to the state ST_c4, the insertion transistor 342 is off, so that the current I C3 does not occur, and the output signal OUT3 of the output circuit 353 is at a low level. C1 is the current I3 to current I4 less than the current I C2 (i.e., "I C1 =I3-I C2 In state ST_c3, the output current from current source 313 to node 361 is current I C1 and current I C2 (The same applies to states ST_c2 and ST_c1 described below).

[0165] In the state ST_c2, the following inequality (c2) holds. The hold of inequality (c2) is due to the reference voltage V REF and feedback voltage V FB "V REF -ΔV L <V FB <V REF ", so in state ST_c2, "V REF -ΔV L <V FB <V REF " holds true. I1B+I3-I4-I5 <I1A+I2<I1B+I3-I4 ···(c2)

[0166] In state ST_c2, the voltage V1 of the node 361 is lower than the upper threshold voltage TH USince the input voltage Vcc is higher than the reference voltage Vcc, the output signal OUT1 of the output circuit 351 goes high and the insert transistor 341 turns on, causing a current I C2 In the state ST_c2, the current I4 from the current source 314 is C2 Furthermore, in state ST_c2, the voltage V2 of the node 362 is equal to or lower than the upper threshold voltage TH U Since the input voltage Vcc is higher than the reference voltage Vcc, the output signal OUT2 of the output circuit 352 also goes high, and the insert transistor 342 turns on, causing a current I C3 A current I C3 corresponds to the drain current of the insert transistor 342, and flows from the node 361 through the insert transistor 341, the node 362, and the insert transistor 342 to the node 363. C3 is sunk into current source 315. current I C3 passes through the channel of the insertion transistor 341, so the current I C3 is the current I C2 As a part of the current I C2 When the current I C1 (The same applies to state ST_c1, which will be described later.) Current I C3 When the current I C2 A part of the current I C2 Of this, a current of current value I4 is drawn by the current source 314, and a current I C2 The remainder is the current I C3 In state ST_c2, the current I C3 The value of I is smaller than the current value I5, and therefore the voltage V3 at the node 363 is sufficiently low, so that the output signal OUT3 of the output circuit 353 is at a low level. C1 The current I3 is divided into two parts: a current I4 and a current I5 less than I5. C3 and subtract (i.e., "I C1 =I3-I4-I C3 ).

[0167] In the state ST_c1, the following inequality (c1) holds. The hold of inequality (c1) is due to the reference voltage VREF and feedback voltage V FB "V FB <V REF -ΔV L " is satisfied, and therefore in state ST_c1, "V FB <V REF -ΔV L " holds true. I1A+I2 <I1B+I3-I4-I5 ···(c1)

[0168] In state ST_c1, the current I C3 In other words, in the state ST_c1, the insertion transistors 341 and 342 are both on, and the current I C2 The value of the current I is the sum of the current value I4 and the current value I5. In the state ST_c1, the voltages V1 to V3 of the nodes 361 to 363 are sufficiently high, so that the output signals OUT1 to OUT3 of the output circuits 351 to 353 are all at a high level. In the state ST_c1, the current I C1 is smaller than the current of current value I3 minus the current of current value (I4 + I5) (i.e., "I C1 <I3-I4-I5)。

[0169] In the comparison circuit 300, when the output signal OUT3 is at a high level, the output signals OUT2 and OUT1 are always at a high level, and when the output signal OUT1 is at a low level, the output signals OUT2 and OUT3 are always at a low level. In other words, the high-low relationship of the three thresholds is not inverted due to manufacturing variations. In the above numerical example, the three thresholds are +5 mV, 0 mV, and -5 mV, and the high-low relationship of these three thresholds is invariant against manufacturing variations.

[0170] An additional explanation will be given regarding the operation of the comparison circuit 300. As described above, the current generating circuit including the current sources 313 to 115 generates a feedback voltage V FB and the reference voltage V REF Current I according to the difference voltage between C1 At node 361, the current generating circuit generates a current I C2can be generated at node 362, and a current I C3 can be generated at node 363. A current I C1 corresponds to the drain current of transistor 134. Current I C2 , I C3 correspond to the drain currents of the insertion transistors 341 and 342, respectively. C1 , I C2 , I C3 are the currents passing through nodes 361, 362, and 363, respectively.

[0171] current I C3 is generated based on the current generated by the current source 315 (the current drawn from node 363). C2 is generated based on the current generated by the current source 314 (the current drawn from the node 362). C3 >0”, the current I C3 passes through the channel of the insertion transistor 341, so the current I C2 includes the current generated by the current source 315 in addition to the current generated by the current source 314 (see FIGS. 24 and 25). C1 is generated based on the generated current of the current source 313 (the output current to the node 361). C2 >0” and “I C3 When the current I C1 is reduced by the amount of current generated by the current source 314 from the amount of current generated by the current source 313, and "I C2 >0” and “I C3 >0”, the current I C1 is decreased from the current generated by the current source 313 by the currents generated by the current sources 314 and 315.

[0172] The current mirror circuit 130 cooperates with the current generating circuits (313 to 315) to generate a current I C1 It operates to reduce the difference between the value of and the current value (I1A+I2).

[0173] For example, the feedback voltage V FB The flow of the change from state ST_c4 to state ST_c1 through states ST_c3 and ST_c2 due to a decrease in the feedback voltage VFB During the decrease in the voltage difference (V FB -V REF The current mirror circuit 130 and the current generating circuit (313 to 315) change in the feedback voltage V FB In response to the decrease in C1 In other words, the feedback voltage V FB The decrease in current I C1 If we ignore the situation where the voltage V1 at node 361 is sufficiently high, the current I C1 The decrease in V1 causes the voltage V1 at node 361 to increase.

[0174] Starting from state ST_c4, a transition from state ST_c4 to state ST_c3 occurs as the voltage V1 of node 361 rises, and during this transition the logical value of the output signal OUT1 of the output circuit 351 is inverted from the second logical value ("0" corresponding to a low level) to the first logical value ("1" corresponding to a high level).

[0175] When the insert transistor 341 is turned on based on a voltage rise at the node 361, the current generating circuit generates a current I C2 Generates a current I C2 When this occurs, the current I C1 is the current I C2 In state ST_c3, the feedback voltage V FB The decrease in current I C2 This results in an increase in the current I C2 As the voltage V2 at node 362 increases,

[0176] As the voltage V2 of the node 362 rises, a transition occurs from state ST_c3 to state ST_c2, and during this transition the logical value of the output signal OUT2 of the output circuit 352 is inverted from the fourth logical value ("0") corresponding to a low level to the third logical value ("1") corresponding to a high level.

[0177] When the insert transistor 342 is turned on based on a voltage rise at the node 362, the current generating circuit generates a current I C3 Generates a current I C3 When this occurs, the current I C3 is the current I C2 As a part of the current I C2 is included in the current I C1 is the current I C3 Including the current I C2 In state ST_c2, the feedback voltage V FB The decrease in current I C3 This results in an increase in the current I C3 As the voltage V3 at node 363 increases, the voltage V3 at node 363 increases.

[0178] As the voltage V3 of the node 363 rises, a transition occurs from state ST_c2 to state ST_c1, and during this transition the logical value of the output signal OUT3 of the output circuit 353 is inverted from the sixth logical value ("0") corresponding to a low level to the fifth logical value ("1") corresponding to a high level.

[0179] In this way, starting from state ST_c4, the feedback voltage V FB In the process of decreasing (i.e., the differential voltage (V FB -V REF ) in the process of decreasing), the logic value of the output signal OUT1 of the output circuit 351 is inverted from the second logic value ("0" corresponding to a low level) to the first logic value ("1" corresponding to a high level) based on the voltage rise of the node 361. FB If decreases further, the current I C2 With the occurrence of this, the voltage of the node 362 rises, and the logical value of the output signal OUT2 of the output circuit 352 is inverted from the fourth logical value ("0" corresponding to a low level) to the third logical value ("1" corresponding to a high level) based on the voltage rise of the node 362. FB If decreases further, the current I C3With the occurrence of the feedback voltage V, the voltage of the node 363 rises, and the logic value of the output signal OUT3 of the output circuit 353 is inverted from the sixth logic value ("0" corresponding to a low level) to the fifth logic value ("0" corresponding to a high level) based on the voltage rise of the node 363. FB The order of occurrence of the above three inversions in the process of decreasing the feedback voltage V FB When the feedback voltage V FB The reverse action occurs when

[0180] <<Fourth Example>> A fourth embodiment will be described. The behavior during load fluctuation when the error correction circuit 50 of FIG. 10 is used will be described. The counter 53 of FIG. 10 counts up or down the count value VALcnt based on the output signals OUT1 to OUT3 in synchronization with the clock signal CLK. The comparison circuit 51 in the error correction circuit 50 of FIG. 10 can be the comparison circuit 100, 200 or 300 of the first, second or third embodiment, or the comparison circuit of another embodiment described later can also be used.

[0181] During a high-level period of the output signal OUT3, the counter 53 performs a first up-count operation. In the first up-count operation, the counter 53 increments the count value VALcnt by a predetermined value L every time a rising edge of the clock signal CLK occurs. UP (For example, 8) As described above, during the high level period of the output signal OUT3, the output signals OUT2 and OUT1 also have a high level.

[0182] During a period when the output signal OUT3 is at a low level and the output signals OUT2 and OUT1 are at a high level, the counter 53 performs a second up-count operation. In the second up-count operation, the counter 53 increments the count value VALcnt by a predetermined value S every time a rising edge of the clock signal CLK occurs. UP (For example, 1) to increase the given value S UP (For example, 1) for a given value L UP(For example, 8) is large.

[0183] During a low level period of the output signal OUT1, the counter 53 performs a first down-counting operation. In the first down-counting operation, the counter 53 increments the count value VALcnt by a predetermined value L every time a rising edge of the clock signal CLK occurs. DWN (For example, it is decreased by 8.) As described above, during the low level period of the output signal OUT1, the output signals OUT2 and OUT3 also have a low level.

[0184] During a period in which the output signal OUT1 is at a high level and the output signals OUT2 and OUT3 are at a low level, the counter 53 performs a second down-counting operation. In the second down-counting operation, the counter 53 increments the count value VALcnt by a predetermined value S every time a rising edge of the clock signal CLK occurs. DWN (For example, 1) to decrease the given value S DWN (For example, 1) for a given value L DWN (For example, 8) is large.

[0185] An upper limit and a lower limit that is smaller than the upper limit are set for the count value VALcnt. In the counter 53, a count-up operation that would cause the count value VALcnt to exceed the upper limit is not performed, and a count-down operation that would cause the count value VALcnt to fall below the lower limit is not performed.

[0186] Refer to Figure 28. FB =V REF Starting from the state where the load current I LD Consider a situation where the load current I LD The output voltage V OUT and feedback voltage V FB However, the error amplifier 31 responds quickly to reduce the output voltage V OUT and feedback voltage V FB The decrease in the feedback voltage V FB The voltage Vmin is the voltage (V FB -ΔVL ) is lower than the feedback voltage V FB After the decline of V FB <V REF -ΔV L During the period when the condition "" is satisfied, the output signal OUT3 has a high level.

[0187] During the high-level period of the output signal OUT3, the count value VALcnt is a relatively large value L UP (for example, 8) at a time, the calibration signal Vcal also rises sharply in tandem with this, resulting in the output voltage V OUT and feedback voltage V FB The feedback voltage V FB is the reference voltage V REF The feedback voltage V FB is the voltage (V REF -ΔV L ), a falling edge occurs in the output signal OUT3. REF -ΔV L <V FB <V REF During the period when "0" is established, the output signal OUT3 is at a low level and the output signals OUT2 and OUT1 are at a high level, so that the count value VALcnt is increased to a relatively small value S UP (for example, 1) at a time. This causes the calibration signal Vcal to rise gradually, resulting in the output voltage V OUT and feedback voltage V FB also rises slowly.

[0188] Then, the feedback voltage V FB is the reference voltage V REF At this time, “V REF <V FB <V REF +ΔV H " is true. "V REF <V FB <V REF +ΔV H During the period when "0" is established, the output signals OUT3 and OUT2 are at a low level and the output signal OUT1 is at a high level, so that the count value VALcnt is synchronized with the clock signal CLK by the second down-counting operation to a relatively small value SDWN (For example, 1). After that, the load current I LD and the input voltage V IN If there are no such fluctuations, the second count-up operation and the second count-down operation are alternately performed, resulting in a stable equilibrium state.

[0189] Although not shown in the figure, the feedback voltage V FB is the reference voltage V REF When the output signal OUT1 becomes low level due to a large increase in the feedback voltage V FB is the reference voltage V REF Then, after the output signal OUT1 becomes high level, the second count-down operation is performed and the above-mentioned equilibrium state is reached.

[0190] After changing the calibration signal Vcal, the output voltage V OUT There is a delay before a change in the output voltage V appears. For this reason, the counter 53 may be configured to perform the second up-count operation only when the state in which the output signal OUT3 is at a low level and the output signals OUT2 and OUT1 are at a high level continues for n periods of the clock signal CLK. n represents an arbitrary integer value of 2 or more. Similarly, the counter 53 may be configured to perform the second down-count operation only when the state in which the output signal OUT1 is at a high level and the output signals OUT2 and OUT3 are at a low level continues for n periods of the clock signal CLK. As a result, the output voltage V OUT The output voltage V OUT (This is expected to reduce ripple.)

[0191] <<Fifth Example>> A fifth embodiment will be described. The error correction circuit 910 in Fig. 5 corrects the differential error signals (ERRP, ERRN) using an analog circuit, whereas the error correction circuit 50 in Fig. 10 corrects the differential error signals (ERRP, ERRN) using a digital circuit. The latter correction has the advantage that the correction can be stopped or easily reset when an irregularity occurs. This will be described with reference to Figs. 29 and 30.

[0192] Figures 29 and 30 show several signal waveforms observed when a ground fault occurs in the power supply device 1. However, in Figure 29, it is assumed that the error correction circuit 910 of Figure 5 is used, and in Figure 30, it is assumed that the error correction circuit 50 of Figure 10 is used. For example, in the event of a ground fault, the switch terminal TM2 is shorted to ground. In this case, the current Iout in Figure 29 or Figure 30 is understood to represent the current flowing through the switch terminal TM2. Or, for example, in the event of a ground fault, the output terminal TM OUT In this case, the current Iout in FIG. 29 or FIG. 30 is understood to represent the coil current IL. The power supply control device 10 limits the current Iout to a predetermined limit current I OCL Keep below or limit current I OCL It shall have an overcurrent protection function that keeps the current at or below this level.

[0193] 29, when the error correction circuit 910 of FIG. 5 is used, the feedback voltage V FB is the reference voltage V REF In response to the larger drop in the output voltage V, the calibration signal V rises to the upper limit level, and then the calibration signal V is maintained at the upper limit level. After that, when the ground fault is eliminated, the overcurrent protection function operates and the output voltage V OUT and feedback voltage V FB rises, but the feedback voltage V FB is the reference voltage V REF Since the calibration signal Vcal1 remains at a high level even after reaching OUT and feedback voltage V FB An overshoot of 100% occurs.

[0194] 30, when the error correction circuit 50 of FIG. 10 is used, the update of the calibration signal Vcal can be stopped at the point when the overcurrent protection function is activated due to the occurrence of a ground fault. That is, for example, the logic circuit 52 detects whether the current Iout is equal to or smaller than the limit current I OCL During the above period, a count stop process is executed to stop the change of the count value VALcnt by the counter 53, regardless of the output signals OUT1 to OUT3 and the clock signal CLK, thereby stopping the update of the calibration signal Vcal. At this time, the count value VALcnt immediately before the execution of the count stop process remains held in the counter 53. Therefore, when the ground fault is eliminated, the current Iout becomes the limited current I OCL When the normal operation including the count-up operation or the count-down operation is resumed due to the output voltage V being lower than the reference voltage Vcal, the normal operation can be restored with the ideal calibration signal Vcal. OUT and feedback voltage V FB 10 is used, complex control such as initializing the correction by initializing the counter 53 can be easily realized.

[0195] 5 is used, the updating of the calibration signal Vcal1 can be temporarily stopped by inserting a switch (not shown) between the error detection amplifier 912 and the capacitor 913 and turning off the switch. However, since the information stored in the capacitor 913 is gradually lost or deteriorated due to a leakage current of the switch or the like, it is difficult to stabilize the recovery operation.

[0196] <<Sixth Example>> A sixth embodiment will be described. In a comparison circuit according to any embodiment, the differences in input voltages can be added up by combining a plurality of differential pairs. For example, a comparison circuit 100a as shown in FIG. 31 may be configured. The comparison circuit 100a is obtained by adding a current source 111a and a differential pair 120a to the comparison circuit 100 in FIG. 12. Although not particularly shown, the current source 111a and the differential pair 120a may be added to the comparison circuit 200 or 300.

[0197] The differential pair 120a is made up of transistors 121a and 122a. The transistors 121a and 122a are P-channel MOSFETs.

[0198] The current source 111a is connected to the power supply line W VDD The current source 111a is connected between the power supply wiring W and the sources of the transistors 121a and 122a. The sources of the transistors 121a and 122a are connected to each other. VDD A current (bias current) having a constant current value I1a is supplied from transistor 121a to a node where the sources of transistors 121a and 122a are connected to each other. A voltage INP is supplied to the gate of transistor 121a, while a voltage INN is supplied to the gate of transistor 122a. The drain of transistor 121a, together with the drain of transistor 121, is connected to the source of transistor 131 and the drain of transistor 132. The drain of transistor 122a, together with the drain of transistor 122, is connected to the source of transistor 133 and the drain of transistor 134.

[0199] The drain current of the transistor 121a has a current value I1aA. The drain current of the transistor 122a has a current value I1aB. Therefore, in the comparison circuit 100a of FIG. 31, as viewed from the comparison circuit 100 of FIG. 12, the current I1aA is added to the current I1A, and the current I1aB is added to the current I1B. In other respects, the comparison circuit 100a is the same as the comparison circuit 100 of the first embodiment. The description of the first embodiment can be applied to the comparison circuit 100a, and in this application, the current I1A in the first embodiment may be regarded as the current after addition (I1A+I1aA) in the comparison circuit 100a, and the current I1B in the first embodiment may be regarded as the current after addition (I1B+I1aB) in the comparison circuit 100a. The same applies when the current source 111a and the differential pair 120a are added to the comparison circuit 200 or 300.

[0200] The differential pair 120a can be used for offset correction. REF =V FB", ideally, the drain current of the transistor 121 and the drain current of the transistor 122 are equal. However, in reality, when "V REF =V FB ", a difference may occur between the drain current of transistor 121 and the drain current of transistor 122. REF =V FB The voltages INP and INN can be adjusted so that the summed current (I1A+I1aA) and the summed current (I1B+I1aB) are equal when "I1A+I1aA" is the same as the summed current (I1B+I1aB). The values ​​of the voltages INP and INN may be set and fixed during the shipping inspection stage of the power supply control device 10 including the comparison circuit 100a.

[0201] <<Seventh Example>> A seventh embodiment will now be described. In the seventh embodiment, applied techniques, modified techniques, or supplementary matters for the above-mentioned items will be described.

[0202] In the comparison circuit 100 of the first embodiment, the output node of the current mirror circuit 130 is the node 163, and the feedback voltage V FB and the reference voltage V REF Current I according to the difference voltage between A1 appears at node 163 (see FIG. 12 and FIG. 14 to FIG. 17). In comparison circuit 100, the feedback voltage V FB and the reference voltage V REF The current I from the current source 113 is generated according to the difference voltage between A1 A current generated by the current source 114 is added to the current source 115, or a current generated by the current sources 114 and 115 is added to the current source 115. As a result, the comparison circuit 100 generates three output signals OUT1 to OUT3, but the comparison circuit 100 may be modified so that the comparison circuit 100 outputs only the output signals OUT1 and OUT2, or so that the comparison circuit 100 outputs four or more output signals. Although not particularly shown, if a current source and an insert transistor equivalent to the current source 115 and the insert transistor 142 are added to the comparison circuit 100, the comparison circuit 100 can output four output signals.

[0203] In the comparison circuit 300 of the third embodiment, the output node of the current mirror circuit 130 is a node 361, and the feedback voltage V FB and the reference voltage V REF Current I according to the difference voltage between C1 appears at node 361 (see FIGS. 23 to 27). In the comparison circuit 300, the feedback voltage V FB and the reference voltage V REF The current I C1 From this, the current generated by the current source 314 is subtracted, or the currents generated by the current sources 314 and 315 are subtracted. As a result, the comparison circuit 300 generates three output signals OUT1 to OUT3, but the comparison circuit 300 may be modified so that the comparison circuit 300 outputs only the output signals OUT1 and OUT2, or so that the comparison circuit 300 outputs four or more output signals. Although not particularly shown, if a current source and an insert transistor equivalent to the current source 315 and the insert transistor 342 are added to the comparison circuit 300, the comparison circuit 300 can output four output signals.

[0204] The comparison circuit 200 of the second embodiment can be understood as a combination of a part of the comparison circuit 100 of the first embodiment and a part of the comparison circuit 300 of the third embodiment. In the comparison circuit 200 of the second embodiment, the output node of the current mirror circuit 130 is the node 262, and the feedback voltage V FB and the reference voltage V REF Current I according to the difference voltage between B1 appears at node 262 (FIGS. 18 to 22). In comparison circuit 200, the feedback voltage V FB and the reference voltage V REF The current I from the current source 213 is generated according to the difference voltage between B1 The current generated by the current source 214 is added to the current I B1The current generated by the current source 215 is subtracted from the current source 214. As a result, the comparison circuit 200 generates three output signals OUT1 to OUT3, but the comparison circuit 200 may be modified so that the comparison circuit 200 outputs only the output signals OUT1 and OUT2 or only the output signals OUT2 and OUT3, or so that the comparison circuit 200 outputs four or more output signals. Although not particularly shown, for example, if a current source and an insert transistor equivalent to the current source 214 and the insert transistor 241 are added to the comparison circuit 200, the comparison circuit 200 can output four output signals. Alternatively, for example, if a current source and an insert transistor equivalent to the current source 215 and the insert transistor 242 are added to the comparison circuit 200, the comparison circuit 200 can output four output signals.

[0205] In addition, the first to third embodiments can be combined in any manner, and the configuration of the comparison circuit can vary depending on the total number of output signals included in the comparison result signal CMP (see FIG. 10). REF and feedback voltage V FB function as two input voltages to the comparator circuit. Here, it is assumed that the differential pair receiving the two input voltages is configured with a pair of P-channel MOSFETs (121, 122), but the differential pair receiving the two input voltages can also be configured with a pair of N-channel MOSFETs, or the differential pair can be configured by combining a P-channel MOSFET and an N-channel MOSFET.

[0206] Although it is assumed that the comparison circuit according to the present disclosure is applied to the power supply control device 10, the comparison circuit according to the present disclosure may be applied to any device.

[0207] For any signal or voltage, the relationship between the high level and the low level thereof may be reversed to that described above without prejudice to the spirit of the above.

[0208] The channel types of FETs (field effect transistors) shown in each embodiment are merely examples. Although the change between P-channel type and N-channel type has been described above with respect to the differential pair, the channel type of any FET in other parts may be changed between P-channel type and N-channel type without departing from the spirit of the above.

[0209] Any of the transistors described above may be any type of transistor, provided that no disadvantage occurs. For example, any of the transistors described above as MOSFETs may be replaced with junction FETs, IGBTs (Insulated Gate Bipolar Transistors), or bipolar transistors, provided that no disadvantage occurs. Any of the transistors has a first electrode, a second electrode, and a control electrode. In a FET, one of the first and second electrodes is a drain, the other is a source, and the control electrode is a gate. In an IGBT, one of the first and second electrodes is a collector, the other is an emitter, and the control electrode is a gate. In a bipolar transistor that does not belong to an IGBT, one of the first and second electrodes is a collector, the other is an emitter, and the control electrode is a base.

[0210] The embodiments of the present disclosure can be modified in various ways as appropriate within the scope of the technical ideas set forth in the claims. The above embodiments are merely examples of the embodiments of the present disclosure, and the meanings of the terms of the present disclosure or each component are not limited to those described in the above embodiments. The specific numerical values ​​shown in the above description are merely examples, and can be changed to various numerical values ​​as a matter of course.

[0211] <<Additional Notes>> Regarding the present disclosure, specific configuration examples of which have been shown in the above-mentioned embodiments, additional notes will be provided.

[0212] A comparison circuit according to an aspect of the present disclosure is a circuit for detecting a difference voltage (e.g., (V FB -V REFa comparison circuit (51, 100, 200, 300) configured to generate a plurality of output signals in response to a differential voltage, each of the output signals being a binary signal, the plurality of output signals including a first output signal and a second output signal (any two of OUT1 to OUT3), and a first current (e.g., I A1 The comparison circuit is provided with a current generating circuit (e.g., 113 to 115) configured to generate a first output signal (e.g., OUT3) based on a voltage of the first node, a first output circuit (e.g., 153) configured to generate the first output signal (e.g., OUT4) based on a voltage of a second node (e.g., 162), and an insertion transistor (e.g., 141) inserted between the first node and the second node, and the first output circuit inverts a logical value of the first output signal (e.g., corresponding to a transition from state ST_a1 to state ST_a2) in a process in which the voltage of the first node changes (e.g., a process in which the voltage of the node 163 decreases) based on a change in the first current accompanying a change in the differential voltage in a predetermined direction, and the current generating circuit generates a second current (e.g., I A2 ), thereby changing the first current by the amount of the second current, and when the second current is generated, the second current changes in accordance with the change in the differential voltage in the predetermined direction, and the second output circuit inverts the logical value of the second output signal in the process of the voltage of the second node changing based on the change in the second current in accordance with the change in the differential voltage in the predetermined direction (first configuration).

[0213] This makes it possible to correctly detect which of three or more voltage ranges the differential voltage between the first input voltage and the second input voltage belongs to.

[0214] In the comparison circuit according to the first configuration (see, for example, FIGS. 14 to 16), the first current (for example, I A1) increases, and the first output circuit (e.g., 153) inverts the logic value of the first output signal (e.g., OUT3) in the process in which the voltage of the first node (e.g., 163) decreases with the increase in the first current, and the current generating circuit generates the second current (e.g., I A2 ), the second current is added to the first current, and when the second current is generated, the difference voltage changes in the predetermined direction, thereby increasing the second current, and the second output circuit may be configured to invert a logical value of the second output signal (e.g., OUT2) in the process in which the voltage of the second node decreases as the second current increases (second configuration).

[0215] The comparison circuit according to the second configuration (see, for example, FIGS. 14 to 16) further includes a differential pair (120) configured to receive the first input voltage and the second input voltage, and a current mirror circuit (130) connected to the differential pair and the first node, and a current according to the difference voltage is generated as the first current (e.g., I A1 ) flows between the first node and the current mirror circuit and the change in the difference voltage in the predetermined direction (for example, V FB The first current may be increased in response to a voltage rise (corresponding to an increase in the first current) (third configuration).

[0216] In the comparison circuit of the third configuration (e.g., see Figures 14 to 16), the current generating circuit may have a first current source and a second current source (e.g., 113 and 114), the first node is provided between the first current source and the current mirror circuit, the first current is generated based on a current generated by the first current source between the first current source and the first node, and the second node is provided between the second current source and the insertion transistor, and the second current is generated based on a current generated by the second current source between the second current source and the second node (fourth configuration).

[0217] In the comparison circuit according to the fourth configuration (see, for example, FIGS. 14 to 16), the insertion transistor (for example, 141) is an N-channel type field effect transistor having a gate that receives a predetermined bias voltage, a drain connected to the second node, and a source connected to the first node, and when the insertion transistor is turned on based on a voltage drop of the first node, the second current (for example, I A2 ) may be directed to the first node via the insertion transistor (fifth configuration).

[0218] In a comparison circuit relating to any of the second to fifth configurations above (see, for example, Figures 14 to 16), there may be a configuration (sixth configuration) in which, after the logical value of the first output signal is inverted based on a voltage drop at the first node during the process of the difference voltage changing in the predetermined direction (for example, after a transition from state ST_a1 to state ST_a2), the logical value of the second output signal is inverted based on a voltage drop at the second node as the difference voltage further changes in the predetermined direction (for example, after a transition from state ST_a2 to state ST_a3).

[0219] In the comparison circuit according to the second configuration (see, for example, FIGS. 14 to 17), the plurality of output signals include a third output signal (for example, OUT1), the insert transistor is a first insert transistor (for example, 141), the comparison circuit further includes a third output circuit (for example, 151) configured to generate the third output signal based on a voltage of a third node (for example, 161), and a second insert transistor (for example, 142) inserted between the second node and the third node, and the current generation circuit generates a third current (for example, I A3), the second current including the third current is added to the first current, and when the third current is generated, the difference voltage changes in the predetermined direction, thereby increasing the third current, and the third output circuit may be configured to invert the logical value of the third output signal in the process in which the voltage of the third node decreases as the third current increases (seventh configuration).

[0220] This makes it possible to correctly detect to which of four or more voltage ranges the differential voltage between the first input voltage and the second input voltage belongs.

[0221] The comparison circuit according to the seventh configuration (see, for example, FIGS. 14 to 17) further includes a differential pair (120) configured to receive the first input voltage and the second input voltage, and a current mirror circuit (130) connected to the differential pair and the first node, and the current mirror circuit and the current generating circuit cause a current corresponding to the differential voltage to flow between the first node and the current mirror circuit as the first current, and the first current (e.g., I A1 ) may be increased (eighth configuration).

[0222] In the comparison circuit according to the eighth configuration (see, for example, Figures 14 to 17), the current generation circuit may have a first current source, a second current source, and a third current source (for example, 113 to 115), the first node is provided between the first current source and the current mirror circuit, the first current is generated based on a current generated by the first current source between the first current source and the first node, the second node is provided between the second current source and the first insert transistor, the second current is generated based on a current generated by the second current source between the second current source and the second node, and the third node is provided between the third current source and the second insert transistor, and the third current may be generated based on a current generated by the third current source between the third current source and the third node (ninth configuration).

[0223] In the comparison circuit according to the ninth configuration (see, for example, FIGS. 14 to 17), the first insert transistor (for example, 141) is an N-channel type field effect transistor having a gate receiving a predetermined bias voltage, a drain connected to the second node, and a source connected to the first node, and the second insert transistor (for example, 142) is an N-channel type field effect transistor having a gate receiving the bias voltage, a drain connected to the third node, and a source connected to the second node, and when the first insert transistor is turned on based on a voltage drop at the first node, the second current (for example, I A2 ) flows through the first insert transistor to the first node, and when the second insert transistor is turned on based on a voltage drop at the second node, the third current (e.g., I A3 ) may be directed to the first node via the second insert transistor, the second node, and the first insert transistor (tenth configuration).

[0224] In a comparison circuit relating to any of the seventh to tenth configurations above (see, for example, Figures 14 to 17), there may be a configuration (an eleventh configuration) in which, after the logical value of the first output signal is inverted based on a voltage drop at the first node during the process of the change of the differential voltage in the predetermined direction (for example, after a transition from state ST_a1 to state ST_a2), the logical value of the second output signal is inverted based on a voltage drop at the second node as the differential voltage further changes in the predetermined direction (for example, a transition from state ST_a2 to state ST_a3), and then, the logical value of the third output signal is inverted based on a voltage drop at the third node as the differential voltage further changes in the predetermined direction (for example, a transition from state ST_a3 to state ST_a4).

[0225] In the comparison circuit according to the second configuration (see, for example, FIGS. 19 to 22), the plurality of output signals include a third output signal (for example, OUT3), the insert transistor is a first insert transistor (for example, 241), and the predetermined direction is a first direction (for example, V FB) in a second direction (e.g., V FB The comparator further includes a third output circuit (e.g., 253) configured to generate the third output signal based on a voltage of a third node (e.g., 263) and a second insertion transistor (e.g., 242) inserted between the first node and the third node, and the first current (e.g., I B1 ) decreases, the first output circuit (e.g., 252) inverts the logical value of the first output signal (e.g., OUT2) from a first logical value to a second logical value (e.g., corresponding to a transition from state ST_b2 to state ST_b3) in the process in which the voltage of the first node (e.g., 262) decreases with the increase in the first current, and inverts the logical value of the first output signal (e.g., OUT2) from the second logical value to the first logical value (e.g., corresponding to a transition from state ST_b3 to state ST_b2) in the process in which the voltage of the first node (e.g., 262) increases with the decrease in the first current, and the current generating circuit generates a third current (e.g., I B3 ), the first current is reduced by the amount of the third current, and when the third current is generated, the difference voltage changes in the second direction, thereby increasing the third current, and the third output circuit may be configured to invert a logical value of the third output signal (e.g., OUT3) in the process in which the voltage of the third node increases with the increase in the third current (twelfth configuration).

[0226] This makes it possible to correctly detect to which of four or more voltage ranges the differential voltage between the first input voltage and the second input voltage belongs.

[0227] The comparison circuit according to the twelfth configuration (see, for example, FIGS. 19 to 22) further includes a differential pair (120) configured to receive the first input voltage and the second input voltage, and a current mirror circuit (130) connected to the differential pair and the first node, and a current according to the differential voltage is generated as the first current (e.g., I B1 ) between the first node and the current mirror circuit and the change in the difference voltage in the first direction (e.g., V FB ) while the first current increases in response to a change in the differential voltage in the second direction (e.g., corresponding to an increase in V FB The first current may be decreased in response to a change in the capacitance (corresponding to a decrease in capacitance).

[0228] In the comparison circuit according to the thirteenth configuration (see, for example, FIGS. 19 to 22), the current generation circuit has a first current source, a second current source, and a third current source (for example, 213 to 215), the first node (for example, 262) is provided between the first current source and the current mirror circuit, and the first current (for example, I B1 ) is generated, the second node (e.g., 261) is provided between the second current source and the first insertion transistor, and the second current (e.g., I B2 ) is generated, the third node (e.g., 263) is provided between the third current source and the second insert transistor, and the third current (e.g., I B3 ) may be generated (fourteenth configuration).

[0229] In the comparison circuit according to the fourteenth configuration (see, for example, FIGS. 19 to 22), the first insert transistor (e.g., 241) is an N-channel type field effect transistor having a gate receiving a predetermined bias voltage, a drain connected to the second node, and a source connected to the first node, and the second insert transistor (e.g., 242) is a P-channel type field effect transistor having a gate receiving another predetermined bias voltage, a drain connected to the third node, and a source connected to the first node, and when the first insert transistor is turned on based on a voltage drop of the first node (see, for example, FIG. 21), the second current (e.g., I B2 ) flows through the first insert transistor to the first node, and when the second insert transistor is turned on based on a voltage rise at the first node (see, for example, FIG. 20), the third current (for example, I B3 ) may extend from the first node through the second insert transistor to the third node (fifteenth configuration).

[0230] In the comparison circuit according to any one of the twelfth to fifteenth configurations (see, for example, FIG. 19 to FIG. 22), the change in the difference voltage in the first direction (for example, V FB In the process of the change in the differential voltage in the first direction (corresponding to a rise in V), the logical value of the first output signal is inverted from the first logical value to the second logical value based on a voltage drop at the first node (for example, after a transition from state ST_b2 to state ST_b3), and then the logical value of the second output signal is inverted based on a voltage drop at the second node due to a further change in the first direction (for example, a transition from state ST_b3 to state ST_b4), and the change in the differential voltage in the second direction (for example, V FBIn a process of inverting the logical value of the first output signal from the second logical value to the first logical value based on a voltage rise at the first node during a transition (corresponding to a drop in state ST_b3), the differential voltage may further change in the second direction, causing the logical value of the third output signal to invert based on a voltage rise at the third node (for example, transitioning from state ST_b2 to state ST_b1) (a sixteenth configuration).

[0231] In the comparison circuit according to the first configuration (see, for example, FIGS. 24 to 27), the difference voltage changes in the predetermined direction (for example, V FB The first current (e.g., I C1 ) decreases, and the first output circuit (e.g., 351) inverts the logical value of the first output signal in the process in which the voltage of the first node (e.g., 361) increases with the decrease in the first current (corresponding to, for example, a transition from state ST_c4 to state ST_c3), and the current generating circuit (e.g., 313 to 315) generates the second current (I C2 ), the first current is reduced by the amount of the second current, and when the second current is generated, the difference voltage changes in the predetermined direction, thereby increasing the second current, and the second output circuit (e.g., 352) inverts the logical value of the second output signal (e.g., OUT2) in the process in which the voltage of the second node increases as the second current increases (seventeenth configuration).

[0232] The comparison circuit according to the seventeenth configuration (see, for example, FIGS. 24 to 27) further includes a differential pair (for example, 120) configured to receive the first input voltage and the second input voltage, and a current mirror circuit (for example, 130) connected to the differential pair and the first node, and a current according to the difference voltage is generated as the first current (for example, I C1 ) flows between the first node and the current mirror circuit and the change in the difference voltage in the predetermined direction (for example, V FBThe first current may be decreased in response to a decrease in the first current (corresponding to a decrease in

[0233] In the comparison circuit according to the 18th configuration (see, for example, FIGS. 24 to 27), the current generation circuit has a first current source and a second current source (e.g., 313, 314), the first node (e.g., 361) is provided between the first current source and the current mirror circuit, and the first current (e.g., I C1 ) is generated, the second node (e.g., 362) is provided between the second current source and the insertion transistor, and the second current (e.g., I C2 ) may be generated (the nineteenth configuration).

[0234] In the comparison circuit of the 19th configuration (e.g., see Figures 24 to 27), the insertion transistor (e.g., 341) is a P-channel field effect transistor having a gate that receives a predetermined bias voltage, a drain connected to the second node, and a source connected to the first node, and when the insertion transistor is turned on based on a voltage increase at the first node (e.g., see Figure 26), the second current including the generated current of the second current source may flow from the first node via the insertion transistor to the second node (20th configuration).

[0235] In a comparison circuit relating to any of the above 17th to 20th configurations (see, for example, Figures 24 to 27), after the logical value of the first output signal is inverted based on a voltage rise at the first node during the process of the difference voltage changing in the predetermined direction (for example, after a transition from state ST_c4 to state ST_c3), the logical value of the second output signal may be inverted based on a voltage rise at the second node as the difference voltage further changes in the predetermined direction (for example, after a transition from state ST_c3 to state ST_c2) (21st configuration).

[0236] In the comparison circuit according to the seventeenth configuration (see, for example, FIGS. 24 to 27), the plurality of output signals include a third output signal (for example, OUT3), the insert transistor is a first insert transistor (for example, 341), the comparison circuit further includes a third output circuit (for example, 353) configured to generate the third output signal (for example, OUT3) based on a voltage of a third node (for example, 363), and a second insert transistor (for example, 342) inserted between the second node and the third node, and the current generation circuit generates a third current (for example, I C3 ), thereby reducing the first current by an amount equivalent to the second current including the third current, and when the third current is generated, the difference voltage changes in the predetermined direction, thereby increasing the third current, and the third output circuit may be configured to invert the logical value of the third output signal in the process in which the voltage of the third node increases as the third current increases (configuration 22).

[0237] This makes it possible to correctly detect to which of four or more voltage ranges the differential voltage between the first input voltage and the second input voltage belongs.

[0238] The comparison circuit according to the twenty-second configuration (see, for example, FIGS. 24 to 27) further includes a differential pair (120) configured to receive the first input voltage and the second input voltage, and a current mirror circuit (130) connected to the differential pair and the first node, and the current mirror circuit and the current generating circuit cause a current corresponding to the differential voltage to flow between the first node and the current mirror circuit as the first current, and a change in the differential voltage in the predetermined direction (for example, V FB The first current may be decreased in response to a decrease in the first current (corresponding to a decrease in

[0239] In the comparison circuit according to the twenty-third configuration (see, for example, Figures 24 to 27), the current generation circuit may have a first current source, a second current source, and a third current source (for example, 313 to 315), the first node (for example, 361) is provided between the first current source and the current mirror circuit, the first current is generated based on a current generated by the first current source between the first current source and the first node, the second node (for example, 362) is provided between the second current source and the first insert transistor, the second current is generated based on a current generated by the second current source between the second current source and the second node, and the third node (for example, 363) is provided between the third current source and the second insert transistor, and the third current may be generated based on a current generated by the third current source between the third current source and the third node (24th configuration).

[0240] In the comparison circuit according to the 24th configuration (see, for example, FIGS. 24 to 27), the first insert transistor (e.g., 341) is a P-channel type field effect transistor having a gate receiving a predetermined bias voltage, a drain connected to the second node, and a source connected to the first node, and the second insert transistor (e.g., 342) is a P-channel type field effect transistor having a gate receiving the bias voltage, a drain connected to the third node, and a source connected to the second node, and when the first insert transistor is turned on based on a voltage rise at the first node (see, for example, FIG. 26), the second current (e.g., I C2 ) flows from the first node to the second node via the first insert transistor, and when the second insert transistor is turned on based on a voltage rise at the second node (see, for example, FIG. 25 ), the third current (for example, I C3 ) may be directed from the first node through the first insert transistor, the second node, and the second insert transistor to the third node (25th configuration).

[0241] In a comparison circuit relating to any of the above 22nd to 25th configurations (see, for example, Figures 24 to 27), there may be a configuration (26th configuration) in which, after the logical value of the first output signal is inverted based on the voltage rise at the first node during the process of the change of the differential voltage in the predetermined direction (for example, after transitioning from state ST_c4 to state ST_c3), the logical value of the second output signal is inverted based on the voltage rise at the second node as the differential voltage further changes in the predetermined direction (for example, transitioning from state ST_c3 to state ST_c2), and then, the logical value of the third output signal is inverted based on the voltage rise at the third node as the differential voltage further changes in the predetermined direction (for example, transitioning from state ST_c2 to state ST_c1).

[0242] A counting circuit according to one aspect of the present disclosure (see, for example, FIG. 10) comprises a comparison circuit (51, 100, 200, 300) according to any one of the first to twenty-sixth configurations above, and a counter (53) configured to increment or decrement a count value based on the plurality of output signals output from the comparison circuit, the counter being configured to determine the direction of change in the count value and the amount of change in the count value based on each logical value of the plurality of output signals (27th configuration).

[0243] This makes it possible to determine the direction and amount of change in the count value based on which of three or more voltage ranges the differential voltage between the first input voltage and the second input voltage belongs to. [Explanation of symbols]

[0244] 1 Power supply 10 Power supply control device 11 Set Circuit 12 Reset Circuit 13 Controller MM output stage MH, ML transistors TM1 input terminal TM2 Switch Terminal TM3 Ground terminal TM4 Feedback terminal TM OUT Output terminal L1 coil C1 Capacitor R1, R2 resistance VS Voltage Source V IN Input voltage V OUT Output Voltage V FB Feedback Voltage V REF Reference Voltage V SW Switch Voltage IL Coil current I LD load current SET, RST signal GH, GL gate signals 31 Error Amplifier 32 Current detection circuit 33 Information synthesis circuit 34 Information retention circuit 35 Lamp circuit 36 Adder 37 PWM Comparator 32a Switch 32b, 33a, 33b resistor 34a, 34b Sample and hold circuits I SNS Sense Signal ERRP, ERRN error signal IP, IN current signal ERRPa, ERRNa, ERRNb signals RAMP Ramp signal HOLD signal WP, WN wiring 51 Comparison circuit 52 Logic Circuits 53 Counter 54DAC 55 Error Correction Amplifier CMPout comparison result signal OUT1~OUT3 output signal VALcnt Count value Vcal Calibration Signal V BIAS Bias Voltage IcP, IcN correction current signal 100, 200, 300 comparison circuit 111~115, 213~215, 313~315 Current source 120 Differential Pair 130 Current mirror circuit 121, 122, 131-134 Transistors 141, 142, 241, 242, 341, 342, Insertion transistor 151~153, 251~253, 351~353 Output circuit 161~163, 261~263, 361~363 nodes V1~V3 voltage V BIAS1 , V BIAS2 Bias Voltage I1A, I1B, I1~I5 current values I A1 ~I A3 , I B1 ~I B3 , I C1 ~I C3 current 100a Comparison circuit 120a differential pair 121a, 122a Transistors I1Aa, I1Ba current value 910, 920, 930 error correction circuit 911, 921, 931 Error Correction Amplifiers 912, 922 Error Detection Amplifier 913 Capacitor 923 Up / Down Counter 924, 934 DAC 932_1~932_3 Comparator 933 Logic Circuit Vcal1, Vcal2, Vcal3 calibration signal

Claims

1. a comparison circuit configured to generate a plurality of output signals responsive to a difference voltage between a first input voltage and a second input voltage, each output signal being a binary signal, the plurality of output signals including a first output signal and a second output signal; a current generating circuit configured to generate a first current through a first node, the first current being responsive to the differential voltage; a first output circuit configured to generate the first output signal based on a voltage at the first node; a second output circuit configured to generate the second output signal based on a voltage at a second node; an insertion transistor is provided in the comparison circuit and is inserted between the first node and the second node; the first output circuit inverts a logical value of the first output signal in a process in which the voltage of the first node changes based on a change in the first current accompanying a change in the differential voltage in a predetermined direction; the current generating circuit generates a second current between the first node and the second node via the insertion transistor based on a voltage change at the first node caused by a change in the differential voltage in the predetermined direction, thereby changing the first current by an amount corresponding to the second current; When the second current is generated, the second current changes in accordance with a change in the differential voltage in the predetermined direction; The second output circuit inverts a logical value of the second output signal in a process in which the voltage of the second node changes based on a change in the second current accompanying a change in the differential voltage in the predetermined direction. , comparison circuit.

2. The first current increases as the differential voltage changes in the predetermined direction, the first output circuit inverts a logical value of the first output signal in a process in which the voltage of the first node decreases with an increase in the first current; the current generating circuit generates the second current flowing from the second node through the insertion transistor to the first node based on a voltage drop of the first node, and adds the second current to the first current; When the second current is generated, the second current increases due to the change in the differential voltage in the predetermined direction; The second output circuit inverts a logical value of the second output signal in the process in which the voltage of the second node decreases with an increase in the second current.

2. The comparison circuit according to claim 1.

3. a differential pair configured to receive the first input voltage and the second input voltage; a current mirror circuit connected to the differential pair and the first node, A current corresponding to the differential voltage flows between the first node and the current mirror circuit as the first current by the current mirror circuit and the current generating circuit, and the first current increases in response to a change in the differential voltage in the predetermined direction.

3. The comparison circuit according to claim 2.

4. the current generating circuit includes a first current source and a second current source; the first node is provided between the first current source and the current mirror circuit, and the first current is generated based on a current generated by the first current source between the first current source and the first node; The second node is provided between the second current source and the insertion transistor, and the second current is generated based on a current generated by the second current source between the second current source and the second node.

4. The comparison circuit according to claim 3.

5. the insertion transistor is an N-channel field effect transistor having a gate that receives a predetermined bias voltage, a drain connected to the second node, and a source connected to the first node; When the insertion transistor is turned on based on a voltage drop of the first node, the second current including the generated current of the second current source flows through the insertion transistor toward the first node.

5. The comparison circuit according to claim 4.

6. In the process of the change of the differential voltage in the predetermined direction, the logical value of the first output signal is inverted based on a voltage drop of the first node, and then the logical value of the second output signal is inverted based on a voltage drop of the second node as the differential voltage further changes in the predetermined direction.

6. A comparison circuit according to claim 2.

7. the plurality of output signals includes a third output signal, the insert transistor is a first insert transistor, a third output circuit configured to generate the third output signal based on a voltage at a third node; a second insertion transistor inserted between the second node and the third node, the current generating circuit generates a third current flowing from the third node through the second insert transistor, the second node, and the first insert transistor based on a voltage drop of the second node accompanied by the generation of the second current, thereby adding the second current including the third current to the first current; When the third current is generated, the third current increases due to the change in the differential voltage in the predetermined direction; The third output circuit inverts a logical value of the third output signal in the process in which the voltage of the third node decreases with an increase in the third current.

3. The comparison circuit according to claim 2.

8. a differential pair configured to receive the first input voltage and the second input voltage; a current mirror circuit connected to the differential pair and the first node, A current corresponding to the differential voltage flows between the first node and the current mirror circuit as the first current by the current mirror circuit and the current generating circuit, and the first current increases in response to a change in the differential voltage in the predetermined direction.

8. The comparison circuit according to claim 7.

9. the current generating circuit includes a first current source, a second current source, and a third current source; the first node is provided between the first current source and the current mirror circuit, and the first current is generated based on a current generated by the first current source between the first current source and the first node; The second node is provided between the second current source and the first insertion transistor, and the second current is generated based on a current generated by the second current source between the second current source and the second node; The third node is provided between the third current source and the second insertion transistor, and the third current is generated based on a current generated by the third current source between the third current source and the third node.

9. The comparison circuit according to claim 8.

10. the first insertion transistor is an N-channel type field effect transistor having a gate that receives a predetermined bias voltage, a drain connected to the second node, and a source connected to the first node; the second insertion transistor is an N-channel field effect transistor having a gate that receives the bias voltage, a drain connected to the third node, and a source connected to the second node; when the first insert transistor is turned on based on a voltage drop of the first node, the second current including the generated current of the second current source flows through the first insert transistor toward the first node; When the second insert transistor is turned on based on a voltage drop of the second node, the third current including the generated current of the third current source flows to the first node via the second insert transistor, the second node, and the first insert transistor.

10. The comparison circuit according to claim 9.

11. In the process of the change of the differential voltage in the predetermined direction, the logical value of the first output signal is inverted based on a voltage drop at the first node, and then the logical value of the second output signal is inverted based on a voltage drop at the second node as the differential voltage further changes in the predetermined direction, and thereafter, the logical value of the third output signal is inverted based on a voltage drop at the third node as the differential voltage further changes in the predetermined direction. A comparison circuit according to any one of claims 7 to 10.

12. the plurality of output signals includes a third output signal, the insert transistor is a first insert transistor, the predetermined orientation is a first orientation, and a second orientation is opposite to the first orientation; a third output circuit configured to generate the third output signal based on a voltage at a third node; a second insertion transistor inserted between the first node and the third node, A change in the differential voltage in the second sense causes a decrease in the first current; the first output circuit inverts a logical value of the first output signal from a first logical value to a second logical value in a process in which the voltage of the first node decreases with an increase in the first current, and inverts a logical value of the first output signal from the second logical value to the first logical value in a process in which the voltage of the first node increases with a decrease in the first current; the current generating circuit generates a third current flowing from the first node to the third node via the second insert transistor based on a voltage increase at the first node, thereby reducing the first current by an amount corresponding to the third current; When the third current is generated, the third current increases due to the change in the differential voltage in the second direction; The third output circuit inverts a logical value of the third output signal in a process in which the voltage of the third node increases with an increase in the third current.

3. The comparison circuit according to claim 2.

13. a differential pair configured to receive the first input voltage and the second input voltage; a current mirror circuit connected to the differential pair and the first node, A current according to the differential voltage flows between the first node and the current mirror circuit as the first current by the current mirror circuit and the current generating circuit, and the first current increases in response to a change in the differential voltage in the first direction, while the first current decreases in response to a change in the differential voltage in the second direction.

13. The comparison circuit according to claim 12.

14. the current generating circuit includes a first current source, a second current source, and a third current source; the first node is provided between the first current source and the current mirror circuit, and the first current is generated based on a current generated by the first current source between the first current source and the first node; The second node is provided between the second current source and the first insertion transistor, and the second current is generated based on a current generated by the second current source between the second current source and the second node; The third node is provided between the third current source and the second insertion transistor, and the third current is generated based on a current generated by the third current source between the third current source and the third node.

14. The comparison circuit according to claim 13.

15. the first insertion transistor is an N-channel type field effect transistor having a gate that receives a predetermined bias voltage, a drain connected to the second node, and a source connected to the first node; the second insertion transistor is a P-channel type field effect transistor having a gate that receives a predetermined other bias voltage, a drain connected to the third node, and a source connected to the first node; when the first insert transistor is turned on based on a voltage drop of the first node, the second current including the generated current of the second current source flows through the first insert transistor toward the first node; When the second insert transistor is turned on based on a voltage rise of the first node, the third current including the generated current of the third current source flows from the first node through the second insert transistor to the third node.

15. The comparison circuit according to claim 14.

16. In the process of the change of the differential voltage in the first direction, the logical value of the first output signal is inverted from the first logical value to the second logical value based on a voltage drop of the first node, and then the logical value of the second output signal is inverted based on a voltage drop of the second node as a result of the differential voltage further changing in the first direction; In the process of the change of the differential voltage in the second direction, the logical value of the first output signal is inverted from the second logical value to the first logical value based on a voltage rise of the first node, and then the logical value of the third output signal is inverted based on a voltage rise of the third node as the differential voltage further changes in the second direction. A comparison circuit according to any one of claims 12 to 15.

17. The first current decreases as the differential voltage changes in the predetermined direction, the first output circuit inverts a logical value of the first output signal in a process in which the voltage of the first node increases with the decrease in the first current; the current generating circuit generates the second current flowing from the first node to the second node via the insertion transistor based on a voltage increase at the first node, thereby reducing the first current by an amount corresponding to the second current; When the second current is generated, the second current increases due to the change in the differential voltage in the predetermined direction; The second output circuit inverts a logical value of the second output signal in a process in which the voltage of the second node increases with an increase in the second current.

2. The comparison circuit according to claim 1.

18. a differential pair configured to receive the first input voltage and the second input voltage; a current mirror circuit connected to the differential pair and the first node, A current corresponding to the differential voltage flows between the first node and the current mirror circuit as the first current by the current mirror circuit and the current generating circuit, and the first current decreases in response to a change in the differential voltage in the predetermined direction.

20. The comparison circuit of claim 17.

19. the current generating circuit includes a first current source and a second current source; the first node is provided between the first current source and the current mirror circuit, and the first current is generated based on a current generated by the first current source between the first current source and the first node; The second node is provided between the second current source and the insertion transistor, and the second current is generated based on a current generated by the second current source between the second current source and the second node.

20. The comparison circuit of claim 18.

20. the insertion transistor is a P-channel type field effect transistor having a gate that receives a predetermined bias voltage, a drain connected to the second node, and a source connected to the first node; When the insert transistor is turned on based on a voltage rise of the first node, the second current including the generated current of the second current source flows from the first node to the second node via the insert transistor.

20. The comparison circuit of claim 19.

21. In the process of the change of the differential voltage in the predetermined direction, the logical value of the first output signal is inverted based on a voltage rise of the first node, and then the logical value of the second output signal is inverted based on a voltage rise of the second node as the differential voltage further changes in the predetermined direction. A comparison circuit according to any one of claims 17 to 20.

22. the plurality of output signals includes a third output signal, the insert transistor is a first insert transistor, a third output circuit configured to generate the third output signal based on a voltage at a third node; a second insertion transistor inserted between the second node and the third node, the current generating circuit generates a third current flowing from the first node through the first insert transistor, the second node, and the second insert transistor to the third node based on a voltage rise of the second node accompanied by the generation of the second current, thereby reducing the first current by an amount of the second current including the third current; When the third current is generated, the third current increases due to the change in the differential voltage in the predetermined direction; The third output circuit inverts a logical value of the third output signal in a process in which the voltage of the third node increases with an increase in the third current.

20. The comparison circuit of claim 17.

23. a differential pair configured to receive the first input voltage and the second input voltage; a current mirror circuit connected to the differential pair and the first node, A current corresponding to the differential voltage flows between the first node and the current mirror circuit as the first current by the current mirror circuit and the current generating circuit, and the first current decreases in response to a change in the differential voltage in the predetermined direction.

23. The comparison circuit of claim 22.

24. the current generating circuit includes a first current source, a second current source, and a third current source; the first node is provided between the first current source and the current mirror circuit, and the first current is generated based on a current generated by the first current source between the first current source and the first node; The second node is provided between the second current source and the first insertion transistor, and the second current is generated based on a current generated by the second current source between the second current source and the second node; The third node is provided between the third current source and the second insertion transistor, and the third current is generated based on a current generated by the third current source between the third current source and the third node.

24. The comparison circuit of claim 23.

25. the first insertion transistor is a P-channel type field effect transistor having a gate that receives a predetermined bias voltage, a drain connected to the second node, and a source connected to the first node; the second insertion transistor is a P-channel field effect transistor having a gate that receives the bias voltage, a drain connected to the third node, and a source connected to the second node; when the first insert transistor is turned on based on a voltage rise of the first node, the second current including the generated current of the second current source flows from the first node through the first insert transistor to the second node; When the second insert transistor is turned on based on a voltage rise of the second node, the third current including the generated current of the third current source flows from the first node through the first insert transistor, the second node, and the second insert transistor to the third node.

25. The comparison circuit of claim 24.

26. In the process of the change of the differential voltage in the predetermined direction, the logical value of the first output signal is inverted based on a voltage rise of the first node, and then the logical value of the second output signal is inverted based on a voltage rise of the second node as the differential voltage further changes in the predetermined direction, and thereafter, the logical value of the third output signal is inverted based on a voltage rise of the third node as the differential voltage further changes in the predetermined direction. A comparison circuit according to any one of claims 22 to 25.

27. A comparison circuit according to any one of claims 1 to 5, 7 to 10, 12 to 15, 17 to 20, and 22 to 25; a counter configured to increment or decrement a count value based on the plurality of output signals output from the comparison circuit; The counter determines a direction of change in the count value and an amount of change in the count value based on each logical value of the plurality of output signals. , counting circuit.

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