Low-noise ultra high-speed image sensor

Abstract

To realize 100ps or less of a temporal resolution against a visible light, a NIR, and 1200nm or less of a SWIR light by a multi framing image sensor with a Ge-on-Si structure so that a final target becomes 10ps, and additionally suppress a generation of a large dark current and a leakage current in accordance with the image sensor with the Ge-on-Si structure.SOLUTION: A low-noise ultra high-speed image sensor comprises three or more opens in an electric charge movement prohibition layer to a vertical direction formed by a p-well or an insulation layer for insulating a circuit spread layer and a photoelectric conversion layer. One means comprises each open at a position of an equivalent distance in a radiation direction from a pixel center, and comprises a vertical type transfer gate reached to each open so as to penetrate the photoelectric conversion layer. Also, the electric charge movement prohibition layer and a fixing electric charge layer are laminated, and a plurality of small holes which is 25 nm or less penetrating them is provided.SELECTED DRAWING: Figure 9

Description

[Technical field]

[0001] This patent relates to technology for simplifying the structure of image sensors and suppressing dark current for ultra-high speed photography.

[0002] In particular, the project relates to achieving higher speeds and lower noise in ultra-high-speed image sensors with a Ge-on-Si structure in which germanium photodiodes (Ge PDs) are mounted on silicon (Si) circuits. [Background technology] Super Time Resolution

[0003] There is a practical upper limit to the time resolution that can be achieved by an image sensor, which is called the time resolution limit.

[0004] In a typical image sensor, signal electrons generated by a photodiode (PD) are transferred vertically within the PD.

[0005] The inventors derived an equation for the time resolution limit when signal electrons are transferred vertically inside a PD, and proposed that a time resolution shorter than the time resolution limit is called super-temporal-resolution (STR) (Non-Patent Document 1).

[0006] The formula for the ultimate time resolution includes several parameters that represent the drift velocity and diffusion coefficient of charges in the PD material, the properties of light, etc. One of them is the absorption coefficient of the PD for the wavelength of the incident light (1 / average penetration depth).

[0007] Historically, a great number of measurements of the absorption coefficient have been reported.

[0008] 550 nm is commonly used as a representative wavelength of visible light.

[0009] When the data on the absorption coefficient and average penetration depth of 550 nm light for silicon (Si) are unified and displayed as the average penetration depth, they are distributed over a wide range from 0.85 μm to 1.73 μm. The average of the two values ​​is 1.29 μm. The average value of most existing data is also close to this value.

[0010] The value of 1.73 μm was taken from a table of values ​​disclosed in Non-Patent Document 2. Most of the data on the absorption coefficient and average penetration depth are given in figures. Reading from a figure is unavoidable arbitrarily. Therefore, the value of 1.73 μm has been used as the average penetration depth of 550 nm light into Si.

[0011] Substituting 1.73 μm as the average penetration depth into the derived equation for the time limit resolution, the time limit resolution for the SiPD and 550 nm light becomes 11.1 ps.

[0012] However, non-patent document 2 is currently inaccessible.

[0013] Non-Patent Document 3 also discloses a numerical table showing the relationship between wavelength and absorption coefficient for Si. The average penetration depth is estimated based on this table.

[0014] According to this table, the absorption coefficient for 550 nm light is 6.39E+03 (1 / cm) at 300° K. The reciprocal of this coefficient, the average penetration depth, is 1.56 μm.

[0015] Figure 1 is a diagram of the numerical table in Non-Patent Document 3, drawn by the author of the table.

[0016] 1.56 μm is also the maximum value of the average penetration depth shown by existing data (excluding the value in Non-Patent Document 2). Therefore, if the limit time resolution is estimated from this value, it may be slightly excessive. However, since 6.39E+03 (1 / cm) is given as a numerical value, 1.56 μm will be used as the average penetration depth from this patent application onwards.

[0017] For ultrafast imaging, we assume a high electric field corresponding to the saturated drift velocity, where the limiting time resolution is approximately inversely proportional to the drift velocity V and proportional to the thickness W of the PD.

[0018] The relationship between the equation for the time resolution limit and the diffusion coefficient in the transport direction (longitudinal diffusion coefficient) D is nonlinear. However, at high electric fields close to the saturated drift velocity, the longitudinal diffusion effect becomes smaller than the drift effect. Therefore, if high accuracy is not required, the time resolution limit is proportional to the average penetration depth.

[0019] Therefore, the time resolution limit when the average penetration depth is 1.56 μm is estimated from the time resolution limit of 11.1 ps when the average penetration depth is 17.3 μm. The result is 10.0 ps (= 11.1 × 1.56 / 1.73). Therefore, in this specification, a time resolution of 1.00 ps or less is defined as STR.

[0020] Incidentally, if an average penetration depth of 1.29 μm is used, the limiting time resolution is estimated to be approximately 8.28 ps (= 11.1 × 1.29 / 1.73).

[0021] Thus, the time resolution limit estimated from past experimental values ​​has a large margin of error, about 30% above and below. However, even if the time resolution limit value changes by this amount, there is no contradiction in the magnitude relationship used as the basis for the following logical development.

[0022] In Non-Patent Document 5, the average penetration depth of 550 nm light into Ge is 0.02 μm. I was unable to find a comprehensive table of values ​​showing the relationship between wavelength and absorption coefficient for Ge. Therefore, I estimated the value of 0.02 μm from a diagram showing the relationship between wavelength and absorption coefficient for Ge that was posted on the Internet.

[0023] Based on the above, in this patent application, the average penetration depth of 550 nm light into Si and Ge is set to 1.56 μm and 0.02 μm. 95% saturated drift velocity

[0024] Figure 2 shows the relationship 100 between the electric field E and the drift velocity V for Si (Figure 9 in Non-Patent Document 5). The relationship between E and V for Ge is also shown.

[0025] The drift velocity increases monotonically with respect to the electric field, and as it approaches the saturated drift velocity, the gradient becomes almost 0. Therefore, there is a great deal of arbitrariness in estimating the electric field corresponding to the saturated drift velocity from the relationship diagram between the electric field and the drift velocity.

[0026] Therefore, we decided to call the electric field at 95% of the saturated drift velocity the "saturation electric field." We also defined the drift velocity at this saturation electric field (95% saturated electric field) as the new "saturation drift velocity."

[0027] In this case, the saturation electric field and saturation drift velocity of Si are estimated to be 25 kV / cm (= 2.5 V / μm) and 0.091 μm / ps, respectively, and those of Ge are estimated to be 4 kV / cm (= 0.4 V / μm) and 0.058 μm / ps.

[0028] Errors also occur when reading values ​​such as the saturated drift velocity. However, even if these values ​​change slightly, there is no contradiction in the magnitude relationships used as the basis for the following logical development.

[0029] At this time, the ratio of the saturated drift velocities of Si and Ge is about 3 / 2 (=0.091 / 0.058). The saturated electric field ratio is about 6 times (≒25 / 4). Lattice constants of silicon crystals and germanium crystals and interface defects

[0030] The lattice constants of Si and Ge at 300°K are 0.54310 nm and 0.56754 nm. Thus, the lattice constant of Ge is 4.5% larger than that of Si.

[0031] This causes two types of crystal defects (dislocations) to occur at the crystal interface between Si and Ge.

[0032] One is a large-scale threading dislocation, which extends from the interface between Ge and Si to the Ge side in a string or ribbon shape, and thus generates very large dark currents and traps. The other is a misfit dislocation, in which the connection between atoms is broken.

[0033] Of these, threading dislocation can be reduced by controlling the temperature during and after the growth of the Ge crystal on the Si crystal.

[0034] For example, the Ge crystal is grown at a low temperature of about 250°C until the thickness is 20 nm. After that, it is grown at about 700°C. This reduces the density of threading dislocations.

[0035] Furthermore, after the Ge crystal growth, the temperature is raised and lowered multiple times between about 200°C and about 700°C, which causes the threading dislocations to coalesce and move.

[0036] The threading dislocations that move in the horizontal direction are restricted in their movement near the vertical oxide film provided on the end face of the Ge PD.

[0037] This temperature control technology can reduce the spatial density of threading dislocations in the center of the PD through which signal electrons pass.

[0038] Currently, the spatial density of threading dislocations can be reduced to less than one per square meter.

[0039] The pixel size of modern image sensors is on the order of 1 micron, so the probability of threading dislocations per pixel can be made smaller than 1.

[0040] As a practical solution, the image signal of a pixel where a large dark current occurs due to threading dislocation can be ignored, and the image signal can be interpolated using the average value of the image signals of the four surrounding pixels.

[0041] In this way, by reducing the spatial density of threading dislocations and moving them horizontally toward the PD end face, the effects of very large dark currents caused by threading dislocations can be practically avoided.

[0042] Misfit dislocations are also reduced by temperature control. However, the size of misfit dislocations is the interatomic distance, that is, on the order of 1 nm. Therefore, it is on a different scale from the size of PDs, which is about 1 μm. Therefore, it will not be eliminated even if the PDs are reduced. Bonding of the Si layer and the Ge layer at nanoholes opened in a thin silicon dioxide layer

[0043] Figure 3 is a figure quoted from Non-Patent Document 6. This figure shows the arrangement of atoms at the interface between Si and Ge observed by TEM.

[0044] A silicon dioxide layer with a thickness of less than a few atomic layers is formed on the surface of the Si layer. Holes with a diameter of a few nm are drilled in this layer. A Ge layer is grown from the exposed surface of the Si layer.

[0045] In Figure 3, misfit dislocations are seen at the interface between Ge and Si. However, several Si atoms in a region 101 of at least 3 nm near the center of the hole appear to be directly connected to Ge atoms. Thus, as the aperture scale approaches the interatomic distance scale, the probability of misfit dislocation generation is expected to decrease.

[0046] On the other hand, at the edge of the opening, a discontinuity of crystals is observed over a width of several atomic layers. Although not shown in Fig. 3, the silicon dioxide layer outside the opening and its upper and lower surfaces are not crystallized at all.

[0047] When the upper Ge layer is used as a photoelectric conversion layer, the non-crystalline regions between the edge of the silicon dioxide opening and the top and bottom surfaces of the silicon dioxide layer become regions where a very large dark current and signal electron traps and re-emissions occur. Dangling bonds and fixed charge layer

[0048] The surface of the PD in a typical Si image sensor is protected by a thin layer of oxide made of silicon dioxide. Most of the Si atoms in the layer at the boundary between the Si layer and the oxide film are dangling bonds.

[0049] Hydrogen gas is supplied to the unbonded silicon atoms at the interface to terminate the dangling bonds with hydrogen, a standard technique.

[0050] Furthermore, in order to suppress the influence of the defect region near the interface, a technique is used to locally form a negative potential near the interface, which reduces the probability that the signal electrons approach the interface. Two techniques are generally used for this purpose:

[0051] One is the implantation of boron ions into the boundary region.

[0052] The other is the lamination of a thin layer with a fixed charge, such as aluminum oxide or hafnium dioxide, on the silicon oxide film at the interface (Patent Document 4, Non-Patent Document 7). The two technologies may be used together. Single-storey multi-framing image sensor

[0053] Patent Documents 1 and 2 disclose one form of pixel for a multi-framing image sensor. In this form, a relatively large opening is provided at the center of the p-well under the PD. Three or more planar transfer gates (TG) are provided on the circuit diffusion layer, arranged in a radial direction from this opening. Signal electrons generated by the photoelectric conversion means are sequentially passed over these TGs and stored in analog memories equidistant in the radial direction from the pixel center. This makes it possible to capture a number of consecutive images equal to the number of TGs at very short time intervals.

[0054] Using an image sensor with this pixel structure, we succeeded in capturing continuous images of flying light for the first time using an image sensor (Non-Patent Document 8).

[0055] Patent Document 3 discloses the pixel structure of an image sensor shown in Fig. 4. Fig. 4(a) is a plan view, and Fig. 4(b) is a cross-sectional view taken along dashed line 103 in Fig. 4(a). This structure is an evolved form of the pixel structures disclosed in Patent Documents 1 and 2, which have been simplified.

[0056] The sensor chip typically includes a PD 104, TGs 105, 106, and 107, and readout circuits (Output Circuits, OCs) 108, 109, and 116.

[0057] As shown in FIG. 4(c), the OC typically includes a floating diffusion (FD) 110 for voltage conversion of signal charges, a reset gate (RS) 111, and a reset drain (RD) 112.

[0058] The PD 104 and the single-electrode vertical TGs 105, 106, and 107 of the sensor chip shown in Fig. 4 are arranged in the same plane space as shown in Fig. 4(b). Therefore, this sensor structure is called a "single-storey type."

[0059] In this sensor, the PD, TG, FD, etc. are all made of Si semiconductors.

[0060] The sensor section is also characterized by having N single-electrode vertical TGs, where N=16 in this case.

[0061] During imaging, a high voltage VH is applied to one TG 105, and a low voltage VL is applied to the remaining 15 TGs 106 and 107. Signal electrons generated by the PD are collected by the TG 105 to which VH is applied, and are converted to voltage by the FD 110 in the OC 108 outside the PD area.

[0062] By changing the TG 105 that applies VH to one of the TGs 106 that applies VL, it is possible to sequentially collect 15 consecutive image signals at the shortest possible time intervals and temporarily store them on a FD.

[0063] One TG107 is used as a drain readout circuit OC116. In other words, RS111 of this OC is always kept at a high voltage VH. VH is applied to TG107, which is in front of the RS of OC116. As a result, electrons generated by dark current and leakage current generated in the PD after shooting are continuously discharged outside the sensor from the RD connected to TG107.

[0064] After shooting, the voltages of the other TGs 105 and 106 are fixed to VL. Therefore, all dark currents generated in the PDs are discharged from the drain to the outside of the image sensor.

[0065] The potential difference before and after the inflow of the signal electronic packets of the 15 FDs 110 is current-amplified and transferred to the junction chip as an image signal.

[0066] As shown in FIG. 5, an actual image sensor is constructed by bonding a chip 152 having a driving circuit 114 and a chip 153 having an image signal processing circuit 115 to the lower part of a sensor chip 113.

[0067] The drive circuit generates a drive voltage for driving the sensor unit. The image signal processing circuit temporarily stores the image signal obtained by shooting, processes the signal, and transfers it to outside the image sensor.

[0068] The image signal voltage-converted by the FD is transferred to an image signal processing circuit 115 through metal wiring (not shown in the figure).

[0069] In the single-storey type, the depth (width) of the PD 104 and the TGs 105, 106, and 107 are substantially the same. In this case, as shown in Figure 4(b), the transfer direction of the signal electrons in the PD is horizontal. This minimizes the signal transfer time in the PD.

[0070] However, a TG with the same height and width as the PD increases the RC delay of the driving voltage. Here, R and C are the electrical resistance and capacitance of the TG. The technology to reduce the RC delay will be discussed later.

[0071] The TG that has VH applied to it is then subjected to VL the next moment. Therefore, once a signal electron leaves a TG, it cannot return to the PD via that TG.

[0072] The upper limit of the drift velocity is determined by the saturated drift velocity. Therefore, if the aim is to achieve the maximum drift velocity, the time resolution of the one-story structure shown in Fig. 4 is determined by the distance until the electron exits the PD, i.e., the diameter 102 of the PD.

[0073] The minimum diameter of a PD is determined by the diffraction limit. For example, for 550 nm light, it is between 250 nm and 500 nm. However, to achieve 250 nm, a special optical system such as an immersion lens is required. Therefore, in the following, the practical diffraction limit for 550 nm light is set to 500 nm.

[0074] When the single-storey image sensor has an all-Si structure, the average penetration depth of 550 nm light is 1.56 μm. The diffraction limit for 550 nm light is about 500 nm. Therefore, the diffraction limit is about 1 / 3 of the average penetration depth (=500 nm / 1.56 μm).

[0075] The direction of transfer of signal electrons in the flat-story structure is horizontal. In the case of silicon, the drift velocity is almost the same whether the transfer is vertical or horizontal.

[0076] In deriving the STR condition, it was assumed that the signal electrons were vertically transferred at the saturated drift velocity through a PD with a thickness equal to the average penetration depth of light. It is reasonable to define the limiting time resolution in the one-story structure shown in Fig. 4 as the time resolution when the signal electrons are horizontally transferred at the saturated drift velocity through a PD with a diameter equal to the diffraction limit of light. Therefore, the limiting time resolution in this case is approximately 1 / 3 of the STR derived for a PD with vertical transfer.

[0077] Therefore, even with an all-Si structure, by using a single-story design, it is possible to achieve STR for the transfer time in PD.

[0078] In this case, however, the width of the TG is on the same order of magnitude as the average penetration depth of 550 nm light, which we will call 1.56 μm. On the other hand, the size of circuit elements used in regular image sensors is on the order of tens to hundreds of nanometers. Therefore, the TG of 1.56 μm is one to two orders of magnitude larger than the size of regular circuit elements.

[0079] The electrical resistance R and capacitance C of the TG alone are proportional to the width. Therefore, in the single-storey type of Figure 4, the RC delay of the TG, which is their product, is very large. Therefore, in a single-storey type pixel with an all-Si structure, the RC delay in sending the drive voltage becomes a major limiting factor in suppressing the time resolution. Ge-on-Si structure two-storey multi-framing image sensor

[0080] 6, a Ge PD 119 is placed on a Si semiconductor layer 118. This is a so-called "two-story type."

[0081] In a two-storey structure, STR can be easily achieved by replacing the normal Si PD with a Ge PD. There are two reasons for this. One is the shortening of the vertical transfer time of the signal electrons in the PD. The other is the shortening of the RC delay of the TG in the Si circuit diffusion layer. These are explained below.

[0082] The average penetration depth of 550 nm light into Si is 1560 nm, and into Ge it is 20 nm. Therefore, the thickness of a Ge PD is about 1 / 78 of that of a Si PD. As shown in Figure 2, there is no significant difference in the saturated drift velocity between Ge and Si.

[0083] Therefore, for 550 nm light, the vertical transfer time in a Ge PD is about two orders of magnitude shorter than that in a Si PD.

[0084] The STR (<10.0 ps) was derived for an average penetration depth of 1.56 μm for 550 nm light in Si. As shown in Figure 2, the saturated drift velocity of Ge is about 2 / 3 that of Si. On the other hand, the average penetration depth of NIR and SWIR (shortwave infrared) light below 1,200 nm in Ge is less than 1 μm (=1.56×2 / 3). Therefore, the Ge PD can realize the STR for these incident light as well.

[0085] In the single-story type, if the PD is also made of Si, this Si layer has two functions: photoelectric conversion and horizontal transfer of signal electrons. On the other hand, in the two-story type shown in Figure 6, photoelectric conversion is essentially completed by the Ge PD. Therefore, the role of the Si layer is only to transfer the signal electrons horizontally.

[0086] For example, when the diameter of the PD is set to 500 nm, which is the diffraction limit, the thickness of the Si layer can be set to about 200 nm, which is one order of magnitude smaller than 1.56 μm.

[0087] As shown in Fig. 6, the width (depth) of the TG is the same as the thickness 118 of the Si layer. The RC delay when driving the TG is proportional to the product of R and C. Therefore, the RC delay of the TG originating from the TG, excluding the RC of the driver and wiring, is about two orders of magnitude smaller than the RC delay in the all-Si single-story case of Fig. 4.

[0088] Therefore, for a two-story Ge-on-Si sensor chip, neither the vertical transfer time in the PD nor the RC delay in driving the TG is a major constraint in achieving STR.

[0089] However, even in the single-story type of Figures 4 and 5, if the PD 104 is Ge, the width of the TG (= the thickness of the PD) becomes thinner for visible light and NIR light. Therefore, both R and C become smaller, and due to a synergistic effect, the RC delay is no longer a major obstacle to realizing STR. Moreover, as shown in Figure 2, the electric field required to achieve a certain drift speed for a Ge PD is about half that for a Si PD. Number of continuous shots, dark current, and readout noise in ultra-high-speed shooting

[0090] When aiming for STR photography with a multi-framing image sensor, the issues of readout noise from pixels and dark current are greatly reduced.

[0091] In a multi-framing image sensor, the acquired signal electron packets are stored on the spot in the in-pixel memory located closest to the photoelectric conversion layer of each pixel. Therefore, the read (transfer) noise associated with transfer from the PD to the in-pixel memory is sufficiently small. In addition, the signal transfer speed from the in-pixel memory after shooting can be made sufficiently slow, so the read noise from the sensor chip to the bonded chip, etc. is also small. In particular, when the sensor is cooled, the read noise can be reduced to less than one electron.

[0092] The shooting speed of a typical video camera is between 30 fps (frames per second) and 120 fps. In order to compare the order of the dark current, a representative value is set to 100 fps (time resolution 10 ms).

[0093] The maximum shooting speed that can be achieved with a normal parallel continuous readout high-speed image sensor is about 1Mfps (time resolution 1μs). However, with a parallel continuous readout image sensor, the shooting speed and the number of pixels are inversely proportional. The number of pixels at the maximum shooting speed is about 1000 pixels (30 x 30 pixels). This spatial resolution is insufficient for many imaging applications.

[0094] The maximum imaging speed required to ensure practically effective spatial resolution is approximately 100 kfps (temporal resolution 10 μs).

[0095] With a multi-framing image sensor, the number of consecutive shots is small, ranging from a few to around 100. Therefore, the shooting speed range in which a multi-framing ultra-high-speed image sensor must be applied is a speed range in which it is difficult to shoot with a parallel continuous readout image sensor, that is, the shooting speed range in which the time resolution is from 10 μs to STR (10 ps).

[0096] In this case, the dark current per frame of the multi-framing image sensor is 1 / 1,000 (=10 μs / 10 ms) to 1 / 1,000,000,000 (=10 ps / 10 ms) of the dark current per 10 ms (100 fps).

[0097] Therefore, the higher the shooting speed, the smaller the dark current per pixel.

[0098] Furthermore, in order to increase the shooting speed of a continuous readout image sensor, it is necessary to increase the speed at which image signals are read out from each pixel to the outside of the sensor, which further increases noise.

[0099] Furthermore, in ultra-high-speed shooting, multi-framing image sensors are also advantageous in terms of spatial resolution: in other words, in a multi-framing image sensor, the number of pixels (spatial resolution) is constant regardless of the shooting speed.

[0100] As described above, the parallel continuous readout image sensor is advantageous in terms of the number of continuous shots that can be taken, while the multi-framing image sensor is far more advantageous in terms of shooting speed, spatial resolution (number of pixels), and noise level.

[0101] In the near future, the number of bonded image sensor chips will increase. In fact, digital circuits may have as many as 10 bonded chips. Increasing the number of bonded memory chips will also increase the number of continuous shots that can be taken by a multi-framing image sensor. Two-level image sensor with vertical transfer gates that reach the p-well

[0102] In the pixel structures disclosed in Patent Documents 1 and 2, the upper photoelectric conversion layer and the lower circuit diffusion layer are separated by a p-well. An opening (hole) is provided in the p-well to transfer signal electrons generated in the photoelectric conversion layer to the circuit diffusion layer. In this case, the area of ​​the opening and the very weak p region around it is large.

[0103] 7, in Patent Document 5, a p-well 122 of p-type is provided between an n-type photoelectric conversion layer 120 and a p-type circuit diffusion layer 121. Such a layer that limits charge transfer in the vertical direction is called a "charge transfer limiting layer."

[0104] In this example, an opening 124 made of p-minus is provided in the charge transfer limiting layer made of p-well. Furthermore, a vertical TG 123 is passed through this opening. The TG is insulated by an oxide film 127.

[0105] When a high voltage is applied to the TG, the potential of the p-minus region 124 around the TG becomes higher than the potential of the n-type photoelectric conversion layer. At this time, signal electrons 126 generated by incident light 125 on the photoelectric conversion layer pass through the p-minus region 124 and are guided to the circuit diffusion layer 121 along the periphery of the TG.

[0106] Compared to the area of ​​the opening and the very weak p-region around it in Patent Documents 1 and 2, the area of ​​the opening 124 required to pass the vertical TG 123 through the opening 124 and apply a positive voltage to, so to speak, force the passage of electrons can be much smaller. This allows the pixel area to be reduced.

[0107] On the other hand, the interface between the insulating layer around the vertical through-type TG and the external Si layer is a defect layer, which causes dark current. However, this problem can be mitigated by inserting a fixed charge layer around the TG.

[0108] On the other hand, in the structures of Patent Documents 1 and 2, there is no insulating layer around the opening, and therefore no dark current or traps arisen from defects at the interface between the Si layer and the insulating layer. [Prior art documents] [Patent documents]

[0109] [Patent Document 1] Patent No. 6188679, date of registration August 10, 2017, non-privileged person: Goji Eto, inventors: Goji Eto, Tetsuo Yamada, Vu Truong Son, Dao [Patent Document 2] Patent No:US9,503,663 B2,Nov.22,2016,Applicant:Takeharu Etoh,Inventors:Takeharu Etoh;Tetso Yamada;Dao Vu Truong Son. [Patent Document 3] Patent application 2023-76972, filing date May 8, 2023, applicant: Hideki Muto, inventors: Hideki Muto, Goji Eto, Edoardo Charbon [Patent Document 4] Patent No. 5136081, Registration date November 22, 2012, Patent holder: Sony Corporation, Inventor: Tomoyuki Hirano [Patent Document 5] Patent No. 5401928, Registration date November 8, 2013, Patent holder: Sony Corporation, Inventor: Akihiro Yamada [Non-patent literature]

[0110] [Non-Patent Document 1] TGEtoh,et al.,The Theoretical Highest Frame Rate of Silicon Image Sensors,Sensors,vol.17,No.3,483,2017. [Non-Patent Document 2] MHJones and SHJones, Optical Properties of Silicon, Virginia Semiconductor, Inc. (accessed on 13 January 2017:no more accessible). [Non-Patent Document 3] MAGreen,Self-consistent optical parameters of intrinsic silicon at 300 K including temperature coeffificants,Solar Energy Materials & Solar Cells,Vol.92,No.11,1305-1310(2008). [Non-Patent Document 4] Handbook of Optical Constants of Solids, edited by Edward D. Palik, Academic Press Inc., (1985). [Non-Patent Document 5] Goji Eto, History and Prospects of Ultrafast Camera Development, Applied Physics, Vol. 90, No. 6, pp. 332-338, 2021. [Non-Patent Document 6] Qiming Li, et al., Morphological evolution and strain relaxation of Ge islands grown on chemically oxidized Si(100) by molecular-beam epitaxi, Journal of Applied Physics, Vol. 98, No. 7, 073504 (2005). [Non-Patent Document 7] Masami Uemura, Masashi Sanka, Tatsuya Naito, Reduction of dark current in back-illuminated CMOS image sensors using an Al2O3 fixed charge layer, Proceedings of the 63rd Spring Meeting of the Japan Society of Applied Physics, 20a-S422-12, 2016. [Non-Patent Document 8] TGEtoh,et al.,Light-in-Flight Imaging by a Silicon Image Sensor:Toward the Theoretical Highest Frame Rate,Sensors,Vol.19,No.10,2247(2019). Summary of the Invention [Problem to be solved by the invention]

[0111] This solves two problems.

[0112] Patent Document 3 discloses a one-story multi-framing image sensor using a vertical TG as shown in Fig. 4. In this invention, vertical TGs 105, 106, and 107, in-pixel memories, and readout circuits OC108, 109, and 116 to outside the pixel are located outside the light receiving surface when viewed in a plan view. Therefore, the pixel size is increased by the area of ​​the circuit elements outside the light receiving surface.

[0113] A first object of the present invention is to reduce the pixel size of a multi-framing image sensor while taking advantage of the advantages of a vertical TG.

[0114] Non-Patent Document 5 and others disclose a multi-framing image sensor with a Ge-on-Si structure. This image sensor can achieve STR for visible light, NIR, and SWIR light of 1200 nm or less.

[0115] The second issue is how to suppress dark current caused by crystal defects at the interface between the Ge PD photoelectric conversion layer and the Si circuit diffusion layer.

[0116] The solution to the first problem is as follows.

[0117] In a pixel formed by laminating an n-type or p-type photoelectric conversion layer, a charge transfer limiting layer made of a semiconductor of the opposite type to that of the photoelectric conversion layer, and a circuit diffusion layer, the pixel is provided with m (m≧3) charge transfer prohibition layer openings that penetrate the circuit diffusion layer vertically and are positioned at equal distances in the radial direction from the center of the photoelectric conversion layer, and a vertical TG that reaches each of the openings.

[0118] The effects of the means for solving the first problem are as follows. In the pixel structure having the vertical TG disclosed in FIG. 4, circuit elements such as the vertical TG and the readout circuit OC are arranged outside the photoelectric conversion layer. By the means for solving the first problem, these circuit elements are arranged below the photoelectric conversion layer. Therefore, the aperture ratio can be made 100% or close to 100%. Therefore, an on-chip microlens for collecting light is substantially unnecessary. Also, the number of pixels can be increased for the same light receiving area.

[0119] The means for solving the second problem is as follows.

[0120] In a pixel formed by laminating a photoelectric conversion layer, a charge transfer restriction layer made of an oxide film, and a circuit diffusion layer, the charge transfer inhibition layer is provided with m (m>>3) minute openings, and a layer that generates a repulsive force against signal charges is provided in the non-opening portion.

[0121] The effect of the means for solving the second problem is as follows. If the aperture size and the aperture pitch are substantially 25 nanometers or less, the generation of threading dislocations originating from the apertures is suppressed. In addition, since the minimum node of the recent image sensor process is about 20 nanometers, if the aperture size is about the same, it will contribute to the practical application of the present invention. Furthermore, if it is 10 nanometers or less, the generation of misfit dislocations is also suppressed, which is even more preferable.

[0122] In addition, the layer in the non-aperture portion that generates a repulsive force against the signal charges prevents the signal charges from approaching the crystal defect layers above and below the charge transfer inhibition layer portion and at the edge of the aperture, thereby suppressing the large dark current and the trapping and re-emission of signal electrons caused by these defect layers.

[0123] For the photoelectric conversion layer, if germanium or InGaAs is used instead of silicon, STR can be realized for incident light up to about 1200 nm. In addition, when the signal charge is electrons, a fixed charge layer such as aluminum oxide or hafnium oxide, or a boron ion layer implanted around a silicon oxide layer is suitable as a layer that generates a repulsive force. [Brief description of the drawings]

[0124] [Figure 1] Relationship between wavelength and absorption coefficient of silicon [Diagram 2] Electric field vs. drift velocity in silicon and germanium. [Diagram 3] TEM image of Ge crystals grown from small holes drilled in a thin oxide layer on a Si crystal [Figure 4] Plan view and cross-sectional view of a pixel of an image sensor disclosed in Patent Document 3 [Diagram 5] Cross-sectional view of one pixel of a multi-framing image sensor with a bonded chip [Figure 6] Cross-section of one pixel of a Ge-on-Si multi-framing image sensor [Figure 7] Cross-sectional view of a pixel of an image sensor disclosed in Patent Document 5 [Figure 8] One pixel of the image sensor according to the first embodiment of the present invention [Figure 9] One pixel of the image sensor according to the second embodiment of the present invention [Figure 10] FIG. 2 is an explanatory diagram of a charge transfer limiting layer according to a second embodiment of the present invention; [Figure 11] FIG. 1 is an explanatory diagram of a photographing device according to the present invention; DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS First embodiment: Structure of the first embodiment

[0125] 8 is a diagram for explaining the first embodiment of the present invention. This diagram shows one pixel of the sensor chip of the first embodiment. The first embodiment is made of a Si semiconductor.

[0126] Figure 8(a) shows a plan view 128. Figure 8(b) 129 and Figure 8(c) 130 show cross-sectional views along dotted lines 131 and 132 shown in the plan view of Figure 8(a).

[0127] 8(b) and 8(c), the upper surface is the light receiving surface 133. The sensor chip is composed of, in order from the top, a protection layer 134 made of silicon oxide, a photoelectric conversion layer 135 basically made of n-type Si, a charge transfer limiting layer 136 made of p-type Si, a p-type circuit diffusion layer 137, and a wiring layer 138 made of wiring in silicon oxide.

[0128] The photoelectric conversion layer 135 is composed of an n-minus layer 139, an n-plus layer 140, and a p-layer 141 doped with boron ions on the surface.

[0129] Eight vertical TGs 142 are made of polysilicon. The eight TGs are arranged at equal radial distances from the center of the photoelectric conversion layer in the horizontal direction. In the vertical direction, they penetrate the circuit diffusion layer 137 and reach the charge transport limiting layer 136. The TGs are insulated by a thin silicon oxide layer 143. Most of the charge transport limiting layer is p-positive. However, the concentration of the part 144 that the TGs reach is p-negative.

[0130] A storage gate (SG) 156 for storing signal electronic packets is disposed outside each TG.

[0131] 8(a), one of the four corner portions 157 is indicated by a dotted circle. The corner portion is provided with an output gate (OG) 145, an FD 146, a reset gate (RS) 147, and a reset drain (RD) 148.

[0132] The center of the pixel is provided with a center drain (CD) 149. A p-plus layer 150 on the CD electrically separates the CD from the circuit diffusion layer.

[0133] TG, OG, FD, RS, RD, SG, and CD are electrically connected to bonding chips 152 and 153 (shown in FIG. 5) by copper wiring 151. Holes are discharged from the front surface side by aluminum wiring 154 from electron-hole pairs generated by incident light.

[0134] In addition, a p-type separation layer 155 is provided to prevent crosstalk between successive image signals.

[0135] Description of circuits 114, 115 in bonded chips 152, 153 in FIG. 5 is omitted in normal patent documents relating to the sensor portion of an image sensor, and therefore is also omitted in this specification.

[0136] The sensor in FIG. 8 is intended for imaging using visible light with wavelengths from 450 nm to 650 nm.

[0137] The pixel size is 10 μm×10 μm. The silicon dioxide protective film 134 is 10 nm thick. The Si photoelectric conversion layer 135 is 7 μm thick. The charge transfer limiting layer 136 is 0.5 μm thick. The circuit diffusion layer 137 is 1 μm thick. The wiring layer 138 is 0.5 μm thick.

[0138] Therefore, the total thickness of the Si layers is 8.5 (=7+0.5+1) μm.

[0139] A voltage of −10 V is applied to the incident surface 133 through the contact 154. In addition, 0 V is applied to the reset drain RD 148 and the center drain CD 149.

[0140] During shooting, 3 V is applied as VH to the vertical transfer gate TG142, and 1 V is applied as VL.

[0141] Therefore, an electric field of about 1.43 V / μm (≒ (3-(-10)) / 7) is applied to the photoelectric conversion layer. This value is about 60% of the saturation electric field of intrinsic silicon, 2.5 V / μm (see Figure 2).

[0142] The reason why it is lower than the saturation electric field is as follows. The lower layer of the photoelectric conversion layer is doped with n-type impurities. Therefore, the saturation electric field is smaller than that of an intrinsic Si layer. Also, at the saturation electric field, the dark current and leakage current become large.

[0143] At the start of shooting, VH is applied to the eight storage gates SG156 and VL is applied to the eight TG142. The voltages of the eight outputs OG145 are constant.

[0144] At the moment when shooting starts, the voltage applied to one TG is changed from VL to VH. Signal electrons generated by incident light move on the charge transfer limiting layer toward the TG to which VH has been applied. Next, they move to the circuit diffusion layer 137 through the p-negative region 144 on the side of the TG. Next, they move to the upper layer on the bottom surface of the TG. Next, they move to the storage gate SG156 adjacent to the TG. Next, the voltage of the TG is returned to VL. As a result, one signal electron packet is temporarily stored on the SG.

[0145] By sequentially applying VH to the remaining seven TGs and then returning them to VL, signal electronic packets are stored in the eight SGs, and eight consecutive image signals are stored on the sensor chip.

[0146] Next, the signal electronic packets stored in the eight SGs are voltage converted and transferred to the junction chip 153. This operation will be described below.

[0147] The corner portion 157 is provided with one set of FD 146, RS 147, and RD 148 for two OGs 145. This makes it possible to reduce the number of circuit elements in the signal readout section and the number of wires connected to each pixel, thereby enabling the pixel size to be reduced.

[0148] On the other hand, some ingenuity is required for the signal transfer operation to the junction chip. Immediately after shooting, VL is applied to one of the two SGs 156 immediately before one corner portion 157. The signal electron packet stored by the VH applied to the SG flows into the FD 146 over the potential barrier of the adjacent output gate OG 145.

[0149] The inflow of signal electronic packets causes the potential of the FD to drop. This potential change is current-amplified, converted into a voltage, and stored in memory area 115 (an example is shown in FIG. 5) on the junction chip 153. The above-mentioned technology for reading out signal electronic packets stored in one SG with the FD is a common technology in the image sensor field.

[0150] The same operation is repeated for the other one of the two OGs 145. As a result, the image signals held in the two SGs connected to the FD of one corner portion 157 are stored in the memory area 115 on the bonded chip 153. At that point, the remaining six image signals are still stored in the six SGs.

[0151] Immediately after the first two signals are read out, TG142, OG145, SG156, and RS147 connected to the corner portion 157 are fixed to VH. As a result, dark current generated in the photoelectric conversion layer 135 during the transfer of the remaining six image signals is discharged to the outside of the sensor chip via the corner portion 157. In other words, it functions as a drain.

[0152] The voltage of OG is kept constant. This is to suppress conversion errors in FD. The voltage of SG is kept at VH while it is being used as a drain path. Therefore, electrons that continue to be generated in the photoelectric conversion layer accumulate and become full. Any dark current that flows in after that will flow over OG and naturally flow out of RD.

[0153] While each gate voltage of the corner portion 157 is maintained under the above conditions, the remaining six image signal packets are successively read out to the bonded chip.

[0154] As a result of the above, eight image signals from each pixel on the sensor chip are sent to the bonding chip and recorded.

[0155] Thereafter, the image signals (number of pixels x 8) stored on the bonded chip are read out from the bonded chip to the outside of the image sensor at a sufficiently slow speed.

[0156] During the standby time just before shooting, the sensor chip must be depleted. During this time, the eight TGs and four RSs are set to VH. VH and VL are applied alternately to the eight SGs. This allows the dark current and leakage current that accumulates in the SGs to cross the adjacent OGs and be continuously removed from the RDs. This keeps the photoelectric conversion layer in a depleted state. It also prevents the accumulation of dark current in the SGs.

[0157] The voltage of CD is kept at VL during shooting, and at VH during standby. This prevents the accumulation of dark current in the circuit diffusion layer before shooting.

[0158] After the image is captured, the image signal stored in the image signal memory on the bonded chip is read out to the outside of the sensor chip.

[0159] As described above, in the first embodiment, ultra-high speed shooting is possible with a multi-framing operation at a substantially 100% aperture ratio.

[0160] The operation of the first embodiment is not limited to the above example.

[0161] When photographing a reproducible phenomenon, the photographing operation can be repeated to accumulate signal electrons on the SG.

[0162] In addition, when the joining chip has 16 or more analog or digital memories, it is possible to continuously send image signals to the joining memories to take 16 or more consecutive images.

[0163] In this case, the image signals temporarily stored in each SG need only be transferred to the bonded chip by the time it takes for signal electrons to be recorded in the remaining seven SGs. Therefore, theoretically, signals can be transferred from the SGs to the bonded chip in eight times the imaging time interval.

[0164] Even if the sensor chip has only one PD and readout circuit, it is possible to incorporate many memories into the bonded chip. However, the size of one pixel increases as the number of memories on the bonded chip increases.

[0165] This allows the sensor chip to have a multi-framing structure if the pixel area is large.

[0166] This allows the signal transfer rate from the sensor chip to the joining chip to be reduced in proportion to the number of frames on the sensor chip, while reducing the noise associated with the transfer inversely proportional to the square root of the transfer rate.

[0167] There are also embodiments that derive from the first embodiment.

[0168] The TG may be arranged in an equal distance from the center of the photoelectric conversion layer in m (m≧3) or more. This has the effect of increasing the number of images that can be captured, adding a drain function, and introducing a reference signal electronic packet.

[0169] The charge transfer limiting layer 136 and the circuit diffusion layer 137 may have the same p-type impurity concentration. In this case, the charge transfer limiting layer and the circuit diffusion layer become one layer. However, the small region 144 surrounding the TG is p-type to allow the passage of signal electrons. In this case, the voltage amplitude (VH-VL) of the TG needs to be very large to transfer the signal electrons.

[0170] The small region surrounding the TG is actually designed with intrinsic Si. During the process, the surrounding p-type impurities diffuse to the TG periphery, making it a p-negative region.

[0171] Moreover, the TG may be a metal instead of polysilicon.

[0172] However, in these derivatives of the first embodiment, it is necessary to adjust the design conditions to suppress crosstalk between eight consecutive image signals, suppress leak current, etc. The first embodiment can be designed and produced with almost no consideration for these adjustments.

[0173] Furthermore, the charge transfer limiting layer 136 may be an insulating layer, provided that the small area surrounding the TG is an opening in the insulating layer made of a semiconductor layer.

[0174] Even if the charge transfer limiting layer is an insulating layer, the area of ​​the opening region 144 for charge collection around the TG can be reduced compared to the case where a planar type TG is used.

[0175] In this case, as disclosed in the second embodiment, it is preferable to provide a fixed charge layer for suppressing the approach of electrons in the region other than the opening of the charge transport limiting layer made of an insulating layer.

[0176] In this case, the photoelectric conversion layer may be made of Ge instead of Si.

[0177] Fig. 9 shows a second embodiment of the present invention. Fig. 9(a) shows a cross-sectional view 158, and Fig. 9(b) shows a plan view 159. Note that only one half of the surface from the center line is shown.

[0178] FIG. 10 is an explanatory diagram of the area enclosed by an ellipse 160 in FIG.

[0179] The main differences between the first and second embodiments are as follows.

[0180] The photoelectric conversion layer 161 is a Ge semiconductor.

[0181] 10, the charge transfer limiting layer 164 at the boundary between the photoelectric conversion layer 161 and the circuit diffusion layer 163 made of Si is formed by laminating a silicon dioxide layer 165 and an aluminum oxide layer 167. The fixed charges of the aluminum oxide layer form a repelling layer 162 for signal electrons.

[0182] The charge transport limiting layer 164 has m (m≫3) openings 166 with a diameter of 5 nm.

[0183] Other features are as follows:

[0184] The photoelectric conversion layer 161 occupies the center of the pixel. Therefore, the surface of a peripheral region 168 on the side of the photoelectric conversion layer is covered with a light-shielding layer 169.

[0185] The side surface 170 and the surface layer 171 of the photoelectric conversion layer 161 are laminated insulating layers. The insulating layer is made of aluminum oxide 173 and germanium dioxide 174.

[0186] In this embodiment, the peripheral region 168 on the outside of the side surface 170 is also made of Ge. The insulating layer 175 between the peripheral region 168 and the underlying Si circuit diffusion layer 163 is made of layers of silicon dioxide 172 and germanium dioxide 174. However, there are no openings.

[0187] In the first embodiment, the vertical TG 142 penetrates the circuit diffusion layer, but in the second embodiment, the TG 176 extends into the circuit diffusion layer 163, but does not reach the charge transfer limiting layer 164.

[0188] The other structures are the same as those of the first embodiment shown in Fig. 8. Therefore, the same reference numbers as those used in Fig. 8 are used for circuit elements common to Fig. 8 and Fig. 9.

[0189] FIG. 8 shows p-plus regions 155 for isolation between gates.

[0190] The second embodiment also includes p-type plus regions for isolating the gates, although their illustration is omitted in FIG.

[0191] The photoelectric conversion layer 161 has a thickness 177 of 1 μm. The circuit diffusion layer 163 has a thickness 178 of 0.5 μm. The wiring layer 179 has a thickness of 0.5 μm.

[0192] The pixel size 180 is 3 μm. The light receiving surface size 181 is 1.8 μm.

[0193] The silicon dioxide 165 and aluminum oxide 167 of the charge transport limiting layer 164 have a thickness of 2 nm.

[0194] The thickness of one vertical aluminum oxide layer 173 and two vertical germanium oxide layers 174 on the sides of the photoelectric conversion layer is 10 nm. The thickness of the aluminum oxide layer 173 and the germanium oxide layer 174 on the surface of the Ge layer is also 10 nm.

[0195] The outermost layer 182 is a scratch protection layer made of silicon dioxide having a thickness of 20 nm.

[0196] The photoelectric conversion layer 161 is an n-type Ge layer. The circuit diffusion layer 163 is an n-type Si layer. However, the gate isolation layer 155 of the p-type layer shown in FIG. 8 is disposed in the circuit diffusion layer. However, it is omitted in FIG. 9.

[0197] Apply 0V to the front contact 154. Apply 4V to the reset drain RD148.

[0198] The voltages of the transfer gate TG176 are VL=1V and VH=3V.

[0199] The voltage of the center drain CD 149 during the photograph is VL = 3 V. Before and after the photograph, VH = 5 V. Since the surface of CD is provided with a p-positive layer 150, the potential (effective voltage) with respect to the circuit diffusion layer above CD is about 2 V with respect to VL and about 4 V with respect to VH.

[0200] The effective voltage of 2V for CD's VL is the intermediate voltage between TG's VH=3V and VL=1V.

[0201] The effective voltage of CD relative to VH, 4V, is the voltage of the reset drain RD.

[0202] Therefore, between the voltage of 0V on the surface of the photoelectric conversion layer 161 and the average voltage of 2V on the circuit diffusion layer 163, an average voltage difference of 2V (=4-2) is applied in the vertical direction.

[0203] However, as shown in Figure 10, the charge transfer limiting layer has a fixed charge region 167 made of aluminum oxide. Also, although the diameter of the opening is 5 nm, the effective opening diameter is approximately 3 nm or less. These factors suppress the very strong electric field in the vertical direction.

[0204] Therefore, the vertical potential difference acting on the photoelectric conversion layer is a fraction of 2V.

[0205] It is difficult to accurately adjust the effective potential difference. If it is set to about 1 / 3 to 1 / 5 of 2V, the effective potential difference in the vertical direction of the photoelectric conversion layer will be 0.67V to 0.2V.

[0206] Since the thickness of the photoelectric conversion layer is 1 μm, the effective vertical electric field is 0.67 V / μm to 0.2 V / μm. This value is of the same order as the saturation electric field of Ge, 0.4 V / μm, shown in FIG.

[0207] Next, the horizontal electric field of the circuit diffusion layer will be explained. Since the TG has VH=3V and VL=1V, the horizontal potential difference is 2V. Since the diameter of the photoelectric conversion layer is 1.8μm, the average horizontal electric field for the diameter is 1.11V / μm (=2 / 1.8). However, since the distance between the TG to which VH is applied and the adjacent TG is short, the average electric field between them is close to the saturated electric field of 2.5V / μm. Since the overall electric field is below the saturated electric field, this is a safe design.

[0208] Next, the role of the CD will be explained. The CD has two roles. One is to make the horizontal electric field of the circuit diffusion layer 163 as constant as possible. When the potentials at both ends of the path are fixed, a constant electric field (linear potential) theoretically minimizes the travel time of the signal electrons. That is, as shown in Figure 2, the drift velocity increases exponentially with respect to the electric field (straight line on a semi-logarithmic diagram). Therefore, when the electric field in some sections of the electron transfer section is small, this causes an increase in the overall transfer time. First, the technology for linearizing the horizontal potential will be explained.

[0209] First, we will explain the case where there is neither the central p-positive region 150 nor the CD 149. In this case, the horizontal potential is not linear.

[0210] The actual shape of the potential curve is a parabolic curve that has a vertex at the TG position of VL=1V and increases from the TG position of VL=1V toward the TG position of VH=3V.

[0211] That is, the electric field from the seven TGs with VL=1V applied toward the vicinity of the pixel center is small, and only the electric field from the vicinity of the pixel center toward the one TG with VH=3V applied is large. By providing a p-positive region in the center, the effective potential becomes approximately 2V, making it possible to make the horizontal electric field closer to a straight line.

[0212] Another role of CD is to drain the dark current generated before and after shooting to the outside of the sensor chip. Therefore, 5V is applied to CD during standby and immediately after shooting. This voltage is effectively equivalent to the reset drain RD potential of 4V.

[0213] The dark current accumulates to a certain extent around the CD, which reduces the potential around the CD. At this time, the voltage difference between the periphery of the CD and the CD becomes large, and the dark current is discharged outside the sensor via the CD.

[0214] The potential of the peripheral region 168 is 0 V. The bottom of the adjacent photoelectric conversion layer 161 is about 0.5 V during imaging. The potential of the upper layer of the circuit diffusion layer is higher. This causes a circulating current to occur inside the peripheral region 168.

[0215] To minimize the generation of circulating currents, the peripheral region 168 is made as highly resistive as possible, whereas an insulator would cause charging. Therefore, the peripheral region 168 in this embodiment is intrinsic germanium.

[0216] Other operations of the second embodiment are the same as those of the first embodiment, so a description thereof will be omitted.

[0217] 10, a voltage lower than that applied to the photoelectric conversion layer 161 may be applied to the peripheral region 168. This can suppress the approach of electrons to the insulating layer 170 on the side surface of the photoelectric conversion layer.

[0218] The photoelectric conversion layer and the peripheral region may be connected. However, the insulating layer 170 on the side of the photoelectric conversion layer is moved to the pixel boundary. Instead of the insulating layer, a conductive layer made of polysilicon or the like may be used, and a negative voltage may be applied. In this case, it is also preferable to have a light-shielding layer.

[0219] The photoelectric conversion layer may be made of InGaAs, and the circuit diffusion layer may be made of InP.

[0220] The fixed charge layer may be hafnium oxide, or may be replaced by implantation of boron ions.

[0221] In FIG. 10, the charge transfer inhibition layer is formed by laminating silicon dioxide and aluminum oxide, but it may be a single layer of aluminum oxide or hafnium oxide.

[0222] The pixel arrangement on the light receiving surface, the configuration of the imaging device, and the method of operation in this patent technology are described in detail in Patent Documents 1 and 2, which are basic patents for branching-type multi-framing image sensors.

[0223] The following is a brief description of the configuration of the image capturing device according to the first embodiment of the present invention shown in Fig. 11. Image capturing device 183 is composed of optical system 184 and camera body 185.

[0224] The camera body comprises an image sensor 186, an AFE (analog front-end circuit) 187, a drive circuit 188, a pixel configuration circuit 189, a DSP (digital signal processing circuit) 190, and an image display circuit 191 according to the first embodiment of the present invention.

[0225] The image sensor includes a pixel array 192 consisting of 1200×700 pixels, a drive signal receiving circuit 193 and an image capturing signal sending circuit 194 .

[0226] The AFE is equipped with a TG (timing generator) and a first-stage image signal recording means (not shown in the diagram). A drive circuit creates a drive signal for the image sensor according to the signal generated by the TG. It also reads out the captured image signal from the image sensor.

[0227] The image signals are rearranged in the pixel configuration circuit, converted into digital image signals by the DSP, and then output to an external monitor or recording device (not shown) as image signals adjusted for display speed, etc. by the image display circuit.

[0228] High-speed video cameras are often used in mechanical engineering research and technology development for the motion of objects, high-speed flows, shock waves, deformations caused by collisions, etc. The high-speed multi-framing camera of the present invention is several orders of magnitude faster than conventional high-speed video cameras, creating a wide range of applications that were previously unimaginable for high-speed photography.

[0229] Here's one example. If we create an image sensor of the present invention using existing technology, we can achieve a time resolution of 100 ps. In principle, we can achieve 10 ps in the very near future. Furthermore, even if the image is taken with a time resolution of 100 ps, ​​if it is repeated 100 times or more, the error will be reduced to 1 / 10 or less, making it possible to analyze phenomena with a time resolution equivalent to 10 ps.

[0230] In 10 ps, ​​light (including X-rays, gamma rays, etc.) travels approximately 2.3 mm through the human body. When applied to TOF PET (Time-of-Flight Positron Emission Tomography), in addition to the conventional method of identifying the location from the intersection of multiple gamma rays emitted from the affected area, it is possible to know the distance from the sensor to the affected area, thereby significantly improving the probability and accuracy of cancer detection. [Explanation of symbols]

[0231] 100 The relationship between electric field E and drift velocity V for silicon 101 Defect-free regions of germanium crystals grown from small openings in thin oxide layers on silicon Diameter of 102 PD 103 Dot-dash line indicating the location of the cross-section 104 Photodiode (PD) 105, 106, 107 Vertical transfer gate (TG) 108, 109, 113 Readout circuit (OC) 110 Floating Diffusion (FD) 111 Reset Gate (RS) 112 Reset Drain (RD) 113 Sensor Chip 114 Drive circuit 115 Image signal processing circuit (including memory) 116 Drain readout circuit OC 117 Sensor Chip 118 Sensor chip Si circuit diffusion layer 119 GePD 120 n-type photoelectric conversion layer 121 p-type circuit diffusion layer Charge transport limiting layer consisting of 122 p-well 123 Vertical TG 124 p-negative charge transport limiting layer opening 125 Incident light 126 Signal Electronics 127 Oxide Film 128 Plan view of the first embodiment 129 Section along dotted line 131 on plan 128 130 Sectional view taken along dotted line 132 on plan view 128 131, 132 Dotted lines indicating the location of the sections on plan 128 133 Photosensitive surface 134 Silicon oxide protective layer 135 Photoelectric conversion layer made of n-type Si 136 p-type Si charge transport limiting layer 137 p-type circuit diffusion layer 138 Wiring layer 139 n-negative layer 140 n-plus layer 141 Surface boron ion doped p-layer 142 Vertical TG 143 Insulation layer around TG 144 p-negative area where TG reaches 145 Output Gate (OG) 146 Floating Diffusion (FD) 147 Reset Gate (RS) 148 Reset Drain (RD) 149 Center Drain(CD) 150 CD top p plus layer 151 Copper wiring 152 Driver circuit bonding chip 153 Bonding chip for image signal processing circuit 154 Aluminum wiring contact on the front side 155 p-positive regions for isolation 156 Storage gates (SG) for signal electronic packets outside each TG 157 Dotted circle showing corner of floor plan 158 Cross-sectional view of the second embodiment of the present invention 159 Plan view of one half of the second embodiment of the present invention from the center line 160 Target area of ​​the charge transfer limiting layer of the second embodiment of the present invention 161 Photoelectric conversion layer made of Ge semiconductor 162 Repulsion layer of signal electrons Circuit diffusion layer made of 163 Si 164 Charge transport limiting layer 165 Silicon dioxide layer constituting the charge transport limiting layer 166 Opening of charge transport limiting layer 167 Aluminum oxide layer constituting the charge transport limiting layer 168 Lateral peripheral region of the photoelectric conversion layer 169 Light-shielding layer on the surface of the photoelectric conversion layer 170 Side of photoelectric conversion layer 171 Surface of photoelectric conversion layer 172 Silicon dioxide layer 173 Aluminum oxide layer 174 Germanium dioxide layer 175 Insulating layer around the outer peripheral area of ​​the photoelectric conversion layer 176 Vertical TG 177 Thickness of photoelectric conversion layer 161 178 Thickness of circuit diffusion layer 163 179 Wiring layer 180 pixel size 181 Photosensitive area size 182 Scratch protection layer made of silicon dioxide on the surface 183 Imaging Equipment 184 Optical system 185 Camera body 186 Image sensor of the first embodiment 187 AFE (Analog Front-End Circuit 188 Drive circuit 189 Pixel Configuration Circuit 190 DSP (digital signal processing circuit) 191 Image display circuit 192 pixel array 193 Drive signal receiving circuit 194 Shooting signal transmission circuit

Claims

1. A semiconductor device; An imaging apparatus comprising: a means for focusing incident electromagnetic waves or incident charged particles (hereinafter referred to as "incident light, etc.") on the semiconductor device; a means for controlling the semiconductor device; and a means for processing a signal output from the semiconductor device, When the average incident direction of the incident light is called the vertical direction and the direction perpendicular to the vertical direction is called the radiation direction, the semiconductor device comprises M rows and N columns of pixels, where M and N are positive integers; Each pixel includes: (1) a photoelectric conversion layer that generates a signal charge by the incident light, etc., extending in a radial direction and stacked in a vertical direction; (2) a charge transfer limiting layer that limits the vertical transfer of the signal charge; and (3) a circuit diffusion layer that temporarily isolates the signal charge or converts it into another electrical signal. The charge transport limiting layer is characterized by comprising a charge transport prohibiting layer that does not allow vertical transport of signal charges, and three or more signal charge vertical transport regions (hereinafter referred to as "openings") opened in the charge transport prohibiting layer.

2. 2. The imaging apparatus according to claim 1, further comprising three or more transfer devices for transferring signal charges at equal distances in a radial direction from the center of said circuit diffusion layer.

3. 3. The imaging device according to claim 2, wherein the transfer device is a vertical transfer gate having vertical electrode portions extending vertically within the circuit diffusion layer, each of the vertical electrodes reaching one of the openings.

4. 2. The image pickup apparatus according to claim 1, wherein the charge transfer inhibition layer comprises a layer that generates a repulsive force against the signal charge.

5. 5. An imaging apparatus according to claim 4, wherein the layer generating a repulsive force against the signal charges is a layer implanted with type 3 or type 5 ions.

6. 5. An imaging apparatus according to claim 4, wherein the layer that generates a repulsive force against the signal charges is a layer that contains at least one element selected from the group consisting of hafnium, aluminum, zirconium, tantalum, titanium, and yttrium.

7. An imaging device according to any one of claims 4 to 6, wherein the size and pitch of the openings are both 25 nanometers or less.

8. 8. The imaging device according to claim 1, wherein the photoelectric conversion layer is made of a semiconductor containing germanium or containing at least one of indium, gallium, and arsenic.

Images