Image sensor and manufacturing method thereof

Abstract

To provide an image sensor and a manufacturing method of the image sensor, capable of reducing performance degradation, such as leakage current of a photodiode, which may occur due to fine particles generated during a manufacturing process.SOLUTION: An image sensor according to the present invention includes: a substrate having first and second surfaces facing each other, separated by a deep trench, and including a plurality of pixel region adjacent to each other along first and second directions; a plurality of photoelectric conversion regions disposed in the plurality of pixel regions; a blocking region disposed in the plurality of pixel regions; a plurality of wiring layers and a plurality of insulating layers disposed on the first surface of the substrate; and a plurality of color filters and a plurality of micro lenses disposed on the second surface of the substrate. The blocking region is disposed adjacent to the second surface of the substrate, the blocking region includes a first element of a first type, and the plurality of photoelectric conversion regions include a second element of a second type different from the first type. A concentration of the first element in the blocking region is 1E16 / cm3 to 1E18 / cm3 on the second surface of the substrate.SELECTED DRAWING: Figure 4

Description

[Technical field]

[0001] The present invention relates to an image sensor and a manufacturing method thereof, and more particularly to an image sensor and a manufacturing method thereof that can reduce performance degradation such as leakage current of a photodiode. [Background technology]

[0002] A CMOS image sensor is a solid-state imaging element that uses Complementary Metal-Oxide Semiconductor (CMOS). Compared to CCD image sensors, which have high-voltage analog circuits, CMOS image sensors have the advantages of lower manufacturing costs, smaller element size, and lower power consumption. CMOS image sensors are primarily used in home appliances, including portable devices such as smartphones and digital cameras. A pixel array constituting a CMOS image sensor includes a photoelectric conversion element such as a photodiode for each pixel. The photoelectric conversion element generates an electrical signal that varies depending on the amount of incident light, and the CMOS image sensor processes the electrical signal to synthesize an image.

[0003] When metal particles generated during the manufacturing process flow into a photoelectric conversion element such as a photodiode, leakage current occurs, resulting in a deterioration in the performance of the photodiode, which in turn causes a deterioration in the performance of the CMOS image sensor. Summary of the Invention [Problem to be solved by the invention]

[0004] The present invention has been made in consideration of the above-mentioned problems in conventional image sensors, and an object of the present invention is to provide an image sensor and a method for manufacturing an image sensor that can reduce performance degradation such as leakage current of a photodiode that can occur due to fine particles generated during a manufacturing process. [Means for solving the problem]

[0005] In order to achieve the above object, an image sensor according to the present invention includes a substrate having a first surface and a second surface facing each other, the substrate being divided by a deep trench and including a plurality of pixel regions adjacent along a first direction and a second direction, a plurality of photoelectric conversion regions disposed in the plurality of pixel regions, a blocking region disposed in the plurality of pixel regions, a plurality of wiring layers and a plurality of insulating layers disposed on the first surface of the substrate, and a plurality of color filters and a plurality of microlenses disposed on the second surface of the substrate, the blocking region being disposed adjacent to the second surface of the substrate, the blocking region including a first element of a first type, the plurality of photoelectric conversion regions including a second element of a second type different from the first type, and a concentration of the first element in the blocking region at the second surface of the substrate being 1E16 / cm 3 ~1E18 / cm 3 It is characterized in that:

[0006] In order to achieve the above-mentioned object, a method for manufacturing an image sensor according to the present invention includes the steps of forming a plurality of deep trenches separating a plurality of adjacent pixel regions along a first direction and a second direction from a first surface of a substrate toward the inside of the substrate, forming a blocking region by injecting a first element of a first type from the first surface of the substrate using a first high-energy injection method, and forming a plurality of photoelectric conversion regions by injecting a second element of a second type from the first surface of the substrate using a second high-energy injection method, wherein the plurality of photoelectric conversion regions are arranged on the blocking region along a third direction that is perpendicular to the first direction and the second direction and toward the first surface of the substrate. Effect of the Invention

[0007] According to the image sensor and the manufacturing method thereof according to the present invention, it is possible to reduce performance degradation such as leakage current of a photodiode that may occur due to fine particles generated during the manufacturing process. [Brief description of the drawings]

[0008] [Figure 1] 1 is a block diagram showing a schematic configuration of an image sensor according to an embodiment of the present invention; [Diagram 2] 1 is a plan view showing a schematic configuration of a portion of an image sensor according to an embodiment of the present invention; [Diagram 3] 1 is a plan view showing a schematic configuration of a portion of an image sensor according to an embodiment of the present invention; [Figure 4] FIG. 4 is a cross-sectional view taken along line II' in FIG. [Diagram 5] FIG. 11 is a cross-sectional view showing a schematic configuration of an image sensor according to another embodiment of the present invention. [Figure 6] 1A to 1C are cross-sectional views illustrating a method for manufacturing an image sensor according to an embodiment of the present invention. [Figure 7] 1A to 1C are cross-sectional views illustrating a method for manufacturing an image sensor according to an embodiment of the present invention. [Figure 8] 1A to 1C are cross-sectional views illustrating a method for manufacturing an image sensor according to an embodiment of the present invention. [Figure 9] 1A to 1C are cross-sectional views illustrating a method for manufacturing an image sensor according to an embodiment of the present invention. [Figure 10] 4 is a graph showing an example of ion implantation energy and ion concentration in a method for manufacturing an image sensor according to an embodiment of the present invention. [Figure 11] 1A to 1C are cross-sectional views illustrating a method for manufacturing an image sensor according to an embodiment of the present invention. [Figure 12] 1A to 1C are cross-sectional views illustrating a method for manufacturing an image sensor according to an embodiment of the present invention. [Figure 13] 4 is a graph showing an example of ion implantation energy and ion concentration in a method for manufacturing an image sensor according to an embodiment of the present invention. [Figure 14] 1A to 1C are cross-sectional views illustrating a method for manufacturing an image sensor according to an embodiment of the present invention. [Figure 15] 1A to 1C are cross-sectional views illustrating a method for manufacturing an image sensor according to an embodiment of the present invention. [Figure 16] 5A to 5C are cross-sectional views illustrating a method of manufacturing an image sensor according to another embodiment of the present invention. [Figure 17] 11 is a graph showing the results of an experimental example of an image sensor according to an embodiment of the present invention. [Figure 18] 11 is a graph showing the results of an experimental example of an image sensor according to an embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] Next, a specific example of an embodiment of an image sensor according to the present invention will be described with reference to the drawings.

[0010] As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention. In order to clearly describe the present invention, parts unnecessary for the description are omitted, and the same reference numerals are used throughout the specification to refer to the same or similar components. Furthermore, the attached drawings are merely intended to facilitate understanding of the embodiments disclosed in this specification, and the attached drawings are not intended to limit the technical ideas disclosed in this specification, but rather should be understood to include all modifications, equivalents, and alternatives included in the idea and technical scope of the present invention.

[0011] In addition, the size and thickness of each component shown in the drawings are arbitrarily shown for convenience of explanation, and the present invention is not necessarily limited to those shown in the drawings. In the drawings, the thickness of layers and regions are exaggerated for clarity. In the drawings, the thicknesses of some layers and regions are exaggerated for ease of explanation. In addition, when a part such as a layer, film, region, or plate is said to be "on" another part, this includes not only the case where it is "directly on" the other part, but also the case where there is another part in between. Conversely, when one part is said to be "directly above" another, it means that there is no other part in between. Furthermore, being "above" a reference part means being located above or below the reference part, and does not necessarily mean being located "above" in the direction opposite to gravity.

[0012] Furthermore, throughout the specification, when a part is said to "comprise" a certain element, this does not mean that it excludes other elements and may further include other elements, unless specifically stated to the contrary. Also, throughout the specification, a reference to "in a plane" means when the subject part is viewed from above, and a reference to "in cross section" means when the subject part is cut vertically and viewed from the side.

[0013] Furthermore, throughout the specification, when the term "connected" is used, this does not only mean that two or more components are directly connected, but also that two or more components are indirectly connected through other components, and may mean that two or more components are not only physically connected, but also electrically connected, or that components are referred to by different names depending on their position or function but are integrated. Hereinafter, various embodiments and modifications will be described in detail with reference to the drawings.

[0014] Referring to FIG. 1, an image sensor according to an embodiment of the present invention will be described briefly. FIG. 1 is a block diagram showing a schematic configuration of an image sensor according to an embodiment of the present invention. Referring to FIG. 1, an image sensor 100 according to one embodiment of the present invention includes a pixel array 140 and logic circuitry that controls the pixel array 140 .

[0015] The logic circuit is a circuit for controlling the pixel array 140, and includes, for example, a controller 110, a timing generator 120, a row driver 130, a readout circuit 150, a ramp signal generator 160, a data buffer 170, and the like. Additionally, the image sensor 100 further includes an image signal processor 180 , which according to other embodiments may be located external to the image sensor 100 . The image sensor 100 converts light received from the outside into an electrical signal to generate an image signal. The image signal is provided to an image signal processor 180 .

[0016] The image sensor 100 is incorporated into an electronic device having image or light sensing capabilities. For example, the image sensor 100 may be installed in electronic devices such as cameras, smartphones, wearable devices, Internet of Things (IoT) devices, home appliances, tablet PCs (Personal Computers), navigation devices, drones, advanced drivers assistance systems (ADAS), and the like. The image sensor 100 can also be mounted on electronic devices that are provided as components in vehicles, furniture, manufacturing equipment, doors, various measuring instruments, and the like.

[0017] The pixel array 140 includes a plurality of pixels PX, a plurality of row lines RL respectively connected to the plurality of pixels PX, and a plurality of column lines CL. In one embodiment, each pixel PX includes at least one photoelectric conversion element. The photoelectric conversion element detects incident light and converts the incident light into an electrical signal according to the amount of light, that is, a plurality of analog pixel signals. The photoelectric conversion element may be a photodiode, a pinned diode, or the like. The photoelectric conversion element may also be a SPAD (Single-Photon Avalanche Diode) applied to a 3D sensor pixel. The level of the analog pixel signal output from the photoelectric conversion element is proportional to the amount of charge output from the photoelectric conversion element. That is, the level of the analog pixel signal output by the photoelectric conversion element is determined by the amount of light received within pixel array 140 .

[0018] A plurality of row lines RL are connected to a plurality of pixels PX. For example, a control signal output from the row driver 130 to a row line RL is transmitted to the gates of transistors of the pixels PX connected to the corresponding row line RL. The column lines CL are arranged to intersect with the row lines RL and are connected to a plurality of pixels PX. A plurality of pixel signals output from a plurality of pixels PX are transmitted to a readout circuit 150 through a plurality of column lines CL.

[0019] The controller 110 controls the operation timing of each of the above-mentioned components (120, 130, 150, 160, 170) using control signals. In one embodiment, the controller 110 receives a mode signal indicating an imaging mode from the application processor, and generally controls the image sensor 100 based on the received mode signal. For example, the application processor determines the imaging mode of the image sensor 100 based on various scenarios such as the illuminance of the imaging environment, the user's resolution setting, and the sensed or learned state, and provides the determined result to the controller 110 as a mode signal. The controller 110 controls the multiple pixels PX of the pixel array 140 to output pixel signals in an imaging mode, the pixel array 140 outputs pixel signals for each of the multiple pixels PX or for a portion of the multiple pixels PX, and the readout circuit 150 samples and processes the pixel signals transmitted from the pixel array 140.

[0020] The timing generator 120 generates a signal that serves as a reference for the operation timing of the components of the image sensor 100 . The timing generator 120 controls the timing of the row driver 130 , the readout circuit 150 , and the ramp signal generator 160 . The timing generator 120 provides control signals that control the timing of the row driver 130 , the readout circuit 150 , and the ramp signal generator 160 .

[0021] The row driver 130 generates control signals for driving the pixel array 140 in response to the control signals of the timing generator 120, and provides the control signals to the pixels PX of the pixel array 140 through the row lines RL. In one embodiment, the row driver 130 controls the pixels PX to sense incident light on a row line basis. A row line unit includes at least one row line RL. For example, the row driver 130 generates a transfer signal for controlling a transfer transistor, a reset control signal for controlling a reset transistor, a selection control signal for controlling a selection transistor, and the like, and provides them to the pixel array 140 .

[0022] The readout circuit 150 converts a pixel signal (or an electrical signal) from a pixel PX connected to a row line RL selected among the multiple pixels PX into a pixel value indicating the amount of light in response to a control signal from the timing generator 120. The readout circuit 150 converts the pixel signal output through the corresponding column line CL into a pixel value. For example, the readout circuit 150 converts the pixel signal into a pixel value by comparing the pixel signal to a ramp signal. A pixel value is image data having multiple bits. Specifically, the readout circuit 150 may include a selector, a number of comparators, and a number of counter circuits.

[0023] The ramp signal generator 160 generates and transfers a reference signal to the readout circuit 150 . The ramp signal generator 160 includes a current source, a resistor, and a capacitor. The ramp signal generator 160 generates a plurality of ramp signals that rise or fall with a slope determined by the magnitude of the current of the variable current source or the resistance value of the variable resistor by adjusting the ramp voltage, which is the voltage applied to the ramp resistor, by adjusting the magnitude of the current of the variable current source or the resistance value of the variable resistor.

[0024] The data buffer 170 stores pixel values ​​of a plurality of pixels PX connected to a selected column line CL transmitted from the readout circuit 150, and outputs the stored pixel values ​​in response to an enable signal from the controller 110. The image signal processor 180 performs image signal processing on the image signal received from the data buffer 170 . For example, the image signal processor 180 receives a plurality of image signals from the data buffer 170 and combines the received image signals to generate one image.

[0025] A pixel arrangement of an image sensor according to an embodiment of the present invention will be described with reference to FIG. FIG. 2 is a plan view showing a schematic configuration of a portion of the image sensor according to one embodiment of the present invention. Referring to FIG. 2, an image sensor 100 according to one embodiment of the present invention includes a pixel group PG, a photodiode PD, a color filter CF, a microlens ML, and other circuitry required for operation of the image sensor 100.

[0026] A plurality of pixels PX are grouped in the form of a plurality of columns and a plurality of rows to form one unit pixel group PG. The pixel group PG that overlaps with the first color filter CF1 senses light of a first color, the pixel group PG that overlaps with the second color filter CF2 senses light of a second color different from the first color, and the pixel group PG that overlaps with the third color filter CF3 senses light of a third color different from the first and second colors. Each of the plurality of pixel groups PG includes an N×M array of N×M pixels PX. N and M are each independently an integer greater than 1. For example, N and M are each 2, and the pixel array has a 2x2 Tetra structure on a plane. That is, each of the pixel groups PG includes pixels PX arranged in a 2×2 format on a plane.

[0027] More specifically, a plurality of pixels PX arranged in the arrangement direction of the column lines CL and a plurality of pixels PX arranged in the arrangement direction of the row lines RL constitute one unit pixel group PG. For example, one unit pixel group PG includes a plurality of pixels PX arranged in the form of two columns and two rows, and one unit pixel group PG outputs one analog pixel signal. However, the embodiment is not limited thereto, and the number of pixels PX included in one pixel group PG can be variously modified.

[0028] Hereinafter, an image sensor according to an embodiment of the present invention will be described in more detail with reference to FIG. 3 and FIG. FIG. 3 is a plan view showing a schematic configuration of a portion of an image sensor according to an embodiment of the present invention, and FIG. 4 is a cross-sectional view taken along line II' in FIG. Referring to FIG. 3, an image sensor 100 according to an embodiment of the present invention includes a plurality of pixels (P1, P2, P3, P4).

[0029] The plurality of pixels (P1, P2, P3, P4) include a first pixel P1, a second pixel P2, a third pixel P3, and a fourth pixel P4 that are adjacent to each other along a first direction DR1 and a second direction DR2 different from the first direction DR1. On a plane formed by a first direction DR1 and a second direction DR2 that are different from each other, a first pixel P1 and a second pixel P2 are arranged adjacent to each other along the first direction DR1, and a third pixel P3 and a fourth pixel P4 are arranged adjacent to each other. Also, on one plane, a first pixel P1 and a third pixel P3 are disposed adjacent to each other along a second direction DR2, and a second pixel P2 and a fourth pixel P4 are disposed adjacent to each other.

[0030] A number of pixels (P1, P2, P3, P4) are partitioned by a pixel separating structure DTI. The pixel separating structures DTI are connected to each other and disposed to surround the first pixel P1, the second pixel P2, the third pixel P3, and the fourth pixel P4, respectively. The pixel isolation structure DTI prevents crosstalk between the multiple pixels (P1, P2, P3, P4). The pixel isolation structure DTI is disposed in a deep trench DT, and at least a portion of the deep trench DT is surrounded by a device isolation film STL located in a shallow trench ST. Each of the multiple pixels (P1, P2, P3, P4) includes multiple gates (TG, SF, SG, RG). The multiple gates (TG, SF, SG, RG) include a transfer gate TG, a drive gate SF, a selection gate SG, and a reset gate RG.

[0031] In one embodiment, the multiple gates (TG, SF, SG, RG) of the first pixel P1 are symmetrical to the multiple gates (TG, SF, SG, RG) of the second pixel P2 with respect to a virtual first line IML1 that is parallel to the second direction DR2 and passes between the first pixel P1 and the second pixel P2, and similarly, the multiple gates (TG, SF, SG, RG) of the third pixel P3 are symmetrical to the multiple gates (TG, SF, SG, RG) of the fourth pixel P4 with respect to the virtual first line IML1. In addition, the multiple gates (TG, SF, SG, RG) of the first pixel P1 are symmetrical to the multiple gates (TG, SF, SG, RG) of the third pixel P3 with respect to a virtual second line IML2 that is parallel to the first direction DR1 and passes between the first pixel P1 and the third pixel P3, and similarly, the multiple gates (TG, SF, SG, RG) of the second pixel P2 are symmetrical to the multiple gates (TG, SF, SG, RG) of the fourth pixel P4 with respect to the virtual second line IML2.

[0032] Referring to FIG. 4 in conjunction with FIGS. 1 to 3, the image sensor 100 includes a substrate 200. The substrate 200 may include silicon (Si), germanium (Ge), or silicon (Si)-germanium (Ge). The substrate 200 may include gallium arsenide (GaAs), indium phosphide (InP), gallium phosphide (GaP), indium arsenide (InAs), indium antimony (InSb), or indium gallium arsenide (InGaAs). The substrate 200 may include zinc telluride (ZnTe) or cadmium sulfide (CdS). The substrate 200 is bulk silicon or silicon-on-insulator (SOI). The substrate 200 may be a silicon substrate, or may include other materials, such as silicon germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide. Alternatively, the substrate 200 may be an epitaxial layer formed on a base substrate.

[0033] The substrate 200 includes a first surface SFA and a second surface SFB opposed to each other. The substrate 200 includes a deep trench DT in which a pixel isolating structure DTI is disposed. As described above, the pixel separating structure DTI surrounds the pixels (P1, P2, P3, P4), and the multiple pixels (P1, P2, P3, P4) are partitioned by the pixel separating structure DTI. The deep trench DT and the pixel separating structure DTI are disposed through the substrate 200 from a first face SFA to a second face SFB of the substrate 200 . That is, the depth of the deep trench DT along the third direction DR3, which is the height direction, is approximately the same as the thickness of the substrate 200.

[0034] The pixel separating structure DTI includes an insulating pattern DTI1, a conductive pattern DTI2, and a capping pattern DTI3. An insulating pattern DTI1 covers the inner walls of the deep trench DT. A capping pattern DTI3 fills the top of the deep trench DT. The conductive pattern DTI2 fills the lower part of the deep trench DT. The upper surface of the capping pattern DTI3 is coplanar with the first surface SFA of the substrate 200, and the lower surface of the conductive pattern DTI2 is coplanar with the second surface SFB of the substrate 200. The insulating pattern DTI1 extends from the first surface SFA of the substrate 200 to the second surface SFB. The conductive pattern DTI2 is separated from the substrate 200 by an insulating pattern DTI1. In other embodiments, the capping pattern DTI3 may be omitted.

[0035] The conductive pattern DTI2 comprises, for example, a semiconductor material, such as n-type or p-type doped polysilicon, or a metal material. The insulating pattern DTI1 and the capping pattern DTI3 may include silicon oxide, silicon nitride, or silicon oxynitride. The insulating pattern DTI1 may include a metal oxide such as hafnium oxide, aluminum oxide, tantalum oxide, etc., in which case the insulating pattern DTI1 acts as a negative fixed charge layer.

[0036] A blocking region HDP is disposed in an area adjacent to the second surface SFB of the substrate 200. The blocking region HDP is doped with an impurity different from that of the photoelectric conversion regions (PD1, PD2, PD3, PD4). For example, the blocking region HDP is doped with a first element which is a P-type impurity. The blocking region HDP is adjacent to the second face SFB of the substrate 200, and the concentration of the first element in the blocking region HDP is higher than the concentration of the first element in other regions of the substrate 200. The first element includes boron-11 (11Boron). The concentration of boron-11 at the second face SFB of the substrate 200 in the blocking region HDP is about 1E16 / cm 3 ~About 1E18 / cm 3 It is. The thickness of the blocking region HDP is about 250 nm to about 2000 nm.

[0037] A first element is implanted into the blocking region HDP by a high energy implant method. At this time, the strength of the implantation energy is about 2.5 MeV to about 6.5 MeV, and the implantation dose is about 5E12 / cm 2 ~About 1E14 / cm 2 The tilt angle during impurity implantation is about 0 degrees to about 7 degrees. The injection dose is per unit area (1 cm 2 ) is the number of impurity elements implanted into the surface of the substrate 200. The blocking regions HDP corresponding to the pixels P1, P2, P3, and P4 are each divided by a pixel separating structure DTI.

[0038] In the substrate 200, photoelectric conversion regions (PD1, PD2, PD3, PD4) corresponding to the respective pixels (P1, P2, P3, P4) are arranged. The photoelectric conversion regions (PD1, PD2, PD3, PD4) are disposed above the blocking region HDP along a third direction DR3 which is the height direction. Externally incident light is converted into an electrical signal in the photoelectric conversion regions (PD1, PD2, PD3, PD4). The photoelectric conversion regions (PD1, PD2, PD3, PD4) include photodiodes formed inside the substrate 200. The photoelectric conversion regions (PD1, PD2, PD3, PD4) are doped with conductive impurities different from the conductive impurities doped into the substrate 200, and the photoelectric conversion regions (PD1, PD2, PD3, PD4) are doped with a different type of impurity than the impurities doped into the blocking region HDP. A pixel separating structure DTI is arranged between photoelectric conversion regions (PD1, PD2, PD3, PD4) corresponding to multiple pixels (P1, P2, P3, P4), and each of the photoelectric conversion regions (PD1, PD2, PD3, PD4) corresponding to the multiple pixels (P1, P2, P3, P4) is separated from each other by the pixel separating structure DTI. The pixel isolation structure DTI electrically and optically isolates adjacent photoelectric conversion regions (PD1, PD2, PD3, PD4).

[0039] The substrate 200 includes a shallow trench ST, and an element isolation film STL is disposed in the shallow trench ST of the substrate 200 . The shallow trench ST does not penetrate the substrate 200 from the first surface SFA of the substrate 200 but is located in a portion of the substrate 200 . Along a third direction DR3 which is the height direction, the depth of the shallow trench ST is smaller than the depth of the deep trench DT. The upper surface of the element isolation film STL is coplanar with the first surface SFA of the substrate 200. The element isolation film STL may include silicon oxide, silicon nitride, or a combination thereof.

[0040] On the first surface SFA of the substrate 200, a plurality of gates (TG, SF, SG, RG) are arranged. The substrate 200 has a plurality of floating diffusion regions FD and a plurality of ground regions (not shown) disposed adjacent to the first surface SFA. The floating diffusion regions FD are adjacent to each of the transfer gates TG. The plurality of floating diffusion regions FD have a conductivity type opposite to that of the substrate 200 . The plurality of ground regions are doped with conductive impurities, such as the conductive impurities doped into the substrate 200, at a concentration higher than that of the rest of the substrate 200. Although not shown in the figure, the substrate 200 may further include a plurality of impurity regions located adjacent to the first surface SFA, the plurality of impurity regions being active regions for the operation of the transistors. A plurality of ground regions, a plurality of gates (TG, SF, SG, RG), and a floating diffusion region FD form a transfer transistor, a drive transistor, a select transistor, and a reset transistor. The plurality of ground regions are ground patterns for grounding at least one of the transfer transistor, the drive transistor, the selection transistor, and the reset transistor.

[0041] A first structure 300 is disposed on the first surface SFA of the substrate 200 . The first structure 300 includes a plurality of vias ML1, a plurality of wiring layers (ML2, ML3), and a plurality of insulating layers (IL1, IL2, IL3). The multiple insulating layers (IL1, IL2, IL3) electrically isolate the multiple vias ML1 and the multiple wiring layers (ML2, ML3). The multiple vias ML1 and the multiple wiring layers (ML2, ML3) are electrically connected to the transistors on the first surface SFA of the substrate 200. The vias ML1 and wiring layers (ML2, ML3) may include tungsten, aluminum, copper, tungsten silicide, titanium silicide, tungsten nitride, titanium nitride, doped polysilicon, and the like. The multiple insulating layers (IL1, IL2, IL3) may include insulating materials such as silicon oxide, silicon nitride, silicon oxynitride, low-k materials, and the like.

[0042] The low dielectric material may include, for example, at least one of flowable oxide (FOX), torene silazene (TOSZ), undoped silica glass (USG), borosilica glass (BSG), phosphosilica glass (PSG), borophosphosilica glass (BPSG), plasma enhanced tetra ethyl ortho silicate (PETEOS), fluoride silicate glass (FSG), carbon doped silicon oxide (CDO), xerogel, aerogel, amorphous fluorinated carbon, organo silicate glass (OSG), parylene, bis-benzocyclobutenes (BCB), SiLK, polyimide, porous polymeric material, and combinations thereof.

[0043] The image sensor 100 further includes a support substrate 400 positioned on the first structure 300, although the support substrate 400 is optional. An adhesive member (not shown) is further disposed between the support substrate 400 and the first structure 300 . An anti-reflection layer (PRL) is disposed on the second surface SFB of the substrate 200. An antireflective layer PRL covers the second face SFB of the substrate 200 and the pixel separating structure DTI.

[0044] The anti-reflection layer PRL is made of hafnium oxide (HfO 2 ), silicon oxide (SiO 2 ), silicon nitride (SiN), aluminum oxide (Al 2 O 3 ), zirconium oxide (ZrO 2 ), tantalum oxide (Ta 2 O 5 ), titanium dioxide (TiO2 ), lanthanum oxide (La 2 O 3 ), praseodymium oxide (Pr 2 O 3 ), cerium oxide (CeO 2 ), neodymium oxide (Nd 2 O 3 ), promethium oxide (Pm 2 O 3 ), samarium oxide (Sm 2 O 3 ), europium oxide (Eu 2 O 3 ), gadolinium oxide (Gd 2 O 3 ), terbium oxide (Tb 2 O 3 ), dysprosium oxide (Dy 2 O 3 ), Holmium oxide (Ho 2 O 3 ), thulium oxide (Tm 2 O 3 ), Ytterbium oxide (Yb 2 O 3 ), ruthenium oxide (Lu 2 O 3 ), yttrium oxide (Y 2 O 3 ), or a combination thereof.

[0045] In one embodiment, the anti-reflection layer PRL includes a number of layers including different materials and having different thicknesses. For example, the antireflection layer PRL includes a first antireflection layer to a third antireflection layer which are laminated in this order on the second surface SFB of the substrate 200. The first antireflection layer is a fixed charge layer having a negative fixed charge. Hole accumulation may occur around the fixed charge layer, which can effectively reduce the generation of dark current and white spots.

[0046] The third anti-reflective layer may include a metal oxide or a metal fluoride including at least one of hafnium (Hf), zirconium (Zr), aluminum (Al), tantalum (Ta), titanium (Ti), and yttrium (Y). For example, the first and third antireflective layers include hafnium oxide layers, and the second antireflective layer includes silicon oxide and / or silicon nitride. However, in other embodiments, the number and relative thicknesses of the layers constituting the anti-reflection layer PRL may vary. In addition, in another embodiment, the antireflection layer PRL may further include a silicon nitride layer disposed between the second antireflection layer and the third antireflection layer.

[0047] The fence pattern IS is disposed below the antireflection layer PRL. On a plane formed by the first direction DR1 and the second direction DR2, the fence pattern IS extends along a portion of the pixel separating structure DTI, and along a third direction DR3, which is the height direction, a portion of the pixel separating structure DTI overlaps with the fence pattern IS. The fence pattern IS surrounds the color filter CF. The fence pattern IS includes a low refractive index material. A low refractive index material has a refractive index greater than about 1.0 and less than or equal to about 1.4. For example, the low refractive index material may include polymethylmetacrylate (PMMA), silicon acrylate, cellulose acetatebutyrate (CAB), silica, or fluoro-silicon acrylate (FSA). For example, the low refractive index material includes a polymeric material having silica (SiOx) particles dispersed therein.

[0048] When the fence pattern IS includes a low refractive index material having a relatively low refractive index, light incident on the fence pattern IS is totally reflected and directed toward the center of each pixel area (P1, P2, P3, P4). The fence pattern IS prevents light that is obliquely incident into a color filter CF arranged in one of the multiple pixel regions (P1, P2, P3, P4) from entering a color filter CF arranged over another adjacent pixel region, thereby preventing crosstalk between the multiple pixel regions (P1 to P4). A plurality of color filters CF are disposed on the anti-reflection layer PRL and are separated from each other by a fence pattern IS. The plurality of color filters CF includes, for example, a green filter, a blue filter, and a red filter. Alternatively, the color filters CF may include, for example, cyan, magenta, or yellow.

[0049] The microlenses ML are disposed on the color filters CF and the fence pattern IS. On a plane formed by the first direction DR1 and the second direction DR2, the microlenses ML are disposed to correspond to the plurality of pixel regions (P1, P2, P3, P4), respectively. The microlenses ML are transparent. The microlenses ML are formed of a resin material such as a styrene resin, an acrylic resin, a styrene-acrylic copolymer resin, or a siloxane resin. The microlenses ML collect incident light, and the collected light passes through color filters CF and enters photoelectric conversion regions (PD1, PD2, PD3, PD4). The capping layer CPL is disposed on the microlens ML to protect the microlens ML.

[0050] As described above, a blocking region HDP is disposed between the photoelectric conversion regions (PD1, PD2, PD3, PD4) of each pixel (P1, P2, P3, P4) separated by the deep trench DT penetrating the substrate 200 from the first surface SFA to the second surface SFB of the substrate 200 and the pixel isolation structure DTI and the second surface SFB of the substrate 200. The blocking region HDP of each pixel (P1, P2, P3, P4) is ion-implanted with a different type of element than the photoelectric conversion region (PD1, PD2, PD3, PD4). During the manufacturing process of the image sensor 100, when the first structure 300 is attached to the first surface SFA of the substrate 200 and the anti-reflection layer PRL, the fence pattern IS, the color filter CF, and the microlens ML are formed on the second surface SFB of the substrate 200, unwanted conductive particles may be generated. Unnecessary conductive particles generated during the manufacturing process may induce leakage current, but the effects of leakage current due to such unnecessary conductive particles are not diffused to the photoelectric conversion regions (PD1, PD2, PD3, PD4) due to the blocking region HDP doped with a first element of a different type from the photoelectric conversion regions (PD1, PD2, PD3, PD4).

[0051] The blocking region HDP is a region where a first element is implanted by a high energy implant method, and the blocking region HDP is doped with boron-11 (11Boron). The blocking region HDP is doped with a first element through the first surface SFA of the substrate 200 by a high energy implantation method. Therefore, the blocking region HDP is formed before forming the photoelectric conversion regions (PD1, PD2, PD3, PD4). In this manner, after forming a blocking region HDP adjacent to the second surface SFB of the substrate 200, photoelectric conversion regions (PD1, PD2, PD3, PD4) are formed in the substrate 200, a first structure 300 is attached to the first surface SFA of the substrate 200, and an anti-reflection layer PRL, a fence pattern IS, a color filter CF, and a microlens ML are formed on the second surface SFB of the substrate 200, thereby preventing the influence of leakage current caused by unnecessary particles generated in subsequent processes from diffusing to the photoelectric conversion regions (PD1, PD2, PD3, PD4) through the blocking region HDP.

[0052] An image sensor 101 according to another embodiment of the present invention will now be described with reference to FIG. 5 as well as FIGS. 1 to 4. FIG. FIG. 5 is a cross-sectional view showing a schematic configuration of an image sensor according to another embodiment of the present invention. Referring to FIG. 5, an image sensor 101 according to this embodiment is similar to the image sensor 100 according to the previous embodiment. A detailed description of the same components will be omitted.

[0053] Referring to FIG. 5, the image sensor 101 according to this embodiment includes a plurality of pixels (P1, P2, P3, P4) including a first pixel P1, a second pixel P2, a third pixel P3, and a fourth pixel P4 adjacent to each other along a first direction DR1 and a second direction DR2, and the plurality of pixels (P1, P2, P3, P4) are separated by a deep trench DT penetrating the substrate 200 from a first surface SFA to a second surface SFB of the substrate 200 and a pixel isolation structure DTI. The pixels (P1, P2, P3, P4) each include a blocking region HDP and a photoelectric conversion region (PD1, PD2, PD3, PD4) doped with different impurities. For example, the blocking region HDP is doped with a first element which is a P-type impurity. The blocking region HDP is adjacent to the second face SFB of the substrate 200, and the concentration of the first element in the blocking region HDP is higher than the concentration of the first element in other regions of the substrate 200.

[0054] The blocking region HDP is doped with boron-11 (11Boron). The concentration of boron-11 in the second face SFB of the substrate 200 in the blocking region HDP is 1E16 / cm 3 ~1E18 / cm 3 It is. The thickness of the blocking region HDP is about 250 nm to about 2000 nm. A first element is implanted into the blocking region HDP by a high energy implant method. At this time, the strength of the implantation energy is about 2.5 MeV to about 6.5 MeV, and the implantation dose is about 5E12 / cm 2 ~About 1E14 / cm 2 The tilt angle during ion implantation is about 0 degrees to about 7 degrees. The blocking regions HDP corresponding to the pixels P1, P2, P3, and P4 are each divided by a pixel separating structure DTI.

[0055] Unlike the image sensor 100 according to the above-described embodiment, the image sensor 101 according to the present embodiment has a fine pattern layer PO disposed between the blocking region HDP and the anti-reflection layer PRL. The fine pattern layer PO includes a plurality of protrusions. The fine pattern layer PO refracts light incident through the second surface SFB of the substrate 200 toward the photoelectric conversion regions (PD1, PD2, PD3, PD4), thereby preventing the incident light from being reflected externally and increasing the efficiency of light incident on the photoelectric conversion regions (PD1, PD2, PD3, PD4). By arranging multiple fine pattern layers PO on the second surface SFB of the substrate 200, the area of ​​the interface between the second surface SFB of the substrate 200 and the multiple fine pattern layers PO becomes larger, making it easier for the effects of leakage current of unnecessary fine particles generated at the interface to diffuse to the photoelectric conversion region (PD1, PD2, PD3, PD4).

[0056] In addition, when forming the fine pattern layers PO, unnecessary fine particles may be generated, and the effects of leakage current caused by such unnecessary fine particles are diffused to the photoelectric conversion regions (PD1, PD2, PD3, PD4). However, the image sensor 101 according to the embodiment includes a deep trench DT penetrating the substrate 200 from the first surface SFA to the second surface SFB of the substrate 200 and a blocking region HDP located between the photoelectric conversion region (PD1, PD2, PD3, PD4) of each pixel (P1, P2, P3, P4) separated by a pixel isolation structure DTI and the second surface SFB of the substrate 200. The blocking region HDP of each pixel (P1, P2, P3, P4) is ion-implanted with a different type of element than the photoelectric conversion region (PD1, PD2, PD3, PD4).

[0057] During the manufacturing process of the image sensor 100, when the first structure 300 is attached to the first surface SFA of the substrate 200 and the fine pattern layer PO, the anti-reflection layer PRL, the fence pattern IS, the color filter CF, and the microlens ML are formed on the second surface SFB of the substrate 200, unwanted conductive particles may be generated. Unnecessary conductive particles generated during the manufacturing process may induce leakage current, but the effects of leakage current due to such unnecessary conductive particles are not diffused to the photoelectric conversion regions (PD1, PD2, PD3, PD4) due to the blocking region HDP doped with a first element of a different type from the photoelectric conversion regions (PD1, PD2, PD3, PD4). The blocking region HDP is a region where a first element is implanted by a high energy implant method, and the blocking region HDP is doped with boron-11 (11Boron).

[0058] The blocking region HDP is doped with a first element through the first surface SFA of the substrate 200 by a high energy implantation method. Therefore, the blocking region HDP is formed before forming the photoelectric conversion regions (PD1, PD2, PD3, PD4). In this manner, after forming a blocking region HDP on the second surface SFB of the substrate 200, photoelectric conversion regions (PD1, PD2, PD3, PD4) are formed on the substrate 200, a first structure 300 is attached to the first surface SFA of the substrate 200, and a fine pattern layer PO, an anti-reflection layer PRL, a fence pattern IS, a color filter CF, and a microlens ML are formed on the second surface SFB of the substrate 200, thereby preventing the influence of leakage current caused by unnecessary particles generated in subsequent processes from diffusing to the photoelectric conversion regions (PD1, PD2, PD3, PD4) through the blocking region HDP. Many of the features of the image sensor 100 according to the embodiment described above are all applicable to the image sensor 101 according to this embodiment.

[0059] Hereinafter, a method for manufacturing an image sensor according to an embodiment of the present invention will be described with reference to FIGS. 3 and 4 as well as FIGS. Figures 6 to 9, Figures 11, 12, 14, and 15 are cross-sectional views illustrating a method for manufacturing an image sensor according to one embodiment of the present invention, and Figures 10 and 13 are graphs showing examples of ion implantation energy and ion concentration in the method for manufacturing an image sensor according to one embodiment of the present invention.

[0060] Referring to FIG. 6, a deep trench DT is formed from the first surface SFA of the substrate 200 toward the preliminary surface SFB1 of the substrate 200. The deep trench DT is formed in the element isolation film STL formed in the shallow trench ST and in the substrate 200 . Deep trenches DT are formed to separate the pixels (P1, P2, P3, P4).

[0061] Referring to FIG. 7, a pixel isolating structure DTI is formed in a deep trench DT in a substrate 200 . The pixel separating structure DTI includes an insulating pattern DTI1, a conductive pattern DTI2, and a capping pattern DTI3.

[0062] Referring to FIG. 8, by implanting (DPB) a first type of first element from a first surface SFA of the substrate 200 toward a preliminary surface SFB1 of the substrate 200 using a high energy implantation method, a blocking region HDP having a high concentration of the first element is formed on the lower side of the pixel isolation structure DTI in the deep trench DT of the substrate 200 and on the preliminary surface SFB1 of the substrate 200, as shown in FIG. 9. The first element is boron-11 (11Boron). When the first element is implanted (DPB), the implantation energy is about 2.5 MeV to about 5.0 MeV, and the implantation dose is about 1E12 / cm 2 ~About 1E14 / cm 2 The tilt angle during ion implantation is about 2 degrees to about 7 degrees. The first element is implanted into a region in the trench DT that is defined by the pixel isolating structure DTI and below the pixel isolating structure DTI. The concentration of the first element is relatively high at the side of the lower surface of the pixel isolation structure DTI in the trench DT, and the concentration of the first element at the side of the lower surface of the pixel isolation structure DTI is about 1E16 / cm 3 ~About 1E18 / cm 3 It is.

[0063] Referring to FIG. 10, the implantation energy of boron-11 (11Boron) is about 3.8 MeV, and the implantation dose is about 3E12 / cm 2 In this case, boron-11 is implanted to a depth of about 4000 nm to about 6000 nm from the first surface SFA of the substrate 200. For example, the concentration of boron-11 (11Boron) is higher at a position that is about 4700 nm to about 4800 nm from the first surface SFA of the substrate 200 than in other regions, and is about 1E16 / cm 3 ~About 1E17 / cm 3 It is. In this manner, by adjusting the impurity implantation energy and implantation dose according to the thickness of the substrate 200, the impurities are implanted to have a higher concentration on the preliminary surface SFB1 of the substrate 200 facing the first surface SFA than on the first surface SFA of the substrate 200 where ion implantation is performed.

[0064] Next, as shown in FIG. 11, a second element of a second type different from the first type is injected (DPN) from the first surface SFA of the substrate 200 toward the preliminary surface SFB1 of the substrate 200 using a high-energy injection method, thereby forming photoelectric conversion regions (PD1, PD2, PD3, PD4) corresponding to pixels (P1, P2, P3, P4) separated by pixel isolation structures DTI in the deep trenches DT of the substrate 200, as shown in FIG. 12.

[0065] Referring to FIG. 13, the maximum implantation energy of the second element is about 4.8 MeV, and when it is about 5.6 MeV, the second element is implanted to a depth of about 6000 nm from the first surface SFA of the substrate 200. In this manner, by adjusting the implantation energy and implantation dose of the impurities according to the thickness of the substrate 200, the impurities can be implanted to a desired concentration to a desired depth from the first surface SFA of the substrate 200 where ion implantation is performed.

[0066] Referring to FIG. 14, a first structure 300 is attached to a first surface SFA of a substrate 200, and a portion of the substrate 200 is removed from a preliminary surface SFB1 of the substrate 200 through a chemical and physical polishing process (CMP) to form a second surface SFB of the substrate 200 coplanar with the deep trench DT and the pixel isolation structure DTI, as shown in FIG. 15. Although not shown in the drawing, a support substrate 400 is further attached to the first structure 300 . Next, an anti-reflection layer PRL, a fence pattern IS, a color filter CF, and a microlens ML are formed on the second surface SFB of the substrate 200 to form the image sensor 100 shown in FIGS.

[0067] As described above, according to the method for manufacturing the image sensor according to the present embodiment, the first element is injected by a high energy injection method, so that the blocking region HDP is formed before the photoelectric conversion regions (PD1, PD2, PD3, PD4) are formed. In this manner, after forming a blocking region HDP on the second surface SFB of the substrate 200, photoelectric conversion regions (PD1, PD2, PD3, PD4) are formed in the substrate 200, a first structure 300 is attached to the first surface SFA of the substrate 200, and an anti-reflection layer PRL, a fence pattern IS, a color filter CF, and a microlens ML are formed on the second surface SFB of the substrate 200, thereby preventing the influence of leakage current caused by unnecessary particles generated in subsequent processes from diffusing to the photoelectric conversion regions (PD1, PD2, PD3, PD4) through the blocking region HDP. In addition, it is possible to prevent the first structure 300 from being damaged on the first surface SFA of the substrate 200 due to the high energy ion implantation process for forming the blocking region HDP.

[0068] Hereinafter, with reference to FIG. 16 together with FIGS. 4 to 15, a method for manufacturing an image sensor according to another embodiment of the present invention will be described. FIG. 16 is a cross-sectional view illustrating a method for manufacturing an image sensor according to another embodiment of the present invention.

[0069] As shown in FIGS. 6 to 15 , the method for manufacturing an image sensor according to the present embodiment includes forming a deep trench DT from the first surface SFA of the substrate 200 toward the preliminary surface SFB1 of the substrate 200, forming a pixel separating structure DTI in the deep trench DT of the substrate 200, injecting (DPB) a first element of a first type from the first surface SFA of the substrate 200 toward the preliminary surface SFB1 of the substrate 200 by a high energy injection method, thereby forming a blocking region HDP having a high concentration of the first element on a side of a lower side of the pixel separating structure DTI in the deep trench DT of the substrate 200 and on the preliminary surface SFB1 of the substrate 200, and A second element of a second type different from the first type is implanted (DPN) toward the preliminary surface SFB1 of the substrate 200 using a high energy implantation method to form photoelectric conversion regions (PD1, PD2, PD3, PD4) corresponding to pixels (P1, P2, P3, P4) separated by the pixel isolation structure DTI in the deep trench DT of the substrate 200, and a part of the preliminary surface SFB1 of the substrate 200 is removed through a chemical and physical polishing process (CMP) to form a second surface SFB of the substrate 200 coplanar with the deep trench DT and the pixel isolation structure DTI, and a first structure 300 is attached to the first surface SFA of the substrate 200.

[0070] Thereafter, a fine pattern layer PO is formed on the second surface SFB of the substrate 200, as shown in FIG. The fine pattern layer PO includes a plurality of fine patterns protruding toward the photoelectric conversion regions (PD1, PD2, PD3, PD4). Next, an anti-reflection layer PRL, a fence pattern IS, a color filter CF, and a microlens ML are formed on the fine pattern layer PO on the second surface SFB of the substrate 200 to form the image sensor 101 of FIG.

[0071] As described above, according to the method for manufacturing the image sensor according to the present embodiment, the first element is injected by a high energy injection method, so that the blocking region HDP is formed before the photoelectric conversion regions (PD1, PD2, PD3, PD4) are formed. In this manner, after forming a blocking region HDP on the second surface SFB of the substrate 200, photoelectric conversion regions (PD1, PD2, PD3, PD4) are formed on the substrate 200, a first structure 300 is attached to the first surface SFA of the substrate 200, and a fine pattern layer PO, an anti-reflection layer PRL, a fence pattern IS, a color filter CF, and a microlens ML are formed on the second surface SFB of the substrate 200, thereby preventing the influence of leakage current caused by unnecessary particles generated in subsequent processes from diffusing to the photoelectric conversion regions (PD1, PD2, PD3, PD4) through the blocking region HDP. In addition, it is possible to prevent the first structure 300 from being damaged on the first surface SFA of the substrate 200 due to the high energy ion implantation process for forming the blocking region HDP.

[0072] An experimental example of the present invention will be described with reference to FIGS. 17 and 18 are graphs showing the results of an experimental example of the present invention. In this experimental example, the depth of the layer into which boron-11 (11Boron) was implanted was measured while varying the energy for implanting boron-11 (11Boron). At this time, the implantation dose is 1E13 / cm 2 was constant. More specifically, results for high energy implants with boron-11 (11Boron) implant energies of about 3000 KeV and about 5500 KeV are shown in FIG. 17, and results for low energy implants with boron-11 (11Boron) implant energies of about 3 KeV, about 30 KeV, and about 100 KeV are shown in FIG. 18.

[0073] 17 and 18, in the case of high energy implantation with an implant energy of about 3000 KeV and an implant energy of about 5500 KeV, the FWHM (full width at half maximum) depth of boron-11 (11Boron) was relatively deep, at 250 nm or more, whereas in the case of low energy implantation with implant energies of about 3 KeV, about 30 KeV, and about 100 KeV, the FWHM (full width at half maximum) depth of boron-11 (11Boron) was relatively shallow, at about 150 nm or less. In this manner, it has been found that when the first element is implanted by a high energy implantation method as in the method of manufacturing an image sensor according to an embodiment of the present invention, a blocking region HDP having a thickness of about 250 nm or more can be formed.

[0074] The present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the technical scope of the present invention. [Explanation of symbols]

[0075] 100, 101 Image sensor 110 Controller 120 Timing Generator 130 Low Driver 140 pixel array 150 Readout circuit 160 Ramp Signal Generator 170 Data Buffer 180 Image signal processor 200 boards 300 1st structure 400 Support Board CF Color Filter CF1, CF2, CF3 (1st, 2nd, 3rd) color filters CPL Capping Layer DT Deep Trench DTI pixel isolation structure DTI1 Insulation Pattern DTI2 Conductive Pattern DTI3 Capping Pattern FD Floating diffusion region HDP cutoff area IL1, IL2, IL3 insulation layers IS fence pattern ML Micro Lens ML1 Vias ML2, ML3 wiring layer P1, P2, P3, P4 pixels PD Photodiode PD1, PD2, PD3, PD4 Photoelectric conversion area PO fine pattern layer PRL anti-reflection layer PX Pixels TG, SF, SG, RG gates ST Shallow Trench STL element isolation film

Claims

1. a substrate having first and second opposing surfaces, the substrate being partitioned by a deep trench and including a plurality of adjacent pixel regions along a first direction and a second direction; A plurality of photoelectric conversion regions disposed in the plurality of pixel regions; a blocking region disposed in the plurality of pixel regions; a plurality of wiring layers and a plurality of insulating layers disposed on the first surface of the substrate; a plurality of color filters and a plurality of microlenses disposed on the second surface of the substrate; the blocking region is disposed adjacent the second surface of the substrate; the blocking region includes a first element of a first type; the plurality of photoelectric conversion regions include a second element of a second type different from the first type; The concentration of the first element in the blocking region is 1E16 / cm ３ ~1E18 / cm ３ 1. An image sensor comprising:

2. 2. The image sensor of claim 1, wherein the first element comprises boron-11 (11Boron).

3. 3. The image sensor of claim 2, wherein a thickness of the blocking region along a third direction perpendicular to the first direction and the second direction and extending from the second surface of the substrate to the first surface is about 250 nm to about 2000 nm.

4. the deep trench extends through the substrate from the first side to the second side; a pixel isolating structure disposed within the deep trench; along the third direction, an upper surface of the pixel separating structure is coplanar with the first surface of the substrate and a lower surface of the pixel separating structure is coplanar with the second surface of the substrate; The image sensor of claim 1 , wherein the blocking region includes a plurality of blocking regions partitioned by the pixel separating structure and corresponding to the plurality of pixel regions.

5. 2. The image sensor of claim 1, further comprising a fine pattern layer including a plurality of protrusions disposed under the blocking region along a third direction perpendicular to the first direction and the second direction and extending from the second surface of the substrate to the first surface of the substrate.

6. forming a plurality of deep trenches extending from a first surface of the substrate toward an interior of the substrate, the deep trenches separating adjacent pixel regions along a first direction and a second direction; implanting a first element of a first type into the first surface of the substrate using a first high energy implantation method to form a blocking region; and injecting a second element of a second type into the first surface of the substrate using a second high energy injection method to form a plurality of photoelectric conversion regions; An image sensor manufacturing method, characterized in that the multiple photoelectric conversion regions are arranged on the blocking region along a third direction perpendicular to the first direction and the second direction and toward the first surface of the substrate.

7. 7. The method of claim 6, wherein the first element comprises boron-11 (11Boron).

8. 8. The method of claim 7, wherein the energy intensity of the first high energy implantation technique is about 2.5 MeV to about 6.5 MeV.

9. The implantation dose of the first high energy implantation method is about 5E12 / cm ２ ~Approx. 1E14 / cm ２ 9. The method for manufacturing an image sensor according to claim 8,

10. forming a plurality of pixel isolating structures within the plurality of deep trenches of the substrate; and polishing an opposing surface of the substrate opposite the first surface to form a second surface of the substrate, along the third direction, an upper surface of the pixel separating structure is coplanar with the first surface of the substrate and a lower surface of the pixel separating structure is coplanar with the second surface of the substrate; 10. The method of claim 9, wherein the blocking region includes a plurality of blocking regions that are partitioned by the pixel separating structure and correspond to the plurality of pixel regions.

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