Information processing device and data transfer control method

Abstract

To increase the performance of an information processing device by reducing a latency in obtaining operation data.SOLUTION: A control unit 7 obtains first information indicating whether data which is first information obtained by source code analysis of a program and which is data transferred from a first memory 6 based on a data transfer request from an operation unit 3 is data used for operation for a predetermined process which is specified based on operation execution time from among a plurality of processes included in a program. The control unit 7 executes, based on the first information for each piece of transferred data, either first transfer control of transferring the data to the operation unit 3 via a second memory 4 from the first memory 6 or second transfer control of bypassing the second memory 4 and transferring the data from the first memory 6 to the operation unit 3.SELECTED DRAWING: Figure 9

Description

[Technical field]

[0001] The present invention relates to an information processing device and a data transfer control method. [Background technology]

[0002] There is known an information processing device that includes a local memory (LM) having a higher data transfer speed than the memory unit between a memory unit such as a memory (e.g., a main storage device) or a cache and a computing unit such as a processor core. When the computing unit performs a calculation in a program, the computing unit transfers (copies) data used in the calculation from the memory unit to the LM, and executes the calculation using the data transferred to the LM. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2008-117388 A [Patent Document 2] JP 2016-206796 A [Patent Document 3] US Patent Application Publication No. 2018 / 0225219 Summary of the Invention [Problem to be solved by the invention]

[0004] In the above-mentioned information processing device, the latency from when the arithmetic unit starts acquiring data to be used for the calculation to when the arithmetic unit executes the calculation using the acquired data (latency for acquiring data for calculation) may be large, compared to a configuration not equipped with an LM. Depending on the program in which the arithmetic unit executes the calculation, the performance of the information processing device may be degraded due to the large latency.

[0005] In one aspect, an object of the present invention is to improve the performance of an information processing device by reducing the latency of acquiring data for calculation. [Means for solving the problem]

[0006] In one aspect, the information processing device may include a calculation unit, a first memory, a second memory, and a control unit. The calculation unit may execute calculations of a program including a plurality of processes. The first memory may store data used in the calculations. The second memory may be a memory provided between the first memory and the calculation unit and having a data transfer rate higher than that of the first memory. The control unit may control the transfer of data from the first memory to the calculation unit based on a data transfer request acquired from the calculation unit. The control unit may acquire first information obtained by analyzing a source code of the program, the first information indicating whether the data transferred from the first memory based on the data transfer request is data used in a calculation of a predetermined process specified based on an execution time of the calculation among the plurality of processes. Furthermore, the control unit may execute, for each data to be transferred, either a first transfer control for transferring the data from the first memory to the calculation unit via the second memory or a second transfer control for transferring the data from the first memory to the calculation unit by bypassing the second memory, based on the first information. Effect of the Invention

[0007] In one aspect, the present invention can improve the performance of an information processing device by reducing the latency of acquiring data for calculation. [Brief description of the drawings]

[0008] [Figure 1] FIG. 2 is a block diagram showing an example of a hardware configuration of a server according to an embodiment. [Diagram 2] 2 is a block diagram showing a configuration example of a calculation function unit of a server. FIG. [Diagram 3] 1 is a diagram showing an example of a data transfer path in an arithmetic function unit; [Figure 4] FIG. 11 is a diagram illustrating an example of a process for calculating a critical path. [Diagram 5]FIG. 11 is a diagram illustrating an example of data to be transferred. [Figure 6] 2 is a block diagram showing a configuration example of a calculation function unit of a server. FIG. [Figure 7] 7 is a block diagram showing a first configuration example of a control unit shown in FIG. 6. [Figure 8] 7 is a block diagram showing a second configuration example of the control unit shown in FIG. 6. [Figure 9] 7 is a diagram for explaining an example of processing in the arithmetic processing unit shown in FIG. 6. FIG. [Figure 10] FIG. 10 is a diagram for explaining an example of a case in which data transfer in FIG. 9 goes through a first route. [Figure 11] 10 is a diagram for explaining an example of a case in which data transfer in FIG. 9 goes through a second route. FIG. [Figure 12] 11 is a diagram for explaining an example of a process for determining whether a data bus is saturated; FIG. [Figure 13] 13 is a flowchart illustrating an example of an analysis process by a compiler. [Figure 14] 13 is a flowchart illustrating an example of a data transfer process by a server. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. However, the embodiment described below is merely an example, and is not intended to exclude various modifications or application of techniques not specified below. For example, this embodiment can be modified in various ways without departing from the spirit of the invention. In the drawings used in the following description, parts with the same reference numerals represent the same or similar parts unless otherwise specified.

[0010] [A] Configuration example of one embodiment 1 is a block diagram showing an example of a hardware (HW) configuration of a computer that realizes the functions of a server 1 according to an embodiment. The server 1 is an example of an information processing device.

[0011] As shown in FIG. 1, the server 1 may, as its HW configuration, illustratively include a CPU (Central Processing Unit) 1a, a graphics processing device 1b, a memory 1c, a storage device 1d, an IF (Interface) device 1e, an IO (Input / Output) device 1f, and a reading device 1g.

[0012] The CPU 1a performs various controls and calculations. The CPU 1a may be connected to each block in the server 1 via a bus 1j so that they can communicate with each other. The CPU 1a may be a multiprocessor including a plurality of processors, a multicore processor having a plurality of processor cores, or a configuration having a plurality of multicore processors.

[0013] Instead of the CPU 1a, a processor such as an integrated circuit (IC) such as an MPU, APU, DSP, ASIC, or FPGA may be provided. A combination of two or more of these integrated circuits may be used as a processor. MPU is an abbreviation for Micro Processing Unit. APU is an abbreviation for Accelerated Processing Unit. DSP is an abbreviation for Digital Signal Processor, ASIC is an abbreviation for Application Specific IC, and FPGA is an abbreviation for Field-Programmable Gate Array.

[0014] The graphics processing device 1b controls screen display for an output device such as a monitor of the IO device 1f. The graphics processing device 1b may also have a configuration as an accelerator that executes machine learning processing and inference processing using a machine learning model. Examples of the graphics processing device 1b include various arithmetic processing devices, such as integrated circuits (ICs) such as a GPU (Graphics Processing Unit), an APU, a DSP, an ASIC, or an FPGA.

[0015] The CPU 1a and the graphics processing unit 1b are each an example of a processing unit.

[0016] The memory 1c is an example of HW that stores various data, programs, and other information. The memory 1c may be, for example, one or both of a volatile memory such as a dynamic random access memory (DRAM) and a non-volatile memory such as a persistent memory (PM). The memory 1c is an example of a first memory or a main storage device.

[0017] The storage device 1d is an example of HW that stores various data, programs, and other information. Examples of the storage device 1d include various storage devices such as a magnetic disk device such as a hard disk drive (HDD), a semiconductor drive device such as a solid state drive (SSD), and a non-volatile memory. Examples of the non-volatile memory include a flash memory, a storage class memory (SCM), and a read only memory (ROM).

[0018] The storage device 1d may store a program 1h. The program 1h is a program executed by the CPU 1a or the graphic processing device 1b. The program 1h may include a plurality of processes. The plurality of processes may include two or more processes that can be executed in parallel with each other. The storage device 1d may store a compiler 20 (analysis program) that generates the program 1h by converting (compiling) the source code of the program 1h into a format executable by the arithmetic unit of the CPU 1a. The compiler 20 may be stored in the server 2 described later, in which case the compiler 20 may be omitted from the storage device 1d.

[0019] For example, the processor 1a of the server 1 loads a program 1h stored in the storage device 1d into the memory 1c and executes it.

[0020] The IF device 1e is an example of a communication IF that controls the connection and communication between the server 1 and other computers. For example, the IF device 1e may include an adapter that complies with a LAN (Local Area Network) such as Ethernet (registered trademark) or optical communication such as FC (Fibre Channel). The adapter may support one or both of wireless and wired communication methods.

[0021] For example, the server 1 may be connected to the server 2 via the IF device 1e and a network so as to be able to communicate with each other. The program 1h may be downloaded from the network to the server 1 via the communication IF and stored in the storage device 1d.

[0022] The IO device 1f may include one or both of an input device and an output device. Examples of the input device include a keyboard, a mouse, a touch panel, etc. Examples of the output device include a monitor, a projector, a printer, etc. The IO device 1f may also include a touch panel in which the input device and the display device are integrated. The output device may be connected to the graphics processing device 1b.

[0023] The reading device 1g is an example of a reader that reads out data or program information recorded on the recording medium 1i. The reading device 1g may include a connection terminal or device to which the recording medium 1i can be connected or inserted. Examples of the reading device 1g include an adapter that complies with USB (Universal Serial Bus) or the like, a drive device that accesses a recording disk, and a card reader that accesses a flash memory such as an SD card. The recording medium 1i may store a program 1h, and the reading device 1g may read the program 1h or a compiled program from the recording medium 1i and store it in the storage device 1d.

[0024] Examples of the recording medium 1i include non-transitory computer-readable recording media such as magnetic / optical disks and flash memories. Examples of the magnetic / optical disks include flexible disks, CDs (Compact Discs), DVDs (Digital Versatile Discs), Blu-ray Discs, and HVDs (Holographic Versatile Discs). Examples of the flash memory include semiconductor memories such as USB memories and SD cards.

[0025] The above-described HW configuration of the server 1 is an example. Therefore, the HW in the server 1 may be increased or decreased (for example, adding or deleting any block), divided, or integrated in any combination, or buses may be added or deleted, etc. as appropriate.

[0026] 1, a server 2 may be connected to the server 1 via an IF device 1e. The server 2 is an example of a compiling device that compiles the source code of the program 1h. The server 2 may transmit data of the program 1h to the server 1 via a network (not shown).

[0027] A computer that realizes the functions of the server 2 may have a HW configuration similar to that of the server 1 illustrated in Fig. 1. For example, the storage device 1d of the server 2 may store a compiler 20 (analysis program) that realizes all or part of the various functions of the server 2.

[0028] Fig. 2 is a block diagram showing a configuration example of the arithmetic function unit 10 of the server 1. The arithmetic function unit 10 is an example of a component between the CPU 1a or the graphic processing device 1b and the memory 1c shown in Fig. 1. Fig. 2 shows a first configuration example and a second configuration example as connection configurations of the arithmetic function unit 10.

[0029] In the first configuration example, the arithmetic function unit 10 of the server 1 includes a calculator 3, a local memory (LM) 4, and a memory 1c. In the second configuration example, the arithmetic function unit 10 of the server 1 includes a calculator 3, a local memory 4, a cache 5, and a memory 1c.

[0030] The computing unit 3 is, for example, an integrated circuit such as a processor core. For example, the computing unit 3 may be one or both of a CPU core included in the CPU 1a and a processor core included in the graphics processing device 1b. The computing unit 3 is an example of a computing unit that executes the calculations of a program 1h including multiple processes.

[0031] The cache 5 is a memory that temporarily stores data read from the memory 1c. The cache 5 may be located within the CPU 1a or the graphic processing device 1b, or may be located outside the CPU 1a or the graphic processing device 1b.

[0032] Hereinafter, the memory 1c in the first configuration example of the arithmetic function unit 10, or the cache 5 (or the memory 1c and the cache 5) in the second configuration example of the arithmetic function unit 10 may be referred to as a memory unit 6.

[0033] The LM4 is an example of a second memory that is provided between the memory unit 6 and the arithmetic unit 3 and has a higher data transfer speed than the memory unit 6. The LM4 may be provided in, for example, the CPU 1a or the graphics processing unit 1b.

[0034] Fig. 3 is a diagram showing an example of a data transfer path in the arithmetic function unit 10 of Fig. 2. The memory unit 6, in other words, at least one of the memory 1c and the cache 5, is an example of a first memory that stores data used in the arithmetic operation by the arithmetic unit 3.

[0035] The LM 4 includes a storage area 4a and a bypass path 4b that bypasses the storage area 4a. The bypass path 4b may be provided inside the LM 4 or outside the LM 4.

[0036] 3, data transfer paths in the arithmetic function unit 10 include a first path and a second path. The first path is a path for transferring data from the memory unit 6 to the arithmetic unit 3 via LM4 (storage area 4a of LM4). On the other hand, the second path is a path for transferring data from the memory unit 6 to the arithmetic unit 3, bypassing LM4 (storage area 4a of LM4). In the second path, data may be transferred from the memory unit 6 to the arithmetic unit 3 via the bypass path 4b of LM4.

[0037] In this embodiment, the program 1h executed by the arithmetic unit 3 has a critical path identified by analyzing the source code.

[0038] The critical path is an example of a predetermined process identified based on the execution time of an operation among a plurality of processes included in the program 1h. The critical path may be, for example, a process (part) in which latency is important among two or more processes that can be executed in parallel with each other.

[0039] For example, the critical path may be a process that is expected to take the longest time among two or more processes that are executed simultaneously in parallel in the program 1h. In one example, the critical path may be a top predetermined number of processes with the largest total execution latency among two or more processes that can be executed in parallel, or may be a plurality of processes whose total execution latency is equal to or greater than a predetermined value.

[0040] The analysis of the source code may be, for example, a static analysis. The static analysis may be performed, for example, when compiling the source code. For example, the compiler 20 or the server 2 may identify, for each of a plurality of processes, whether it is a critical path identified based on the execution time of an operation or a normal process other than the critical path.

[0041] The arithmetic function unit 10 executes a first transfer control for transferring data used in the calculation of normal processing other than the critical path via a first path based on the result identified by the analysis. Also, the arithmetic function unit 10 executes a second transfer control for transferring data used in the calculation of the critical path via a second path based on the result identified by the analysis.

[0042] Fig. 4 is a diagram showing an example of a critical path calculation process. In Fig. 4, a program 1h includes process block #1, process block #2, and process block #3 (process group), which are processing units executed in parallel with each other. These multiple process blocks are an example of two or more processes that can be executed in parallel with each other among multiple processes.

[0043] The compiler 20 or the server 2 counts the number of executions (number of executed instructions) for each type of instruction executed in the processing block for each of the multiple processing blocks. The compiler 20 or the server 2 calculates a total execution latency by summing up the number of instructions multiplied by the execution latency for each type of instruction executed in the calculation of each processing block across all types of instructions. The total execution latency may be calculated, for example, according to the following formula (1). Total execution latency = Σ(number of instructions executed per type of instruction × execution latency per type of instruction) (1)

[0044] Execution latency may be called execution delay time, and may be the delay time from when a computer processes an input signal to when it outputs the processing result. The execution latency is a value that differs depending on the type of instruction and the architecture of the arithmetic function unit 10.

[0045] In the example shown in FIG. 4, the total execution latencies of processing block #1, processing block #2, and processing block #3 are 150, 200, and 180, respectively. The compiler 20 or server 2 may, for example, identify a predetermined number of processes (e.g., the top one (top) process) having the largest total execution latency as the critical path. The compiler 20 or server 2 sets a critical path flag for each processing block indicating that it is a critical path based on the value of the total execution latency. The critical path flag is an example of critical path information, and is an example of second information indicating whether each process is a critical path, which is a predetermined process among a plurality of processes.

[0046] The right column of Fig. 4 shows the value of the critical path flag. In Fig. 4, the critical path flag has a first value for a process that is a critical path among a plurality of processes, and has a second value different from the first value for a process that is not a critical path, i.e., a normal process. In the example of Fig. 4, the first value is 1 (ON) and the second value is 0 (OFF), but the opposite is also possible.

[0047] 4 shows a case where the highest process having the greatest total execution latency is set as the critical path, but the setting of the critical path is not limited to this case. A predetermined number of processes having the greatest total execution latency may be set as the critical path.

[0048] 5 is a diagram showing an example of transferred data 60. The transferred data 60 is data used in an operation, and may be various information such as an instruction, an address, a value, a parameter, etc., of the operation. The data 60 may include a flag 61 and a payload 62.

[0049] The flag 61 is an example of first information indicating whether the data is used for a calculation of a critical path, which is a predetermined process specified based on the execution time of an operation among a plurality of processes. The flag 61 indicates whether the data is on a critical path calculated by the calculation procedure shown in Fig. 4, that is, whether the data is used for a calculation process of the critical path. The flag 61 may be used for route allocation between the first route and the second route shown in Fig. 3. The payload 62 is the main body of the data. The payload 62 may be referred to as a body portion.

[0050] In one embodiment, the data 60 may be generated by, for example, the compiler 20 or the server 2 adding a flag 61 indicating a first value to a payload 62 used in an operation executed on a critical path. The critical path may be identified by static analysis of the source code by the compiler 20 or the server 2. The generation of the data 60 may be performed, for example, when the compiler 20 or the server 2 compiles the source code.

[0051] In one example, when the flag 61 is OFF, this indicates that data is transferred to the calculator 3 via a first path that passes through the memory area 4a of the LM 4. When the flag 61 is OFF, this may include, for example, a case where the flag 61 is not included in the data 60.

[0052] The flag 61 being ON indicates that data is to be transferred to the calculator 3 via a second path that passes through the bypass path 4b that bypasses the memory area 4a of the LM 4. When the flag 61 is ON, the flag 61 may be included in the data 60, for example.

[0053] 6 is a block diagram showing an example of the configuration of the arithmetic function unit 10 of the server 1. The configurations of the arithmetic unit 3, the LM 4, and the memory unit 6 are similar to the configuration described in FIG.

[0054] The arithmetic function unit 10 includes a control unit 7 in addition to the arithmetic unit 3, the LM 4, and the memory unit 6. The control unit 7 controls the transfer of data 60 from the memory unit 6 to the arithmetic unit 3 based on a data transfer request obtained from the arithmetic unit 3.

[0055] The data bus 11 is a bus for transferring data 60 among the arithmetic unit 3, the LM 4, the memory unit 6, and the control unit 7. The DMA (Direct Memory Access) request bus 12 is a bus for communicating a DMA transfer request from the arithmetic unit 3 among the arithmetic unit 3, the memory unit 6, and the control unit 7.

[0056] DMA is a method in which a device other than the arithmetic unit 3 of the CPU 1a or the graphics processing device 1b executes data transfer between memories, such as between the memory unit 6 and the LM4, and in the example of Fig. 6, it is executed by the control unit 7. The arithmetic unit 3 outputs a DMA transfer request via a DMA request bus 12. The DMA transfer request is an example of a data transfer request.

[0057] When the control unit 7 receives a DMA transfer request, it sends the data 60 stored in the memory unit 6 to either one of a first route via the storage area 4a of the LM4 or a second route via a bypass route 4b that bypasses (detouring) the storage area 4a of the LM4, based on a flag 61 corresponding to the data 60. The control unit 7 may have a switch function for switching between the first route and the second route.

[0058] Fig. 7 is a block diagram showing a first configuration example of the control unit 7 shown in Fig. 6. The control unit 7 shown in Fig. 7 has a DMA request receiving unit 7a, a DMA executing unit 7b, and a transfer control unit 7c. In the example of Fig. 7, it is assumed that the data 60 stored in the memory unit 6 includes a flag 61.

[0059] The DMA request receiving unit 7 a receives a DMA transfer request from the arithmetic unit 3 via a DMA request bus 12 .

[0060] The DMA execution unit 7b executes DMA (data transfer) from the memory unit 6 in response to a DMA transfer request. In one example, the DMA execution unit 7b reads data 60 of a data size from a source address according to a source address, a destination address, a data size, and the like specified based on the DMA transfer request, and transfers the read data 60 to the destination address. The source address is, for example, an address in the memory unit 6. The destination address may be an address in the storage area 4a of the LM4.

[0061] In one example, a descriptor describing information related to the transfer of data 60 may be stored in an address in memory unit 6 designated by the DMA transfer request. DMA execution unit 7b may read the descriptor from the address in memory unit 6 designated by the DMA transfer request, and obtain information such as a source address, a destination address, and a data size described in the descriptor.

[0062] The transfer control unit 7c executes transfer control based on a flag 61 of the data 60 transferred from the memory unit 6 by the DMA execution unit 7b. The transfer control unit 7c executes either a first transfer control for transferring the data 60 from the memory unit 6 to the arithmetic unit 3 via a first path, or a second transfer for transferring the data 60 from the memory unit 6 to the arithmetic unit 3 via a second path, for each data 60 to be transferred, based on the flag 61. For example, the transfer control unit 7c may have a switch function for switching the transfer path.

[0063] In one example, when the flag 61 indicates that the data 60 is data used in the calculation of the critical path, the transfer control unit 7c changes the transfer destination address from the address of the memory area 4a of the LM4 to the address of the buffer 3a included in the calculator 3. In this case, the transfer control unit 7c sends the data 60 to the second path of the data bus 11.

[0064] When the flag 61 indicates that the data 60 is used for calculation of general processing other than the critical path, the transfer control unit 7c maintains the transfer destination address as the address of LM4. In this case, the transfer control unit 7c transmits the data 60 to the first path of the data bus 11.

[0065] Fig. 8 is a block diagram showing a second configuration example of the control unit 7 shown in Fig. 6. The control unit 7 shown in Fig. 8 includes a DMA request receiving unit 7a, a DMA executing unit 7b', a transfer control unit 7c, a path determining unit 7d, and a critical path information storage unit 7e.

[0066] The example of Fig. 8 shows a case where the flag 61 is not set in advance in the data 60. In the example of Fig. 8, a case will be described where the control unit 7 identifies the data 60 used in the calculation of the critical path in response to receiving a DMA transfer request, and adds the flag 61 to the payload 62 of the data 60. Note that in the example of Fig. 8, the process of the compiler 20 or the server 2 adding the flag 61 to the payload 62 may be omitted.

[0067] The DMA request receiving unit 7a and the transfer control unit 7c are similar to the control unit 7 of the first configuration example shown in FIG.

[0068] The path determination unit 7d compares information specified based on the DMA transfer request (e.g., information added to the DMA transfer request) with information stored in the critical path information storage unit 7e to determine whether the command specified based on the DMA transfer request is a command to be processed with priority. In other words, the path determination unit 7d determines whether the data 60 transferred based on the DMA transfer request is data used in the calculation of the critical path. When the path determination unit 7d determines that the data 60 is data used in the calculation of the critical path, it notifies the DMA execution unit 7b' to add a flag 61 (first value) to the payload 62 of the data 60.

[0069] In the second configuration example shown in FIG. 8, the DMA transfer request may include information indicating in which processing block in the program 1h the data 60 to be transferred is used.

[0070] As shown in FIG. 4, the critical path information storage unit 7e stores, for each process block, a critical path flag indicating whether or not a process block is a critical path that is a predetermined process among a plurality of processes.

[0071] The critical path flag may be stored in the critical path information storage unit 7e when the program 1h is executed, for example. Alternatively, the critical path flag may be included in the DMA transfer request. When the critical path flag is included in the DMA transfer request, the critical path information storage unit 7e may be omitted in the control unit 7', and in this case, the path determination unit 7d may make a determination based on the DMA transfer request.

[0072] In response to a DMA transfer request, the DMA execution unit 7b' executes DMA (data transfer) from the memory unit 6. The execution of DMA is similar to the processing of the DMA execution unit 7b in the first configuration example shown in FIG.

[0073] Furthermore, when the DMA execution unit 7b' is notified that, for example, a flag 61 (first value) is to be added to the payload 62 as a result of the determination by the route determination unit 7d, the DMA execution unit 7b' includes the flag 61 indicating the first value in the data 60 to be transferred.

[0074] The transfer control unit 7c executes transfer control based on the flag 61 of the data 60 read from the memory unit 6 by the DMA execution unit 7b.

[0075] 7, in the first configuration example, the control unit 7 controls the transfer of the data 60 to the first path or the second path based on the flag 61 already added to the data 60. On the other hand, in the second configuration example, the control unit 7 controls the addition of the flag 61 (first value) to the data 60 to which the flag 61 has not been added in response to receiving a DMA transfer request, and controls the transfer of the data 60 to the first path or the second path based on the flag 61.

[0076] The control unit 7 may have either the first or second configuration example. In the following description, for convenience, the first configuration example shown in Fig. 7 is used as the control unit 7, but the present invention is not limited to this. The following description can also be applied to the case where the second configuration example shown in Fig. 8 is used as the control unit 7.

[0077] Fig. 9 is a diagram for explaining an example of processing in the arithmetic function unit 10 shown in Fig. 6. The arithmetic unit 3 issues a DMA transfer request to request data 60 used in the arithmetic operation from the memory unit 6 (process (i)).

[0078] When a DMA transfer request arrives at the control unit 7 (process (ii)), the control unit 7 reads data 60 to be transferred from the memory unit 6 based on the received DMA transfer request (process (iii)). Based on a flag 61 corresponding to the data 60, the control unit 7 sends the data 60 to either a first route that passes through the memory area 4a of LM4 or a second route that passes through a bypass route 4b that bypasses (detouring) the memory area 4a of LM4 (process (iv)). The transfer route may be specified depending on the presence or absence of the flag 61, or the transfer route may be specified depending on the value of the flag 61.

[0079] Fig. 10 is a diagram for explaining an example of a case where data transfer passes through the first route in Fig. 9. When the flag 61 corresponding to the data 60 is OFF, the data 60 is transferred to the memory area 4a of the LM4 and stored in the memory area 4a (process (v)).

[0080] The calculator 3 waits for the completion of the transfer of the data 60 to the LM 4, in other words, for the completion of storing the data in the memory area 4a of the LM 4. When the calculator 3 detects the completion of the transfer to the LM 4, it transfers the data 60 from the LM 4 to the buffer 3a of the calculator 3 (process (vi)).

[0081] Fig. 11 is a diagram for explaining an example of a case where data transfer passes through the second path in Fig. 9. When the flag 61 corresponding to the data 60 is ON, the data 60 is transferred directly to the buffer 3a of the arithmetic unit 3 through the bypass path 4b (without passing through the memory area 4a) and stored in the buffer 3a (process (vii)).

[0082] The calculator 3 normally waits for data 60 to be written to the LM4, but when data 60 from the bypass path 4b is directly written to a buffer 3a (data buffer) in the calculator 3, the calculator 3 prioritizes completing the DMA transfer request processing.

[0083] Here, in the above-mentioned data transfer control, the transfer path may be determined depending on whether the data bus 11 is saturated or not.

[0084] For example, when the data bus 11 is saturated based on the saturation determination result of the data bus 11, the control unit 7 may transfer the data 60 to the first path regardless of whether the flag 61 is ON or OFF. That is, when the data bus 11 is saturated, the control unit 7 may transfer the data 60 to the memory area 4a of the LM4 even if the flag 61 is ON. In other words, when the data bus 11 is saturated, the control unit 7 may suppress the execution of the data transfer to the second path (data transfer via the bypass path 4b) even if the flag 61 is ON.

[0085] Fig. 12 is a diagram for explaining an example of a process for determining saturation of the data bus 11. As shown in Fig. 12, the arithmetic unit 3 may include a monitor unit 3b.

[0086] The monitor 3b acquires and accumulates the data size of the transfer data input to the input port of the calculator 3 via the first path. The monitor 3b also acquires and accumulates the data size of the transfer data input to the input port of the calculator 3 via the second path. In this way, the monitor 3b calculates the data transfer amount for each path in a unit time. The unit time may be a specific time, for example, one second.

[0087] The monitoring unit 3b may determine that the data bus 11 connected to the bypass path 4b is saturated when the ratio of the amount of data transferred via the second path (the bypass path 4b) to the total amount of data transferred to the input port of the computing unit 3 is equal to or greater than a predetermined first threshold value.

[0088] When it is determined that the data bus 11 is saturated, the monitor unit 3b or the calculator 3 transmits a flag invalidation instruction to the control unit 7 via the DMA request bus 12. The flag invalidation instruction is an instruction to transfer the data 60 to the LM 4 via the first path, regardless of the presence or absence and content of the flag 61. The control unit 7 that receives the flag invalidation instruction executes data transfer control so as to transfer the data 60 via the first path, regardless of the presence or absence and content of the flag 61.

[0089] Specifically, the control unit 7 receives a flag invalidation instruction, and while the flag invalidation instruction is valid, transfers data 60 to the storage area 4a of LM4 based on a DMA transfer request, regardless of the presence and content of the flag 61. The calculator 3 waits for the transfer of the data 60 to LM4 to be completed, in other words, for the data to be saved in the storage area 4a of LM4 to be completed. When the calculator 3 detects the completion of the transfer to LM4, it transfers the data 60 from LM4 to the buffer 3a of the calculator 3.

[0090] Furthermore, the monitoring unit 3b may determine that the saturation of the data bus 11 connected to the bypass path 4b has been resolved when the ratio of the amount of data transferred via the second path to the total amount of data transferred to the input port of the arithmetic unit 3 is less than a predetermined second threshold. The second threshold may be the same value as the above-mentioned first threshold, or may be a value less than the first threshold.

[0091] When it is determined that the saturation of the data bus 11 has been resolved, the monitor unit 3b or the calculator 3 transmits a flag validation instruction to the control unit 7 via the DMA request bus 12. The flag validation instruction is an instruction to cause the control unit 7 to control data transfer so as to send the data 60 to either the first path or the second path depending on the presence or absence or content of the flag 61. Note that the transmission of the flag validation instruction may be the stopping (deassertion) of the signal of the flag invalidation instruction. The control unit 7 that has received the flag validation instruction transmits the data 60 to either the first path or the second path based on the flag 61.

[0092] [B] Example of operation [B-1] Example of compiler operation Next, an example of the operation of a computer functioning as the compiler 20 according to an embodiment will be described. Note that the computer functioning as the compiler 20 may be, for example, the server 1 when the server 1 also functions as the compiler 20, or may be the server 2 when the server 2 functions as the compiler 20.

[0093] Fig. 13 is a flowchart showing an example of an analysis process by the compiler 20 according to an embodiment. In Fig. 13, a case where the computer functioning as the compiler 20 is the server 2 is taken as an example, but the same applies when the server 1 functions as the compiler 20.

[0094] The server 2 divides the processing of the program 1h into a plurality of processing blocks by statically analyzing the source code of the program 1h (step S1). The plurality of processing blocks may be, for example, processing blocks that can be executed in parallel with each other.

[0095] The server 2 analyzes the execution instructions in the processing block (step S2). Steps S1 and S2 are an example of a process for identifying two or more processes that can be executed in parallel from among a plurality of processes included in the program 1h by analyzing the source code of the program 1h.

[0096] If there is an unprocessed processing block (step S3, YES in step S3), the server 2 executes the processing of steps S4 to S6. The server 2 selects one processing block and calculates the total execution latency within that processing block (step S4).

[0097] If the calculated total execution latency within the processing block is the largest among the multiple processing blocks (step S5, YES in step S5), the server 2 sets the selected processing block to the critical path (step S6), and the process proceeds to step S3.

[0098] If the calculated total execution latency within the processing block is not the greatest among the multiple processing blocks (NO in step S5), the server 2 refrains from setting the selected processing block as a critical path, and the process proceeds to step S3.

[0099] In steps S4 to S6, the processing block with the greatest total execution latency among the multiple processing blocks is set as the critical path, but this is not limited to this. For example, the server 2 may set a top predetermined number (2 or more) of processing blocks with the greatest total execution latency among the multiple processing blocks as the critical path, or may set a process with a total execution latency equal to or greater than a predetermined value as the critical path.

[0100] When the processing of all the processing blocks is completed and there are no unprocessed processing blocks (NO in step S3), the server 2 adds a flag to the processing block set on the critical path (step S7), and the processing ends.

[0101] For example, in step S7, the server 2 may generate data 60 by adding a flag 61 to the payload 62, as shown in FIG. 5, with multiple data (e.g., instructions, addresses, values, parameters, etc.) used in the calculation of the processing block set on the critical path as the payload 62.

[0102] Alternatively, the server 2 may set a critical path flag for a processing block that is set on a critical path, as shown in Fig. 4. The critical path flag may be stored in the critical path information storage unit 7e.

[0103] [B-2] Example of data transfer control process Next, an example of the operation of the server 1 that executes the data transfer control process according to an embodiment will be described below.

[0104] When the arithmetic unit 3 starts executing the program 1h, the arithmetic unit 3 requests the data 60 to be used in the calculation (step S11).

[0105] If the requested data 60 exists in LM4 (step S12, YES in step S12), the calculator 3 loads the data 60 to be used in the calculation from LM4 (step S19), executes the calculation using the data 60 (step S20), and the process ends.

[0106] If the requested data does not exist in the LM 4 (NO in step S12), the calculator 3 issues a DMA transfer request (step S13).

[0107] The control unit 7 executes DMA based on the DMA transfer request (step S14). For example, the DMA execution unit 7b reads the data 60 to be transferred from the memory unit 6 based on the DMA transfer request received by the DMA request receiving unit 7a, and outputs the data 60 to the transfer control unit 7c.

[0108] Based on a flag 61 corresponding to the data 60, the transfer control unit 7c sends the data 60 to either a first route via the memory area 4a of LM4 or a second route via a bypass route 4b that bypasses (detours) the memory area 4a of LM4.

[0109] The transfer control unit 7c judges whether or not the flag 61 is ON in the data 60 (step S15). If the flag 61 is ON (YES in step S15), the transfer control unit 7c judges whether or not the data bus 11 between the control unit 7 and the arithmetic unit 3 is saturated (step S16). This judgment may be made based on whether or not a flag invalidation instruction has been received from the monitoring unit 3b.

[0110] If the data bus 11 is not saturated (NO in step S16), the control unit 7 transfers the data from the memory unit 6 to the arithmetic unit 3 via the bypass route 4b (step S17), and the process proceeds to step S20.

[0111] If the flag 61 in the data 60 is OFF (NO in step S15), or if the data bus 11 is saturated (YES in step S16), the control unit 7 transfers the data 60 from the memory unit 6 to the LM4 (step S18), and the process proceeds to step S19.

[0112] [C] Effects of one embodiment According to a method according to an embodiment, the control unit 7 acquires a flag 61 indicating whether or not the data 60 transferred from the memory unit 6 based on a data transfer request is data used in an operation of a critical path process identified based on the execution time of an operation among a plurality of processes. The flag 61 is a flag 61 obtained by analyzing the source code of the program 1h. The control unit 7 executes either the first transfer control or the second transfer control for each of the data 60 to be transferred based on the flag 61. For example, in the first transfer control, the control unit 7 transfers the data 60 from the memory unit 6 to the arithmetic unit 3 via the LM4, and in the second transfer control, the control unit 7 transfers the data 60 from the memory unit 6 to the arithmetic unit 3 bypassing the LM4.

[0113] This makes it possible to reduce the latency (latency for acquiring data for computation) from when the computing unit 3 starts acquiring data 60 used for computation to when the computing unit 3 executes computation using the acquired data 60 according to the processing content included in the program, thereby improving the performance of the server 1 related to the execution of the program 1h. For example, the data 60 used for computation of the critical path is transferred from the memory unit 6 to the computing unit 3 without passing through the LM4, so that the data transfer time from the memory unit 6 to the LM4 can be reduced. In addition, the data 60 used for computation of normal processing other than the critical path is transferred to the computing unit 3 via the LM4, so that it is possible to prevent the data bus 11 between the computing unit 3 and the memory unit 6 from being saturated.

[0114] Furthermore, the control unit 7 executes either the first transfer control or the second transfer control for each data 60 to be transferred, depending on the flag 61 corresponding to the data 60 and obtained by analyzing the source code. In this way, the control unit 7 can switch the transfer path of the data 60 according to a condition previously determined for each data 60. Therefore, compared to a case where the transfer path of the data 60 is dynamically switched depending on conditions such as the cache status of the data 60, cache hit or miss, etc., the hardware configuration including the control unit 7 can be simplified and manufacturing costs can be reduced.

[0115] Furthermore, the control unit 7 acquires the flag 61 added to the data 60 specified in the data transfer request. This allows the control unit 7 to simply refer to the flag 61 added to the data 60, thereby reducing the processing load on the control unit 7 and further simplifying the hardware configuration including the control unit 7.

[0116] Furthermore, the control unit 7 refers to a critical path flag indicating a predetermined process among the multiple processes, and when it determines that the process specified based on the data transfer request is a critical path, it adds a flag 61 to each of the multiple data 60 specified in the data transfer request. This allows the control unit 7 to refer to the critical path flag and add the flag 61 even if the flag 61 is not added to the data stored in the memory unit 6. Therefore, the compiler 20 only needs to specify the critical path, and the compilation processing load can be reduced.

[0117] Furthermore, the critical path flag is set based on the total execution latency obtained by multiplying the number of instructions and the execution latency for each type of instruction executed in the computation of each of the multiple processes, over all types of instructions. The control unit 7 executes a second transfer control for the data 60 used for each instruction included in a critical path, which is a top predetermined number of processes among the multiple processes having the largest total execution latency. This makes it possible to refer to the critical path using a quantitative comparison, and to transfer the data 60 used for each instruction included in the critical path from the memory unit 6 to the computing unit 3, bypassing the LM4. This makes it possible to perform transfer control based on more accurate criteria, thereby improving the performance of the information processing device.

[0118] According to a method of an embodiment, the server 1 or 2 that executes the compiler 20 (analysis program) analyzes the source code of the program 1h to identify two or more processes that can be executed in parallel from the processes included in the program. The server 1 or 2 identifies a critical path from the two or more processes based on an estimation result of the execution time of each operation of the two or more processes. The server 1 or 2 adds a flag 61 to the data 60 used in the operation of the critical path. The flag 61 is a flag for specifying the second path out of the first path and the second path as a transfer path when the data 60 is transferred from the memory unit 6 that stores the data 60 to the arithmetic unit 3 that executes the operation when the operation of the program 1h is executed. This makes it possible to reduce the latency from when the arithmetic unit 3 starts to acquire the data 60 used for the operation to when the arithmetic unit 3 executes the operation using the acquired data 60 according to the processing content included in the program, and improve the performance of the server 1 related to the execution of the program 1h.

[0119] [D] Other The technology according to the above-described embodiment can be modified and changed as follows.

[0120] For example, blocks 7a to 7c included in the control unit 7 shown in Fig. 7 may be merged in any combination or may be divided. Also, blocks 7a, 7b', and 7c to 7e included in the control unit 7 shown in Fig. 8 may be merged in any combination or may be divided.

[0121] [E] Notes Regarding the above embodiment, the following supplementary notes are further disclosed.

[0122] (Appendix 1) A calculation unit that executes calculations of a program including a plurality of processes; A first memory that stores data used in the calculation; a second memory provided between the first memory and the calculation unit and having a data transfer rate higher than that of the first memory; a control unit that controls a transfer of data from the first memory to the calculation unit based on a data transfer request obtained from the calculation unit; The control unit is acquiring first information obtained by analyzing a source code of the program, the first information indicating whether or not the data to be transferred from the first memory based on the data transfer request is data to be used in an operation of a predetermined process identified based on an execution time of an operation among the plurality of processes; executes, for each data to be transferred, either a first transfer control for transferring the data from the first memory to the arithmetic unit via the second memory or a second transfer control for transferring the data from the first memory to the arithmetic unit by bypassing the second memory, based on the first information. Information processing device.

[0123] (Appendix 2) the control unit acquires the first information added to the data specified in the data transfer request. 2. An information processing device according to claim 1.

[0124] (Appendix 3) The control unit is referring to second information indicating the predetermined process among the plurality of processes, and when the process specified based on the data transfer request is the predetermined process, adding the first information indicating that the data is used in a calculation of the predetermined process to each of the plurality of data specified based on the data transfer request; Executing one of the first transfer control and the second transfer control based on the added first information. 3. An information processing device according to claim 1 or 2.

[0125] (Appendix 4) the second information is set based on a total execution latency obtained by multiplying the number of instructions and the execution latency for each type of instruction executed in the computation of each of two or more processes among the plurality of processes that can be executed in parallel with each other, the total execution latency being obtained by summing up the value obtained by multiplying the number of instructions and the execution latency for all types of instructions; the control unit adds the first information to the data used for each instruction included in a top predetermined number of the predetermined processes having the largest total execution latency among the plurality of processes, or one or more of the predetermined processes having the total execution latency equal to or greater than a predetermined value; 4. The information processing device according to claim 3.

[0126] (Appendix 5) A data transfer control method for an information processing device including: a calculation unit that executes calculations of a program including a plurality of processes; a first memory that stores data used in the calculations; a second memory that is provided between the first memory and the calculation unit and has a data transfer speed higher than that of the first memory; and a control unit that controls transfer of data from the first memory to the calculation unit based on a data transfer request output from the calculation unit, The control unit: acquiring first information obtained by analyzing a source code of the program, the first information indicating whether or not the data to be transferred from the first memory based on the data transfer request is data to be used in an operation of a predetermined process identified based on an execution time of an operation among the plurality of processes; executes, for each data to be transferred, either a first transfer control for transferring the data from the first memory to the arithmetic unit via the second memory or a second transfer control for transferring the data from the first memory to the arithmetic unit by bypassing the second memory, based on the first information. A data transfer control method for executing a process.

[0127] (Appendix 6) the control unit acquires the first information added to the data specified in the data transfer request. 6. A data transfer control method as described in appendix 5.

[0128] (Appendix 7) The control unit: referring to second information indicating the predetermined process among the plurality of processes, and when the process specified based on the data transfer request is the predetermined process, adding the first information indicating that the data is used in a calculation of the predetermined process to each of the plurality of data specified based on the data transfer request; Executing one of the first transfer control and the second transfer control based on the added first information. 7. A data transfer control method according to claim 5 or 6.

[0129] (Appendix 8) the second information is set based on a total execution latency obtained by multiplying the number of instructions and the execution latency for each type of instruction executed in the computation of each of two or more processes among the plurality of processes that can be executed in parallel with each other, the total execution latency being obtained by summing up the value obtained by multiplying the number of instructions and the execution latency for all types of instructions; the control unit adds the first information to the data used for each instruction included in a top predetermined number of the predetermined processes having the largest total execution latency among the plurality of processes, or one or more of the predetermined processes having the total execution latency equal to or greater than a predetermined value; 8. The data transfer control method according to claim 7.

[0130] (Appendix 9) Identifying two or more processes that can be executed in parallel from the plurality of processes by analyzing source code of a program including the plurality of processes; Identifying a predetermined process from the two or more processes based on an estimated execution time of each of the two or more processes; adding first information for specifying a transfer path for data used in the operation of the predetermined process from a first memory that stores the data when the operation is executed to an operation unit that executes the operation, the transfer path being one of a first path for transferring the data from the first memory to the operation unit via a second memory that is provided between the first memory and the operation unit and has a higher data transfer rate than the first memory, and a second path for transferring the data from the first memory to the operation unit, bypassing the second memory; An analysis program that causes a computer to carry out processing.

[0131] (Appendix 10) The process of identifying the predetermined process is calculating a total execution latency for each of the two or more processes by multiplying the number of instructions by the execution latency for each type of instruction executed in the computation of the process, and summing the results across all types of instructions; A process of identifying a top predetermined number of processes having the largest total execution latency, or one or more processes having the total execution latency equal to or greater than a predetermined value, as the one or more predetermined processes. The analysis program described in Appendix 9. [Explanation of symbols]

[0132] 1 Server 1a CPU 1b Graphics Processing Unit 1c Memory 1d storage section 1e IF section 1f IO section 1g Reading unit 1h Program 1i Recording medium 1j Bus 10 Calculation Function Unit 11 Data Bus 12 DMA Request Bus 2 Server 20 Compiler 3 Arithmetic unit 3a Buffer 3b Monitoring section 4 LM 4a Storage area 4b Bypass route 5. Cache 6 Memory section 60 Data 61 Flags 62 Payload 7 Control section 7a DMA request receiver 7b, 7b´ DMA execution unit 7c Transfer control section 7d Path determination section 7e Critical path information storage unit

Claims

1. A calculation unit that executes calculations of a program including a plurality of processes; A first memory that stores data used in the calculation; a second memory provided between the first memory and the calculation unit and having a data transfer rate higher than that of the first memory; a control unit that controls a transfer of data from the first memory to the calculation unit based on a data transfer request obtained from the calculation unit; The control unit is acquiring first information obtained by analyzing a source code of the program, the first information indicating whether or not the data to be transferred from the first memory based on the data transfer request is data to be used in an operation of a predetermined process specified based on an execution time of an operation among the plurality of processes; executes, for each data to be transferred, either a first transfer control for transferring the data from the first memory via the second memory to the arithmetic unit, or a second transfer control for transferring the data from the first memory to the arithmetic unit, bypassing the second memory, based on the first information. Information processing device.

2. the control unit acquires the first information added to the data specified in the data transfer request. The information processing device according to claim 1 .

3. The control unit is referring to second information indicating the predetermined process among the plurality of processes, and when the process specified based on the data transfer request is the predetermined process, adding the first information indicating that the data is used in a calculation of the predetermined process to each of the plurality of data specified based on the data transfer request; Executing one of the first transfer control and the second transfer control based on the added first information.

3. The information processing device according to claim 1 or 2.

4. the second information is set based on a total execution latency obtained by multiplying the number of instructions and the execution latency for each type of instruction executed in the computation of each of two or more processes among the plurality of processes that can be executed in parallel with each other, the total execution latency being obtained by summing up, across all types of instructions, a value obtained by multiplying the number of instructions and the execution latency for each type of instruction executed in the computation of each of the processes; the control unit adds the first information to the data used for each instruction included in a top predetermined number of the predetermined processes having the largest total execution latency among the plurality of processes, or one or more of the predetermined processes having the total execution latency equal to or greater than a predetermined value; The information processing device according to claim 3 .

5. A data transfer control method for an information processing device including: a calculation unit that executes calculations of a program including a plurality of processes; a first memory that stores data used in the calculations; a second memory that is provided between the first memory and the calculation unit and has a data transfer speed higher than that of the first memory; and a control unit that controls a transfer of data from the first memory to the calculation unit based on a data transfer request output from the calculation unit, The control unit: acquiring first information obtained by analyzing a source code of the program, the first information indicating whether or not the data to be transferred from the first memory based on the data transfer request is data to be used in an operation of a predetermined process specified based on an execution time of an operation among the plurality of processes; executes, for each data to be transferred, either a first transfer control for transferring the data from the first memory via the second memory to the arithmetic unit, or a second transfer control for transferring the data from the first memory to the arithmetic unit, bypassing the second memory, based on the first information. A data transfer control method for executing a process.

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