Power supply control device and switching power supply

Abstract

To realize a configuration capable of transferring information between power supply control devices.SOLUTION: A power supply control device comprises: a synchronous input terminal (S_IN); a synchronous output terminal (S_OUT); a switching control circuit (20) which performs switching control of an output stage (MM); a synchronous output circuit (40) capable of setting a state of the synchronous output terminal to a first, second or third output state; and a synchronous input circuit (50) capable of setting a state of the synchronous input terminal to a first or second input state. The synchronous output circuit outputs signals at first and second levels from the synchronous output terminal in the first and second output states, and increases its own output impedance in the third output state higher than that in the first output state and the second output state. The synchronous input circuit pulls down the synchronous input terminal via a resistor in the first input state and pulls up the synchronous input terminal via the resistor in the second input state.SELECTED DRAWING: Figure 4

Description

[Technical field]

[0001] The present disclosure relates to a power supply control device and a switching power supply device. [Background technology]

[0002] 2. Description of the Related Art A method is known in which a multi-phase DC / DC converter is configured by synchronizing DC / DC converters for multiple channels (see, for example, Patent Document 1 below). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Patent Publication No. 2022-6829

[0004] [overview] There is a method of configuring a switching power supply device by providing multiple power supply control devices, each of which is responsible for switching control, and synchronizing the multiple power supply control devices. In this case, if it were possible to transmit information other than synchronization information between the multiple power supply control devices without requiring the addition of special dedicated terminals, the range of applications for various controls would be expanded.

[0005] A power supply control device according to one aspect of the present disclosure is a power supply control device provided in a switching power supply device configured to generate an output voltage from an input voltage, and includes a synchronous input terminal, a synchronous output terminal, an output stage for power converting the input voltage to the output voltage, a switching control circuit configured to power convert the input voltage to the output voltage by controlling the switching of the output stage in synchronization with a reference clock signal, a synchronous output circuit configured to set the state of the synchronous output terminal to one of a plurality of output states including first, second and third output states, and a synchronous output circuit configured to set the state of the synchronous input terminal to one of a plurality of input states including first and second input states. and a synchronous input circuit configured to set a first level signal from the synchronous output terminal in the first output state, a second level signal higher than the first level from the synchronous output terminal in the second output state, and a higher output impedance of the synchronous output circuit in the third output state than in the first output state and the second output state, the synchronous input circuit being capable of pulling down the synchronous input terminal to the first level or pulling up the synchronous input terminal to the second level via a resistor, and pulling down the synchronous input terminal in the first input state and pulling up the synchronous input terminal in the second input state. [Brief description of the drawings]

[0006] [Figure 1] FIG. 1 is an overall configuration diagram of a switching power supply device according to an embodiment of the present disclosure. [Diagram 2] FIG. 2 is an external perspective view of the power supply control device according to the embodiment of the present disclosure. [Diagram 3] FIG. 3 is an overall configuration diagram of a switching power supply device according to an embodiment of the present disclosure. [Figure 4] FIG. 4 is a diagram illustrating an internal configuration of a power supply control device according to an embodiment of the present disclosure. [Diagram 5] FIG. 5 is a diagram illustrating an internal configuration of a power supply control device in a first switch state according to an embodiment of the present disclosure. [Figure 6] FIG. 6 is a diagram illustrating an internal configuration of the power supply control device in the second switch state according to an embodiment of the present disclosure. [Figure 7] FIG. 7 is a timing chart of the power supply control device according to an embodiment of the present disclosure. [Figure 8] FIG. 8 is a diagram illustrating an example of an internal configuration of a synchronous output circuit according to an embodiment of the present disclosure. [Figure 9] FIG. 9 is a diagram illustrating an example of an internal configuration of a synchronous input circuit according to an embodiment of the present disclosure. [Figure 10] FIG. 10 is a diagram illustrating an internal configuration of a power supply control device according to an embodiment of the present disclosure. [Figure 11] FIG. 11 relates to a first example belonging to an embodiment of the present disclosure and is a diagram for explaining a method of transmitting information from a power supply control device on a subsequent stage to a power supply control device on a previous stage. [Figure 12] FIG. 12 is a conceptual diagram of the waveform of a clock signal output from a power supply control device on a front-stage side to a power supply control device on a rear-stage side according to a first example belonging to an embodiment of the present disclosure. [Figure 13] FIG. 13 relates to a first example belonging to an embodiment of the present disclosure, and is a waveform diagram of a clock signal and a level detection signal when a synchronous input circuit is in a pull-down state in a power supply control device on the downstream side. [Figure 14] FIG. 14 relates to a first example belonging to an embodiment of the present disclosure, and is a waveform diagram of a clock signal and a level detection signal when a synchronous input circuit is in a pull-up state in a power supply control device on the downstream side. [Figure 15] FIG. 15 is a diagram showing how three clock signals are propagated among a plurality of power supply control devices according to a first example of the embodiment of the present disclosure. [Figure 16] FIG. 16 is a diagram showing how two clock signals are propagated among a plurality of power supply control devices according to a first example of an embodiment of the present disclosure. [Figure 17] FIG. 17 is an operation flowchart of a power supply control device operating in a first mode according to a first example of an embodiment of the present disclosure. [Figure 18] FIG. 18 is an operation flowchart of a power supply control device operating in the second mode according to a first example belonging to an embodiment of the present disclosure. [Figure 19] FIG. 19 is a waveform diagram of four clock signals used for synchronizing switching in four power supply control devices according to a first example belonging to an embodiment of the present disclosure. [Figure 20] FIG. 20 is a diagram showing an internal configuration of a synchronous output circuit according to a first example of an embodiment of the present disclosure. [Figure 21] FIG. 21 is a conceptual diagram of the waveform of a clock signal output from a power supply control device on a front-stage side to a power supply control device on a rear-stage side according to a second example belonging to an embodiment of the present disclosure. [Figure 22] FIG. 22 relates to a second example belonging to an embodiment of the present disclosure, and is a waveform diagram of a clock signal and a level detection signal when a synchronous input circuit is in a pull-down state in a power supply control device on the downstream side. [Diagram 23] FIG. 23 relates to a second example belonging to an embodiment of the present disclosure, and is a waveform diagram of a clock signal and a level detection signal when a synchronous input circuit is in a pull-up state in a power supply control device on the downstream side. [Figure 24] FIG. 24 is an operation flowchart of a power supply control device operating in the first mode according to a second example belonging to an embodiment of the present disclosure. [Diagram 25] FIG. 25 is an operation flowchart of a power supply control device operating in the second mode according to a second example of the embodiment of the present disclosure. [Figure 26] FIG. 26 is a diagram showing an internal configuration of a synchronous output circuit according to a second example of an embodiment of the present disclosure. [Figure 27] FIG. 27 relates to a fifth example belonging to the embodiment of the present disclosure and is a waveform diagram of a clock signal that can be output from a power supply control device on a front stage side to a power supply control device on a rear stage side. [Figure 28] FIG. 28 is a waveform diagram of four clock signals used for synchronizing switching in four power supply control devices according to a fifth example belonging to an embodiment of the present disclosure. [Figure 29] FIG. 29 relates to a sixth example belonging to an embodiment of the present disclosure and is a waveform diagram of a clock signal that can be output from a power supply control device on a front-stage side to a power supply control device on a rear-stage side.

[0007] [Detailed Description] Hereinafter, examples of the embodiments of the present disclosure will be specifically described with reference to the drawings. In each of the drawings, the same parts are given the same reference numerals, and duplicated descriptions of the same parts are omitted as a rule. In this specification, for the sake of simplicity, a symbol or code referring to information, signal, physical quantity, functional part, circuit, element, or part, etc. may be written, and the name of the information, signal, physical quantity, functional part, circuit, element, or part, etc. corresponding to the symbol or code may be omitted or abbreviated. For example, the synchronous input terminal referred to by "S_IN" described later (see FIG. 1) may be written as synchronous input terminal S_IN or abbreviated as terminal S_IN, but they refer to the same thing.

[0008] First, some terms used in the description of the embodiments of the present disclosure will be explained. Ground refers to a reference conductive part having a reference potential of 0V (zero volts), or refers to the potential of 0V itself. The reference conductive part may be formed using a conductor such as a metal. The potential of 0V may also be called ground potential. In the embodiments of the present disclosure, a voltage shown without a particular reference represents a potential seen from ground.

[0009] A level refers to a level of potential, and for any signal or voltage of interest, a high level has a higher potential than a low level. For any signal of interest, when the signal is at a high level, the inverted signal of the signal is at a low level, and when the signal is at a low level, the inverted signal of the signal is at a high level. For any signal or voltage of interest, a transition from a low level to a high level is called a rising edge, and a transition from a high level to a low level is called a falling edge.

[0010] For any transistor configured as a FET (field effect transistor) including a MOSFET, the on state refers to a state in which conduction exists between the drain and source of the transistor, and the off state refers to a state in which non-conduction (cut-off state) exists between the drain and source of the transistor. The same applies to transistors not classified as FETs. Unless otherwise specified, a MOSFET is understood to be an enhancement-type MOSFET. MOSFET is an abbreviation of "metal-oxide-semiconductor field-effect transistor". Also, unless otherwise specified, in any MOSFET, the back gate may be considered to be short-circuited to the source.

[0011] Hereinafter, for any transistor, the on state and off state may also be simply expressed as on and off, respectively. For any transistor, the switching from the off state to the on state is expressed as turn-on, and the switching from the on state to the off state is expressed as turn-off. For any transistor, the period during which the transistor is in the on state is referred to as the on period, and the period during which the transistor is in the off state is referred to as the off period.

[0012] For any signal taking a high-level or low-level signal level, the period during which the level of the signal is high is referred to as the high-level period, and the period during which the level of the signal is low is referred to as the low-level period. The same applies to any voltage taking a high-level or low-level voltage level.

[0013] Unless otherwise specified, the connection between a plurality of parts forming a circuit, such as any circuit element, wiring, node, etc., may be understood to refer to an electrical connection.

[0014] When any two voltages to be compared are voltage v1 and v2, "v1>v2" represents that voltage v1 is higher than voltage v2, and "v1<v2" represents that voltage v1 is lower than voltage v2. The same applies to other expressions including physical quantities other than voltage.

[0015] 1 shows the overall configuration of a switching power supply device 1 according to an embodiment of the present disclosure. The switching power supply device 1 receives a positive input voltage V IN The input voltage V IN By stepping down the OUT Therefore, the output voltage V OUT is the input voltage V IN The switching power supply 1 has an output voltage V OUT is stabilized at a predetermined target voltage. In other words, in the steady state, the output voltage V OUT The target voltage is substantially the same as the target voltage. Hereinafter, the target voltage is represented by the symbol "V TG The switching power supply device 1 includes n power supply control devices 10, where n is an arbitrary integer of 2 or more.

[0016] FIG. 2 is an external perspective view of one power supply control device 10. The power supply control device 10 is an electronic component including a semiconductor chip having a semiconductor integrated circuit formed on a semiconductor substrate, a housing (package) that houses the semiconductor chip, and a plurality of external terminals exposed from the housing to the outside of the power supply control device 10. The power supply control device 10 is formed by sealing the semiconductor chip in a housing (package) made of resin. Note that the number of external terminals of the power supply control device 10 and the type of housing of the power supply control device 10 shown in FIG. 2 are merely examples, and can be designed arbitrarily. The plurality of external terminals provided in the power supply control device 10 include an input terminal IN, a switch terminal SW, a ground terminal GND, a feedback terminal FB, an error output terminal EOUT, a synchronous input terminal S_IN, and a synchronous output terminal S_OUT. External terminals other than these can also be provided in the power supply control device 10. Note that the synchronous input terminal can be read as a synchronous clock input terminal, and the synchronous output terminal can be read as a synchronous clock output terminal.

[0017] The switching power supply device 1 includes n coils L and output capacitors C in addition to the n power supply control devices 10. OUTand feedback resistors R1 and R2. The n coils L are associated one-to-one with the n power supply control devices 10. That is, one coil L is associated with one power supply control device 10. The first end of the coil L associated with a certain power supply control device 10 is connected to the switch terminal SW of that power supply control device 10. The second ends of all the coils L are connected to the output node ND OUT The current flowing through each coil L is called the coil current IL. In principle, the coil current IL flows from the switch terminal SW to the output node ND OUT (In what follows, we will only consider the principles.)

[0018] Output node ND OUT An output capacitor C OUT That is, the output capacitor C OUT The first end of the output node ND OUT connected to the output capacitor C OUT The second end of the output node ND is connected to ground. OUT The voltage at is the output voltage V OUT The output node ND OUT The load LD is connected to the output voltage V OUT Any load driven based on the output node ND OUT The current supplied to the load LD from the load current I LD It is called.

[0019] The first end of the feedback resistor R1 is connected to the output node ND OUT The second end of the feedback resistor R1 is connected to the first end of the feedback resistor R2, and the second end of the feedback resistor R2 is connected to ground. An output voltage V OUT Feedback voltage V according to FB The feedback voltage V FB is the output voltage V OUT Therefore, the output voltage V OUT The feedback resistors R1 and R2 are proportional to the feedback voltage V FBA feedback terminal FB of one of the n power supply control devices 10 is connected to a connection node between the feedback resistors R1 and R2, and a feedback voltage V FB The feedback terminal FB of the other power supply control device 10 receives a sufficiently high voltage (for example, the input voltage V IN or the power supply voltage VDD described later). OUT It is the feedback voltage V FB In any case, the feedback voltage V FB is the output voltage V OUT The voltage depends on

[0020] The input terminal IN of each power supply control device 10 is connected to an input voltage V IN The ground terminal GND of each power supply control device 10 is connected to the ground. The n error output terminals EOUT of the n power supply control devices 10 are connected to each other. The n power supply control devices 10 can be referred to as the first to n-th power supply control devices 10. Of these, the feedback voltage V FB is input. The synchronous output terminal S_OUT of the i-th power supply control device 10 and the synchronous input terminal S_IN of the (i+1)th power supply control device 10 are connected to each other via a wiring that connects them. i represents any integer. However, since the total number of power supply control devices 10 is n, "i" in the (i+1)th power supply control device 10 represents any natural number equal to or less than (n-1).

[0021] A set of one power supply control device 10 and one coil L is connected to an output capacitor C OUT In cooperation with the output capacitor C, a one-channel DC / DC converter that performs current mode control is formed. Therefore, the switching power supply device 1 forms an n-channel DC / DC converter. OUT is shared by the n-channel DC / DC converter. In the switching power supply unit 1, the feedback voltage V FB A signal corresponding to this (an error signal, described later) is shared by the power supply control devices 10 of all the channels, and multi-phase control can be performed by shifting the phase of switching control among a plurality of channels.

[0022] Hereinafter, when it is necessary to distinguish between the n power control devices 10, the n power control devices 10 will be referred to as power control devices 10[1] to 10[n], as shown in Fig. 3. Also, the coils L associated with the power control devices 10[1] to 10[n] will be referred to as coils L[1] to L[n], respectively. That is, for each integer i that satisfies "1≦i≦n", the switch terminal SW of the power control device 10[i] is connected to the first end of the coil L[i], and the second end of the coil L[i] is connected to the output node ND OUT The coil current IL flowing through the coil L[i] is specifically referred to as the coil current IL[i]. The power supply control devices 10[1] to 10[n] correspond to the first to n-th power supply control devices described above, respectively. Therefore, only the feedback terminal FB of the power supply control device 10[1] is connected to the connection node between the feedback resistors R1 and R2, and the feedback voltage V FB A sufficiently high voltage (for example, the input voltage V IN Or a power supply voltage VDD (described later) is applied.

[0023] In addition, the synchronous input terminal S_IN and the synchronous output terminal S_OUT in the power supply control device 10[i] may be specifically referred to as the synchronous input terminal S_IN[i] and the synchronous output terminal S_OUT[i], respectively. A clock signal may or may not be input from the outside to the synchronous input terminal S_IN[1]. For each integer i that satisfies "1≦i≦(n-1)", the synchronous output terminal S_OUT[i] and the synchronous input terminal S_IN[i+1] are connected to each other through wiring provided between the power supply control devices 10[i] and 10[i+1]. Thus, for example, the terminals S_OUT[1] and S_IN[2] are connected to each other, the terminals S_OUT[2] and S_IN[3] are connected to each other, and the terminals S_OUT[3] and S_IN[4] are connected to each other.

[0024] FIG. 4 shows the internal configuration of one power supply control device 10. The internal configurations of the power supply control devices 10[1] to 10[n] are the same as each other. Therefore, the internal configuration of the power supply control device 10 will be described by focusing on one power supply control device 10. The power supply control device 10 includes an output stage MM and a switching control circuit 20 for controlling the switching of the output stage MM, as well as a mode setting circuit 30, a synchronous output circuit 40, a synchronous input circuit 50, a level detection circuit 60, a pattern determination circuit 70, and a clock management circuit 80. Although not particularly shown, any circuit in the power supply control device 10 may be able to output any signal and information to any other circuit. Note that the synchronous output circuit can be read as a synchronous clock output circuit, and the synchronous input circuit can be read as a synchronous clock input circuit. Hereinafter, for the sake of simplicity of description, the power supply control devices 10, 10[i] are often abbreviated to device 10, 10[i].

[0025] The output stage MM includes transistors MH and ML configured as N-channel MOSFETs. The transistors MH and ML are a pair of switching elements connected in series between the input terminal IN and the ground terminal GND (in other words, ground). The input voltage V IN is switched, and a square-wave switch voltage appears at the switch terminal SW. The transistor MH is provided on the higher potential side than the transistor ML. Specifically, the drain of the transistor MH is connected to the input voltage V IN The transistor MH is connected to the input terminal IN, which is the application terminal of the transistor ML, and is supplied with the input voltage Vin. The source of the transistor MH and the drain of the transistor ML are commonly connected to the switch terminal SW. The source of the transistor ML is connected to the ground terminal GND (and therefore is connected to ground). However, a resistor for current detection may be inserted between the source of the transistor ML and the ground terminal GND.

[0026] The transistor MH functions as an output element (output transistor), and the transistor ML functions as a rectifier element (synchronous rectifier transistor). In the switching control of the output stage MM, the output element (MH) and the rectifier element (ML) are alternately turned on and off. The coil L and the output capacitor C connected to the switch terminal SW OUT constitutes a rectifying and smoothing circuit that rectifies and smoothes the square-wave-shaped switch voltage appearing at the switch terminal SW.

[0027] Gate signals GH and GL are supplied to the gates of the transistors MH and ML as drive signals, respectively, and the transistors MH and ML are turned on and off in response to the gate signals GH and GL. When the gate signal GH is at a high level, the transistor MH is turned on, and when the gate signal GH is at a low level, the transistor MH is turned off. Similarly, when the gate signal GL is at a high level, the transistor ML is turned on, and when the gate signal GL is at a low level, the transistor ML is turned off. Basically, the transistors MH and ML are turned on and off alternately, but both the transistors MH and ML may be maintained in an off state. The transistors MH and ML are never turned on at the same time. At least one of the output element (MH) and the rectifier element (ML) may be provided outside the device 10. The entire output stage MM may be provided outside the device 10.

[0028] During the ON period of the transistor MH, the coil current IL flows through the channel (between the drain and source) of the transistor MH, and during the OFF period of the transistor MH, the coil current IL flows through the channel of the transistor ML or the parasitic diode of the transistor ML.

[0029] The output stage MM is switched and the input voltage V IN is the output voltage V OUT The switching control circuit 20 controls the switching of the output stage MM, and the input voltage V IN The output voltage V OUTIn the switching control, the switching control circuit 20 controls the on / off states of the transistors MH and ML through the level control of the gate signals GH and GL, thereby converting the output node ND OUT to the desired output voltage V OUT When two or more switching control circuits 20 in two or more devices 10 simultaneously perform switching control, the two or more devices 10 cooperate to generate an input voltage V IN is the output voltage V OUT is converted to

[0030] Although not specifically shown, the device 10 has an input voltage V IN An internal power supply circuit is provided that generates various internal power supply voltages based on the input voltage Vin. Each circuit in the device 10 is driven based on the input voltage Vin or the internal power supply voltage. A power supply voltage VDD is generated as one of the internal power supply voltages. The power supply voltage VDD has a predetermined positive DC voltage value. The gate signal GL is a signal based on the ground potential, whereas the gate signal GH is a signal based on the potential of the switch terminal SW. The low-level gate signal GH has the potential of the switch terminal SW, and the high-level gate signal GH is a predetermined voltage higher than the potential of the switch terminal SW. The predetermined voltage here is higher than the gate threshold voltage of the transistor MH. A well-known bootstrap circuit (not shown) can be used to generate a boost power supply for generating the gate signal GH. The transistor MH may be configured as a P-channel MOSFET, in which case the boost power supply is not required.

[0031] As a modification, a diode rectification method may be adopted in the device 10. In this case, instead of the transistor ML, a synchronous rectification diode having an anode connected to the ground terminal GND and a cathode connected to the switch terminal SW is used as the rectification element. In this case, only the output element (MH) is turned on and off in the switching control of the output stage MM. In either case, the output voltage V is changed based on the current (IL) flowing through the coil L by switching the output element (MH) between on and off in the switching control of the output stage MM. OUT is generated.

[0032] Prior to describing the operation of the switching control circuit 20, the mode setting circuit 30 provided in the device 10 will be described.

[0033] The mode setting circuit 30 sets the operation mode of the device 10 to a first mode or a second mode. The operation mode of the device 10 (which may hereinafter be simply referred to as the operation mode) may be understood to be the operation mode of the components of the device 10 other than the mode setting circuit 30 (circuits 20, 40, 50, 60, 70, and 80).

[0034] In the switching power supply device 1, only the operation mode of device 10[1] is set to the first mode, and the operation modes of devices 10[2] to 10[n] are all set to the second mode. The mode setting circuit 30 of device 10[i] sets the operation mode of device 10[i] based on mode setting information provided to device 10[i].

[0035] Here, the voltage of the feedback terminal FB is used as the mode setting information. In the switching power supply device 1, the feedback voltage V FB In the specifications of the switching power supply unit 1, the feedback voltage V FB It is determined that the voltage value is within a specified range. The specified range is from 0V to a certain voltage V FBH (for example, 1.0 V). The mode setting circuit 30 of the device 10[i] determines whether the voltage of the feedback terminal FB of the device 10[i] is a predetermined threshold voltage V THMODE When the voltage of the feedback terminal FB of the device 10[i] is equal to or lower than a predetermined threshold voltage V THMODE If the voltage V is higher than the threshold voltage V , the operation mode of the device 10[i] is set to the second mode. THMODE >V FBH " holds true.

[0036] The feedback terminal FB of device 10[1] is connected to the feedback voltage V FB is supplied, the voltage at the feedback terminal FB of the device 10[1] becomes the threshold voltage V THMODETherefore, the mode setting circuit 30 of the device 10[1] sets the operation mode of the device 10[1] to the first mode. Meanwhile, in the switching power supply device 1, the feedback terminal FB of each of the devices 10[2] to 10[n] has a threshold voltage V THMODE Voltages exceeding the input voltage V IN Or power supply voltage VDD) is applied. As a result, the mode setting circuits 30 of the devices 10[2] to 10[n] set the operation modes of the devices 10[2] to 10[n] to the second mode, respectively.

[0037] A dedicated external terminal (not shown) for setting the operation mode may be provided in each device 10. In this case, the input voltage to the dedicated external terminal functions as mode setting information. The mode setting circuit 30 of the device 10[i] detects whether the input voltage to the dedicated external terminal in the device 10[i] is greater than or equal to the threshold voltage V THMODE the operation mode of the device 10[i] is set to the first mode when the threshold voltage V THMODE If the operating mode of the device 10[i] is higher, the operating mode of the device 10[i] can be set to the second mode (and vice versa). Alternatively, the mode setting information may be stored in a memory (not shown) in the device 10. A higher-level system (not shown) connected to the device 10 so as to be able to communicate bidirectionally can write the mode setting information to the memory in the device 10.

[0038] The mode setting circuit 30 supplies each circuit in the device 10 with a mode setting signal indicating the result of the setting of the operation mode. Specifically, when the mode setting circuit 30 of the device 10[i] sets the operation mode of the device 10[i] to the first mode, it supplies a first mode setting signal indicating that to each circuit in the device 10[i]. When the mode setting circuit 30 of the device 10[i] sets the operation mode of the device 10[i] to the second mode, it supplies a second mode setting signal indicating that to each circuit in the device 10[i]. Hereinafter, the device 10 in the first mode refers to the device 10 in which the first mode is set as the operation mode, and the device 10 in the second mode refers to the device 10 in which the second mode is set as the operation mode.

[0039] The switching control circuit 20 includes an error amplifier 21, a ramp circuit 22, a sense circuit 23, an adder 24, a PWM comparator 25, a switch circuit 26, a clock supply circuit 27, and a controller .

[0040] The error amplifier 21 is a current output type transconductance amplifier. The error amplifier 21 has an inverting input terminal, a non-inverting input terminal, and an output terminal. The inverting input terminal of the error amplifier 21 is connected to a feedback terminal FB. A predetermined reference voltage V REF The reference voltage V REF is a DC voltage having a positive predetermined voltage value, and is generated by a reference voltage generating circuit (not shown) in the device 10. The output terminal of the error amplifier 21 is connected to a wiring WR ERR is connected to.

[0041] The error amplifier 21 operates only in the device 10 in the first mode, and stops in the device 10 in the second mode. In the device 10[i], a first or second mode setting signal from the mode setting circuit 30 is supplied to the switching control circuit 20. The switching control circuit 20 operates the error amplifier 21 when the first mode setting signal is supplied to the switching control circuit 20, and stops the error amplifier 21 (stops the operation of the error amplifier 21) when the second mode setting signal is supplied to the switching control circuit 20. Therefore, among the error amplifiers 21 of the devices 10[1] to 10[n], only the error amplifier 21 of the device 10 in the first mode, i.e., only the error amplifier 21 of the device 10[1], operates. Note that when the device 10[1] is started up, the reference voltage V REF A soft start control may be performed to gradually increase the value of from 0 V to a positive predetermined voltage value, but in the following, the existence of the soft start control will be ignored.

[0042] In the device 10[1], the inverting input terminal of the error amplifier 21 is connected to a feedback voltage V FB In the device 10[1], the error amplifier 21 receives the feedback voltage V FB and the reference voltage V REFThe feedback voltage V FB and the reference voltage V REF The error signal ERR corresponding to the difference between ERR The error signal ERR, as well as the ramp signal RAMP, sense signal ISNS, and slope signal SLP described below, are all voltage signals. In any voltage signal, an increase or decrease in the voltage signal means an increase or decrease in the potential of the voltage signal. The same applies to other similar expressions.

[0043] In the device 10[1], the error amplifier 21 outputs a feedback voltage V FB is the reference voltage V REF When the potential of the error signal ERR is lower than ERR It outputs current to the feedback voltage V FB is the reference voltage V REF When the potential of the error signal ERR is higher than ERR The current is drawn from the wiring WR ERR A phase compensation circuit including a capacitor may be connected between the input and ground.

[0044] The ramp circuit 22 generates a predetermined initial voltage V during the on-period of the transistor MH. INT Generates a ramp signal RAMP with a potential that rises monotonically at a predetermined rate from the initial voltage V INT is, for example, 0 V, but may be different from 0 V. During the off-period of the transistor MH, the potential of the ramp signal RAMP is the initial voltage V INT It is fixed at.

[0045] The sense circuit 23 detects the coil current IL and generates a sense signal ISNS that represents the detection result of the coil current IL. The sense signal ISNS has a voltage value that is proportional to the value of the coil current IL with a positive proportionality coefficient. Therefore, the potential of the sense signal ISNS increases as the coil current IL increases, and the potential of the sense signal ISNS decreases as the coil current IL decreases. The coil current IL detected by the sense circuit 23 of the device 10[i] is the coil current IL[i].

[0046] The sense circuit 23 can generate the sense signal ISNS by detecting the current (hence the coil current IL) flowing through the transistor MH during the on-period of the transistor MH, or by detecting the current (hence the coil current IL) flowing through the transistor ML during the on-period of the transistor ML. Alternatively, a shunt resistor (not shown) can be inserted between the connection node between the transistors MH and ML and the coil L, in which case the sense circuit 23 can generate the sense signal ISNS based on the voltage drop across the shunt resistor. Alternatively, the sense signal ISNS can be generated by detecting a voltage at any point where a voltage corresponding to the coil current IL is generated. Note that the sense signal ISNS represents the detection value of the coil current IL only during the on-period of the transistor MH. During the off-period of the transistor MH, the sense signal ISNS is fixed to the ground potential.

[0047] The adder 24 adds the sense signal ISNS to the ramp signal RAMP to generate a slope signal SLP, which is the sum signal of these signals, i.e., "SLP=RAMP+ISNS."

[0048] The slope signal SLP is input to a non-inverting input terminal of the PWM comparator 25, and the error signal ERR′ is input to an inverting input terminal of the PWM comparator 25.

[0049] Here, the inverting input terminal of the PWM comparator 25 and the wiring WR ERRand the error output terminal EOUT, a switch circuit 26 is provided. The switch circuit 26 has either a first switch state or a second switch state. When a first mode setting signal is supplied to the switching control circuit 20, the switching control circuit 20 sets the switch circuit 26 to the first switch state, and when a second mode setting signal is supplied to the switching control circuit 20, the switching control circuit 20 sets the switch circuit 26 to the second switch state. Therefore, the switch circuit 26 of the device 10[1] is set to the first switch state, and each switch circuit 26 of the devices 10[2] to 10[n] is set to the second switch state.

[0050] 5 shows the state where the switch circuit 26 of the device 10[1] is set to the first switch state, and FIG. 6 shows the state where the switch circuit 26 of the device 10[2] is set to the second switch state. As shown in FIG. 5, the switch circuit 26 in the first switch state is connected to the wiring WR ERR is connected to the inverting input terminal of the PWM comparator 25 and the error output terminal EOUT. Therefore, the error signal ERR' of the device 10[1] is equal to the error signal ERR generated by the error amplifier 21 in the device 10[1]. As shown in FIG. 6, the switch circuit 26 in the second switch state is connected to the wiring WR ERR and the inverting input terminal of PWM comparator 25 are disconnected, and error output terminal EOUT is connected to the inverting input terminal of PWM comparator 25. As described above, all of the error output terminals EOUT in devices 10[1] to 10[n] are connected to each other (see FIG. 3), so that error signal ERR' in devices 10[2] to 10[n] also coincides with error signal ERR generated by error amplifier 21 in device 10[1].

[0051] The PWM comparator 25 compares the error signals ERR' and SLP input thereto, and generates and outputs a signal RST indicating the comparison result. When the potential of the error signal ERR' is higher than the potential of the slope signal SLP, the PWM comparator 25 outputs a low-level signal RST, and when the potential of the slope signal SLP is higher than the potential of the error signal ERR', the PWM comparator 25 outputs a high-level signal RST. When "ERR'=SLP", the signal RST has a high level or a low level.

[0052] The clock supply circuit 27 includes an oscillator circuit 27a. The oscillator circuit 27a generates a clock having a predetermined frequency f PWM An internal clock signal CLK having A The clock supply circuit 27 is connected to a synchronous input terminal S_IN. An internal clock signal CLK is supplied to the synchronous input terminal S_IN of a certain device 10 from another device 10 or from an external clock supply circuit (not shown). A The clock signal input to the synchronous input terminal S_IN may be different from the input clock signal CLK. B An arbitrary clock signal alternates between high and low levels. The clock supply circuit 27 supplies an internal clock signal CLK A or the input clock signal CLK B A clock signal based on the reference clock signal CLK REF Basically, the internal clock signal CLK is supplied to the controller 28. A or the input clock signal CLK B is the reference clock signal CLK REF However, the internal clock signal CLK may be supplied to the controller 28. A or the input clock signal CLK B The reference clock signal CLK is a signal that is logically inverted or a signal that has been waveform-shaped. REF The internal clock signal CLK may be supplied to the controller 28 unless otherwise specified. A or the input clock signal CLK B is the reference clock signal CLK REF to the controller 28.

[0053] Of the oscillator circuits 27a of the devices 10[1] to 10[n], only the oscillator circuit 27a of the device 10 in the first mode, i.e., only the oscillator circuit 27a of the device 10[1], operates. Therefore, in the device 10[1], the internal clock signal CLK A or the input clock signal CLK B is the reference clock signal CLK REFIn each of the devices 10[2] to 10[n], an input clock signal CLK is input to a synchronous input terminal S_IN. B The reference clock signal CLK is supplied only when REF At this time, the input clock signal CLK B is the reference clock signal CLK REF The clock supply circuit 27 outputs the input clock signal CLK to the synchronous input terminal S_IN. B Whether or not a synchronization signal is being supplied can be determined based on the signal at the synchronization input terminal S_IN.

[0054] When the first mode setting signal is supplied from the mode setting circuit 30 to the switching control circuit 20, the clock supply circuit 27 supplies the input clock signal CLK to the synchronous input terminal S_IN. B During the period when the input clock signal CLK is supplied, B Reference clock signal CLK REF to the controller 28, and the input clock signal CLK is input to the synchronous input terminal S_IN. B When the internal clock signal CLK is not supplied, A Reference clock signal CLK REF Therefore, in the device 10[1] operating in the first mode, the clock supply circuit 27 provides the input clock signal CLK to the synchronous input terminal S_IN[1]. B During the period when the input clock signal CLK is supplied, B Reference clock signal CLK REF to the controller 28, and the input clock signal CLK is input to the synchronous input terminal S_IN[1]. B When the internal clock signal CLK is not supplied, A Reference clock signal CLK REF Therefore, the input clock signal CLK is input to the synchronous input terminal S_IN[1]. B During the period when the clock signal CLK is supplied to the synchronous input terminal S_IN[1], B The output stage MM of the device 10[1] is switched in synchronization with the input clock signal CLK BDuring the period when the internal clock signal CLK is not supplied, the internal clock signal CLK generated by the device 10[1] A In synchronization with this, the switching of the output stage MM of the device 10[1] is controlled.

[0055] When the second mode setting signal is supplied from the mode setting circuit 30 to the switching control circuit 20, the clock supply circuit 27 supplies the input clock signal CLK to the synchronization input terminal S_IN. B During the period when the input clock signal CLK is supplied, B Reference clock signal CLK REF to the controller 28, and the input clock signal CLK is input to the synchronous input terminal S_IN. B During the period when the input clock signal CLK is not being supplied, no clock signal is provided to the controller 28. Therefore, in the device 10[i] (where i is an integer between 2 and n) operating in the second mode, the clock supply circuit 27 supplies the input clock signal CLK to the synchronous input terminal S_IN[i]. B During the period when the input clock signal CLK is supplied, B Reference clock signal CLK REF to the controller 28, and the input clock signal CLK is input to the synchronous input terminal S_IN[i]. B During the period when no clock signal is supplied, no clock signal is provided to the controller 28. Therefore, for each integer i that satisfies "2≦i≦n", the input clock signal CLK B During the period in which the clock signal CLK is supplied to the synchronous input terminal S_IN[i], B For each integer i that satisfies “2≦i≦n”, the input clock signal CLK is input to the synchronous input terminal S_IN[i]. B During the period when is not supplied, switching control of the output stage MM of the device 10[i] is stopped. When switching control of the output stage MM in the device 10[i] is stopped, both transistors MH and ML of the output stage MM are fixed to be off.

[0056] A reference clock signal CLK is provided to the controller 28. REFThe controller 28 receives the signal RST from the PWM comparator 25. The controller 28 receives the reference clock signal CLK REF In this case, the controller 28 controls the switching of the output stage MM in synchronization with the signal CLK. REF By supplying gate signals GH and GL to the transistors MH and ML based on the signals CLK and RST, the states of the transistors MH and ML are individually controlled. REF , ERR', SLP, RST, GH and GL. REF The duty is not limited to the duty shown in FIG. 7, but is arbitrary.

[0057] The controller 28 receives a reference clock signal CLK REF 7, a predetermined set edge in the reference clock signal CLK is generated, which causes a rising edge in the gate signal GH to turn on the transistor MH, and a falling edge in the gate signal GL to turn off the transistor ML. The set edge is a rising edge in the example of FIG. 7. For this reason, the controller 28 according to the example of FIG. 7 controls the reference clock signal CLK REF A rising edge in the gate signal GH is generated and a falling edge in the gate signal GL is generated, however, the set edge may be a falling edge.

[0058] After the transistor MH is turned on and the transistor ML is turned off, the slope signal SLP rises monotonically, and the potential of the slope signal SLP transitions from a state lower than the potential of the error signal ERR' to a state higher than the potential of the error signal ERR', causing a rising edge in the signal RST. When the rising edge occurs in the signal RST, the controller 28 generates a falling edge in the gate signal GH to turn off the transistor MH, and generates a rising edge in the gate signal GL to turn on the transistor ML. As the transistor MH turns off, the potential of the ramp signal RAMP becomes a sufficiently low initial voltage V INT, the potential of the slope signal SLP returns to a state lower than the potential of the error signal ERR', and a falling edge is quickly generated in the signal RST.

[0059] "V OUT =V TG "When "V FB =V REF " "V OUT =V TG Starting from the condition that " " is satisfied, the load current I LD Through the increase in OUT <V TG "So, "V FB <V REF ", the potential of the error signal ERR of the device 10[1] rises, and in conjunction with this, the potential of each error signal ERR' of the devices 10[1] to 10[n] also rises. In the device 10 in which switching control is performed, the rise in the potential of the error signal ERR' leads to an increase in the on-period of the transistor MH. The increase in the on-period of the transistor MH increases the coil current IL, and as a result, the output voltage V OUT is the target voltage V TG On the other hand, the “V OUT =V TG Starting from the condition that " " is satisfied, the load current I LD Through the reduction of “V OUT >V TG "So, "V FB >V REF ", the potential of the error signal ERR drops, and in conjunction with this, the potential of each error signal ERR' of the devices 10[1] to 10[n] also drops. In the device 10 where switching control is performed, the drop in the potential of the error signal ERR' reduces the on-period of the transistor MH. The reduction in the on-period of the transistor MH reduces the coil current IL, and as a result, the output voltage V OUT is the target voltage V TG In this way, in the switching power supply device 1 (the device 10 in which switching control is performed), the output voltage V OUT and the target voltage V TG A control is performed to reduce the difference between the

[0060] The synchronous output circuit 40 is connected to the synchronous output terminal S_OUT and outputs a signal from the synchronous output terminal S_OUT. The synchronous output circuit 40 operates based on the power supply voltage VDD. The synchronous output circuit 40 sets the state of the synchronous output terminal S_OUT to one of a plurality of output states including a low level output state, a high level output state, and a Hi-Z state. In this embodiment, the state of the synchronous output terminal S_OUT and the state of the synchronous output circuit 40 are understood to be synonymous with each other. Therefore, the synchronous output terminal S_OUT being in a low level output state and the synchronous output circuit 40 being in a low level output state refer to the same thing. The same applies to the high level output state and the Hi-Z state.

[0061] The synchronous output circuit 40 outputs a low-level signal with sufficiently low output impedance from the synchronous output terminal S_OUT in a low-level output state, and outputs a high-level signal with sufficiently low output impedance from the synchronous output terminal S_OUT in a high-level output state. In a Hi-Z state, the synchronous output circuit 40 increases the output impedance of the synchronous output terminal S_OUT higher than the output impedance in the low-level output state and the output impedance in the high-level output state. In the switching power supply device 1 of FIG. 1, the output impedance of the synchronous output circuit 40 in the device 10[i] refers to the output impedance when the synchronous output circuit 40 of the device 10[i] outputs a signal to the outside of the device 10[i] through the synchronous output terminal S_OUT.

[0062] 8 shows the configuration of a synchronous output circuit 40A, which is an example of the synchronous output circuit 40. The synchronous output circuit 40A includes a transistor 41, which is a P-channel MOSFET, a transistor 42, which is an N-channel MOSFET, and an output setting circuit 43. The source of the transistor 41 is connected to an application terminal of a power supply voltage VDD and is supplied with the power supply voltage VDD. The drains of the transistors 41 and 42 are connected to a synchronous output terminal S_OUT. The source of the transistor 42 is connected to ground. The output setting circuit 43 is connected to the gates of the transistors 41 and 42, and controls the gate potentials of the transistors 41 and 42 to set the states of the transistors 41 and 42 to on or off individually.

[0063] When the output setting circuit 43 sets the transistor 41 to OFF and the transistor 42 to ON, the state of the synchronous output terminal S_OUT is a low level output state, and the synchronous output circuit 40A outputs a low level signal from the synchronous output terminal S_OUT. When the output setting circuit 43 sets the transistor 41 to ON and the transistor 42 to OFF, the state of the synchronous output terminal S_OUT is a high level output state, and the synchronous output circuit 40A outputs a high level signal from the synchronous output terminal S_OUT. The output impedance of the synchronous output circuit 40A in the low level output state is equal to the on resistance of the transistor 42, and the output impedance of the synchronous output circuit 40A in the high level output state is equal to the on resistance of the transistor 41. When the output setting circuit 43 sets both the transistors 41 and 42 to OFF, the state of the synchronous output terminal S_OUT is a Hi-Z state. The output impedance of the synchronous output circuit 40A in the Hi-Z state is much larger than the on resistance of the transistor 41 and the on resistance of the transistor 42. In the following, the on resistances of the transistors 41 and 42 are considered to be sufficiently small and are ignored.

[0064] With respect to the signal or voltage at the synchronous output terminal S_OUT and the synchronous input terminal S_IN, a high level is a predetermined upper threshold voltage V THH The low level refers to a level above a certain lower threshold voltage V THL This refers to the following levels:THH >V THL For example, the upper threshold voltage V THH is set to 0.7 times the power supply voltage VDD, and the lower threshold voltage V THL is set to 0.3 times the power supply voltage VDD.

[0065] In addition, the above-mentioned multiple output states for the synchronous output circuit 40 may include other output states that do not belong to any of the low level output state, the high level output state, and the Hi-Z state (for example, a state in which a signal of an intermediate potential that is not classified as either a high level or a low level is output from the synchronous output terminal S_OUT).

[0066] Referring again to FIG. 4, the synchronous input circuit 50 is connected to the synchronous input terminal S_IN. The synchronous input circuit 50 operates based on the power supply voltage VDD. The synchronous input circuit 50 sets the state of the synchronous input terminal S_IN to one of a plurality of input states including a pull-down state and a pull-up state. In this embodiment, the state of the synchronous input terminal S_IN and the state of the synchronous input circuit 50 are understood to be synonymous with each other. Therefore, the synchronous input terminal S_IN being in a pull-down state and the synchronous input circuit 50 being in a pull-down state refer to the same thing, and the synchronous input terminal S_IN being in a pull-up state and the synchronous input circuit 50 being in a pull-up state refer to the same thing.

[0067] The synchronous input circuit 50 pulls down the synchronous input terminal S_IN to a low level via a pull-down resistor in the pull-down state, and pulls up the synchronous input terminal S_IN to a high level via a pull-up resistor in the pull-up state. The pull-down resistor and the pull-up resistor may be a common resistor, or may be two resistors independent of each other.

[0068] 9 shows a configuration of a synchronous input circuit 50A, which is an example of the synchronous input circuit 50. The synchronous input circuit 50A includes a transistor 51 which is a P-channel MOSFET, a transistor 52 which is an N-channel MOSFET, an input setting circuit 53, and a resistor 54. The source of the transistor 51 is connected to an application terminal of a power supply voltage VDD and is supplied with the power supply voltage VDD. The first terminal of the resistor 54 is connected to the synchronous input terminal S_IN. The second terminal of the resistor 54 is connected to each drain of the transistors 51 and 52. The source of the transistor 52 is connected to ground. The input setting circuit 53 is connected to each gate of the transistors 51 and 52, and sets the states of the transistors 51 and 52 to on or off individually by controlling the gate potentials of the transistors 51 and 52.

[0069] When the input setting circuit 53 sets the transistor 51 to be off and the transistor 52 to be on, the synchronous input terminal S_IN is pulled down to ground (low level) via the resistor 54 and the transistor 52, so that the state of the synchronous input terminal S_IN is a pull-down state. When the input setting circuit 53 sets the transistor 51 to be on and the transistor 52 to be off, the synchronous input terminal S_IN is pulled up to the power supply voltage VDD application terminal (high level) via the resistor 54 and the transistor 51, so that the state of the synchronous input terminal S_IN is a pull-up state. The on-resistance values ​​of the transistors 51 and 52 are sufficiently smaller than the value of the resistor 54, and in the following, the on-resistances of the transistors 51 and 52 are ignored. In the synchronous input circuit 50A, the resistor 54 functions as a pull-down resistor in the pull-down state, and the resistor 54 functions as a pull-up resistor in the pull-up state, but the pull-down resistor and the pull-up resistor may be provided separately.

[0070] The value of resistor 54 is sufficiently larger than the output impedance of the synchronous output terminal S_OUT in a low-level output state and the output impedance of the synchronous output terminal S_OUT in a high-level output state, and is sufficiently smaller than the output impedance of the synchronous output terminal S_OUT in a Hi-Z state.

[0071] It should be noted that the multiple input states for the synchronous input circuit 50 may include other input states that do not belong to either the pull-down state or the pull-up state (eg, a state in which both transistors 51 and 52 are set to off).

[0072] In the following, unless otherwise specified, it is assumed that the synchronous output circuit 40A and the synchronous input circuit 50A are used as the synchronous output circuit 40 and the synchronous input circuit 50.

[0073] Referring again to FIG. 4, the level detection circuit 60 is connected to the synchronous output terminal S_OUT and outputs a level detection signal S according to the level of the synchronous output terminal S_OUT. DET The pattern determination circuit 70 is connected to the synchronous input terminal S_IN and outputs a pattern determination signal S according to the pattern of the signal supplied to the synchronous input terminal S_IN. PTN The signal S DET and S PTN is a binary signal having a value of "1" or "0". The clock management circuit 80 generates the sense signal ISNS, the level detection signal S DET and the pattern determination signal S PTN The circuits 60, 70 and 80 manage and control the state of the synchronous output circuit 40 based on information including the above. The circuits 60, 70 and 80 will be described in detail later.

[0074] In the following, for convenience of explanation, just as the synchronous input terminal S_IN and the synchronous output terminal S_OUT in the device 10[i] may be referred to by the symbols "S_IN[i]" and "S_OUT[i]", respectively, the output stage MM, the switching control circuit 20, the mode setting circuit 30, the synchronous output circuit 40, the synchronous input circuit 50, the level detection circuit 60, the pattern determination circuit 70 and the clock management circuit 80 in the device 10[i] may be referred to by the symbols "MM[i]", "20[i]", "30[i]", "40[i]", "50[i]", "60[i]", "70[i]" and "80[i]", respectively, as shown in FIG. 10. Furthermore, the sense signal ISNS, the level detection signal S DET and the pattern determination signal S PTN In particular, the symbols “ISNS[i]” and “S DET [i]”, “SPTN It may be referred to in [i].

[0075] <<Reference power supply>> Before describing detailed operation examples of the switching power supply device 1, several reference power supplies will be described. In a first reference power supply device, DC / DC converters for multiple channels are built into one electronic component. In the first reference power supply device, multi-phase control can be easily achieved by shifting the phase of the switching control of each channel based on an internal clock signal generated within one electronic component. In the first reference power supply device, the operating state of the DC / DC converter for each channel can be grasped within one electronic component, so that it is relatively easy to increase or decrease the number of channels to be operated according to the load current.

[0076] On the other hand, there is a method (hereinafter referred to as the multi-component method) of forming a multi-phase DC / DC converter with multiple electronic components separated from each other, as in the switching power supply device 1 of Fig. 1. When the multi-component method is adopted, one electronic component is in charge of main control as the main electronic component and issues operation-related commands to the other electronic components. For example, in a second reference power supply device constituting a four-phase DC / DC converter, the main electronic component individually transmits a clock signal to the remaining three electronic components (secondary electronic components) to realize multi-phase control. However, in this case, output terminals and output circuits for the clock signal are required for the number of secondary electronic components, which increases the size of each electronic component.

[0077] Taking this into consideration, in the third reference power supply, multiple electronic components, each responsible for switching control for one channel, are connected in tandem. That is, in the third reference power supply, a synchronizing clock signal is sent from the main electronic component responsible for the first phase to the secondary electronic component responsible for the second phase, a synchronizing clock signal is sent from the secondary electronic component responsible for the second phase to the secondary electronic component responsible for the third phase, and a synchronizing clock signal is sent from the secondary electronic component responsible for the third phase to the secondary electronic component responsible for the fourth phase. A four-phase DC / DC converter can be configured by sending synchronizing clock signals such that the phases of the clock signals used for switching control are shifted between the four electronic components.

[0078] However, in the third reference power supply, the main electronic component cannot recognize how many auxiliary electronic components are connected from the main electronic component, and cannot grasp how many of them are in operation. In the third reference power supply, when a plurality of power supply control devices (a plurality of electronic components) and a plurality of coils are connected in the same manner as the switching power supply device 1 of FIG. 1, the same current flows in the coil corresponding to the main power supply control device (main electronic component) and the coil corresponding to the sub power supply control device (auxiliary electronic component) in principle. Therefore, if the total number of electronic components in operation is known, it is also possible to grasp the load current (= the total number of electronic components in operation × the current flowing through one coil). However, in the third reference power supply formed by simply connecting a plurality of electronic components in series, the main electronic component cannot grasp the load current (the same applies to the auxiliary electronic components). As a result, it is difficult to increase or decrease the number of channels to be operated (the total number of electronic components in operation) according to the load current.

[0079] If it were possible to transmit information from a device 10 placed in a later stage to a device 10 placed in a previous stage without adding a dedicated terminal, etc., it would be possible to control the operation / non-operation of each channel according to the load current, which would be beneficial.

[0080] In the following, specific configuration examples, operation examples, application techniques, modified techniques, etc., related to the switching power supply device 1 will be described in several examples. The matters described above in this embodiment are applied to the following examples (excluding matters related to the first to third reference power supplies) unless otherwise specified and unless there is a contradiction. In the cases where there are matters in the examples that contradict the matters described above, the descriptions in the respective examples may take precedence. Furthermore, unless there is a contradiction, matters described in any of the following examples can also be applied to any of the other examples (i.e., any two or more of the multiple examples can also be combined).

[0081] <<First Example>> A first embodiment will be described. In the first embodiment, it is assumed that the synchronous input terminal S_IN of the device 10[1] is open. That is, in the first embodiment, the input clock signal CLK is input to the synchronous input terminal S_IN of the device 10[1]. B Therefore, in the first embodiment, the controller 28 of the device 10[1] does not supply the internal clock signal CLK generated within the device 10[1]. A Reference clock signal CLK REF It is used to control the switching of the output stage MM[1].

[0082] In the switching power supply device 1, the signal between terminals S_OUT and S_IN can be used not only to transmit a synchronization clock signal from device 10[i] to device 10[i+1], but also to transmit information from device 10[i+1] to device 10[i].

[0083] A method of transmitting information from device 10[i+1] to device 10[i] will be described with reference to Figure 11. A clock signal for synchronization is output from a synchronous output circuit 40[i]. The clock signal output by the synchronous output circuit 40[i] is referred to as a clock signal CLK[i]. The reference clock signal CLK for devices 10[i] and 10[i+1] REF Specifically, the symbols “CLK REF [i]”, “CLK REF[i+1]". Note that hereinafter, a period during which switching control is executed may be referred to as a switching execution period, and a period during which switching control is not executed may be referred to as a switching stop period. A period during which the clock signal CLK[i] is output by the synchronous output circuit 40[i] may be referred to as an output period of the clock signal CLK[i], and a period during which the clock signal CLK[i] is not output by the synchronous output circuit 40[i] may be referred to as a non-output period of the clock signal CLK[i] or a stop period of the clock signal CLK[i].

[0084] In any device 10[i], during a period when the switching control circuit 20[i] is performing switching control and the clock signal CLK[i] is not being output from the synchronous output circuit 40[i], the clock management circuit 80[i] monitors whether or not a predetermined clock output condition is met. Then, when the clock output condition is met, the clock management circuit 80[i] monitors whether or not a reference clock signal CLK REF The synchronous output circuit 40[i] is controlled to output a clock signal CLK[i] based on [i] from the synchronous output terminal S_OUT[i], and as a result, the clock signal CLK[i] is output. If the clock output condition is not satisfied, the synchronous output circuit 40[i] does not output the clock signal CLK[i]. When the clock signal CLK[i] is not output, the state of the synchronous output terminal S_OUT[i] may be fixed to a Hi-Z state by the synchronous output circuit 40[i].

[0085] The clock signal CLK[i] is an output clock signal for the device 10[i] and an input clock signal for the device 10[i+1]. The device 10[i+1] receives the clock signal CLK[i] as an input clock signal at the synchronous input terminal S_IN[i+1] and converts the clock signal CLK[i] into a reference clock signal CLK REF [i+1] is used for switching control.

[0086] The synchronous output circuit 40[i] receives a clock signal CLK REF CLK[i] and CLK[i] have the same frequency as each other, and the clock signal CLKREF The reference clock signal CLK[i] and CLK[i] have different phases from each other. REF [i] to generate a clock signal CLK[i].

[0087] FIG. 12 shows a conceptual diagram of the waveform of the clock signal CLK[i]. As time progresses, times T1, T2, T3, and T4 arrive in this order. The unit time t U1 has a length of one period of the clock signal CLK[i], and in the first embodiment, the internal clock signal CLK A The length of one period of (i.e., frequency f PWM In the first embodiment, it is considered that each period of a given clock signal starts from the rising edge of the clock signal.

[0088] At time T1, the synchronous output circuit 40[i] switches the state of the synchronous output terminal S_OUT[i] from a low level output state to a high level output state. After that, at time T2, the synchronous output circuit 40[i] switches the state of the synchronous output terminal S_OUT[i] from a high level output state to a Hi-Z state. Further after that, at time T3, the synchronous output circuit 40[i] switches the state of the synchronous output terminal S_OUT[i] from a Hi-Z state to a low level output state. Further after that, at time T4, the synchronous output circuit 40[i] switches the state of the synchronous output terminal S_OUT[i] from a low level output state to a high level output state. Thereafter, the same operation is repeated. When time T1 is the start time of the jth period of the clock signal CLK[i], time T4 corresponds to the start time of the (j+1)th period of the clock signal CLK[i]. j represents any natural number.

[0089] Thus, in the output period of the clock signal CLK[i], the synchronous output circuit 40[i] includes in each cycle of the clock signal CLK[i] a period P11 (between times T1 and T2 in FIG. 12) in which the state of the synchronous output terminal S_OUT[i] is set to a high-level output state, a period P13 (between times T3 and T4 in FIG. 12) in which the state of the synchronous output terminal S_OUT[i] is set to a low-level output state, and a period P12 (between times T2 and T3 in FIG. 12) in which the state of the synchronous output terminal S_OUT[i] is set to a Hi-Z state. For example, the lengths of the periods P11, P12, and P13 are each unit time t U1 25%, 25%, and 50% of the unit time t U1 The ratio of each of the periods P11, P12, and P13 in this example may be arbitrary. Note that the output pattern of the clock signal CLK[i] by the synchronous output circuit 40[i] of the first example example is referred to as a pattern PTN1a.

[0090] The on-resistance values ​​of the transistors 41 and 42 are negligibly small compared to the value of the resistor 54 (see FIGS. 8 and 9). Therefore, when the state of the synchronous output terminal S_OUT[i] is a low-level output state, the clock signal CLK[i] has a low level (substantially has the ground potential), and when the state of the synchronous output terminal S_OUT[i] is a high-level output state, the clock signal CLK[i] has a high level (substantially has the potential of the power supply voltage VDD). During the period when the state of the synchronous output terminal S_OUT[i] is the Hi-Z state (i.e., the period between times T2 and T3), the level of the clock signal CLK[i] depends on the state of the synchronous input circuit 50[i+1].

[0091] 13 shows the waveform of the clock signal CLK[i] when the synchronous input circuit 50[i+1] is in a pull-down state. When the synchronous input circuit 50[i+1] is in a pull-down state, after time T2, the potential of the clock signal CLK[i] drops from the potential of the power supply voltage VDD toward the ground potential, and at time T3 PRE The potential drops to a low level before time T3. PRE is a time that is later than time T2 and a predetermined small time before time T3.

[0092] 14 shows the waveform of the clock signal CLK[i] when the synchronous input circuit 50[i+1] is in the pull-up state. When the synchronous input circuit 50[i+1] is in the pull-up state, after time T2, at time T3 PRE Until time T3, the potential of the clock signal CLK[i] is maintained at the potential of the power supply voltage VDD (and therefore maintained at a high level), and at time T3, the potential of the clock signal CLK[i] suddenly drops from the potential of the power supply voltage VDD to ground potential.

[0093] The level detection circuit 60[i] detects when the clock signal CLK[i] is output by the synchronous output circuit 40[i] at time T3 PRE The level detection circuit 60[i] detects whether the voltage to be detected is a high level or a low level when the voltage to be detected is higher than or equal to the upper threshold voltage V THH If the detected voltage is equal to or higher than the lower threshold voltage V THL If it is equal to or lower than this, it is determined that the voltage to be detected is at a low level.

[0094] When the level detection circuit 60[i] determines that the detection target voltage is at a low level, it outputs a level detection signal S DET [i] is output (see FIG. 13). The level detection signal S DET When [i] is output, “S DET When the level detection circuit 60[i] determines that the detection target voltage is at a high level, it outputs a level detection signal S DET [i] is output (see FIG. 14). The “0” level detection signal S DET When [i] is output, “S DET [i]=0" is maintained. Note that, during the non-output period of the clock signal CLK[i], the level detection signal S DET [i] has no significant value.

[0095] In this way, by switching the synchronous input circuit 50[i+1] between the pull-down state and the pull-up state, information can be transmitted from the rear-stage device 10[i+1] to the front-stage device 10[i]. Furthermore, regardless of the state of the synchronous input circuit 50[i+1], a rising edge always occurs in the clock signal CLK[i] at time T1. Therefore, the rising edge of the clock signal CLK[i] can be used to synchronize switching between the devices 10[i] and 10[i+1]. In order to ensure this synchronization, in the first embodiment in which the pattern PTN1a of FIG. 12 is adopted, the set edge is a rising edge. That is, when the clock signal CLK[i] of the pattern PTN1a is supplied to the device 10[i+1], the controller 28 of the device 10[i+1] turns on the transistor MH and turns off the transistor ML at the rising edge of the clock signal CLK[i].

[0096] In any device 10[i], while the switching control circuit 20[i] is executing switching control and the synchronous output circuit 40[i] is outputting the clock signal CLK[i], the clock management circuit 80[i] monitors whether a predetermined clock stop condition is met. When the clock stop condition is met, the clock management circuit 80[i] controls the synchronous output circuit 40[i] to stop outputting the clock signal CLK[i] from the synchronous output terminal S_OUT[i], and as a result, the output of the clock signal CLK[i] is stopped.

[0097] In the first embodiment, the following first rule is adopted in each device 10. A device 10[i] that follows the first rule sets the state of the synchronous input terminal S_IN[i] to a pull-down state during the output period of the clock signal CLK[i], and sets the state of the synchronous input terminal S_IN[i] to a pull-up state during the non-output period of the clock signal CLK[i].

[0098] FIG. 15 shows the state of the switching power supply device 1 when clock signals CLK[1] to CLK[3] are being output when "n=4." In response to the output of the clock signals CLK[1] to CLK[3], the synchronous input terminals S_IN[1] to S_IN[3] are set to a pull-down state. In the state of FIG. 15, the clock signal CLK[4] is not output, and therefore the synchronous input terminal S_IN[4] is set to a pull-up state. Note that if the clock signal CLK[4] is output from the synchronous output terminal S_OUT[4], the synchronous input terminal S_IN[4] is set to a pull-down state (however, there is no device 10 that receives the clock signal CLK[4]). In the state of FIG. 15, switching control is performed in each of the devices 10[1] to 10[4], and significant coil currents IL[1] to IL[4] are generated.

[0099] FIG. 16 shows the state of the switching power supply device 1 when clock signals CLK[1] and CLK[2] are output and clock signal CLK[3] is not output, in the case of “n=4.” In response to the clock signals CLK[1] and CLK[2] being output, the synchronous input terminals S_IN[1] and S_IN[2] are set to a pull-down state, while in response to the clock signal CLK[3] not being output, the synchronous input terminal S_IN[3] is set to a pull-up state. Also, in the example of FIG. 16, when the clock signal CLK[3] is not supplied, In the device 10[4], the synchronous input terminal S_IN[4] is set to the initial state, that is, the pull-up state. In addition, not limited to the examples of Figures 15 and 16, the state of the synchronous input terminal S_IN[i] may be arbitrary only in the device 10[1] operating in the first mode, regardless of the output of the clock signal CLK[1]. In the state of Figure 16, significant coil currents IL[1] to IL[3] are generated by switching control in each of the devices 10[1] to 10[3], but the switching control in the device 10[4] is stopped, so the coil current IL[4] is zero.

[0100] 17 shows an operational flowchart of the device 10[1] operating in the first mode. The flow of operation of the device 10[1] will be described with reference to FIG.

[0101] First, in step S10, the input voltage V IN The supply of power starts, and the device 10[1] starts up. In the following step S11, a predetermined initialization process is executed in the device 10[1], and the state of the device 10[1] becomes the initial state. In the initial state, the synchronization input terminal S_IN[1] is in a pull-up state, and switching control is stopped. Also, in the initialization process, the mode setting circuit 30 sets the operation mode of the device 10[1] to the first mode. After step S11, the process proceeds to step S12.

[0102] In step S12, a clock signal CLK is applied to the synchronous input terminal S_IN[1]. B It is determined whether the clock signal CLK is input to the synchronous input terminal S_IN[1]. B If so, the process proceeds from step S12 to step S18, where an external clock corresponding process (details of which will be described in other embodiments) is executed. B If no clock signal CLK is input to the synchronous input terminal S_IN[1], the process proceeds from step S12 to step S13. B Since it is assumed that no input is made, the process proceeds to step S13. As a modification, the process may always proceed to step S13 after step S11.

[0103] In the device 10[1] operating in the first mode, the internal clock signal CLK A is the reference clock signal CLK REF For ease of explanation, the reference clock signal CLK provided to the controller 28 of the device 10[1] is REF Hereinafter, this may be referred to as clock signal CLK[0].

[0104] In step S13, the device 10[1] starts switching control of the output stage MM[1] in synchronization with the clock signal CLK[0]. The controller 28 of the device 10[1] turns on the transistor MH and turns off the transistor ML at the rising edge of the clock signal CLK[0]. The coil current IL[1] is generated by the switching control of the device 10[1]. The coil current IL[1] is periodically detected by the sense circuit 23 of the device 10[1], and a sense signal ISNS[1] indicating the detected value of the coil current IL[1] is generated. After step S13, proceed to step S14.

[0105] In step S14, the clock management circuit 80[1] adjusts the detected coil current IL[1] to a predetermined upper threshold current I THH The clock output condition is determined to be satisfied by comparing with the clock output condition in step S14. THH In step S14, "IL[1]>I THH If "IL[1]>I" is true, the transition to step S15 occurs. THH If "IL[1]>I" is not satisfied, the process returns to step S14, and the clock output condition is judged whether or not the clock output condition is satisfied (i.e., "IL[1]>I THH The process of determining whether the "success or failure" has been completed is repeated.

[0106] In step S15, the clock management circuit 80[1] controls the synchronous output circuit 40[1] to start outputting the clock signal CLK[1]. Also in step S15, the clock management circuit 80[1] controls the synchronous input circuit 50[1] to change the state of the synchronous input terminal S_IN[1] from the pull-up state to the pull-down state. After step S15, the process proceeds to step S16.

[0107] In step S16, the clock management circuit 80[1] judges whether the clock stop condition is satisfied. If the clock stop condition is not satisfied, the judgment process of step S16 is repeated. If the clock stop condition is satisfied, a transition from step S16 to step S17 occurs. The clock stop condition will be described later.

[0108] In step S17, the clock management circuit 80[1] controls the synchronous output circuit 40[1] to stop outputting the clock signal CLK[1]. Also in step S17, the clock management circuit 80[1] controls the synchronous input circuit 50[1] to change the state of the synchronous input terminal S_IN[1] from the pull-down state to the pull-up state. After step S17, the process returns to step S14.

[0109] The clock stop condition in step S16 is that the detected coil current IL[1] is “IL[1] THL " and the level detection signal S DET This is true if and only if the value of [1] is “0”. THL The success or failure of " can be determined based on the sense signal ISNS[1]. THL is the upper threshold current I THH represents a predetermined lower threshold current that is lower than "S DET [1]=0" indicates that the synchronous input terminal S_IN[2] is in a pull-up state (see FIG. 14), that is, the clock signal CLK[2] is not being output (hence the switching control of the device 10[3] is stopped). In other words, assuming that the drive (switching control) of the device 10[3] is stopped, the coil current IL[1] is equal to or lower than the lower threshold current I THL If the voltage drops below this level, it is determined that driving of the device 10[2] is also unnecessary, and the output of the clock CLK[1] is stopped (S17).

[0110] ​​Fig. 18 shows an operational flowchart of device 10[i] operating in the second mode. The variable i in each step (S20 to S28) shown in Fig. 18 represents an arbitrary integer equal to or greater than 2. The flow of operation of device 10[i] operating in the second mode will be described with reference to Fig. 18.

[0111] First, in step S20, the input voltage V IN The supply of power starts, and the device 10[i] starts up. In the following step S21, a predetermined initialization process is executed in the device 10[i], and the state of the device 10[i] becomes the initial state. In the initial state, the synchronization input terminal S_IN[i] is in a pull-up state, and switching control is stopped. In addition, in the initialization process, the mode setting circuit 30 sets the operation mode of the device 10[i] to the second mode (as described above, here i is any integer equal to or greater than 2). After step S21, the process proceeds to step S22.

[0112] In step S22, a clock signal CLK is applied to the synchronous input terminal S_IN[i]. B It is determined whether a clock signal CLK that can be input to the synchronous input terminal S_IN[i] of the device 10[i] is B is the clock signal CLK[i-1] from the device 10[i-1]. B If no clock signal CLK is input to the synchronous input terminal S_IN[i], the determination process of step S22 is repeated. B If (CLK[i-1]) is being input, the process proceeds from step S22 to step S23.

[0113] In the device 10[i] operating in the second mode, the input clock signal CLK to the synchronous input terminal S_IN[i] B (CLK[i-1]) is the reference clock signal CLK REF to the controller 28.

[0114] In step S23, the device 10[i] receives the reference clock signal CLKREF The controller 28 of the device 10[i] starts switching control of the output stage MM[i] in synchronization with the clock signal CLK[i-1], which is a rising edge of the clock signal CLK[i-1]. The controller 28 of the device 10[i] turns on the transistor MH and turns off the transistor ML at the rising edge of the clock signal CLK[i-1]. The coil current IL[i] is generated by the switching control of the device 10[i]. The coil current IL[i] is periodically detected by the sense circuit 23 of the device 10[i], and a sense signal ISNS[i] indicating the detected value of the coil current IL[i] is generated. After step S23, the process proceeds to step S24.

[0115] In step S24, the clock management circuit 80[i] adjusts the detected coil current IL[i] to a predetermined upper threshold current I THH The clock output condition is determined to be satisfied by comparing with the clock output condition in step S24. THH In step S24, "IL[i]>I THH If the condition “IL[i]>I” is satisfied, the process proceeds to step S25. THH If "IL[i]>I" is not satisfied, the process returns to step S24, and the clock output condition is judged whether or not the clock output condition is satisfied (i.e., "IL[i]>I THH The process of determining whether the "success or failure" has been completed is repeated.

[0116] In step S25, the clock management circuit 80[i] controls the synchronous output circuit 40[i] to start outputting the clock signal CLK[i]. Also in step S25, the clock management circuit 80[i] controls the synchronous input circuit 50[i] to change the state of the synchronous input terminal S_IN[i] from the pull-up state to the pull-down state. After step S25, the process proceeds to step S26.

[0117] In step S26, the clock management circuit 80[i] determines whether the clock stop condition is satisfied. If the clock stop condition is not satisfied, the determination process of step S26 is repeated. If the clock stop condition is satisfied, a transition from step S26 to step S27 occurs. The clock stop condition will be described later.

[0118] In step S27, the clock management circuit 80[i] controls the synchronous output circuit 40[i] to stop the output of the clock signal CLK[i]. Also in step S27, the clock management circuit 80[i] controls the synchronous input circuit 50[i] to change the state of the synchronous input terminal S_IN[i] from the pull-down state to the pull-up state. After step S27, the process returns to step S24.

[0119] The clock stop condition in step S26 is that the detected coil current IL[i] is “IL[i] THL " and the level detection signal S DET This is true if and only if the value of [i] is “0”. THL The success or failure of “S DET [i]=0” is based on the assumption that device 10[i+1] exists. This indicates that the synchronous input terminal S_IN[i+1] is in a pull-up state (see FIG. 14). DET [i]=0" indicates that the clock signal CLK[i+1] is not being output (therefore, the switching control of the device 10[i+2] is stopped). In other words, assuming that the drive (switching control) of the device 10[i+2] is stopped, the coil current IL[i] is equal to or lower than the lower threshold current I THL If the clock CLK[i] falls below 1, it is determined that the operation of device 10[i+1] is also unnecessary, and the output of clock CLK[i] is stopped (S27). However, if i here is "i=n-1", device 10[i+2] does not exist, and if i=n, ​​devices 10[i+1] and 10[i+2] do not exist.

[0120] ​​Although not shown in the figure, after the process proceeds from step S22 to step S23, when the supply of the clock signal CLK[i-1] to the synchronous input signal S_IN[i] is interrupted, the reference clock signal CLK REF Since no rising edge occurs in the output stage MM[i], the switching control of the device 10[i] stops. After proceeding from step S22 to step S23, the switching control circuit 20[i] monitors the signal change of the synchronous input signal S_IN[i], and if there is no change in the signal of the synchronous input signal S_IN[i] for a certain period of time or more, it determines that the supply of the clock signal CLK[i-1] has been interrupted and fixes the transistors MH and ML of the output stage MM[i] to the off state, and then causes a transition to step S22.

[0121] In the switching power supply device 1, switching control is performed on the output stages MM[1] to MM[m] among the output stages MM[1] to MM[n], and the input voltage V IN The output voltage V OUT The application end (output node ND OUT ) is supplied with current. m is a natural number less than or equal to n.

[0122] A specific operation example of the switching power supply device 1 will be given assuming that “n=4”. IN When the supply of the load current I starts, switching control is first performed only in the device 10[1], and at this time, of the coil currents IL[1] to IL[4], only the coil current IL[1] is generated. LD When the load current I is relatively large, the clock output condition is satisfied in the device 10[1], so that the output of the clock signal CLK[1] is started, and the coil current IL[2] is generated in addition to the coil current IL[1]. LDIn some cases, the clock output condition is also satisfied in the devices 10[2] and 10[3] in sequence. As a result, the devices 10[1] to 10[4] all reach a state where they perform switching control (hereinafter referred to as a 4-channel driving state; the state shown in FIG. 15). In the 4-channel driving state assumed here, the clock output condition is not satisfied in the device 10[4], and as a result, the synchronization input terminal S_IN[4] is in a pull-up state.

[0123] Since current mode control is performed using a common error signal between the devices 10[1] to 10[4], when switching control is performed in each of the devices 10[1] to 10[4], the magnitudes of the coil currents IL[1] to IL[4] are approximately the same. Thus, the load current I LD When I is relatively large, the current can be distributed by operating the subsequent channels as well. Now, starting from the 4-channel driving state, the load current I LD For the sake of clarity, let us consider the case where the lower threshold current I THL is 1.0A, and the load current I LD Suppose that decreases from 5.0 A to 3.9 A. Due to this decrease, the coil currents IL[1] to IL[4] all decrease to 0.975 A (ignoring errors here).

[0124] At this time, the coil current IL in each of the devices 10[1] to 10[4] is equal to or lower than the lower threshold current I THL Although it is detected that the level of the level determination signal S is below the threshold, the clock stop condition is satisfied only in the device 10[3] among the devices 10[1] to 10[3]. DET [1]~S DET [3] Signal S DET This is because only [3] has a “0” (see S16 in FIG. 17 and S26 in FIG. 18). Therefore, starting from the 4-channel driving state, the load current I LDWhen the load current I drops from 5.0A to 3.9A, the output of the clock signal CLK[3] from the device 10[3] is stopped, and the 4-channel drive state corresponding to FIG. 15 changes to the state corresponding to FIG. 16 (hereinafter referred to as the 3-channel drive state). When the output of the clock signal CLK[3] is stopped, the state of the synchronization input terminal S_IN[3] is changed from the pull-down state to the pull-up state. In the 3-channel drive state, only the devices 10[1] to 10[3] perform switching control. In the 3-channel drive state, the load current I LD If the load current I is maintained at 3.9A, the coil currents IL[1] to IL[3] are stabilized at 1.3A each. Then, the load current I LD has dropped sufficiently, switching control of device 10[3] can be stopped by stopping the output of clock signal CLK[2], and then switching control of device 10[2] can be stopped by stopping the output of clock signal CLK[1].

[0125] In this way, in the switching power supply device 1, information is transmitted from the device 10 arranged in the subsequent stage to the device 10 arranged in the preceding stage by switching the synchronization input terminal S_IN between pull-down and pull-up without adding a dedicated terminal or the like. As a result, the load current I LD It is possible to control the operation / non-operation of each channel depending on the situation.

[0126] In the above-mentioned third reference power supply device, when the load current is reduced from 5.0 A to 3.9 A while the four channels are operating, each electronic component can only recognize that the current of the coil connected to it has been reduced to 0.975 A. If the main electronic component (corresponding to device 10[1]) located in the first stage stops supplying a clock signal to the subsequent stage electronic component (corresponding to device 10[2]), the operation of all electronic components connected to the main electronic component will stop. As a result, it becomes necessary to cover the load current of 3.9 A only with the channel of the main electronic component, which causes inconvenience.

[0127] Figure 19 shows the waveforms of the clock signals CLK[0] to CLK[3] in the above-mentioned 4-channel driving state. For convenience of illustration, it is assumed in Figure 19 that the clock signals CLK[0] to CLK[3] are all square wave signals with a duty of 50%, and the existence of a Hi-Z state is ignored.

[0128] In the 4-channel driving state, the clock signals CLK[0] to CLK[3] are the reference clock signals CLK in the devices 10[1] to 10[4], respectively. REF Therefore, the controller 28 of the device 10[1] turns on the transistor MH and turns off the transistor ML of the output stage MM[1] at the rising edge of the clock signal CLK[0]. The controller 28 of the device 10[2] turns on the transistor MH and turns off the transistor ML of the output stage MM[2] at the rising edge of the clock signal CLK[1]. The controller 28 of the device 10[3] turns on the transistor MH and turns off the transistor ML of the output stage MM[3] at the rising edge of the clock signal CLK[2]. The controller 28 of the device 10[4] turns on the transistor MH and turns off the transistor ML of the output stage MM[4] at the rising edge of the clock signal CLK[3].

[0129] The synchronous output circuit 40[1] generates the clock signal CLK[1] by delaying the phase of the clock signal CLK[0] by a predetermined shift amount SHT[1]. The shift amount SHT[1] is 180°. That is, the synchronous output circuit 40[1] generates the clock signal CLK[1] by delaying the phase of the clock signal CLK[0] by 180° from the rising edge of the clock signal CLK[0] (i.e., “t U1 The clock signal CLK[1] is generated so that a rising edge of the clock signal CLK[1] occurs at a timing delayed by 1 / 2″.

[0130] The synchronous output circuit 40[2] generates the clock signal CLK[2] by delaying the phase of the clock signal CLK[1] by a predetermined shift amount SHT[2]. The shift amount SHT[2] is 90°. That is, the synchronous output circuit 40[2] generates the clock signal CLK[2] by delaying the phase of the clock signal CLK[1] by 90° from the rising edge of the clock signal CLK[1] (i.e., “t U1 The clock signal CLK[2] is generated so that the rising edge of the clock signal CLK[2] occurs at a timing delayed by 1 / 4”.

[0131] The synchronous output circuit 40[3] generates the clock signal CLK[3] by delaying the phase of the clock signal CLK[2] by a predetermined shift amount SHT[3]. The shift amount SHT[3] is 180°. That is, the synchronous output circuit 40[3] generates the clock signal CLK[3] at a timing when the phase is delayed by 180° from the rising edge of the clock signal CLK[2] (i.e., “t U1 The clock signal CLK[3] is generated so that the rising edge of the clock signal CLK[3] occurs at a timing delayed by 1 / 2”.

[0132] As shown in FIG. 19, by shifting the phases of the clock signals CLK[0] to CLK[3] from one another, multi-phase control for four channels can be performed.

[0133] Any synchronous output circuit 40[i] determines the shift amount SHT[i] based on the shift amount setting information given to the device 10[i]. The external terminal of the device 10[i] may include a dedicated external terminal for specifying the shift amount setting information, in which case the synchronous output circuit 40[i] may obtain the shift amount setting information based on the voltage of the dedicated external terminal (voltage given to the dedicated external terminal from outside the device 10[i]). Alternatively, the shift amount setting information may be stored in a memory (not shown) in the device 10[i]. A higher-level system (not shown) connected to the device 10 so as to be able to communicate bidirectionally can write the shift amount setting information to the memory in the device 10.

[0134] Incidentally, the synchronous output terminal S_OUT of the final stage device 10 (10[n]) is not connected to the synchronous input terminal S_IN of the other devices 10 and is open. For this reason, in the final stage device 10, during the period when the synchronous output terminal S_OUT is in the Hi-Z state (period P12 in FIG. 12), the voltage of the synchronous output terminal S_OUT may become unstable, and the level detection signal S DET may have a value of "1" (see FIG. 13). This may lead to the final stage device 10 mistakingly determining that a virtual device is outputting a clock signal, even though there is no further stage device 10 (virtual device) from the perspective of the final stage device 10.

[0135] For this reason, in the first embodiment, it is preferable to use the synchronous output circuit 40B of FIG. 20 as the synchronous output circuit 40 of each device 10. The synchronous output circuit 40B has a configuration in which a pull-up resistor 44 is added to the synchronous output circuit 40A of FIG. 8, and is the same as the synchronous output circuit 40A except for this addition. A first terminal of the pull-up resistor 44 is connected to the application terminal of the power supply voltage VDD and is supplied with the power supply voltage VDD. A second terminal of the pull-up resistor 44 is connected to the synchronous output terminal S_OUT. Here, the value of the pull-up resistor 44 is sufficiently larger than the value of the resistor 54 of FIG. 9. For example, when the resistor 54 has a value of 50 kΩ (kilo ohms), the value of the pull-up resistor 44 is set to 5 MΩ (mega ohms).

[0136] As a result, during the period in which the synchronous output terminal S_OUT[i] is in the Hi-Z state, if the synchronous input terminal S_IN[i+1] is in the pull-down state, the potential of the synchronous output terminal S_OUT[i] becomes approximately 1 / 100 of the power supply voltage VDD (the lower threshold voltage V THL Since the voltage to be detected (at time T3 PRE During the period in which the synchronous output terminal S_OUT[i] is in the Hi-Z state, if the synchronous input terminal S_IN[i+1] is in the pull-up state, the potential of the synchronous output terminal S_OUT[i] will match the power supply voltage VDD, so the level determination circuit 60[i] can reliably determine that the detection target voltage (the voltage of the synchronous output terminal S_OUT[i] at time T3 PREThe voltage at the synchronous output terminal S_OUT[i] in

[0137] For the final stage device 10[n], during the period in which the synchronous output terminal S_OUT[n] is in the Hi-Z state, the level of the synchronous output terminal S_OUT[i] is maintained at the power supply voltage VDD due to the presence of the pull-up resistor 44. As a result, the level determination circuit 60[n] detects the detection target voltage (at time T3 PRE The voltage of the synchronous output terminal S_OUT[n] at DET Therefore, the above-mentioned erroneous recognition does not occur.

[0138] The value of the pull-up resistor 44 is much larger than the on-resistance value of the transistor 41 and the on-resistance value of the transistor 42. Therefore, in the synchronous output circuit 40B, similarly to the synchronous output circuit 40A, the output impedance of the synchronous output terminal S_OUT in the Hi-Z state is sufficiently higher than the output impedance of the low-level output state and the output impedance of the high-level output state. It can be said that the synchronous output circuit 40B as the synchronous output circuit 40[i] outputs a high-level signal from the synchronous output terminal S_OUT[i] in the Hi-Z state with an output impedance higher than that in the high-level output state.

[0139] <<Second Example>> The second embodiment will be described. The second embodiment and the third to seventh embodiments described later are based on the first embodiment, and for matters not specifically mentioned in the second to seventh embodiments, the description of the first embodiment may also be applied to the second to seventh embodiments, unless there is a contradiction. However, when interpreting the description of the second embodiment, the description of the second embodiment may take precedence for matters that contradict between the first and second embodiments (the same applies to the third to seventh embodiments described later). As long as there is no contradiction, any combination of the first to seventh embodiments may be used.

[0140] In the second embodiment, as in the first embodiment, it is assumed that the synchronous input terminal S_IN of the device 10[1] is open. Therefore, in the second embodiment, the controller 28 of the device 10[1] receives the internal clock signal CLK generated in the device 10[1]. A Reference clock signal CLK REF It is used to control the switching of the output stage MM[1].

[0141] FIG. 21 shows a conceptual diagram of the waveform of the clock signal CLK[i] according to the second embodiment. In the second embodiment, it is considered that each period of an arbitrary clock signal starts from the falling edge of the clock signal. The synchronous output circuit 40[i] according to the second embodiment switches the state of the synchronous output terminal S_OUT[i] from a high-level output state to a low-level output state at time T1, then switches from the low-level output state to a Hi-Z state at time T2, then switches from the Hi-Z state to a high-level output state at time T3, and then switches from the high-level output state to a low-level output state at time T4. Thereafter, the same operation is repeated. When time T1 is the start time of the j-th period of the clock signal CLK[i], time T4 corresponds to the start time of the (j+1)-th period of the clock signal CLK[i]. j represents any natural number.

[0142] Thus, in the output period of the clock signal CLK[i], the synchronous output circuit 40[i] according to the second embodiment includes, in each cycle of the clock signal CLK[i], a period P21 (between times T1 and T2 in FIG. 21) in which the state of the synchronous output terminal S_OUT[i] is set to a low-level output state, a period P23 (between times T3 and T4 in FIG. 21) in which the state of the synchronous output terminal S_OUT[i] is set to a high-level output state, and a period P22 (between times T2 and T3 in FIG. 21) in which the state of the synchronous output terminal S_OUT[i] is set to a Hi-Z state. For example, the lengths of the periods P21, P22, and P23 are each unit time t U1 25%, 25%, and 50% of the unit time t U1The ratio of each of the periods P11, P12, and P13 in the second embodiment may be arbitrary. The output pattern of the clock signal CLK[i] according to the second embodiment is referred to as a pattern PTN1b.

[0143] 22 shows the waveform of the clock signal CLK[i] when the synchronous input circuit 50[i+1] is in the pull-down state. When the synchronous input circuit 50[i+1] is in the pull-down state, after time T2, at time T3 PRE The potential of the clock signal CLK[i] is maintained at ground potential (and therefore at a low level) until time T3, at which point the potential of the clock signal CLK[i] suddenly rises from ground potential to the potential of the power supply voltage VDD.

[0144] 23 shows the waveform of the clock signal CLK[i] when the synchronous input circuit 50[i+1] is in a pull-up state. When the synchronous input circuit 50[i+1] is in a pull-up state, after time T2, the potential of the clock signal CLK[i] rises from the ground potential toward the potential of the power supply voltage VDD, and at time T3 PRE Since the potential of the power supply voltage VDD increases before time T3 PRE The synchronous output terminal S_OUT[i] at has a high level.

[0145] As in the first embodiment, when the clock signal CLK[i] is output by the synchronous output circuit 40[i], the level detection circuit 60[i] detects PRE The voltage of the synchronous output terminal S_OUT[i] in is specified as a detection target voltage, and it is detected whether the detection target voltage belongs to a high level or a low level.

[0146] However, when the level detection circuit 60[i] according to the second embodiment determines that the detection target voltage is at a high level, it outputs a level detection signal S DET [i] is output (see FIG. 23). The level detection signal S DET When [i] is output, “S DET[i]=1" is maintained. When the level detection circuit 60[i] according to the second embodiment determines that the detection target voltage is at a low level, it outputs a level detection signal S DET [i] is output (see FIG. 22). The “0” level detection signal S DET When [i] is output, “S DET [i]=0” is maintained.

[0147] In the second embodiment, a fall edge always occurs in the clock signal CLK[i] at time T1 regardless of the state of the synchronous input circuit 50[i+1]. Therefore, the falling edge of the clock signal CLK[i] can be used to synchronize switching between the devices 10[i] and 10[i+1]. In order to ensure this synchronization, in the second embodiment in which the pattern PTN1b of FIG. 21 is adopted, the set edge is a fall edge. That is, when the clock signal CLK[i] of the pattern PTN1b is supplied to the device 10[i+1], the controller 28 of the device 10[i+1] turns on the transistor MH and turns off the transistor ML in response to the falling edge of the clock signal CLK[i].

[0148] In the second embodiment, the following second rule is adopted in each device 10. In the second rule, the relationship between the pull-down state and the pull-up state is the opposite of that in the first rule. That is, a device 10[i] that follows the second rule sets the state of the synchronous input terminal S_IN[i] to the pull-up state during the output period of the clock signal CLK[i], and sets the state of the synchronous input terminal S_IN[i] to the pull-down state during the non-output period of the clock signal CLK[i].

[0149] Fig. 24 shows an operational flowchart of device 10[1] operating in the first mode. In the second embodiment, the operation of device 10[1] is similar to the processing of steps S10 to S18 shown in Fig. 17, except for the following differences. That is, in the second embodiment, steps S11, S15, S16, and S17 are replaced with steps S11a, S15a, S16a, and S17a, respectively.

[0150] In step S11a, the synchronous input terminal S_IN[1] is set to a pull-down state. In other respects, step S11a is similar to step S11. In step S15a, the state of the synchronous input terminal S_IN[1] is changed from a pull-down state to a pull-up state. In other respects, step S15a is similar to step S15. The processing content of step S16a itself is the same as that of step S16. However, in the second embodiment, "S DET [1]=0" indicates that the synchronous input terminal S_IN[2] is in a pull-down state (see FIG. 22). In step S17a, the state of the synchronous input terminal S_IN[1] is changed from a pull-up state to a pull-down state. Otherwise, step S17a is similar to step S17.

[0151] Fig. 25 shows an operational flowchart of device 10[i] operating in the second mode. The variable i in each step shown in Fig. 25 represents any integer equal to or greater than 2. In the second embodiment, the operation of device 10[i] is similar to the processing of steps S20 to S27 shown in Fig. 18, except for the following differences. That is, in the second embodiment, steps S21, S25, S26, and S27 are replaced with steps S21a, S25a, S26a, and S27a, respectively.

[0152] In step S21a, the synchronous input terminal S_IN[i] is set to a pull-down state. In other respects, step S21a is similar to step S21. In step S25a, the state of the synchronous input terminal S_IN[i] is changed from a pull-down state to a pull-up state. In other respects, step S25a is similar to step S25. The process content of step S26a itself is the same as that of step S26. However, in the second embodiment, "S DET [i]=0" indicates that the synchronous input terminal S_IN[i+1] is in a pull-down state (see FIG. 22). In step S27a, the state of the synchronous input terminal S_IN[i] is changed from a pull-up state to a pull-down state. Otherwise, step S27a is similar to step S27.

[0153] In the second embodiment, it is preferable to use the synchronous output circuit 40C of FIG. 26 as the synchronous output circuit 40 of each device 10. The synchronous output circuit 40C has a configuration in which a pull-down resistor 45 is added to the synchronous output circuit 40A of FIG. 8, and is the same as the synchronous output circuit 40A except for the addition. A first end of the pull-down resistor 45 is connected to ground, and a second end of the pull-down resistor 45 is connected to the synchronous output terminal S_OUT. Here, the value of the pull-down resistor 45 is sufficiently larger than the value of the resistor 54 of FIG. 9. For example, when the resistor 54 has a value of 50 kΩ (kilo ohms), the value of the pull-down resistor 45 is set to 5 MΩ (mega ohms).

[0154] As a result, during the period in which the synchronous output terminal S_OUT[i] is in the Hi-Z state, if the synchronous input terminal S_IN[i+1] is in the pull-up state, the potential of the synchronous output terminal S_OUT[i] becomes approximately 99 / 100 of the power supply voltage VDD (the upper threshold voltage V THH Since the voltage to be detected (at time T3 PRE During the period in which the synchronous output terminal S_OUT[i] is in the Hi-Z state, if the synchronous input terminal S_IN[i+1] is in the pull-down state, the potential of the synchronous output terminal S_OUT[i] will match the ground potential, so the level determination circuit 60[i] can reliably determine that the detection target voltage (the voltage of the synchronous output terminal S_OUT[i] at time T3 PRE The voltage at the synchronous output terminal S_OUT[i] in is determined to be at a low level.

[0155] In the final stage device 10[n], during the period in which the synchronous output terminal S_OUT[n] is in the Hi-Z state, the potential of the synchronous output terminal S_OUT[i] is maintained at the ground potential due to the presence of the pull-down resistor 45. As a result, the level determination circuit 60[n] detects the detection target voltage (at time T3 PRE In this embodiment, the voltage at the synchronous output terminal S_OUT[n] in the first embodiment is determined to be at a low level. In other words, the erroneous recognition described in the first embodiment does not occur.

[0156] The value of the pull-down resistor 45 is much larger than the on-resistance value of the transistor 41 and the on-resistance value of the transistor 42. Therefore, in the synchronous output circuit 40C, similarly to the synchronous output circuit 40A, the output impedance of the synchronous output terminal S_OUT in the Hi-Z state is sufficiently higher than the output impedance of the low-level output state and the output impedance of the high-level output state. It can be said that the synchronous output circuit 40C as the synchronous output circuit 40[i] outputs a low-level signal from the synchronous output terminal S_OUT[i] in the Hi-Z state with an output impedance higher than that in the low-level output state.

[0157] The waveforms of the clock signals CLK[0] to CLK[3] in the 4-channel driving state are the same as those shown in FIG. 19. However, in the second embodiment, the falling edge of the clock signal functions as a set edge for the controller 28, so the timing of the falling edge of the clock signal CLK[i+1] is determined based on the timing of the falling edge of the clock signal CLK[i]. In other words, the synchronous output circuit 40[1] is set to a timing that is 180° phase delayed from the falling edge of the clock signal CLK[0] (i.e., "t U1 Similarly, the synchronous output circuit 40[2] generates the clock signal CLK[1] so that the falling edge of the clock signal CLK[1] occurs at a timing delayed by a phase of 90° from the falling edge of the clock signal CLK[0] (i.e., a timing delayed by a time of “t U1 Similarly, the synchronous output circuit 40[3] generates the clock signal CLK[2] so that the falling edge of the clock signal CLK[2] occurs at a timing delayed by a phase of 180° from the falling edge of the clock signal CLK[0] (i.e., a timing delayed by a phase of “t U1 The clock signal CLK[3] is generated so that the falling edge of the clock signal CLK[3] occurs at a timing delayed by 1 / 2”.

[0158] <<Third Example>> A third embodiment will be described. In the first embodiment, the pattern PTN1a shown in FIG. 12 is combined with the first rule. As already mentioned, the device 10[i] following the first rule sets the state of the synchronous input terminal S_IN[i] to a pull-down state during the output period of the clock signal CLK[i], while setting the state of the synchronous input terminal S_IN[i] to a pull-up state during the non-output period of the clock signal CLK[i]. In the second embodiment, the pattern PTN1b shown in FIG. 21 is combined with the second rule. As already mentioned, the device 10[i] following the second rule sets the state of the synchronous input terminal S_IN[i] to a pull-up state during the output period of the clock signal CLK[i], while setting the state of the synchronous input terminal S_IN[i] to a pull-down state during the non-output period of the clock signal CLK[i].

[0159] However, a first modified configuration that combines the pattern PTN1a and the second rule in Fig. 12 may be adopted. In the first modified configuration, in response to the adoption of the second rule, it is possible to use the synchronous output circuit 40C in Fig. 26 as the synchronous output circuit 40 of each device 10. However, when the synchronous output circuit 40C is used in the first modified configuration, the slope of the potential drop of the synchronous output terminal S_OUT[n] from time T2 in Fig. 12 becomes smaller due to the influence of the parasitic capacitance added to the synchronous output terminal S_OUT[n] of the final stage. As a result, the slope of the potential drop of the synchronous output terminal S_OUT[n] from time T3 in Fig. 12 becomes smaller. PRE In this case, the potential of the synchronous output terminal S_OUT[n] in the pattern PTN1a may be determined to be high level when it should be determined to be low level. Therefore, it is preferable to adopt the first rule for the pattern PTN1a.

[0160] Similarly, a second modified configuration may be adopted that combines the pattern PTN1b in Fig. 21 with the first rule. In the second modified configuration, the synchronous output circuit 40B in Fig. 20 can be used as the synchronous output circuit 40 of each device 10 in response to the adoption of the first rule. However, when the synchronous output circuit 40B is used in the second modified configuration, the slope of the potential rise of the synchronous output terminal S_OUT[n] from time T2 in Fig. 21 becomes smaller due to the influence of the parasitic capacitance added to the synchronous output terminal S_OUT[n] of the final stage. As a result, the slope of the potential rise of the synchronous output terminal S_OUT[n] from time T3 in Fig. 21 becomes smaller. PRE In this case, the potential of the synchronous output terminal S_OUT[n] in the pattern PTN1b may be determined to be at a low level, even though it should be determined to be at a high level. Therefore, it is preferable to adopt the second rule for the pattern PTN1b.

[0161] In the first or second embodiment, the output pattern of the clock signal CLK[i] by the synchronous output circuit 40[i] is not limited to the pattern PTN1a or PTN1b. That is, in the first or second embodiment, as long as each cycle of the clock signal CLK[i] includes a period in which the state of the synchronous output terminal S_OUT[i] is set to a high-level output state, a period in which the state of the synchronous output terminal S_OUT[i] is set to a low-level output state, and a period in which the state of the synchronous output terminal S_OUT[i] is set to a Hi-Z state, the output pattern of the clock signal CLK[i] may be any. However, in consideration of the ease of implementing various controls and judgments, it is preferable to adopt the pattern PTN1a or PTN1b.

[0162] <<Fourth Example>> A fourth embodiment will now be described. In the first or second embodiment, a clock signal CLK is input to the synchronous input terminal S_IN[1]. B However, in the first and second embodiments, it is assumed that a clock signal CLK is not input to the synchronous input terminal S_IN[1] of the device 10[1] from an external clock supply circuit (not shown). B If input, in step S18 (see FIG. 17 or FIG. 24), the input clock signal CLK to the synchronous input terminal S_IN[1] Bclock signal CLK[0] (reference clock signal CLK REF In this case, after proceeding from step S18 to step S13, the device 10[1] may set the input clock signal CLK to the synchronous input terminal S_IN[1]. B The switching control of the output stage MM[1] starts in synchronization with the clock signal CLK[0].

[0163] <<Fifth Example>> A fifth embodiment will be described. The above-mentioned clock signal CLK[i] allows the preceding device 10[i] to notify the following device 10[i+1] of synchronization timing. In the fifth embodiment, a method of transmitting information other than synchronization timing from the preceding device 10[i] to the following device 10[i+1] using the clock signal CLK[i] will be described.

[0164] In each device 10, the synchronous output circuit 40 may output a clock signal CLK[i] of the pattern PTN2a of Fig. 27. Pattern PTN2a will be described. As time progresses, times T11, T12, T13, T14, T15, T16, and T17 arrive in this order. The time difference between times T11 and T14 is unit time t U2 The time difference between times T14 and T17 is also the unit time t U2 The time difference between times T11 and T12 and the time difference between times T15 and T16 are both time (t U2 / 4), but at time (t U2 The time difference between times T12 and T13, the time difference between times T13 and T15, and the time difference between times T16 and T17 are all times (t U2 / 2), but at time (t U2 However, in the clock signal CLK[i] of the pattern PTN2a, the interval between two adjacent rising edges is constant, and the unit time t U2 Matches.

[0165] In pattern PTN2a, the state of the synchronous output terminal S_OUT[i] is a low level output state at time T11, then switches from the low level output state to a high level output state at time T12, then switches from the high level output state to the low level output state at time T13, then switches from the low level output state to the high level output state at time T15, then switches from the high level output state to the low level output state at time T16, and is then maintained in the low level output state until time T17.

[0166] One cycle of the clock signal CLK[i] in the pattern PTN2a corresponds to the period between times T11 and T17. In the pattern PTN2a, if the period between times T11 and T17 is the j-th cycle of the clock signal CLK[i], then the period from time T17 to the time (2×t U2 ) period is the (j+1)th period of the clock signal CLK[i], where j represents any natural number. The waveform of the clock signal CLK[i] is the same in each period of the clock signal CLK[i] of the pattern PTN2a.

[0167] In pattern PTN2a, waveforms WV1 and WV2 appear alternately in clock signal CLK[i]. Focusing on the period between times T11 and T17, waveform WV1 is the waveform of clock signal CLK[i] between times T11 and T14, and waveform WV2 is the waveform of clock signal CLK[i] between times T14 and T17.

[0168] In this way, the synchronous output circuit 40[i] alternately sets the state of the synchronous output terminal S_OUT[i] to a low level output state and a high level output state during the output period of the clock signal CLK[i] of the pattern PTN2a, and does not set the state of the synchronous output terminal S_OUT[i] to a Hi-Z state. U2 is the unit time t U1 or unit time t U1 (See FIG. 12.) Here, “t U2 =t U1 " I believe that.

[0169] The pattern determination circuit 70[i] in any device 10[i] determines whether a clock signal of pattern PTN2a is input to the synchronous input terminal S_IN[i] based on the voltage of the synchronous input terminal S_IN[i], and outputs a pattern determination signal S PTN The pattern determination circuit 70[i] outputs a pattern determination signal S_IN[i] having a value of “1” only when it determines that the clock signal of the pattern PTN2a is input to the synchronous input terminal S_IN[i]. PTN [i], and otherwise outputs a pattern judgment signal S PTN Output [i].

[0170] The pattern determination circuit 70[i] determines the determination time T K1 and T K2 The above determination is made based on the voltage of the synchronous input terminal S_IN[i] at the determination time T K1 is a time a predetermined time Δt after a rising edge occurs in the signal of the synchronous input terminal S_IN[i], and is a judgment time T K2 is the time a predetermined time Δt after the next rising edge occurs in the signal of the synchronous input terminal S_IN[i]. K1 is a time that is a predetermined time Δt after time T12 and is also a judgment time T K2 is a time a predetermined time Δt after time T15. K1 Time from T12 to (t U2 / 4) later than time T13 and before time T14. K2 is later than time T16 and is longer than time (t U2 For example, the given time Δt is the time before the time that is unit time t U2 It is 3 / 8 times larger than that.

[0171] When the clock signal CLK[i] of the pattern PTN2a shown in Fig. 27 is output from the device 10[i], it is the device 10[i+1] that receives the clock signal CLK[i] (see Fig. 11). For convenience of explanation, the operation of the pattern determination circuit 70[i+1] will be described in detail with reference to Fig. 27 (see also Fig. 11). Note that the output impedance of the synchronous output circuit 40[i] during the output period of the clock signal CLK[i] of the pattern PTN2a is sufficiently smaller than the input impedance of the synchronous input circuit 50[i+1] (corresponding to the value of the resistor 54 in Fig. 9), so the voltage of the synchronous input terminal S_IN[i+1] does not substantially depend on the state of the synchronous input circuit 50[i+1].

[0172] The pattern determination circuit 70[i+1] determines whether the clock signal CLK[i] has a waveform that switches between the waveforms WV1 and WV2 based on the voltage of the synchronous input terminal S_IN[i+1], thereby determining whether the clock signal CLK[i] has the pattern PTN2a. More specifically, when the signal level of the synchronous input terminal S_IN[i+1] changes between a high level and a low level, the pattern determination circuit 70[i+1] extracts two consecutive rising edges in the signal of the synchronous input terminal S_IN[i+1] as the first and second rising edges. Then, the pattern determination circuit 70[i+1] identifies the level of the synchronous input terminal S_IN[i+1] at a time a predetermined time Δt after the first rising edge and the level of the synchronous input terminal S_IN[i+1] at a time a predetermined time Δt after the second rising edge. The pattern determination circuit 70[i+1] determines that a clock signal of the pattern PTN2a is input to the synchronization input terminal S_IN[i+1] only when one of the two identified levels is a high level and the other is a low level, and outputs a pattern determination signal S of "1". PTN [i+1] is output, and otherwise the pattern judgment signal S has a value of “0”. PTN One of the time a predetermined time Δt after the first rising edge and the time a predetermined time Δt after the second rising edge is the judgment time T K1 and the other is the judgment time T K2 It is.

[0173] The synchronous output circuit 40[i] according to the fifth embodiment can selectively output a clock signal CLK[i] of the pattern PTN2a and a clock signal CLK[i] of the pattern PTN1a shown in FIG.

[0174] When the synchronous input terminal S_IN[i+1] is set to a pull-up state by the synchronous input circuit 50[i+1], if the clock signal CLK[i] of the pattern PTN2a is composed of only the waveform WV1, the signal waveform appearing at the synchronous input terminal S_IN[i+1] is unlikely to differ between when the clock signal CLK[i] is the pattern PTN2a and when it is the pattern PTN1a. Similarly, when the synchronous input terminal S_IN[i+1] is set to a pull-down state by the synchronous input circuit 50[i+1], if the clock signal CLK[i] of the pattern PTN2a is composed of only the waveform WV2, the signal waveform appearing at the synchronous input terminal S_IN[i+1] is unlikely to differ between when the clock signal CLK[i] is the pattern PTN2a and when it is the pattern PTN1a. Therefore, in practice, the clock signal CLK[i] of the pattern PTN2a includes the waveforms WV1 and WV2, as shown in FIG.

[0175] When the clock signal CLK[i] has the pattern PTN1a, and the synchronous input terminal S_IN[i+1] is set to a pull-up state, the signal at the synchronous input terminal S_IN[i+1] is always at a high level after a predetermined time Δt from the rising edge of the signal at the synchronous input terminal S_IN[i+1]. PTN [i+1] becomes "0". Similarly, when the clock signal CLK[i] has the pattern PTN1a, when the synchronous input terminal S_IN[i+1] is set to the pull-down state, the signal at the synchronous input terminal S_IN[i+1] always has a low level after a predetermined time Δt from the rising edge of the signal at the synchronous input terminal S_IN[i+1], so that the pattern determination signal S PTN [i+1] becomes “0”.

[0176] On the other hand, when the clock signal CLK[i] has the pattern PTN2a, the two decision times T K1 and T K2 Since the levels of the synchronous input terminals S_IN[i+1] at this time are high and low, the pattern determination signal S PTN [i+1] is generated. Therefore, the pattern decision signal S of “1” is generated. PTN [i+1] indicates that the clock signal CLK[i] input to the synchronous input terminal S_IN[i+1] has the pattern PTN2a.

[0177] By using the clock signal CLK[i] having the pattern PTN2a, it is possible to forcibly perform switching control on all channels. This will be described in detail.

[0178] A forced output determination circuit in the device 10[1] operating in the first mode determines whether a predetermined forced output condition is satisfied. Here, it is assumed that the forced output condition is satisfied when a clock signal having a predetermined duty is input to the synchronous input terminal S_IN[1], and that the forced output condition is not satisfied when a clock signal having a predetermined duty is not input to the synchronous input terminal S_IN[1]. In this case, the forced output determination circuit may be the pattern determination circuit 70[1] or the switching control circuit 20[1]. The above-mentioned predetermined duty is a duty within a certain range, and here, for example, it is assumed to be a duty of 40% or more and 60% or less. The duty of a certain clock signal refers to the ratio of the high level period of the clock signal to the sum of the high level period and the low level period of the clock signal.

[0179] Alternatively, the forced output setting information may be stored in a memory (not shown) in the device 10[1]. In this case, when the forced output setting information in the memory is "1", the forced output condition is met, and when the forced output setting information in the memory is "0", the forced output condition is not met. A higher-level system (not shown) connected to the device 10[1] so as to be able to communicate bidirectionally can write "1" or "0" to the forced output setting information in the memory in the device 10[1].

[0180] The fifth embodiment can be implemented in combination with the first embodiment, and the combination will be described below. In the fifth embodiment, the first rule described in the first embodiment is adopted, and the set edge is the rising edge. That is, the controller 28 of the device 10[i+1] turns on the transistor MH and turns off the transistor ML in response to the rising edge of the clock signal CLK[i]. In the fifth embodiment combined with the first embodiment, it is preferable to use the synchronous output circuit 40B of FIG. 20 as the synchronous output circuit 40 of each device 10.

[0181] After the device 10[1] is started, a clock signal CLK having a duty of 50% is supplied from an external clock supply circuit (not shown) to the synchronous input terminal S_IN[1] of the device 10[1]. B Consider the situation FORCE_ON in which the input clock signal CLK to the synchronous input terminal S_IN[1] is input. In this case, the forced output condition is satisfied. In the situation FORCE_ON, B is the reference clock signal CLK REF For convenience of explanation, the reference clock signal CLK supplied to the controller 28 of the device 10[1] is REF may be referred to as the clock signal CLK[0]. In the FORCE_ON state, the output stage MM[1] is switched synchronously with the clock signal CLK[0]. That is, the input clock signal CLK B At the rising edge of the clock signal CLK[0], the transistor MH of the output stage MM[1] is turned on and the transistor ML is turned off.

[0182] When switching control is executed in the device 10[1] in the FORCE_ON state, the clock management circuit 80[1] controls the synchronous output circuit 40[1] to output the clock signal CLK[1] having the pattern PTN2a from the synchronous output terminal S_OUT[1] in the synchronous output circuit 40[1] regardless of whether the clock output condition (the clock output condition in step S14 in FIG. 17) is satisfied. The clock signal CLK[1] having the pattern PTN2a is reference clock signal CLK of the device 10[1]. REF (i.e., it is generated based on the clock signal CLK[0]).

[0183] When the clock signal CLK[1] having the pattern PTN2a is input to the synchronous input terminal S_IN[2], the clock signal CLK[1] having the pattern PTN2a is input to the reference clock signal CLK of the device 10[2]. REF The signal PTN2a is input to the controller 28 of the device 10[2] as a signal PTN2b. Therefore, the output stage MM[2] is switched in synchronization with the clock signal CLK[1]. That is, the transistor MH of the output stage MM[2] is turned on and the transistor ML is turned off at the rising edge of the clock signal CLK[1] having the pattern PTN2a.

[0184] In addition, when a clock signal CLK[1] having a pattern PTN2a is input to the synchronous input terminal S_IN[2], a pattern determination signal S PTN [2] has a value of “1”. PTN When [2]=1", the clock management circuit 80[2] controls the synchronous output circuit 40[2] to output a clock signal CLK[2] having the pattern PTN2a from the synchronous output terminal S_OUT[2] in the synchronous output circuit 40[2] regardless of whether the clock output condition (the clock output condition in step S24 in FIG. 18) is satisfied. The clock signal CLK[2] having the pattern PTN2a is used as the reference clock signal CLK of the device 10[2]. REF (i.e., the input clock signal CLK[1] to device 10[2]).

[0185] The operation of another device 10 (e.g., device 10[3]) operating in the second mode is similar to that of device 10[2]. That is, for example, when a clock signal CLK[2] having a pattern PTN2a is input to the synchronous input terminal S_IN[3], the clock signal CLK[2] having the pattern PTN2a becomes the reference clock signal CLK of device 10[3]. REF The signal PTN2a is input to the controller 28 of the device 10[3] as a signal PTN2b. Therefore, the output stage MM[3] is switched in synchronization with the clock signal CLK[2]. That is, the transistor MH of the output stage MM[3] is turned on and the transistor ML is turned off at the rising edge of the clock signal CLK[2] having the pattern PTN2a.

[0186] In addition, when the clock signal CLK[2] having the pattern PTN2a is input to the synchronous input terminal S_IN[3], the pattern determination signal S PTN [3] has a value of “1”. PTN When [3]=1", the clock management circuit 80[3] controls the synchronous output circuit 40[3] to output the clock signal CLK[3] having the pattern PTN2a from the synchronous output terminal S_OUT[3] in the synchronous output circuit 40[3] regardless of whether the clock output condition (the clock output condition in step S24 in FIG. 18) is satisfied. The clock signal CLK[3] having the pattern PTN2a is used as the reference clock signal CLK of the device 10[3]. REF (i.e., the input clock signal CLK[2] to device 10[3]).

[0187] The same is true for the devices 10[4] to 10[n]. Therefore, in the FORCE_ON state, switching control is performed in the devices 10 of all channels, regardless of whether the clock output conditions are met.

[0188] In addition, the operation of the device 10[1] when the forced output condition is not satisfied is the same as that shown in FIG. 17, and the operation of each of the devices 10[2] to 10[n] when the forced output condition is not satisfied is the same as that shown in FIG. 18. However, the clock signal CLK[i] that can be output from the device 10[i] when the forced output condition is not satisfied has a pattern PTN1a as in the first embodiment. Therefore, when the forced output condition is not satisfied, if the clock signal CLK[1] is not supplied to the synchronous input terminal S_IN[2], the synchronous output circuit 40[2] of the device 10[2] does not output any clock signal (the synchronous output terminal S_OUT[2] is kept in a Hi-Z state). When the forced output condition is not satisfied, when the clock signal CLK[1] of the pattern PTN1a is supplied to the synchronous input terminal S_IN[2], the device 10[2] executes switching control synchronized with the clock signal CLK[1], and if the clock output condition is satisfied in the device 10[2], the clock signal CLK[2] of the pattern PTN1a based on the clock signal CLK[1] (the input clock signal CLK[1] to the device 10[2]) is output from the synchronous output terminal S_OUT[2] by the synchronous output circuit 40[2]. The same applies to other devices 10 (e.g., device 10[3]) operating in the second mode.

[0189] In a device 10[1] operating in a first mode, when the forced output condition is not satisfied, after the synchronous output circuit 40[1] starts outputting a clock signal CLK[1] of pattern PTN1a, the output of the clock signal CLK[1] of pattern PTN1a is stopped in response to the satisfaction of the clock stop condition (the clock stop condition of step S16 in FIG. 17).

[0190] When the forced output condition is not satisfied, the clock signal CLK[1] of the pattern PTN1a may be supplied to the synchronous input terminal S_IN[2]. In the device 10[2] operating in the second mode, when the clock signal CLK[1] of the pattern PTN1a is supplied to the synchronous input terminal S_IN[2], after the synchronous output circuit 40[2] starts outputting the clock signal CLK[2] of the pattern PTN1a, in response to the satisfaction of the clock stop condition (the clock stop condition of step S26 in FIG. 18), the output of the clock signal CLK[2] of the pattern PTN1a is stopped. The same applies to other devices 10 (e.g., device 10[3]) operating in the second mode.

[0191] 28 shows the waveforms of the clock signals CLK[0] to CLK[3] in a 4-channel driving state under the FORCE_ON state. Under the FORCE_ON state, the clock signal CLK[0] supplied to the device 10[1] from an external clock supply circuit (not shown) is a square wave signal having a duty of 50%, and the length of one cycle of the clock signal CLK[0] is unit time t U2 It is.

[0192] In the four-channel driving state relating to the status FORCE_ON, the clock signals CLK[0] to CLK[3] correspond to the reference clock signals CLK[1] to CLK[4] in the devices 10[1] to 10[4], respectively. REF Therefore, the controller 28 of the device 10[1] turns on the transistor MH and turns off the transistor ML of the output stage MM[1] at the rising edge of the clock signal CLK[0]. The controller 28 of the device 10[2] turns on the transistor MH and turns off the transistor ML of the output stage MM[2] at the rising edge of the clock signal CLK[1]. The controller 28 of the device 10[3] turns on the transistor MH and turns off the transistor ML of the output stage MM[3] at the rising edge of the clock signal CLK[2]. The controller 28 of the device 10[4] turns on the transistor MH and turns off the transistor ML of the output stage MM[4] at the rising edge of the clock signal CLK[3].

[0193] In the FORCE_ON state, the synchronous output circuit 40[1] generates a clock signal CLK[1] based on the clock signal CLK[0]. In this case, the synchronous output circuit 40[1] generates the clock signal CLK[1] so that the time delayed by the shift amount SHT[1] from the time when the rising edge of the clock signal CLK[0] occurs is time T12 for the clock signal CLK[1] (see also FIG. 27).

[0194] In the FORCE_ON state, the synchronous output circuit 40[2] generates a clock signal CLK[2] based on the clock signal CLK[1]. At this time, the synchronous output circuit 40[2] generates the clock signal CLK[2] so that the time delayed by the shift amount SHT[2] from the time when the rising edge of the clock signal CLK[1] occurs is time T12 for the clock signal CLK[2] (see also FIG. 27).

[0195] In the FORCE_ON state, the synchronous output circuit 40[3] generates a clock signal CLK[3] based on the clock signal CLK[2]. At this time, the synchronous output circuit 40[3] generates the clock signal CLK[3] so that the time delayed by the shift amount SHT[3] from the time when the rising edge of the clock signal CLK[2] occurs is time T12 for the clock signal CLK[3] (see also FIG. 27).

[0196] The shift amounts SHT[1], SHT[2], and SHT[3] are the time (t U2 / 2), time (t U2 / 4), time (t U2 As a result, the phases of the clock signals CLK[0] to CLK[3] are shifted from one another (the rising edge timings of the clock signals CLK[0] to CLK[3] are shifted from one another), so multi-phase control is performed for four channels.

[0197] <<Sixth Example>> The sixth embodiment will be described. The fifth embodiment may be modified in the same way as the first embodiment is changed to the second embodiment. That is, in each device 10 according to the sixth embodiment, the synchronous output circuit 40 may output the clock signal CLK[i] of the pattern PTN2b in FIG. 29. The clock signal CLK[i] of the pattern PTN2b corresponds to the inverted signal of the clock signal CLK[i] of the pattern PTN2a according to the fifth embodiment. The sixth embodiment is a partial modification of the fifth embodiment, and the description of the fifth embodiment may be applied to the sixth embodiment for matters not described in the sixth embodiment, unless there is a contradiction.

[0198] Pattern PTN2b will be described. The relationship between times T11 to T17 is as described in the fifth embodiment. However, the state of the synchronous output terminal S_OUT[i] is inverted between patterns PTN2a and PTN2b. That is, in pattern PTN2b, the state of the synchronous output terminal S_OUT[i] is a high level output state at time T11, then switches from the high level output state to a low level output state at time T12, then switches from the low level output state to a high level output state at time T13, then switches from the high level output state to a low level output state at time T15, then switches from the low level output state to a high level output state at time T16, and is then maintained in the high level output state until time T17.

[0199] One period of the clock signal CLK[i] in the pattern PTN2b corresponds to the period between times T11 and T17. In the pattern PTN2b, if the period between times T11 and T17 is the j-th period of the clock signal CLK[i], then the period from time T17 to the time (2×t U2 ) period is the (j+1)th period of the clock signal CLK[i], where j represents any natural number. The waveform of the clock signal CLK[i] is the same in each period of the clock signal CLK[i] of the pattern PTN2b.

[0200] In pattern PTN2b, waveforms WV3 and WV4 appear alternately in clock signal CLK[i]. Focusing on the period between times T11 and T17, waveform WV3 is the waveform of clock signal CLK[i] between times T11 and T14, and waveform WV4 is the waveform of clock signal CLK[i] between times T14 and T17.

[0201] In this way, the synchronous output circuit 40[i] alternately sets the state of the synchronous output terminal S_OUT[i] to a low level output state and a high level output state during the output period of the clock signal CLK[i] of the pattern PTN2b, and does not set the state of the synchronous output terminal S_OUT[i] to a Hi-Z state. U2 is the unit time t U1 or unit time t U1 (See FIG. 21.) Here, “t U2 =t U1 " I believe that.

[0202] The operation of the pattern determination circuit 70 according to the sixth embodiment is similar to that of the fifth embodiment. However, when applying the description of the fifth embodiment to the sixth embodiment, the waveform symbols "WV1" and "WV2" in the fifth embodiment are replaced with "WV3" and "WV4" in the sixth embodiment, respectively, and the pattern symbol "PTN2a" in the fifth embodiment is replaced with "PTN2b" in the sixth embodiment.

[0203] The pattern determination circuit 70[i] determines whether a clock signal of pattern PTN2b is input to the synchronous input terminal S_IN[i] based on the voltage of the synchronous input terminal S_IN[i], and outputs a pattern determination signal S PTN At this time, the pattern decision circuit 70[i] outputs the decision time T K1 and T K2 The above determination is made based on the voltage of the synchronous input terminal S_IN[i] at the determination time T K1is the time a predetermined time Δt after the fall edge occurs in the signal of the synchronous input terminal S_IN[i], and is the judgment time T K2 is the time a predetermined time Δt after the next fall edge occurs in the signal at the synchronous input terminal S_IN[i].

[0204] When the clock signal CLK[i] of the pattern PTN2b shown in Fig. 29 is output from the device 10[i], it is the device 10[i+1] that receives the clock signal CLK[i] (see Fig. 11). Therefore, when attention is paid to the operation of the pattern determination circuit 70[i+1] in 10[i+1], the operation of the pattern determination circuit 70[i+1] is as follows.

[0205] The pattern determination circuit 70[i+1] determines whether the clock signal CLK[i] has a pattern PTN2b by determining whether the clock signal CLK[i] has a waveform that switches between the waveforms WV3 and WV4 based on the voltage of the synchronous input terminal S_IN[i+1]. More specifically, when the signal level of the synchronous input terminal S_IN[i+1] changes between a high level and a low level, the pattern determination circuit 70[i+1] extracts two consecutive fall edges in the signal of the synchronous input terminal S_IN[i+1] as the first and second fall edges. Then, the pattern determination circuit 70[i+1] identifies the level of the synchronous input terminal S_IN[i+1] at a time a predetermined time Δt after the first fall edge and the level of the synchronous input terminal S_IN[i+1] at a time a predetermined time Δt after the second fall edge. The pattern determination circuit 70[i+1] determines that a clock signal of the pattern PTN2b is input to the synchronization input terminal S_IN[i+1] only when one of the two identified levels is a high level and the other is a low level, and outputs a pattern determination signal S of "1". PTN [i+1] is output, and otherwise the pattern judgment signal S has a value of “0”. PTN [i] is output. One of the time a predetermined time Δt after the first fall edge and the time a predetermined time Δt after the second fall edge is the judgment time T K1 and the other is the judgment time TK2 It is.

[0206] The synchronous output circuit 40[i] according to the sixth embodiment can selectively output a clock signal CLK[i] of the pattern PTN2b and a clock signal CLK[i] of the pattern PNT1b shown in FIG.

[0207] When the clock signal CLK[i] is in the pattern PTN1b and the synchronous input terminal S_IN[i+1] is set to the pull-up state, the signal at the synchronous input terminal S_IN[i+1] is always at a high level after a predetermined time Δt from the falling edge of the signal at the synchronous input terminal S_IN[i+1]. PTN [i+1] becomes "0". Similarly, when the clock signal CLK[i] is in the pattern PTN1b and the synchronous input terminal S_IN[i+1] is set to the pull-down state, the signal at the synchronous input terminal S_IN[i+1] always has a low level after a predetermined time Δt from the falling edge of the signal at the synchronous input terminal S_IN[i+1]. PTN [i+1] becomes “0”.

[0208] On the other hand, when the clock signal CLK[i] has the pattern PTN2b, the two decision times T K1 and T K2 Since the levels of the synchronous input terminals S_IN[i+1] at this time are high and low, the pattern determination signal S PTN [i+1] is generated. Therefore, the pattern decision signal S of “1” is generated. PTN [i+1] indicates that the clock signal CLK[i] input to the synchronous input terminal S_IN[i+1] has the pattern PTN2b.

[0209] As in the fifth embodiment, it is possible to forcibly perform switching control on all channels by using a clock signal CLK[i] having a pattern PTN2b. The matters described in the fifth embodiment regarding the forced output conditions are also applied to the sixth embodiment.

[0210] The sixth embodiment can be implemented in combination with the second embodiment, and the combination will be described below. In the sixth embodiment, the second rule described in the second embodiment is adopted, and the set edge is a fall edge. That is, the controller 28 of the device 10[i+1] turns on the transistor MH and turns off the transistor ML at the timing of the fall edge of the clock signal CLK[i]. Therefore, when applying the description of the fifth embodiment to the sixth embodiment, it is preferable to read the description of the "rise edge" of the fifth embodiment as "fall edge" in the sixth embodiment. In addition, in the sixth embodiment combined with the second embodiment, it is preferable to use the synchronous output circuit 40C of FIG. 26 as the synchronous output circuit 40 of each device 10.

[0211] When switching control is executed in the device 10[1] in the FORCE_ON state, the clock management circuit 80[1] controls the synchronous output circuit 40[1] to output the clock signal CLK[1] having the pattern PTN2b from the synchronous output terminal S_OUT[1] in the synchronous output circuit 40[1] regardless of whether the clock output condition (the clock output condition in step S14 in FIG. 24) is satisfied. The clock signal CLK[1] having the pattern PTN2b is reference clock signal CLK of the device 10[1]. REF (i.e., it is generated based on the clock signal CLK[0]).

[0212] When the clock signal CLK[1] having the pattern PTN2b is input to the synchronous input terminal S_IN[2], the clock signal CLK[1] having the pattern PTN2b is input to the reference clock signal CLK of the device 10[2]. REF The signal PTN2b is input to the controller 28 of the device 10[2] as a signal PTN2b. Therefore, the output stage MM[2] is switched in synchronization with the clock signal CLK[1]. That is, the falling edge of the clock signal CLK[1] having the pattern PTN2b is used as a trigger to turn on the transistor MH of the output stage MM[2] and turn off the transistor ML.

[0213] In addition, when the clock signal CLK[1] having the pattern PTN2b is input to the synchronous input terminal S_IN[2], the pattern determination signal S PTN [2] has a value of “1”. PTN When [2]=1", the clock management circuit 80[2] controls the synchronous output circuit 40[2] to output a clock signal CLK[2] having the pattern PTN2b from the synchronous output terminal S_OUT[2] in the synchronous output circuit 40[2] regardless of whether the clock output condition (the clock output condition in step S24 in FIG. 25) is satisfied. The clock signal CLK[2] having the pattern PTN2b is used as the reference clock signal CLK of the device 10[2]. REF (i.e., the input clock signal CLK[1] to device 10[2]).

[0214] The operation of another device 10 (e.g., device 10[3]) operating in the second mode is similar to that of device 10[2]. That is, for example, when a clock signal CLK[2] having a pattern PTN2b is input to the synchronous input terminal S_IN[3], the clock signal CLK[2] having the pattern PTN2b becomes the reference clock signal CLK of device 10[3]. REF The signal PTN2b is input to the controller 28 of the device 10[3] as a signal PTN2b. Therefore, the output stage MM[3] is switched in synchronization with the clock signal CLK[2]. That is, the falling edge of the clock signal CLK[2] having the pattern PTN2b triggers the transistor MH of the output stage MM[3] to be turned on and the transistor ML to be turned off.

[0215] In addition, when the clock signal CLK[2] having the pattern PTN2b is input to the synchronous input terminal S_IN[3], the pattern determination signal S PTN [3] has a value of “1”. PTNWhen [3]=1", the clock management circuit 80[3] controls the synchronous output circuit 40[3] to output the clock signal CLK[3] having the pattern PTN2b from the synchronous output terminal S_OUT[3] in the synchronous output circuit 40[3] regardless of whether the clock output condition (the clock output condition in step S24 in FIG. 25) is satisfied. The clock signal CLK[3] having the pattern PTN2b is used as the reference clock signal CLK of the device 10[3]. REF (i.e., the input clock signal CLK[2] to device 10[3]).

[0216] The same is true for the devices 10[4] to 10[n]. Therefore, in the FORCE_ON state, switching control is performed in the devices 10 of all channels, regardless of whether the clock output conditions are met.

[0217] In addition, the operation of the device 10[1] when the forced output condition is not satisfied is the same as that shown in FIG. 24, and the operation of each of the devices 10[2] to 10[n] when the forced output condition is not satisfied is the same as that shown in FIG. 25. However, the clock signal CLK[i] that can be output from the device 10[i] when the forced output condition is not satisfied has the pattern PTN1b as in the second embodiment. Therefore, when the forced output condition is not satisfied, if the clock signal CLK[1] is not supplied to the synchronous input terminal S_IN[2], the synchronous output circuit 40[2] of the device 10[2] does not output any clock signal (the synchronous output terminal S_OUT[2] is kept in a Hi-Z state). When the forced output condition is not satisfied, when the clock signal CLK[1] of the pattern PTN1b is supplied to the synchronous input terminal S_IN[2], the device 10[2] executes switching control synchronized with the clock signal CLK[1], and if the clock output condition is satisfied in the device 10[2], the clock signal CLK[2] of the pattern PTN1b based on the clock signal CLK[1] (the input clock signal CLK[1] to the device 10[2]) is output from the synchronous output terminal S_OUT[2] by the synchronous output circuit 40[2]. The same applies to other devices 10 (e.g., device 10[3]) operating in the second mode.

[0218] In a device 10[1] operating in a first mode, when the forced output condition is not satisfied, after the synchronous output circuit 40[1] starts outputting a clock signal CLK[1] of pattern PTN1b, the output of the clock signal CLK[1] of pattern PTN1b is stopped in response to the satisfaction of the clock stop condition (the clock stop condition of step S16a in FIG. 24).

[0219] When the forced output condition is not satisfied, the clock signal CLK[1] of pattern PTN1b may be supplied to the synchronous input terminal S_IN[2]. In the device 10[2] operating in the second mode, when the clock signal CLK[1] of pattern PTN1b is supplied to the synchronous input terminal S_IN[2], after the synchronous output circuit 40[2] starts outputting the clock signal CLK[2] of pattern PTN1b, in response to the satisfaction of the clock stop condition (the clock stop condition of step S26a in FIG. 25), the output of the clock signal CLK[2] of pattern PTN1b is stopped. The same applies to other devices 10 (e.g., device 10[3]) operating in the second mode.

[0220] In the sixth embodiment, the waveforms of the clock signals CLK[0] to CLK[3] in the 4-channel driving state under the FORCE_ON state are shown as the clock signal CLK[0] for convenience. EX6 ~CLK[3] EX6 For the sake of convenience, the waveforms of the clock signals CLK[0] to CLK[3] in the 4-channel driving state under the FORCE_ON state according to the fifth embodiment are referred to as the clock signal CLK[0]. EX5 ~CLK[3] EX5 The clock signal CLK[0] EX5 ~CLK[3] EX5 are the clock signals CLK[0] to CLK[3] shown in Fig. 28. In the sixth embodiment, the set edge corresponds to the fall edge, and for an integer i between 0 and 3, the clock signal CLK[i] EX6 is the clock signal CLK[i] EX5 It is sufficient if the inverted signal is used.

[0221] <<Seventh Example>> A seventh embodiment will now be described.

[0222] In the switching power supply device 1 of Figures 1 and 3, the device 10[1] operates in the first mode, and the devices 10[2] to 10[n] operate in the second mode. For this reason, the operation of the device 10[1] has been described as the operation of the device 10 in the first mode, and the operation of the devices 10[2] to 10[n] has been described as the operation of the device 10 in the second mode. However, depending on how the individual devices 10 are incorporated into the switching power supply device 1, they may operate in the first mode or in the second mode. In other words, depending on the operating mode, each of the devices 10 can realize the operation of the device 10[1], and can also realize the operation of any of the devices 10[2] to 10[n].

[0223] Therefore, in one arbitrary device 10[i] of interest (hereinafter referred to as the target device 10[i]), the switching control circuit 20[i] When the target device 10[i] operates in the first mode, the internal clock signal CLK A Based on the input clock signal CLK B A reference clock signal CLK based on REF The switching of the output stage MM[i] is controlled in synchronization with When the target device 10[i] operates in the second mode, the input clock signal CLK is B When is not supplied, the switching control of the output stage MM[i] is stopped; When the target device 10[i] operates in the second mode, the input clock signal CLK is B If provided, the input clock signal CLK B A reference clock signal CLK based on REF The switching of the output stage MM[i] is controlled in synchronization with this.

[0224] For example, in the target device 10[i] according to the fifth or sixth embodiment, the synchronous output circuit 40[i] When the target device 10[i] operates in the first mode and the forced output condition is not satisfied, the reference clock signal CLK is generated in response to the satisfaction of the clock output condition during the execution period of the switching control to the output stage MM[i]. REF from a synchronous output terminal S_OUT[i], When the target device 10[i] operates in the first mode and the forced output condition is satisfied, the reference clock signal CLK is generated during the execution period of the switching control to the output stage MM[i] regardless of whether the clock output condition is satisfied. REF from the synchronous output terminal S_OUT[i], When the target device 10[i] operates in the second mode, the input clock signal CLK is B When (CLK[i]) is not supplied, neither the first pattern output clock signal nor the second pattern output clock signal is output from the synchronous output terminal S_OUT[i], When the target device 10[i] operates in the second mode, and the input clock signal CLK of the first pattern (PTN1a or PTN1b) is input to the synchronous input terminal S_IN[i], B When (CLK[i-1]) is supplied, the input clock signal CLK is generated in response to the establishment of the clock output condition during the execution period of the switching control to the output stage MM[i]. B An output clock signal CLK[i] of a first pattern (PTN1a or PTN1b) based on (CLK[i-1]) is output from a synchronous output terminal S_OUT[i]; When the target device 10[i] operates in the second mode, the input clock signal CLK of the second pattern (PTN2a or PTN2b) is applied to the synchronous input terminal S_IN[i]. B When (CLK[i-1]) is supplied, the input clock signal CLK is supplied regardless of whether the clock output condition is satisfied during the execution period of switching control to the output stage MM[i]. BThe output clock signal CLK[i] of the second pattern (PTN2a or PTN2b) based on the above is output from the synchronous output terminal S_OUT[i]. Various other actions are contemplated similarly.

[0225] In the above description, it is assumed that an electronic component including only one device 10 is configured in one housing, but an electronic component including two or more devices 10 may be configured in one housing. That is, for example, when "n=4", a first electronic component (first semiconductor device) formed by accommodating devices 10[1] and 10[2] in a common first housing, and a second electronic component (second semiconductor device) formed by accommodating devices 10[3] and 10[4] in another common second housing may be provided in the switching control device 1. Even in this case, if the method of each of the above-mentioned embodiments is used, information other than a clock signal for synchronization can be transmitted between the first and second electronic components using the terminals S_OUT[2] and S_IN[3].

[0226] When switching control is performed in two or more devices 10 in the switching power supply device 1, it is not necessary to shift the phases of the switching control in the two or more devices 10 from each other. Therefore, for example, the phases of the clock signals CLK[0] to CLK[3] in the above-mentioned four-channel driving state may be the same. That is, for example, when the set edge is a rising edge, in the four-channel driving state, the rising edges of the clock signals CLK[0] to CLK[3] may occur simultaneously. Similarly, for example, when the set edge is a falling edge, in the four-channel driving state, the falling edges of the clock signals CLK[0] to CLK[3] may occur simultaneously.

[0227] Alternatively, for example, when the set edge is a rising edge, in the 4-channel driving state, the rising edges of the clock signals CLK[0] and CLK[2] may be generated simultaneously, and the rising edges of the clock signals CLK[1] and CLK[3] may be generated simultaneously, and the timing of the rising edge of the clock signal CLK[0] may be made different from the timing of the rising edge of the clock signal CLK[1]. Similarly, for example, when the set edge is a falling edge, in the 4-channel driving state, the falling edges of the clock signals CLK[0] and CLK[2] may be generated simultaneously, and the falling edges of the clock signals CLK[1] and CLK[3] may be generated simultaneously, and the timing of the falling edge of the clock signal CLK[0] may be made different from the timing of the falling edge of the clock signal CLK[1].

[0228] The DC / DC converter of each channel constituting the above-mentioned switching switching power supply device 1 is a step-down DC / DC converter, but the DC / DC converter of each channel may be a step-up or step-up / step-down DC / DC converter.

[0229] For any signal or voltage, the relationship between the high level and the low level thereof may be reversed to that described above without prejudice to the spirit of the above.

[0230] The channel types of FETs (field effect transistors) shown in each embodiment are merely examples, and the channel type of any FET may be changed between P-channel and N-channel without departing from the spirit of the above.

[0231] Any of the transistors described above may be any type of transistor, provided that no disadvantage occurs. For example, any of the transistors described above as MOSFETs may be replaced with junction FETs, IGBTs (Insulated Gate Bipolar Transistors), or bipolar transistors, provided that no disadvantage occurs. Any of the transistors has a first electrode, a second electrode, and a control electrode. In a FET, one of the first and second electrodes is a drain, the other is a source, and the control electrode is a gate. In an IGBT, one of the first and second electrodes is a collector, the other is an emitter, and the control electrode is a gate. In a bipolar transistor that does not belong to an IGBT, one of the first and second electrodes is a collector, the other is an emitter, and the control electrode is a base.

[0232] The embodiments of the present disclosure can be modified in various ways as appropriate within the scope of the technical ideas set forth in the claims. The above embodiments are merely examples of the embodiments of the present disclosure, and the meanings of the terms of the present disclosure or each component are not limited to those described in the above embodiments. The specific numerical values ​​shown in the above description are merely examples, and can be changed to various numerical values ​​as a matter of course.

[0233] <<Additional Notes>> Regarding the present disclosure, specific configuration examples of which have been shown in the above-mentioned embodiments, additional notes will be provided.

[0234] A power supply control device according to one aspect of the present disclosure is a device for controlling an input voltage (V IN ) to output voltage (V OUT A power supply control device (10) provided in a switching power supply device (1) configured to generate a reference clock signal (CLK), the power supply control device (10) having a synchronous input terminal (S_IN), a synchronous output terminal (S_OUT), an output stage (MM) for power converting the input voltage to the output voltage, and REFa switching control circuit (20) configured to perform switching control of the output stage in synchronization with a first output state (a low level output state) to convert the input voltage into the output voltage; a synchronous output circuit (40) configured to set a state of the synchronous output terminal to one of a plurality of output states including a first, second and third output state; and a synchronous input circuit (50) configured to set a state of the synchronous input terminal to one of a plurality of input states including a first and a second input state, wherein the synchronous output circuit outputs a signal of a first level (low level) from the synchronous output terminal in the first output state (low level output state) and In the third output state (Hi-Z state), the synchronous input circuit outputs a signal of a second level (high level) higher than the first level from the synchronous output terminal, and in the third output state (Hi-Z state), the synchronous input circuit has its own output impedance higher than those in the first output state and the second output state, and the synchronous input circuit is capable of pulling down the synchronous input terminal to the first level or pulling up the synchronous input terminal to the second level via a resistor (54), and is configured (first configuration) to pull down the synchronous input terminal in the first input state (pull-down state) and pull up the synchronous input terminal in the second input state (pull-up state).

[0235] According to this configuration, the synchronization output terminal of the first power supply control device and the synchronization input terminal of the second power supply control device are connected, and a synchronization clock signal can be supplied to the synchronization input terminal of the second power supply control device by switching the state of the synchronization output terminal of the first power supply control device. At this time, the synchronization input circuit of the second power supply control device selectively pulls down or pulls up the synchronization input terminal, so that when the synchronization output terminal of the first power supply control device is in the third output state, information can be transmitted from the second power supply control device to the first power supply control device. In other words, without providing a dedicated terminal for information transmission, information can be transmitted from the second power supply control device to the first power supply control device using the synchronization terminals (synchronization output terminal and synchronization input terminal). Using this information, it becomes possible to operate the switching power supply device appropriately.

[0236] The power supply control device according to the first configuration further includes a mode setting circuit (30) configured to set the operation mode of the power supply control device to a first mode or a second mode based on given mode setting information, and the switching control circuit is configured to, in the first mode, set an internal clock signal (CLK A ) or an input clock signal (CLK B ), and when the input clock signal is not supplied to the synchronization input terminal in the second mode, the switching control is stopped, and when the input clock signal is supplied to the synchronization input terminal in the second mode, the switching control is performed in synchronization with the reference clock signal based on the input clock signal (second configuration).

[0237] When multiple power control devices are connected in series, the first-stage power control device can be operated in a first mode and the other power control devices can be operated in a second mode. At this time, information can be transmitted from the second-stage power control device to the first-stage power control device by using the synchronization terminals (synchronization output terminal and synchronization input terminal).

[0238] In the power supply control device of the second configuration, the synchronous output circuit outputs an output clock signal based on the reference clock signal from the synchronous output terminal in response to the satisfaction of a predetermined clock output condition (for example, Y of S14 in FIG. 17, Y of S24 in FIG. 18) during the execution period of the switching control in the first mode or the second mode, and the synchronous output circuit may be configured (third configuration) to include, in each period of the output clock signal during the output period of the output clock signal (see FIG. 12 or FIG. 21), a first period during which the state of the synchronous output terminal is set to the first output state, a second period during which the state of the synchronous output terminal is set to the second output state, and a third period during which the state of the synchronous output terminal is set to the third output state.

[0239] In the power supply control device of the third configuration, the synchronous input circuit may be configured (fourth configuration) to set the state of the synchronous input terminal to one of the first and second input states (pull-down state / pull-up state) during an output period of the output clock signal, and to set the state of the synchronous input terminal to the other of the first and second input states (pull-up state / pull-down state) during a non-output period of the output clock signal.

[0240] In the power supply control device according to the fourth configuration, a level detection circuit (60) may be further provided connected to the synchronous output terminal, and the level detection circuit may be configured (fifth configuration) to detect whether the voltage of the synchronous output terminal in the third period belongs to the first level or the second level when the output clock signal is output by the synchronous output circuit.

[0241] Based on the detection result of the level detection circuit, information can be received from the power supply control device at the subsequent stage.

[0242] In the power supply control device of the fifth configuration, the synchronous input circuit sets the state of the synchronous input terminal to the first input state (pull-down state) during the output period of the output clock signal, and sets the state of the synchronous input terminal to the second input state (pull-up state) during the non-output period of the output clock signal, and the synchronous output circuit stops the output of the output clock signal in response to the establishment of a predetermined clock stop condition (for example, Y at S16 in Figure 17 or Y at S26 in Figure 18) after starting to output the output clock signal, and the clock stop condition may be a configuration (sixth configuration) that includes a condition in which the voltage of the synchronous output terminal during the third period is detected by the level detection circuit to belong to the second level (high level).

[0243] This makes it possible to control the stopping of the output clock signal to the power supply control device in the subsequent stage, with the prerequisite that the power supply control device in the subsequent stage has stopped outputting the output clock signal to the power supply control device in the further subsequent stage.

[0244] In the power supply control device of the fifth configuration, the synchronous input circuit sets the state of the synchronous input terminal to the second input state (pull-up state) during the output period of the output clock signal, and sets the state of the synchronous input terminal to the first input state (pull-down state) during the non-output period of the output clock signal, and the synchronous output circuit stops output of the output clock signal in response to the establishment of a predetermined clock stop condition (for example, Y at S16 in FIG. 17 or Y at S26 in FIG. 18) after starting to output the output clock signal, and the clock stop condition may be a configuration (seventh configuration) that includes a condition in which the voltage of the synchronous output terminal during the third period is detected by the level detection circuit to belong to the first level (high level).

[0245] This makes it possible to control the stopping of the output clock signal to the power supply control device in the subsequent stage, with the prerequisite that the power supply control device in the subsequent stage has stopped outputting the output clock signal to the power supply control device in the further subsequent stage.

[0246] In the power supply control device of any of the first to seventh configurations above, the synchronous output circuit (40C in FIG. 26 or 40B in FIG. 20) may be configured (8th configuration) to output a signal of the first level with an output impedance higher than that in the first output state in the third output state, or to output a signal of the second level with an output impedance higher than that in the second output state.

[0247] This makes it possible to prevent the potential of the synchronous output terminal from becoming unstable in the third output state.

[0248] In the power supply control device according to the second configuration (see the fifth or sixth embodiment), the synchronous output circuit outputs or does not output an output clock signal from the synchronous output terminal, and when a predetermined forced output condition is not satisfied in the first mode, the synchronous output circuit outputs an output clock signal of a first pattern (PTN1a or PTN1b) based on the reference clock signal from the synchronous output terminal in response to satisfaction of a predetermined clock output condition during the execution period of the switching control, and when the forced output condition is satisfied in the first mode, outputs an output clock signal of a second pattern (PTN2a or PTN2b) based on the reference clock signal from the synchronous output terminal regardless of whether the clock output condition is satisfied during the execution period of the switching control, and when the input clock signal is not supplied to the synchronous input terminal in the second mode, A configuration (ninth configuration) may be adopted in which neither the output clock signal of the first pattern nor the output clock signal of the second pattern is output from the synchronous output terminal, and when the input clock signal is supplied to the synchronous input terminal in the second mode and the input clock signal has the first pattern, the output clock signal of the first pattern based on the input clock signal is output from the synchronous output terminal in response to the clock output condition being satisfied during the execution period of the switching control, and when the input clock signal is supplied to the synchronous input terminal in the second mode and the input clock signal has the second pattern, the output clock signal of the second pattern based on the input clock signal is output from the synchronous output terminal regardless of whether the clock output condition is satisfied during the execution period of the switching control.

[0249] When a plurality of power supply control devices are connected in series, by using the output clock signal of the second pattern, it is possible to forcibly perform switching control in all the power supply control devices.

[0250] In the power supply control device of the ninth configuration, the synchronous output circuit may be configured (tenth configuration) to alternately set the state of the synchronous output terminal to the first output state and the second output state during the output period of the output clock signal of the second pattern (see FIG. 27 or FIG. 29), including a first period during which the state of the synchronous output terminal is set to the first output state, a second period during which the state of the synchronous output terminal is set to the second output state, and a third period during which the state of the synchronous output terminal is set to the third output state, during the output period of the output clock signal of the first pattern (see FIG. 12 or FIG. 21).

[0251] In the power supply control device of the tenth configuration (see FIG. 27 or FIG. 29), the synchronous output circuit may mix a period in which the output clock signal has a first waveform (WV1 / WV3) with a period in which the output clock signal has a second waveform (WV2 / WV4) during the output period of the output clock signal of the second pattern, and the power supply control device may be provided with a pattern determination circuit (70) connected to the synchronous input terminal, and the pattern determination circuit may be configured to determine whether the input clock signal has the second pattern by determining whether the input clock signal has a waveform that switches between the first waveform and the second waveform based on the voltage of the synchronous input terminal (eleventh configuration).

[0252] The power supply control device according to the eleventh configuration may further include a level detection circuit (60) connected to the synchronous output terminal, and the level detection circuit may be configured to detect whether the voltage of the synchronous output terminal in the third period belongs to the first level or the second level when the output clock signal of the first pattern is output by the synchronous output circuit (twelfth configuration).

[0253] When the first pattern is used, information can be received from a downstream power supply control device based on the detection result of the level detection circuit.

[0254] In the power supply control device according to the twelfth configuration, the synchronous input circuit sets the state of the synchronous input terminal to the first input state (pull-down state) during a period in which the synchronous output circuit outputs the output clock signal of the first pattern, and sets the state of the synchronous input terminal to the second input state (pull-up state) during a period in which the output of the output clock signal of the first pattern by the synchronous output circuit is stopped, and the synchronous output circuit stops outputting the output clock signal of the first pattern in response to the establishment of a predetermined clock stop condition (for example, Y at S16 in FIG. 17 or Y at S26 in FIG. 18) after starting to output the output clock signal of the first pattern when the forced output condition is not established in the first mode, or after starting to output the output clock signal of the first pattern when the input clock signal of the first pattern is supplied to the synchronous input terminal in the second mode, and the clock stop condition may be a configuration (thirteenth configuration) that includes a condition in which the voltage of the synchronous output terminal in the third period is detected as belonging to the second level (high level) by the level detection circuit.

[0255] As a result, when using the first pattern, it is possible to control the stopping of the output clock signal to the power supply control device in the subsequent stage, with the prerequisite that the power supply control device in the subsequent stage has stopped outputting the output clock signal to the power supply control device in the further subsequent stage.

[0256] In the power supply control device according to the twelfth configuration, the synchronous input circuit sets the state of the synchronous input terminal to the second input state (pull-up state) during a period in which the synchronous output circuit outputs the output clock signal of the first pattern, and sets the state of the synchronous input terminal to the first input state (pull-down state) during a period in which the output of the output clock signal of the first pattern by the synchronous output circuit is stopped, and the synchronous output circuit stops outputting the output clock signal of the first pattern in response to the establishment of a predetermined clock stop condition (for example, Y at S16 in FIG. 17 or Y at S26 in FIG. 18) after starting to output the output clock signal of the first pattern when the forced output condition is not established in the first mode, or after starting to output the output clock signal of the first pattern when the input clock signal of the first pattern is supplied to the synchronous input terminal in the second mode, and the clock stop condition may be a configuration (fourteenth configuration) including a condition in which the voltage of the synchronous output terminal in the third period is detected as belonging to the first level (low level) by the level detection circuit.

[0257] As a result, when using the first pattern, it is possible to control the stopping of the output clock signal to the power supply control device in the subsequent stage, with the prerequisite that the power supply control device in the subsequent stage has stopped outputting the output clock signal to the power supply control device in the further subsequent stage.

[0258] In a power supply control device according to any of the ninth to fourteenth configurations above, the synchronous output circuit (40C in FIG. 26 or 40B in FIG. 20) may be configured (fifteenth configuration) to output, in the third output state, a signal of the first level with an output impedance higher than that in the first output state, or to output a signal of the second level with an output impedance higher than that in the second output state, when outputting an output clock signal of the first pattern.

[0259] This makes it possible to prevent the potential of the synchronous output terminal from becoming unstable in the third output state when the first pattern is used.

[0260] In a power supply control device according to any one of the first to fifteenth configurations above, the output stage may have an output element (MH) constituted by a switching element, and a rectifying element (ML) connected to the output element, a coil (L) is connected to a connection node between the output element and the rectifying element, and the output voltage may be generated based on a current (IL) flowing through the coil by switching the output element between on and off in switching control of the output stage (sixteenth configuration).

[0261] In the power supply control device according to any of the above first to sixteenth configurations, the synchronous output terminal of the power supply control device may be configured to be connected to a synchronous input terminal of another power supply control device provided in the switching power supply device (seventeenth configuration).

[0262] In the power supply control device according to any of the above first to sixteenth configurations, the synchronization input terminal of the power supply control device may be configured to be connected to a synchronization output terminal of another power supply control device provided in the switching power supply device (an eighteenth configuration).

[0263] A switching power supply device according to one aspect of the present disclosure is configured to: IN ) to output voltage (V OUTa synchronous output terminal (S_OUT[i]) of the ith power supply control device is connected to a synchronous input terminal (S_IN[i+1]) of the (i+1)th power supply control device, and i represents a natural number equal to or less than (n-1). Of the first to nth power supply control devices, the first power supply control device (10[1]) operates in the first mode, and the other power supply control devices (10[2] to 10[n]) operate in the second mode. The output stages in the first to nth power supply control devices are first to nth output stages, and a current is supplied from the application terminal of the input voltage to the application terminal of the output voltage through one or more output stages in which the switching control is performed among the first to nth output stages (a nineteenth configuration).

[0264] According to this configuration, for example, by switching the state of the synchronous output terminal of the first power supply control device, a clock signal for synchronization can be supplied to the synchronous input terminal of the second power supply control device. At this time, the synchronous input circuit of the second power supply control device selectively pulls down or pulls up the synchronous input terminal, so that when the synchronous output terminal of the first power supply control device is in the third output state, information can be transmitted from the second power supply control device to the first power supply control device. In other words, without providing a dedicated terminal for information transmission, information can be transmitted from the second power supply control device to the first power supply control device using the terminals for synchronization (synchronous output terminal and synchronous input terminal). Using this information, it becomes possible to operate the switching power supply device appropriately. [Explanation of symbols]

[0265] 1 Switching power supply 10, 10[i] Power supply control device L, L[i] coil C OUT Output Capacitor N.D. OUT Output Node R1, R2 Feedback resistors LD load I LDload current IL, IL[i] Coil current V OUT Output Voltage V FB Feedback Voltage IN Input terminal SW Switch terminal GND Ground terminal FB Feedback pin EOUT Error output terminal S_IN, S_IN[i] Synchronous input terminal S S_OUT, S_OUT[i] Synchronous output terminal MM, MM[i] output stage MH, ML transistors 20, 20[i] Switching control circuit 21 Error Amplifier 22 Lamp circuit 23 Sense Circuit 24 Adder 25 PWM Comparator 26 Switch Circuit 27 Clock supply circuit 28 Controller 28a Oscillator circuit 30, 30[i] Mode setting circuit 40, 40[i], 40A, 40B, 40C Synchronous output circuit 41, 42 Transistors 43 Output setting circuit 44 Pull-up resistor 45 Pull-down resistor 50, 50[i], 50A Synchronous Input Circuit 51, 52 Transistors 53 Input setting circuit 54 Resistance 60, 60[i] Level detection circuit 70, 70[i] Pattern judgment circuit 80, 80[i] Clock management circuit ERR, ERR' error signal RAMP Ramp signal ISNS, ISNS[i] Sense signal SLP Slope signal RST signal CLK A Internal Clock Signal CLK B Input Clock Signal CLK REF Reference Clock Signal CLK[i] Clock signal GH, GL gate signals S DET , S DET [i] Level detection signal S PTN , S PTN [i] Pattern judgement signal PTN1a, PTN1b, PTN2a, PTN2b patterns

Claims

1. A power supply control device provided in a switching power supply device configured to generate an output voltage from an input voltage, A sync input terminal; A synchronous output terminal; an output stage for power converting the input voltage to the output voltage; a switching control circuit configured to perform power conversion of the input voltage to the output voltage by controlling switching of the output stage in synchronization with a reference clock signal; a synchronous output circuit configured to set a state of the synchronous output terminal to one of a plurality of output states including a first output state, a second output state, and a third output state; a synchronous input circuit configured to set a state of the synchronous input terminal to one of a plurality of input states including a first input state and a second input state; the synchronous output circuit outputs a signal of a first level from the synchronous output terminal in the first output state, outputs a signal of a second level higher than the first level from the synchronous output terminal in the second output state, and increases its own output impedance in the third output state to be higher than those in the first output state and the second output state; The synchronous input circuit is capable of pulling down the synchronous input terminal to the first level or pulling up the synchronous input terminal to the second level via a resistor, and pulls down the synchronous input terminal in the first input state and pulls up the synchronous input terminal in the second input state. , power control device.

2. a mode setting circuit configured to set an operation mode of the power supply control device to a first mode or a second mode based on given mode setting information; The switching control circuit includes: In the first mode, the switching control is performed in synchronization with the reference clock signal based on an internal clock signal or based on an input clock signal supplied to the synchronization input terminal from outside the power supply control device; When the input clock signal is not supplied to the synchronization input terminal in the second mode, the switching control is stopped; When the input clock signal is supplied to the synchronization input terminal in the second mode, the switching control is performed in synchronization with the reference clock signal based on the input clock signal. The power supply control device according to claim 1 .

3. the synchronous output circuit outputs an output clock signal based on the reference clock signal from the synchronous output terminal in response to establishment of a predetermined clock output condition during an execution period of the switching control in the first mode or the second mode; In an output period of the output clock signal, the synchronous output circuit includes, in each cycle of the output clock signal, a first period during which the state of the synchronous output terminal is set to the first output state, a second period during which the state of the synchronous output terminal is set to the second output state, and a third period during which the state of the synchronous output terminal is set to the third output state. The power supply control device according to claim 2 .

4. The synchronous input circuit sets the state of the synchronous input terminal to one of the first and second input states during an output period of the output clock signal, and sets the state of the synchronous input terminal to the other of the first and second input states during a non-output period of the output clock signal. The power supply control device according to claim 3 .

5. A level detection circuit connected to the synchronous output terminal is further provided. The level detection circuit detects whether the voltage of the synchronous output terminal in the third period belongs to the first level or the second level when the output clock signal is output by the synchronous output circuit. The power supply control device according to claim 4 .

6. the synchronous input circuit sets a state of the synchronous input terminal to the first input state during an output period of the output clock signal, and sets a state of the synchronous input terminal to the second input state during a non-output period of the output clock signal; the synchronous output circuit stops output of the output clock signal in response to establishment of a predetermined clock stop condition after starting output of the output clock signal; The clock stop condition includes a condition that the voltage of the synchronous output terminal during the third period is detected by the level detection circuit as belonging to the second level. The power supply control device according to claim 5 .

7. the synchronous input circuit sets the state of the synchronous input terminal to the second input state during an output period of the output clock signal, and sets the state of the synchronous input terminal to the first input state during a non-output period of the output clock signal; the synchronous output circuit stops output of the output clock signal in response to establishment of a predetermined clock stop condition after starting output of the output clock signal; The clock stop condition includes a condition that the voltage of the synchronous output terminal during the third period is detected by the level detection circuit as belonging to the first level. The power supply control device according to claim 5 .

8. In the third output state, the synchronous output circuit outputs a signal of the first level with the output impedance higher than that in the first output state, or outputs a signal of the second level with the output impedance higher than that in the second output state. The power supply control device according to claim 1 .

9. the synchronous output circuit outputs or does not output an output clock signal from the synchronous output terminal; The synchronous output circuit includes: when a predetermined forced output condition is not satisfied in the first mode, an output clock signal of a first pattern based on the reference clock signal is output from the synchronous output terminal in response to satisfaction of a predetermined clock output condition during an execution period of the switching control; When the forced output condition is satisfied in the first mode, an output clock signal of a second pattern based on the reference clock signal is output from the synchronous output terminal during an execution period of the switching control, regardless of whether the clock output condition is satisfied; When the input clock signal is not supplied to the synchronous input terminal in the second mode, neither the output clock signal of the first pattern nor the output clock signal of the second pattern is output from the synchronous output terminal; when the input clock signal is supplied to the synchronization input terminal in the second mode and the input clock signal has the first pattern, an output clock signal of the first pattern based on the input clock signal is output from the synchronization output terminal in response to establishment of the clock output condition during an execution period of the switching control; When the input clock signal is supplied to the synchronization input terminal in the second mode and the input clock signal has the second pattern, an output clock signal of the second pattern based on the input clock signal is output from the synchronization output terminal during an execution period of the switching control, regardless of whether the clock output condition is satisfied. The power supply control device according to claim 2 .

10. The synchronous output circuit includes: during an output period of the output clock signal of the first pattern, each cycle of the output clock signal of the first pattern includes a first period during which the state of the synchronous output terminal is set to the first output state, a second period during which the state of the synchronous output terminal is set to the second output state, and a third period during which the state of the synchronous output terminal is set to the third output state, During an output period of the output clock signal of the second pattern, the state of the synchronous output terminal is alternately set to the first output state and the second output state. The power supply control device according to claim 9 .

11. the synchronous output circuit mixes a period in which the output clock signal has a first waveform and a period in which the output clock signal has a second waveform during an output period of the output clock signal of the second pattern; The power supply control device is provided with a pattern determination circuit connected to the synchronization input terminal, The pattern determination circuit determines whether the input clock signal has the second pattern by determining whether the input clock signal has a waveform that switches between the first waveform and the second waveform based on a voltage of the synchronization input terminal. The power supply control device according to claim 10.

12. A level detection circuit connected to the synchronous output terminal is further provided. The level detection circuit detects whether the voltage of the synchronous output terminal in the third period belongs to the first level or the second level when the output clock signal of the first pattern is output by the synchronous output circuit. The power supply control device according to claim 11.

13. the synchronous input circuit sets a state of the synchronous input terminal to the first input state during a period in which the synchronous output circuit outputs the output clock signal of the first pattern, and sets a state of the synchronous input terminal to the second input state during a period in which the output of the output clock signal of the first pattern by the synchronous output circuit is stopped; the synchronous output circuit starts outputting the output clock signal of the first pattern when the forced output condition is not satisfied in the first mode, or starts outputting the output clock signal of the first pattern when the input clock signal of the first pattern is supplied to the synchronous input terminal in the second mode, and stops outputting the output clock signal of the first pattern in response to satisfaction of a predetermined clock stop condition; The clock stop condition includes a condition that the voltage of the synchronous output terminal during the third period is detected by the level detection circuit as belonging to the second level. The power supply control device according to claim 12.

14. the synchronous input circuit sets a state of the synchronous input terminal to the second input state during a period in which the synchronous output circuit outputs the output clock signal of the first pattern, and sets a state of the synchronous input terminal to the first input state during a period in which the output of the output clock signal of the first pattern by the synchronous output circuit is stopped; the synchronous output circuit starts outputting the output clock signal of the first pattern when the forced output condition is not satisfied in the first mode, or starts outputting the output clock signal of the first pattern when the input clock signal of the first pattern is supplied to the synchronous input terminal in the second mode, and stops outputting the output clock signal of the first pattern in response to satisfaction of a predetermined clock stop condition; The clock stop condition includes a condition that the voltage of the synchronous output terminal during the third period is detected by the level detection circuit as belonging to the first level. The power supply control device according to claim 12.

15. When outputting the output clock signal of the first pattern, the synchronous output circuit outputs the signal of the first level with the output impedance higher than that of the first output state in the third output state, or outputs the signal of the second level with the output impedance higher than that of the second output state. The power supply control device according to claim 9 .

16. the output stage includes an output element configured with a switching element, and a rectifying element connected to the output element, A coil is connected to a connection node between the output element and the rectifying element, and the output voltage is generated based on a current flowing through the coil by switching the output element between on and off in switching control of the output stage. A power supply control device according to any one of claims 1 to 15.

17. The synchronous output terminal of the power supply control device is configured to be connected to a synchronous input terminal of another power supply control device provided in the switching power supply device. A power supply control device according to any one of claims 1 to 15.

18. The synchronous input terminal of the power supply control device is configured to be connected to a synchronous output terminal of another power supply control device provided in the switching power supply device. A power supply control device according to any one of claims 1 to 15.

19. 1. A switching power supply configured to generate an output voltage from an input voltage, comprising: The power supply control device includes first to nth power supply control devices, where n is an integer of 2 or more; Each power supply control device is a power supply control device according to any one of claims 2 to 7 and claims 9 to 15, The synchronous output terminal of the i-th power supply control device is connected to the synchronous input terminal of the (i+1)-th power supply control device, where i is a natural number equal to or smaller than (n-1); Among the first to n-th power supply control devices, the first power supply control device operates in the first mode, and the other power supply control devices operate in the second mode; the output stages in the first to nth power supply control devices are first to nth output stages, A current is supplied from the input voltage application terminal to the output voltage application terminal through one or more output stages in which the switching control is performed among the first to nth output stages. , switching power supply.

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