Semiconductor device

Abstract

To provide a semiconductor device whose surge current tolerance is improved.SOLUTION: A semiconductor device in an embodiment includes a transistor region and a diode region. The transistor region includes an n-type first silicon carbide region having a first part in contact with a first surface, a plurality of p-type second silicon carbide regions, an n-type third silicon carbide region, a plurality of p-type fourth silicon carbide regions connecting between the second silicon carbide regions, a first electrode, a second electrode, and a gate electrode. The diode region includes an n-type first silicon carbide region having a second part in contact with the first surface, p-type fifth silicon carbide regions, a plurality of p-type sixth silicon carbide regions connecting between the fifth silicon carbide regions, a first electrode, and a second electrode. In addition, a seventh silicon carbide region connecting the third silicon carbide region and the fifth silicon carbide region is included.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] FIELD An embodiment of the present invention relates to a semiconductor device. [Background technology]

[0002] Silicon carbide is one of the materials used in semiconductor devices. Compared to silicon, silicon carbide has excellent physical properties, such as a band gap about three times larger, a breakdown electric field strength about ten times larger, and a thermal conductivity about three times larger. By utilizing these characteristics, it is possible to realize, for example, MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) that have high breakdown voltage, low loss, and can operate at high temperatures.

[0003] A vertical MOSFET using silicon carbide has a pn junction diode as a built-in diode. For example, the MOSFET is used as a switching element connected to an inductive load. In this case, the built-in diode allows a return current to flow even when the MOSFET is off.

[0004] However, when a return current is passed using a body diode, stacking faults grow in the silicon carbide layer due to carrier recombination energy, which causes an increase in the on-resistance of the MOSFET. An increase in the on-resistance of the MOSFET leads to a decrease in the reliability of the MOSFET. For example, by providing a Schottky Barrier Diode (SBD) that operates in unipolar mode as a built-in diode in the MOSFET, it is possible to suppress the growth of stacking faults in the silicon carbide layer. Providing an SBD as a built-in diode in the MOSFET improves the reliability of the MOSFET.

[0005] There are cases where a large surge current flows through a MOSFET momentarily, exceeding the steady state. When a large surge current flows, a large surge voltage is applied, causing the MOSFET to heat up and destroy itself. The maximum allowable peak current value of the surge current allowed for a MOSFET (I FSMIt is desirable to improve the surge current capability of MOSFETs equipped with SBDs. [Prior art documents] [Patent documents]

[0006] [Patent Document 1] JP 2023-77119 A Summary of the Invention [Problem to be solved by the invention]

[0007] An object of the present invention is to provide a semiconductor device having improved surge current resistance. [Means for solving the problem]

[0008] A semiconductor device according to an embodiment includes a plurality of transistor regions and a plurality of diode regions arranged alternately in a first direction, the transistor region being a silicon carbide layer having a first surface and a second surface opposed to the first surface, the transistor region including an n-type first silicon carbide region in contact with the first surface, extending in a second direction perpendicular to the first direction, and having a plurality of first portions arranged in the first direction, and a plurality of p-type second silicon carbide regions provided between the first silicon carbide region and the first surface, extending in the second direction, and arranged in the first direction. a silicon carbide layer including: an n-type third silicon carbide region provided between the second silicon carbide region and the first surface; and a plurality of p-type fourth silicon carbide regions provided between the first silicon carbide region and the first surface, arranged in the second direction, and connecting two adjacent second silicon carbide regions; a first electrode in contact with the first portion, the second silicon carbide region, the third silicon carbide region, and the fourth silicon carbide region; a second electrode in contact with the second surface; and a second electrode facing the second silicon carbide region. a gate insulating layer provided between the gate electrodes and the second silicon carbide region, and the diode region includes an n-type first silicon carbide region having a plurality of second portions in contact with the first surface and extending in the second direction, a plurality of p-type fifth silicon carbide regions provided between the first silicon carbide region and the first surface, extending in the second direction and arranged in the first direction, and a gate insulating layer provided between the first silicon carbide region and the first surface, the n-type first silicon carbide region having a plurality of second portions in contact with the first surface and extending in the second direction, the silicon carbide layer including a plurality of p-type sixth silicon carbide regions arranged in a second direction and connecting two adjacent fifth silicon carbide regions, the first electrode in contact with the second portion, the fifth silicon carbide regions, and the sixth silicon carbide regions, and the second electrode, wherein the silicon carbide layer further includes a plurality of p-type seventh silicon carbide regions provided between the first silicon carbide regions and the first surface, arranged in the second direction, and connecting adjacent second silicon carbide regions and the fifth silicon carbide regions. [Brief description of the drawings]

[0009] [Figure 1]1 is a schematic top view of a semiconductor device according to a first embodiment. [Diagram 2] 1 is a schematic cross-sectional view of a portion of a semiconductor device according to a first embodiment. [Diagram 3] FIG. 2 is a schematic top view of a portion of the semiconductor device according to the first embodiment. [Figure 4] FIG. 2 is an enlarged schematic cross-sectional view of a portion of the semiconductor device according to the first embodiment. [Diagram 5] FIG. 2 is an enlarged schematic cross-sectional view of a portion of the semiconductor device according to the first embodiment. [Figure 6] 1 is a schematic cross-sectional view of a portion of a semiconductor device according to a first embodiment. [Figure 7] FIG. 2 is a schematic top view of a portion of the semiconductor device according to the first embodiment. [Figure 8] FIG. 2 is an enlarged schematic cross-sectional view of a portion of the semiconductor device according to the first embodiment. [Figure 9] FIG. 2 is an enlarged schematic cross-sectional view of a portion of the semiconductor device according to the first embodiment. [Figure 10] 1 is a schematic cross-sectional view of a portion of a semiconductor device according to a first embodiment. [Figure 11] FIG. 2 is a schematic top view of a portion of the semiconductor device according to the first embodiment. [Figure 12] FIG. 2 is an enlarged schematic cross-sectional view of a portion of the semiconductor device according to the first embodiment. [Figure 13] FIG. 2 is an enlarged schematic cross-sectional view of a portion of the semiconductor device according to the first embodiment. [Figure 14] 1 is a schematic top view of a semiconductor device according to a first embodiment. [Figure 15] FIG. 2 is a schematic top view of a semiconductor device according to a first comparative example. [Figure 16] FIG. 2 is a schematic cross-sectional view of a semiconductor device according to a first comparative example. [Figure 17] FIG. 2 is an equivalent circuit diagram of a semiconductor device according to a first comparative example. [Figure 18] 5A to 5C are explanatory diagrams illustrating the operation and effects of the semiconductor device according to the first embodiment. [Figure 19] 5A to 5C are explanatory diagrams illustrating the operation and effects of the semiconductor device according to the first embodiment. [Figure 20] 5A to 5C are explanatory diagrams illustrating the operation and effects of the semiconductor device according to the first embodiment. [Figure 21] FIG. 13 is a schematic top view of a semiconductor device according to a third comparative example. [Figure 22] 5A to 5C are explanatory diagrams illustrating the operation and effects of the semiconductor device according to the first embodiment. [Figure 23] 5A to 5C are explanatory diagrams illustrating the operation and effects of the semiconductor device according to the first embodiment. [Figure 24] FIG. 4 is a schematic cross-sectional view of a semiconductor device according to a first modified example of the first embodiment. [Diagram 25] FIG. 4 is a schematic cross-sectional view of a semiconductor device according to a first modified example of the first embodiment. [Figure 26] FIG. 6 is a schematic cross-sectional view of a portion of a semiconductor device according to a second embodiment. [Figure 27] FIG. 11 is a schematic top view of a portion of a semiconductor device according to a second embodiment. [Figure 28] FIG. 6 is a schematic cross-sectional view of a portion of a semiconductor device according to a second embodiment. [Figure 29] FIG. 11 is a schematic top view of a portion of a semiconductor device according to a second embodiment. [Diagram 30] FIG. 6 is a schematic cross-sectional view of a portion of a semiconductor device according to a second embodiment. [Diagram 31] FIG. 11 is a schematic top view of a portion of a semiconductor device according to a second embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. In the following description, the same reference numerals will be used to designate the same or similar components, and the description of components that have already been described may be omitted as appropriate.

[0011] In the following description, n + , n, n - And, p + , p, p - The notation indicates the relative level of impurity concentration in each conductivity type. + has a relatively higher n-type impurity concentration than n, - indicates that the n-type impurity concentration is relatively lower than that of n. + has a relatively higher p-type impurity concentration than p, - indicates that the p-type impurity concentration is relatively lower than that of p. + type, n- The types are simply n-type and p-type. + type, p - The type is sometimes simply referred to as p-type.

[0012] The impurity concentration can be measured, for example, by SIMS (Secondary Ion Mass Spectrometry). The relative level of the impurity concentration can also be determined from the level of the carrier concentration obtained, for example, by SCM (Scanning Capacitance Microscopy). The distance, such as the depth and thickness, of the impurity region can be obtained, for example, from an image obtained by SEM (Scanning Electron Microscope) or by SIMS.

[0013] In this specification, the impurity concentration of a semiconductor region means the maximum impurity concentration of the semiconductor region, unless otherwise specified.

[0014] (First embodiment) The semiconductor device of the first embodiment includes a plurality of transistor regions and a plurality of diode regions arranged alternately in a first direction. The transistor region is a silicon carbide layer having a first surface and a second surface facing the first surface, and includes an n-type first silicon carbide region in contact with the first surface, extending in a second direction perpendicular to the first direction and having a plurality of first portions arranged in the first direction, a plurality of p-type second silicon carbide regions provided between the first silicon carbide region and the first surface, extending in the second direction and arranged in the first direction, an n-type third silicon carbide region provided between the second silicon carbide region and the first surface, and a plurality of p-type third silicon carbide regions between the first silicon carbide region and the first surface. the first surface and a second surface of the first silicon carbide layer, the second surface and a third surface of the second silicon carbide region, and a plurality of p-type fourth silicon carbide regions connecting two adjacent second silicon carbide regions; a first electrode in contact with the first portion, the second silicon carbide regions, the third silicon carbide region, and the fourth silicon carbide region; a second electrode in contact with the second surface; a plurality of gate electrodes extending in the second direction opposite the second silicon carbide regions and arranged in the first direction; and a gate insulating layer provided between the gate electrodes and the second silicon carbide regions. The diode region includes a silicon carbide layer including an n-type first silicon carbide region having a plurality of second portions in contact with the first surface and extending in the second direction, a plurality of p-type fifth silicon carbide regions provided between the first silicon carbide region and the first surface, extending in the second direction and arranged in the first direction, and a plurality of p-type sixth silicon carbide regions provided between the first silicon carbide region and the first surface, arranged in the second direction, and connecting two adjacent fifth silicon carbide regions, a first electrode in contact with the second portions, the fifth silicon carbide region, and the sixth silicon carbide region, and a second electrode. The silicon carbide layer further includes a plurality of p-type seventh silicon carbide regions provided between the first silicon carbide region and the first surface, arranged in the second direction, and connecting adjacent second silicon carbide regions and the fifth silicon carbide region.

[0015] The semiconductor device of the first embodiment is a planar gate vertical MOSFET 100 using silicon carbide. The MOSFET 100 of the first embodiment is, for example, a Double Implantation MOSFET (DIMOSFET) in which a body region and a source region are formed by ion implantation. The semiconductor device of the first embodiment also includes an SBD (Shottky Barrier Diode) as a built-in diode. The MOSFET 100 is a vertical n-channel MOSFET that uses electrons as carriers.

[0016] 1(a) and 1(b) are schematic top views of a semiconductor device according to a first embodiment. Fig. 1(a) is a layout diagram of each region included in a MOSFET 100. Fig. 1(b) is a diagram showing the patterns of electrodes and wiring on the top surface of the MOSFET 100.

[0017] Figures 2(a) and 2(b) are schematic cross-sectional views of a portion of the semiconductor device of the first embodiment. Figure 3 is a schematic top view of a portion of the semiconductor device of the first embodiment. Figures 4 and 5 are enlarged schematic cross-sectional views of a portion of the semiconductor device of the first embodiment.

[0018] Fig. 2(a) is a cross-section taken along line AA' in Fig. 3. Fig. 2(b) is a cross-section taken along line BB' in Fig. 3. Fig. 4 is an enlarged schematic cross-sectional view of a portion of Fig. 2(a). Fig. 5 is an enlarged schematic cross-sectional view of a portion of Fig. 2(b).

[0019] Figures 6(a) and 6(b) are schematic cross-sectional views of a portion of the semiconductor device of the first embodiment. Figure 7 is a schematic top view of a portion of the semiconductor device of the first embodiment. Figures 8 and 9 are enlarged schematic cross-sectional views of a portion of the semiconductor device of the first embodiment.

[0020] Fig. 6(a) is a cross-section taken along CC' in Fig. 7. Fig. 6(b) is a cross-section taken along DD' in Fig. 7. Fig. 8 is an enlarged schematic cross-sectional view of a portion of Fig. 6(a). Fig. 9 is an enlarged schematic cross-sectional view of a portion of Fig. 6(b).

[0021] Fig. 10(a) and Fig. 10(b) are schematic cross-sectional views of a portion of the semiconductor device of the first embodiment. Fig. 11 is a schematic top view of a portion of the semiconductor device of the first embodiment. Fig. 12 and Fig. 13 are enlarged schematic cross-sectional views of a portion of the semiconductor device of the first embodiment.

[0022] Fig. 10(a) is an EE' cross section of Fig. 11. Fig. 10(b) is an FF' cross section of Fig. 11. Fig. 12 is an enlarged schematic cross section of a portion of Fig. 10(a). Fig. 13 is an enlarged schematic cross section of a portion of Fig. 10(b).

[0023] As shown in FIG. 1( a ), the MOSFET 100 includes a number of transistor regions 101 , a number of diode regions 102 , and a termination region 103 .

[0024] The multiple transistor regions 101 and the multiple diode regions 102 are alternately arranged in a first direction parallel to the first plane P1. The transistor region 101 is sandwiched between, for example, two diode regions 102 in the first direction. The diode region 102 is sandwiched between, for example, two transistor regions 101 in the first direction.

[0025] The width (w1 in FIG. 1(a)) of the transistor region 101 in the first direction is greater than, for example, the width (w2 in FIG. 1(a)) of the diode region 102 in the first direction.

[0026] 1(a) illustrates an example in which two transistor regions 101 and three diode regions 102 are arranged in the first direction. However, the numbers of the transistor regions 101 and the diode regions 102 are not limited to this number.

[0027] A MOSFET and an SBD are provided in the transistor region 101. An SBD is provided in the diode region 102. No MOSFET is provided in the diode region 102.

[0028] The termination region 103 surrounds the transistor region 101 and the diode region 102. The termination region 103 is provided with a structure that improves the breakdown voltage of the MOSFET 100. The structure that improves the breakdown voltage of the MOSFET 100 is, for example, a resurf or a guard ring.

[0029] The MOSFET 100 includes a silicon carbide layer 10, a source electrode 12 (first electrode), a drain electrode 14 (second electrode), a gate insulating layer 16, a gate electrode 18, an interlayer insulating layer 20, a gate electrode pad 22, and a gate wiring .

[0030] In the silicon carbide layer 10, n + Drain region 26, n - a p-type drift region 28 (first silicon carbide region), a p-type body region 30 (second silicon carbide region), + The semiconductor device includes a first bridge region 36 (fourth silicon carbide region) of p type, a second bridge region 38 (sixth silicon carbide region) of p type, and a third bridge region 40 (seventh silicon carbide region) of p type.

[0031] The drift region 28 includes a plurality of first portions 28a and a plurality of second portions 28b.

[0032] 2(a), 2(b), 3, 4, and 5 are diagrams showing the transistor region 101. FIG.

[0033] As shown in Figures 2(a), 2(b), 3, 4, and 5, the transistor region 101 includes a silicon carbide layer 10, a source electrode 12 (first electrode), a drain electrode 14 (second electrode), a gate insulating layer 16, a gate electrode 18, and an interlayer insulating layer 20. The silicon carbide layer 10 of the transistor region 101 includes n + Drain region 26, n - a first silicon carbide region, a plurality of p-type body regions 30, a plurality of n-type body regions 31, a plurality of n-type drift regions 28, a plurality of n-type body regions 30, a plurality of n-type body regions 31, a plurality of n-type body regions 32, a plurality of n-type body regions 33, a plurality of n-type body regions 34, a plurality of n-type body regions 35, a plurality of n-type body regions 36 +The semiconductor device further includes a p-type source region 32 (third silicon carbide region), and a plurality of p-type first bridge regions 36 (fourth silicon carbide regions).

[0034] It should be noted that FIG. 3 only shows the patterns of the drift region 28, the body region 30, the first bridging region 36, and the gate electrode 18.

[0035] In the transistor region 101, the source electrode 12, the first portion 28a of the drift region 28, the drain region 26, and the drain electrode 14 form an SBD. Also, the source electrode 12, the body region 30, the drift region 28, the drain region 26, and the drain electrode 14 form a pn junction diode.

[0036] The silicon carbide layer 10 is provided between the source electrode 12 and the drain electrode 14. The silicon carbide layer 10 is provided between the gate electrode 18 and the drain electrode 14. The silicon carbide layer 10 is single crystal SiC. The silicon carbide layer 10 is, for example, 4H—SiC.

[0037] Silicon carbide layer 10 has a first surface ("P1" in Figures 2(a) and 2(b)) and a second surface ("P2" in Figures 2(a) and 2(b)). The first surface P1 and the second surface P2 are opposed to each other. Hereinafter, the first surface may be referred to as the front surface, and the second surface may be referred to as the back surface. Note that, hereinafter, "depth" refers to the depth based on the first surface.

[0038] The first surface P1 is, for example, a surface inclined at an angle of 0 to 8 degrees with respect to the (0001) surface. The second surface P2 is, for example, a surface inclined at an angle of 0 to 8 degrees with respect to the (000-1) surface. The (0001) surface is called a silicon surface. The (000-1) surface is called a carbon surface.

[0039] n + The n-type drain region 26 is provided on the back surface side of the silicon carbide layer 10. The drain region 26 contains, for example, nitrogen (N) as an n-type impurity. The n-type impurity concentration of the drain region 26 is, for example, 1×10 18 cm -3 More than 1×10 21 cm-3 The following is the result.

[0040] n - A drift region 28 of the type is provided between the drain region 26 and the first surface P1. The drift region 28 is provided between the source electrode 12 and the drain electrode 14. The drift region 28 is provided between the gate electrode 18 and the drain electrode 14.

[0041] The drift region 28 is provided on the drain region 26. The drift region 28 contains, for example, nitrogen (N) as an n-type impurity. The n-type impurity concentration of the drift region 28 is lower than the n-type impurity concentration of the drain region 26. The n-type impurity concentration of the drift region 28 is, for example, 4×10 14 cm -3 More than 1×10 17 cm -3 The thickness of the drift region 28 is, for example, not less than 5 μm and not more than 150 μm.

[0042] The drift region 28 includes a plurality of first portions 28a. The first portions 28a are in contact with the first plane P1.

[0043] The first portion 28a extends in a second direction perpendicular to the first direction. The first portion 28a is repeatedly arranged in the first direction. The first portion 28a is sandwiched between two body regions 30 adjacent to each other in the first direction.

[0044] The first portion 28a functions as an n-type semiconductor region of the SBD.

[0045] The p-type body region 30 is provided between the drift region 28 and the first plane P1. The body region 30 extends in the second direction. The body regions 30 are repeatedly arranged in the first direction.

[0046] A part of the body region 30 functions as a channel region of the MOSFET 100. The body region 30 functions as a p-type semiconductor region of a pn junction diode.

[0047] The body region 30 includes, for example, a low concentration portion and a high concentration portion. The high concentration portion is provided between the low concentration portion and the first plane P1. The p-type impurity concentration of the high concentration portion is higher than the p-type impurity concentration of the low concentration portion.

[0048] The body region 30 contains, for example, aluminum (Al) as a p-type impurity. The p-type impurity concentration of the body region 30 is, for example, 1×10 16 cm -3 More than 1×10 21 cm -3 The p-type impurity concentration of the body region 30 is defined as the p-type impurity concentration at a position halfway to the depth of the body region 30.

[0049] The depth of the body region 30 is, for example, not less than 0.3 μm and not more than 1.0 μm.

[0050] The body region 30 is fixed to the potential of the source electrode 12 .

[0051] n + A source region 32 of the type is provided between the body region 30 and the first face P1. The source region 32 is provided between the body region 30 and the first face P1. The source region 32 extends, for example, in the second direction.

[0052] The source region 32 contains, for example, phosphorus (P) as an n-type impurity. The concentration of the n-type impurity in the source region 32 is higher than the concentration of the n-type impurity in the drift region .

[0053] The n-type impurity concentration of the source region 32 is, for example, 1×10 18 cm -3 More than 1×10 21 cm -3 The depth of the source region 32 is shallower than the depth of the body region 30. The depth of the source region 32 is, for example, not less than 0.1 μm and not more than 0.3 μm.

[0054] The p-type first bridging regions 36 are provided between the drift region 28 and the first plane P1. The first bridging regions 36 are repeatedly arranged in the second direction.

[0055] The first bridging region 36 connects two body regions 30 adjacent to each other in a first direction. The first bridging region 36 extends in the first direction, for example. The first bridging region 36 intersects with the body region 30, for example. The first bridging region 36 overlaps with the body region 30, for example.

[0056] The first bridging region 36 divides the first portion 28a extending in the second direction. The first bridging region 36 connects, via a p-type silicon carbide region, two adjacent body regions 30 that are separated from each other with the n-type first portion 28a therebetween.

[0057] The distance in the second direction between two adjacent first bridging regions 36 in the second direction (dx in FIG. 3) is smaller than, for example, the width in the first direction (w1 in FIG. 1(a)) of the transistor region 101. The distance in the second direction dx between two adjacent first bridging regions 36 is, for example, not less than 10 μm and not more than 200 μm.

[0058] The width in the second direction of the first cross-linked region 36 (wx in FIG. 3) is, for example, smaller than the first distance in the first direction between two adjacent first portions 28a (d1 in FIG. 2(a) and FIG. 3). The width in the second direction of the first cross-linked region 36 (wx in FIG. 3) is, for example, half or less of the first distance in the first direction between two adjacent first portions 28a (d1 in FIG. 2(a) and FIG. 3).

[0059] The first distance d1 in the first direction between two adjacent first portions 28a is, for example, not less than 3 μm and not more than 30 μm. The width wx in the second direction of the first cross-linked region 36 is, for example, not less than 1 μm and not more than 10 μm.

[0060] The first bridging region 36 contains, for example, aluminum (Al) as a p-type impurity. The p-type impurity concentration of the first bridging region 36 is, for example, 1×10 16 cm -3 More than 1×10 21 cm -3 The following is the result.

[0061] The p-type impurity concentration of the first bridging region 36 is, for example, substantially the same as the p-type impurity concentration of the body region 30. Note that the p-type impurity concentration of the first bridging region 36 is defined as the p-type impurity concentration at a position halfway to the depth of the first bridging region 36.

[0062] The depth of the first bridging region 36 is, for example, 0.3 μm or more and 1.0 μm or less. The depth of the first bridging region 36 is, for example, substantially the same as the depth of the body region 30.

[0063] The potential of the first bridging region 36 is fixed to the potential of the source electrode 12 .

[0064] Although FIG. 3 illustrates an example in which two first cross-linked regions 36 are arranged in the second direction, three or more first cross-linked regions 36 may be arranged.

[0065] The gate electrode 18 is provided on the first face P1 side of the silicon carbide layer 10. The gate electrode 18 extends in a second direction parallel to the first face P1 and perpendicular to the first direction. A plurality of gate electrodes 18 are arranged parallel to each other in the first direction. The gate electrodes 18 have a so-called stripe shape.

[0066] The gate electrode 18 is a conductive layer, for example, polycrystalline silicon containing p-type impurities or n-type impurities.

[0067] The gate electrode 18 faces, for example, a portion of the body region 30 in contact with the first face P1. The gate electrode 18 faces, for example, a portion of the drift region 28 in contact with the first face P1.

[0068] The gate insulating layer 16 is provided between the gate electrode 18 and the body region 30. The gate insulating layer 16 is provided between the gate electrode 18 and the drift region .

[0069] The gate insulating layer 16 is, for example, silicon oxide. For example, a high-k insulating material (high dielectric constant insulating material) can be used for the gate insulating layer 16.

[0070] The interlayer insulating layer 20 is provided on the gate electrode 18 and on the silicon carbide layer 10. The interlayer insulating layer 20 is provided between the gate electrode 18 and the source electrode 12. The interlayer insulating layer 20 is, for example, silicon oxide.

[0071] The source electrode 12 is provided on the first face P1 side of the silicon carbide layer 10. The source electrode 12 contacts the first face P1.

[0072] The source electrode 12 contacts a first portion 28 a of the drift region 28 , the body region 30 , the source region 32 , and the first bridging region 36 .

[0073] The source electrode 12 includes a metal. The metal forming the source electrode 12 has a laminated structure of, for example, titanium (Ti) and aluminum (Al).

[0074] The portions of the source electrode 12 in contact with the body region 30, the source region 32, and the first bridging region 36 are, for example, a metal silicide. The metal silicide is, for example, titanium silicide or nickel silicide. The portion of the source electrode 12 in contact with the first portion 28a of the drift region 28 is, for example, not provided with a metal silicide.

[0075] The junctions between the body region 30, the source region 32, and the first bridging region 36 and the source electrode 12 are, for example, ohmic junctions. The junction between the first portion 28a of the drift region 28 and the source electrode 12 is, for example, a Schottky junction.

[0076] The drain electrode 14 is provided on the second face P2 side of the silicon carbide layer 10. The drain electrode 14 contacts the second face P2. The drain electrode 14 contacts the drain region 26.

[0077] The drain electrode 14 is, for example, a metal or a metal-semiconductor compound, and includes at least one material selected from the group consisting of nickel silicide, titanium (Ti), nickel (Ni), silver (Ag), and gold (Au).

[0078] The junction between the drain region 26 and the drain electrode 14 is, for example, an ohmic junction.

[0079] 6(a), 6(b), 7, 8, and 9 are diagrams illustrating the diode region 102. FIG.

[0080] As shown in Figures 6(a), 6(b), 7, 8, and 9, the diode region 102 includes a silicon carbide layer 10, a source electrode 12 (first electrode), and a drain electrode 14 (second electrode). + Drain region 26, n - The semiconductor device includes a p-type drift region 28 (first silicon carbide region), a plurality of p-type anode regions 34 (fifth silicon carbide regions), and a p-type second bridge region 38 (sixth silicon carbide region).

[0081] It should be noted that FIG. 7 only shows the patterns of the drift region 28, the anode region 34, and the second bridge region 38.

[0082] In the diode region 102, the source electrode 12, the second portion 28b of the drift region 28, the drain region 26, and the drain electrode 14 form an SBD. Also, the source electrode 12, the anode region 34, the drift region 28, the drain region 26, and the drain electrode 14 form a pn junction diode.

[0083] The drift region 28 includes a plurality of second portions 28b. The second portions 28b are in contact with the first plane P1.

[0084] The second portions 28b extend in the second direction. The second portions 28b are repeatedly arranged in the first direction. The second portions 28b are sandwiched between two anode regions 34 adjacent to each other in the first direction.

[0085] The second portion 28b functions as an n-type semiconductor region of the SBD.

[0086] The p-type anode region 34 is provided between the drift region 28 and the first face P1. The anode region 34 functions as a p-type semiconductor region of the pn junction diode.

[0087] The anode region 34 includes, for example, a low concentration portion and a high concentration portion. The high concentration portion is provided between the low concentration portion and the first plane P1. The p-type impurity concentration of the high concentration portion is higher than the p-type impurity concentration of the low concentration portion.

[0088] The anode region 34 contains, for example, aluminum (Al) as a p-type impurity. The p-type impurity concentration of the anode region 34 is, for example, 1×10 16 cm -3 More than 1×10 21 cm -3 The p-type impurity concentration of the anode region is defined as the p-type impurity concentration at a position halfway to the depth of the anode region .

[0089] The width (wb in FIG. 7) of the anode region 34 in the first direction is greater than the width of the body region 30 in the first direction, for example.

[0090] The depth of the anode region 34 is, for example, substantially the same as the depth of the body region 30. The depth of the anode region 34 is, for example, not less than 0.3 μm and not more than 1.0 μm.

[0091] The anode region 34 is fixed at the potential of the source electrode 12 .

[0092] The p-type second bridging regions 38 are provided between the drift region 28 and the first plane P1. The second bridging regions 38 are repeatedly arranged in the second direction.

[0093] The second bridging region 38 connects two adjacent anode regions 34 in the first direction. The second bridging region 38 extends in the first direction, for example. The second bridging region 38 intersects with the anode region 34, for example. The second bridging region 38 overlaps with the anode region 34, for example.

[0094] The second bridging region 38 divides the second portion 28b extending in the second direction. The second bridging region 38 connects, via a p-type silicon carbide region, two adjacent anode regions 34 that are separated from each other with the n-type second portion 28b therebetween.

[0095] The distance in the second direction between two adjacent second bridging regions 38 (dy in FIG. 7) is, for example, smaller than the width in the first direction (w1 in FIG. 1(a)) of the transistor region 101. The distance in the second direction dy between two adjacent second bridging regions 38 is, for example, not less than 10 μm and not more than 200 μm.

[0096] The width in the second direction of the second bridging region 38 (wy in FIG. 7) is, for example, smaller than the width in the first direction of the anode region 34 (wb in FIG. 7). The width in the second direction of the second bridging region 38 (wy in FIG. 7) is, for example, half or less of the width in the first direction of the anode region 34 (wb in FIG. 7).

[0097] Furthermore, the width in the second direction of the second cross-linked region 38 (wy in FIG. 7) is smaller than, for example, the second distance in the first direction between two adjacent second portions 28b (d2 in FIG. 6(a) and FIG. 7). The width in the second direction of the second cross-linked region 38 (wy in FIG. 7) is, for example, half or less of the second distance in the first direction between two adjacent second portions 28b (d2 in FIG. 6(a)).

[0098] The second distance d2 in the first direction between two adjacent second portions 28b is, for example, not less than 3 μm and not more than 30 μm. The width wy in the second direction of the second cross-linked region 38 is, for example, not less than 1 μm and not more than 10 μm.

[0099] The second distance in the first direction between two adjacent second portions 28b (d2 in Figures 6(a) and 7) is, for example, substantially equal to the first distance in the first direction between two adjacent first portions 28a (d1 in Figure 2(a)).

[0100] The second bridging region 38 contains, for example, aluminum (Al) as a p-type impurity. The p-type impurity concentration of the second bridging region 38 is, for example, 1×10 16 cm -3 More than 1×10 21 cm -3 The following is the result.

[0101] The p-type impurity concentration of the second bridging region 38 is, for example, substantially the same as the p-type impurity concentration of the anode region 34. The p-type impurity concentration of the second bridging region 38 is, for example, substantially the same as the p-type impurity concentration of the first bridging region 36. Note that the p-type impurity concentration of the second bridging region 38 is defined as the p-type impurity concentration at a position halfway through the depth of the second bridging region 38.

[0102] The depth of the second cross-linked region 38 is, for example, 0.3 μm or more and 1.0 μm or less. The depth of the second cross-linked region 38 is, for example, substantially the same as the depth of the anode region 34. The depth of the second cross-linked region 38 is, for example, substantially the same as the depth of the first cross-linked region 36.

[0103] The potential of the second bridging region 38 is fixed to the potential of the source electrode 12 .

[0104] Although FIG. 7 illustrates an example in which two second cross-linked regions 38 are arranged in the second direction, three or more second cross-linked regions 38 may be arranged.

[0105] The source electrode 12 is provided on the first face P1 side of the silicon carbide layer 10. The source electrode 12 contacts the first face P1.

[0106] The source electrode 12 contacts the second portion 28b of the drift region 28, the anode region 34, and the second bridging region 38.

[0107] The portions of the source electrode 12 in contact with the body region 30, the anode region 34, and the second bridging region 38 are, for example, a metal silicide. The metal silicide is, for example, titanium silicide or nickel silicide. The portion of the source electrode 12 in contact with the second portion 28b of the drift region 28 is, for example, free of a metal silicide.

[0108] The junction between the anode region 34 and the second bridging region 38 and the source electrode 12 is, for example, an ohmic junction. The junction between the second portion 28b of the drift region 28 and the source electrode 12 is, for example, a Schottky junction.

[0109] 10(a), 10(b), 11, 12, and 13 are diagrams showing the boundary portion between the transistor region 101 and the diode region 102. FIG.

[0110] As shown in FIGS. 10(b), 11, and 13, the silicon carbide layer 10 at the boundary between the transistor region 101 and the diode region 102 includes a p-type third bridging region 40 (seventh silicon carbide region).

[0111] The p-type third bridging region 40 is provided between the drift region 28 and the first plane P1. The third bridging regions 40 are repeatedly arranged in the second direction.

[0112] The third bridging region 40 connects the body region 30 and the anode region 34 adjacent to each other in the first direction.

[0113] The third bridging region 40 divides the drift region 28 extending in the second direction on the first surface. The third bridging region 40 connects, via a p-type silicon carbide region, the body region 30 and the anode region 34 that are adjacent to each other and are separated from each other with the n-type drift region 28 therebetween.

[0114] The third cross-linking region 40, for example, contacts the first cross-linking region 36 and the second cross-linking region 38. The first cross-linking region 36, the second cross-linking region 38, and the third cross-linking region 40 are, for example, continuous in the first direction.

[0115] The distance in the second direction between two adjacent third bridging regions 40 (dz in FIG. 11) is, for example, smaller than the width in the first direction (w1 in FIG. 1(a)) of the transistor region 101. The distance in the second direction dz between two adjacent third bridging regions 40 is, for example, not less than 10 μm and not more than 200 μm.

[0116] The width in the second direction of the third cross-linked region 40 (wz in FIG. 11) is, for example, smaller than the second distance in the first direction between two adjacent second portions 28b (d2 in FIG. 11). The second distance d2 in the first direction between two adjacent second portions 28b is, for example, not less than 3 μm and not more than 30 μm. The width wz in the second direction of the third cross-linked region 40 is, for example, not less than 1 μm and not more than 10 μm.

[0117] The third bridging region 40 contains, for example, aluminum (Al) as a p-type impurity. The p-type impurity concentration of the third bridging region 40 is, for example, 1×10 16 cm -3 More than 1×10 21 cm -3 The following is the result.

[0118] The p-type impurity concentration of the third bridging region 40 is, for example, substantially the same as the p-type impurity concentration of the body region 30 and the anode region 34. The p-type impurity concentration of the third bridging region 40 is, for example, substantially the same as the p-type impurity concentration of the first bridging region 36. The p-type impurity concentration of the third bridging region 40 is, for example, substantially the same as the p-type impurity concentration of the second bridging region 38. The p-type impurity concentration of the third bridging region 40 is defined as the p-type impurity concentration at a position half the depth of the third bridging region 40.

[0119] The depth of the third bridging region 40 is, for example, 0.3 μm or more and 1.0 μm or less. The depth of the third bridging region 40 is, for example, substantially the same as the depth of the body region 30 and the anode region 34. The depth of the third bridging region 40 is, for example, substantially the same as the depth of the first bridging region 36. The depth of the third bridging region 40 is, for example, substantially the same as the depth of the second bridging region 38.

[0120] The potential of the third bridging region 40 is fixed to the potential of the source electrode 12 .

[0121] Although FIG. 11 illustrates an example in which two third cross-linking regions 40 are arranged in the second direction, three or more third cross-linking regions 40 may be arranged.

[0122] The source electrode 12 is provided on the first face P1 side of the silicon carbide layer 10. The source electrode 12 contacts the first face P1.

[0123] The source electrode 12 contacts the third bridging region 40 .

[0124] The portion of the source electrode 12 in contact with the third bridging region 40 is, for example, a metal silicide. The metal silicide is, for example, titanium silicide or nickel silicide.

[0125] The junction between the third bridging region 40 and the source electrode 12 is, for example, an ohmic junction.

[0126] Fig. 14 is a schematic top view of the semiconductor device of the first embodiment. Fig. 14 is a diagram showing a pattern of the body region 30 projected onto the first surface P1 and a pattern of the anode region 34 projected onto the first surface P1. The pattern of the body region 30 and the pattern of the anode region 34 in Fig. 14 are patterns projected onto the first surface P1 in a direction perpendicular to the first surface P1.

[0127] 14, the region where the first bridge region 36 intersects with the body region 30 is also recognized as the body region 30. In addition, the region where the second bridge region 38 intersects with the anode region 34 is also recognized as the anode region 34.

[0128] The occupancy rate per unit area of ​​the anode region 34 projected onto the first surface P1 is greater than the occupancy rate per unit area of ​​the body region 30 projected onto the first surface P1. In other words, in a region of a given size, the occupancy rate of the anode region 34 projected onto the first surface P1 is greater than the occupancy rate of the body region 30 projected onto the first surface P1. That is, the occupancy rate of the pn junction diode in the diode region 102 is greater than the occupancy rate of the pn junction diode in the transistor region 101.

[0129] The occupancy rate per unit area of ​​the anode region 34 projected onto the first surface P1 is, for example, 1.2 times or more and 3 times or less than the occupancy rate per unit area of ​​the body region 30 projected onto the first surface P1.

[0130] The unit area is not particularly limited as long as it is a size that allows comparison of the average occupancy rate of the body region 30 in the transistor region 101 and the average occupancy rate of the anode region 34 in the diode region 102. The unit area is, for example, 30 μm×30 μm=900 μm 2 It is.

[0131] In addition, the contact area per unit area between the source electrode 12 and the anode region 34 in the diode region 102 is larger than the contact area per unit area between the source electrode 12 and the body region 30 in the transistor region 101. That is, the contact resistance per unit area between the source electrode 12 and the anode region 34 in the diode region 102 is smaller than the contact resistance per unit area between the source electrode 12 and the body region 30 in the transistor region 101.

[0132] Next, the operation and effects of the MOSFET 100 of the first embodiment will be described.

[0133] Fig. 15(a) and Fig. 15(b) are schematic top views of a semiconductor device of a first comparative example. Fig. 15(a) is a layout diagram of each region included in a MOSFET of the first comparative example. Fig. 15(b) is a diagram showing electrode and wiring patterns on the top surface of the MOSFET of the first comparative example. Fig. 15(a) and Fig. 15(b) are views corresponding to Fig. 1(a) and Fig. 1(b) of the first embodiment.

[0134] Fig. 16 is a schematic cross-sectional view of a semiconductor device of a first comparative example. Fig. 16 is a cross-sectional view of the transistor region 101 of Fig. 15(a). Fig. 16 is a view corresponding to Fig. 2(a) of the first embodiment.

[0135] The MOSFET of the first comparative example differs from the MOSFET 100 of the first embodiment in that it does not include the diode region 102.

[0136] The transistor region 101 of the MOSFET of the first comparative example is provided with a MOSFET and an SBD, similar to the MOSFET 100 of the first embodiment.

[0137] 17 is an equivalent circuit diagram of the semiconductor device of the first comparative example. A pn ​​junction diode and an SBD are connected as an internal diode between the source electrode 12 and the drain electrode 14 in parallel with the transistor.

[0138] For example, consider a case where a MOSFET is used as a switching element connected to an inductive load. When the MOSFET is off, a voltage may be applied to the source electrode 12 that is positive with respect to the drain electrode 14 due to a load current caused by the inductive load. In this case, a forward current flows through the built-in diode. This state is also called a reverse conduction state.

[0139] The forward voltage (Vf) at which forward current begins to flow through the SBD is lower than the forward voltage (Vf) of a pn junction diode. Therefore, initially, forward current flows through the SBD.

[0140] The forward voltage (Vf) of the SBD is, for example, 1.0 V. The forward voltage (Vf) of the pn junction diode is, for example, 2.5 V.

[0141] The SBD operates in a unipolar manner, so that stacking faults do not grow in silicon carbide layer 10 due to carrier recombination energy even when a forward current flows.

[0142] 18(a) and 18(b) are explanatory diagrams of the operation and effect of the semiconductor device of the first embodiment. FIG. 18(a) and FIG. 18(b) are schematic cross-sectional views of a first comparative example. FIG. 18(a) and FIG. 18(b) are diagrams corresponding to FIG. 16.

[0143] 18(a) and 18(b) are diagrams showing the current flowing through the built-in diode of the MOSFET of the first comparative example. Fig. 18(a) shows a state in which a forward current flows only through the SBD, and Fig. 18(b) shows a state in which a forward current flows through the SBD and the pn junction diode.

[0144] That is, Fig. 18(a) shows a state in which the voltage applied across the pn junction of the pn junction diode is lower than the forward voltage (Vf) of the pn junction diode, and Fig. 18(b) shows a state in which the voltage applied across the pn junction of the pn junction diode is higher than the forward voltage (Vf) of the pn junction diode.

[0145] In Figures 18(a) and 18(b), the dotted arrows indicate the current flowing through the SBD, and in Figure 18(b), the solid arrows indicate the current flowing through the pn junction diode.

[0146] 18(a), the current flowing through the SBD flows around the bottom of the body region 30. This causes an electrostatic potential to flow around the drift region 28 facing the bottom of the body region 30. The electrostatic potential flow reduces the voltage applied between the body region 30 and the drift region 28.

[0147] Therefore, the forward voltage (Vf) of the pn junction diode is less likely to be exceeded at the bottom of the body region 30. In other words, the forward voltage (Vf) of the pn junction diode of the MOSFET of the first comparative example can be made higher than when no SBD is provided. Therefore, the bipolar operation of the pn junction diode is suppressed, and the formation of stacking faults in the silicon carbide layer 10 due to carrier recombination energy is suppressed.

[0148] The forward voltage (Vf) of the pn junction diode of the MOSFET of the first comparative example depends on the distance between two SBDs adjacent to each other in the first direction. By reducing the distance between two SBDs adjacent to each other in the first direction, the forward voltage (Vf) of the pn junction diode of the MOSFET of the first comparative example can be increased.

[0149] There are cases where a large surge current exceeding the steady state is momentarily applied to a MOSFET. The surge current flows from the source electrode 12 to the drain electrode 14.

[0150] When a large surge current flows, a large surge voltage is applied, causing the MOSFET to heat up and break down. The maximum allowable peak current value of the surge current allowed for a MOSFET (I FSM It is desirable to improve the surge current capability of MOSFETs equipped with SBDs.

[0151] When a large surge voltage is applied to the MOSFET of the first comparative example, the voltage applied across the pn junction of the pn junction diode becomes higher than the forward voltage (Vf) of the pn junction diode.

[0152] When the voltage applied across the pn junction of the pn junction diode becomes higher than the forward voltage (Vf) of the pn junction diode, a current also flows through the pn junction diode, as shown in FIG. 18(b).

[0153] Fig. 19 is an explanatory diagram of the operation and effect of the semiconductor device of the first embodiment. Fig. 19 is a schematic cross-sectional view of a second comparative example. Fig. 19 is a diagram corresponding to Fig. 16 of the first comparative example.

[0154] The MOSFET of the second comparative example differs from the MOSFET of the first comparative example in that the transistor region does not include an SBD. The built-in diode of the MOSFET of the second comparative example is only a pn junction diode.

[0155] Fig. 20 is an explanatory diagram of the operation and effect of the semiconductor device of the first embodiment, and is a diagram showing voltage-current characteristics of the built-in diodes of the MOSFET of the first comparative example and the MOSFET of the second comparative example.

[0156] 20, in the MOSFET of the second comparative example, a current flows through the pn junction diode when a voltage equal to or greater than the forward voltage Vf2 of the pn junction diode is applied. On the other hand, in the MOSFET of the first comparative example, a current flows through the SBD until the forward voltage Vf1 of the pn junction diode is applied. In the MOSFET of the first comparative example, a current flows through the pn junction diode when a voltage equal to or greater than the forward voltage Vf1 of the pn junction diode is applied.

[0157] The MOSFET of the first comparative example operates in a unipolar manner up to a forward voltage Vf1, so the slope of the current increase is smaller than that of the MOSFET of the second comparative example. Therefore, the maximum allowable peak current value I FSM 2, the maximum allowable peak current value I FSM 1 becomes smaller. In other words, the surge current withstand capability of the MOSFET of the first comparative example becomes smaller than the surge current withstand capability of the MOSFET of the second comparative example.

[0158] Fig. 21 is a schematic top view of a semiconductor device of a third comparative example, which corresponds to Fig. 11 of the first embodiment.

[0159] The MOSFET of the third comparative example differs from the MOSFET 100 of the first embodiment in that the silicon carbide layer 10 does not include a p-type first bridging region 36 (fourth silicon carbide region), a p-type second bridging region 38 (sixth silicon carbide region), and a p-type third bridging region 40 (seventh silicon carbide region).

[0160] The MOSFET of the third comparative example includes diode regions 102 arranged alternately with transistor regions 101, similar to the MOSFET 100 of the first embodiment. The MOSFET of the third comparative example has improved surge current resistance due to the inclusion of diode regions 102. This will be described in detail below.

[0161] 22(a) and 22(b) are explanatory diagrams of the operation and effect of the semiconductor device of the first embodiment. FIGS. 22(a) and 22(b) are schematic cross-sectional views of a MOSFET of a third comparative example. FIGS. 22(a) and 22(b) are diagrams corresponding to FIG. 10(a) of the first embodiment. The MOSFET of the third comparative example has a structure similar to the structure shown in FIG. 10(a) of the first embodiment.

[0162] 22(a) and 22(b) are diagrams showing the current flowing through the built-in diode of the MOSFET of the third comparative example. Fig. 22(a) shows a state in which a forward current flows only through the SBD, and Fig. 22(b) shows a state in which a forward current flows through the SBD and the pn junction diode.

[0163] That is, Fig. 22(a) shows a state in which the voltage applied across the pn junction of the pn junction diode is lower than the forward voltage (Vf) of the pn junction diode, and Fig. 22(b) shows a state in which the voltage applied across the pn junction of the pn junction diode is higher than the forward voltage (Vf) of the pn junction diode.

[0164] In Figures 22(a) and 22(b), the dotted arrows indicate the current flowing through the SBD, and in Figure 22(b), the solid arrows indicate the current flowing through the pn junction diode.

[0165] In the diode region 102, a second distance d2 in the first direction between two adjacent second portions 28b with the anode region 34 therebetween is substantially equal to a first distance d1 in the first direction between two adjacent first portions 28a with the body region 30 therebetween in the transistor region 101. In other words, the second portions 28b are provided in the diode region 102 at the same intervals as the first portions 28a in the transistor region 101. In further other words, the SBD regions are provided in the diode region 102 at the same intervals as the transistor region 101.

[0166] 22(a), in the diode region 102, the current flowing through the SBD flows around to the bottom of the anode region 34. This makes it difficult for the current to exceed the forward voltage (Vf) of the pn junction diode at the bottom of the anode region 34. The forward voltage (Vf) of the pn junction diode in the diode region 102 becomes higher by providing the SBD region.

[0167] When the voltage applied across the pn junction of the pn junction diode becomes higher than the forward voltage (Vf) of the pn junction diode, a current also flows through the pn junction diode, as shown in FIG. 22(b).

[0168] In the MOSFET of the third comparative example, for example, the occupancy rate per unit area of ​​the anode region 34 projected onto the first surface P1 is larger than the occupancy rate per unit area of ​​the body region 30 projected onto the first surface P1. That is, the occupancy rate of the pn junction diode in the diode region 102 is larger than the occupancy rate of the pn junction diode in the transistor region 101.

[0169] Also, for example, the contact area per unit area between the source electrode 12 and the anode region 34 in the diode region 102 is larger than the contact area per unit area between the source electrode 12 and the body region 30 in the transistor region 101. That is, the contact resistance per unit area between the source electrode 12 and the anode region 34 in the diode region 102 is smaller than the contact resistance per unit area between the source electrode 12 and the body region 30 in the transistor region 101.

[0170] Therefore, the current flowing through the pn junction diode in the diode region 102 is larger than the current flowing through the pn junction diode in the transistor region 101 .

[0171] In addition, a large current flows through the pn junction diode of the diode region 102, which causes carrier propagation and heat propagation to the adjacent transistor region 101. This promotes conductivity modulation in the transistor region 101 adjacent to the diode region 102. This increases the current flowing through the pn junction diode of the transistor region 101 adjacent to the diode region 102.

[0172] Fig. 23 is an explanatory diagram of the operation and effect of the semiconductor device of the first embodiment, and is a diagram showing voltage-current characteristics of the built-in diodes of the MOSFET of the first comparative example, the MOSFET of the second comparative example, and the MOSFET of the third comparative example.

[0173] 23, in the MOSFET of the third comparative example, a current flows through the SBD until a forward voltage Vf3 of the pn junction diode is applied. In the MOSFET of the third comparative example, when a voltage equal to or greater than the forward voltage Vf3 of the pn junction diode is applied, a current flows through the pn junction diode.

[0174] In the diode region 102 of the MOSFET of the third comparative example, SBD regions are provided at the same intervals as those of the transistor region 101. Therefore, the forward voltage Vf3 of the pn junction diode of the MOSFET of the third comparative example is equivalent to the forward voltage Vf1 of the pn junction diode of the MOSFET of the first comparative example.

[0175] On the other hand, the current after the forward voltage Vf3 of the pn junction diode is exceeded in the MOSFET of the third comparative example is larger than the current after the forward voltage Vf1 of the pn junction diode is exceeded in the MOSFET of the first comparative example. This is because the current flowing through the pn junction diode in the diode region 102 and the pn junction diode in the transistor region 101 adjacent to the diode region 102 is larger than that in the MOSFET of the first comparative example.

[0176] The current increases after exceeding the forward voltage Vf3 of the pn junction diode, and the maximum allowable peak current I FSM 3 is the maximum allowable peak current value I FSM 1. In other words, the surge current withstand capability of the MOSFET of the third comparative example is greater than the surge current withstand capability of the MOSFET of the first comparative example.

[0177] As described above, the MOSFET of the third comparative example has an improved surge current resistance by including the diode region 102 provided between the transistor regions 101.

[0178] In the MOSFET 100 of the first embodiment, the silicon carbide layer 10 includes the p-type first bridging region 36 (fourth silicon carbide region), the p-type second bridging region 38 (sixth silicon carbide region), and the p-type third bridging region 40 (seventh silicon carbide region), thereby further improving the surge current resistance compared to the MOSFET of the third comparative example. This will be described in detail below.

[0179] For example, in the MOSFET of the third comparative example, the surge current flowing through the MOSFET may vary within the chip. The surge current varies within the chip due to variations in the start of operation of the pn junction diodes provided in the diode region 102 and the transistor region 101 and the rise of the forward current after the start of operation.

[0180] If the surge current varies within a chip, for example, heat generation increases locally, which can cause localized destruction of MOSFETs, resulting in a decrease in surge current resistance.

[0181] In the MOSFET 100 of the first embodiment, by providing the p-type first bridging region 36 (fourth silicon carbide region), the p-type second bridging region 38 (sixth silicon carbide region), and the p-type third bridging region 40 (seventh silicon carbide region), the plurality of p-type body regions 30 and the plurality of p-type anode regions 34 extending in the second direction are connected in the first direction by the p-type region. The first bridging region 36, the second bridging region 38, and the third bridging region 40 connecting the body region 30 and the anode region 34 promote the movement of holes in the first direction, so that the start of operation of the pn junction diodes provided in the diode region 102 and the transistor region 101 and the rise of the forward current after the start of operation can be made uniform within the chip.

[0182] According to the MOSFET 100 of the first embodiment, the variation in the surge current flowing through the MOSFET can be suppressed within the chip, and therefore, according to the MOSFET 100 of the first embodiment, the surge current resistance is improved.

[0183] The distance in the second direction between two adjacent first bridging regions 36 (dx in FIG. 3) is preferably smaller than the width in the first direction (w1 in FIG. 1(a)) of the transistor region 101. By making the distance dx in the second direction smaller than the width w1 in the first direction of the transistor region 101, the start of operation of the pn junction diode provided in the transistor region 101 and the rise of the forward current after the start of operation can be made more uniform within the chip.

[0184] The width in the second direction of the first bridging region 36 (wx in FIG. 3) is preferably smaller than the first distance in the first direction between two adjacent first portions 28a (d1 in FIG. 2(a) and FIG. 3). By making the width wx in the second direction of the first bridging region 36 smaller than the first distance d1 in the first direction between two adjacent first portions 28a, a decrease in the pn junction diode forward voltage (Vf) of the transistor region 101 can be suppressed.

[0185] The width in the second direction of the second bridging region 38 (wy in FIG. 7) is preferably smaller than, for example, the width in the first direction of the anode region 34 (wb in FIG. 7). By making the width in the second direction of the second bridging region 38 (wy in FIG. 7) smaller than, for example, the width in the first direction of the anode region 34 (wb in FIG. 7), a decrease in the pn junction diode forward voltage (Vf) of the diode region 102 can be suppressed.

[0186] From the viewpoint of suppressing a decrease in the pn junction diode forward voltage (Vf) of the diode region 102, the width in the second direction of the second bridging region 38 (wy in FIG. 7) is preferably equal to or less than half the width in the first direction of the anode region 34 (wb in FIG. 7). From the viewpoint of suppressing a decrease in the pn junction diode forward voltage (Vf) of the diode region 102, the width in the second direction of the second bridging region 38 (wy in FIG. 7) is preferably equal to or less than 10 μm.

[0187] The width in the second direction of the second bridging region 38 (wy in FIG. 7) is preferably smaller than the second distance in the first direction between two adjacent second portions 28b (d2 in FIG. 6(a) and FIG. 7). By making the width wy in the second direction of the second bridging region 38 smaller than the second distance d2 in the first direction between two adjacent second portions 28b, a decrease in the pn junction diode forward voltage (Vf) of the diode region 102 can be suppressed.

[0188] From the viewpoint of increasing the on-state current of the MOSFET 100, it is preferable that the width in the first direction of the transistor region 101 (w1 in FIG. 1(a)) is larger than the width in the first direction of the diode region 102 (w2 in FIG. 1(a)).

[0189] (First Modification) The semiconductor device of the first variant differs from the semiconductor device of the first embodiment in that the depth of the fourth silicon carbide region is deeper than the depth of the second silicon carbide region, and the depth of the sixth silicon carbide region is deeper than the depth of the fifth silicon carbide region.

[0190] Figures 24(a), 24(b), 25(a), and 25(b) are schematic cross-sectional views of a semiconductor device according to a first modified example of the first embodiment. Figures 24(a) and 24(b) correspond to Figures 2(a) and 2(b) of the first embodiment. Figures 25(a) and 25(b) correspond to Figures 6(a) and 6(b) of the first embodiment.

[0191] As shown in Figures 24(a) and 24(b), in the MOSFET of the first modification, the depth of the p-type first bridging region 36 (fourth silicon carbide region) is deeper than the depth of the p-type body region 30 (second silicon carbide region). Also, as shown in Figures 25(a) and 25(b), the depth of the p-type second bridging region 38 (sixth silicon carbide region) is deeper than the depth of the p-type anode region 34 (fifth silicon carbide region).

[0192] The movement of holes in the first direction is further promoted by the deep p-type first bridging region 36 and the deep p-type second bridging region 38. Therefore, the surge current resistance of the MOSFET of the first modification is further improved.

[0193] (Second Modification) The semiconductor device of the second modified example differs from the semiconductor device of the first embodiment in that the p-type impurity concentration of the fourth silicon carbide region is higher than the p-type impurity concentration of the second silicon carbide region, and the p-type impurity concentration of the sixth silicon carbide region is higher than the p-type impurity concentration of the fifth silicon carbide region.

[0194] In the MOSFET of the second modification, the p-type first bridging region 36 (fourth silicon carbide region) has a higher p-type impurity concentration than the p-type body region 30 (second silicon carbide region). Also, the p-type second bridging region 38 (sixth silicon carbide region) has a higher p-type impurity concentration than the p-type anode region 34 (fifth silicon carbide region).

[0195] The movement of holes in the first direction is further promoted by the high p-type impurity concentrations in the p-type first bridging region 36 and the p-type second bridging region 38. Therefore, the surge current resistance of the MOSFET of the second modification is further improved.

[0196] As described above, according to the first embodiment and its modifications, a semiconductor device with improved surge current resistance can be provided.

[0197] Second embodiment The semiconductor device of the second embodiment differs from the semiconductor device of the first embodiment in that the fourth silicon carbide region does not intersect with the second silicon carbide region, and the sixth silicon carbide region does not intersect with the fifth silicon carbide region. Hereinafter, some of the contents that overlap with the first embodiment may be omitted.

[0198] The semiconductor device of the second embodiment is a planar gate vertical MOSFET 200 using silicon carbide, similar to the semiconductor device of the first embodiment.

[0199] Figures 26(a) and 26(b) are schematic cross-sectional views of a portion of the semiconductor device of the second embodiment. Figure 27 is a schematic top view of a portion of the semiconductor device of the second embodiment. Figure 26(a) is a cross-sectional view taken along line AA' in Figure 27. Figure 26(b) is a cross-sectional view taken along line BB' in Figure 27.

[0200] Figures 28(a) and 28(b) are schematic cross-sectional views of a portion of the semiconductor device of the second embodiment. Figure 29 is a schematic top view of a portion of the semiconductor device of the second embodiment. Figure 28(a) is a CC' cross section of Figure 29. Figure 28(b) is a DD' cross section of Figure 29.

[0201] Figures 30(a) and 30(b) are schematic cross-sectional views of a portion of the semiconductor device of the second embodiment. Figure 31 is a schematic top view of a portion of the semiconductor device of the second embodiment. Figure 30(a) is an E-E' cross section of Figure 31. Figure 30(b) is an F-F' cross section of Figure 31.

[0202] The MOSFET 200 includes a silicon carbide layer 10, a source electrode 12 (first electrode), a drain electrode 14 (second electrode), a gate insulating layer 16, a gate electrode 18, an interlayer insulating layer 20, a gate electrode pad 22, and a gate wiring .

[0203] In the silicon carbide layer 10, n + Drain region 26, n - a p-type drift region 28 (first silicon carbide region), a p-type body region 30 (second silicon carbide region), + The semiconductor device includes a first bridge region 36 (fourth silicon carbide region) of p type, a second bridge region 38 (sixth silicon carbide region) of p type, and a third bridge region 40 (seventh silicon carbide region) of p type.

[0204] The drift region 28 includes a plurality of first portions 28a and a plurality of second portions 28b.

[0205] 26(a), 26(b), and 27 are diagrams showing the transistor region 101. FIG.

[0206] As shown in Figures 26(a), 26(b), and 27, the transistor region 101 includes a silicon carbide layer 10, a source electrode 12 (first electrode), a drain electrode 14 (second electrode), a gate insulating layer 16, a gate electrode 18, and an interlayer insulating layer 20. The silicon carbide layer 10 of the transistor region 101 includes n + Drain region 26, n - a first silicon carbide region, a plurality of p-type body regions 30, a plurality of n-type body regions 31, a plurality of n-type drift regions 28, a plurality of n-type body regions 30, a plurality of n-type body regions 31, a plurality of n-type body regions 32, a plurality of n-type body regions 33, a plurality of n-type body regions 34, a plurality of n-type body regions 35, a plurality of n-type body regions 36 +The semiconductor device further includes a p-type source region 32 (third silicon carbide region), and a plurality of p-type first bridge regions 36 (fourth silicon carbide regions).

[0207] 27 shows only the patterns of the drift region 28, the body region 30, the first bridging region 36, and the gate electrode 18.

[0208] The p-type first bridging regions 36 are provided between the drift region 28 and the first plane P1. The first bridging regions 36 are repeatedly arranged in the second direction.

[0209] The first bridging region 36 connects two body regions 30 adjacent to each other in the first direction. The first bridging regions 36 are, for example, repeatedly arranged in the first direction. The two first bridging regions 36 adjacent to each other in the first direction sandwich the body region 30 therebetween.

[0210] The first bridging region 36 divides the first portion 28a extending in the second direction. The first bridging region 36 connects, via a p-type silicon carbide region, two adjacent body regions 30 that are separated from each other with the n-type first portion 28a therebetween.

[0211] The distance in the second direction between two adjacent first bridging regions 36 is, for example, smaller than the width in the first direction of the transistor region 101. The distance in the second direction between two adjacent first bridging regions 36 is, for example, not less than 10 μm and not more than 200 μm.

[0212] The width of the first cross-linked region 36 in the second direction is, for example, smaller than the distance between two adjacent first portions 28a. The distance between two adjacent first portions 28a is, for example, 3 μm or more and 30 μm or less. The width of the first cross-linked region 36 in the second direction is, for example, 1 μm or more and 10 μm or less.

[0213] The first bridging region 36 contains, for example, aluminum (Al) as a p-type impurity. The p-type impurity concentration of the first bridging region 36 is, for example, 1×10 16 cm -3 More than 1×10 21 cm-3 The p-type impurity concentration of the first bridging region 36 is, for example, substantially the same as the p-type impurity concentration of the body region 30.

[0214] The depth of the first bridging region 36 is, for example, 0.3 μm or more and 1.0 μm or less. The depth of the first bridging region 36 is, for example, substantially the same as the depth of the body region 30.

[0215] Although FIG. 27 illustrates an example in which two first cross-linking regions 36 are arranged in the second direction, three or more first cross-linking regions 36 may be arranged.

[0216] 28(a), 28(b), and 29 are diagrams showing the diode region 102. FIG.

[0217] As shown in Fig. 28(a), Fig. 28(b), and Fig. 29, the diode region 102 includes a silicon carbide layer 10, a source electrode 12 (first electrode), and a drain electrode 14 (second electrode). + Drain region 26, n - The semiconductor device includes a p-type drift region 28 (first silicon carbide region), a plurality of p-type anode regions 34 (fifth silicon carbide regions), and a p-type second bridge region 38 (sixth silicon carbide region).

[0218] It should be noted that FIG. 29 only shows the patterns of the drift region 28, the anode region 34, and the second bridge region 38.

[0219] The drift region 28 includes a plurality of second portions 28b. The second portions 28b are in contact with the first plane P1.

[0220] The p-type second bridging regions 38 are provided between the drift region 28 and the first plane P1. The second bridging regions 38 are repeatedly arranged in the second direction.

[0221] The second bridging region 38 connects two adjacent anode regions 34 in the first direction. The second bridging regions 38 are, for example, repeatedly arranged in the first direction. Two second bridging regions 38 adjacent to each other in the first direction sandwich an anode region 34 therebetween.

[0222] The second bridging region 38 divides the second portion 28b extending in the second direction. The second bridging region 38 connects, via a p-type silicon carbide region, two adjacent anode regions 34 that are separated from each other with the n-type second portion 28b therebetween.

[0223] The distance in the second direction between two adjacent second bridging regions 38 is, for example, smaller than the width in the first direction of the transistor region 101. The distance in the second direction between two adjacent second bridging regions 38 is, for example, not less than 10 μm and not more than 200 μm.

[0224] The width of the second cross-linked region 38 in the second direction is, for example, smaller than the distance between two adjacent second portions 28b. The distance between two adjacent second portions 28b is, for example, 3 μm or more and 30 μm or less. The width of the second cross-linked region 38 in the second direction is, for example, 1 μm or more and 10 μm or less.

[0225] The distance between two adjacent second portions 28b is, for example, substantially equal to the distance between two adjacent first portions 28a.

[0226] The second bridging region 38 contains, for example, aluminum (Al) as a p-type impurity. The p-type impurity concentration of the second bridging region 38 is, for example, 1×10 16 cm -3 More than 1×10 21 cm -3 The p-type impurity concentration of the second bridging region 38 is, for example, substantially the same as the p-type impurity concentration of the anode region 34. The p-type impurity concentration of the second bridging region 38 is, for example, substantially the same as the p-type impurity concentration of the first bridging region 36.

[0227] The depth of the second cross-linked region 38 is, for example, 0.3 μm or more and 1.0 μm or less. The depth of the second cross-linked region 38 is, for example, substantially the same as the depth of the anode region 34. The depth of the second cross-linked region 38 is, for example, substantially the same as the depth of the first cross-linked region 36.

[0228] Although FIG. 29 illustrates an example in which two second cross-linking regions 38 are arranged in the second direction, three or more second cross-linking regions 38 may be arranged.

[0229] 30(a), 30(b), and 31 are diagrams showing the boundary portion between the transistor region 101 and the diode region 102. FIG.

[0230] As shown in FIGS. 30(b) and 31, the silicon carbide layer 10 at the boundary between the transistor region 101 and the diode region 102 includes a p-type third bridging region 40 (seventh silicon carbide region).

[0231] The p-type third bridging region 40 is provided between the drift region 28 and the first plane P1. The third bridging regions 40 are repeatedly arranged in the second direction.

[0232] The third bridging region 40 connects the body region 30 and the anode region 34 adjacent to each other in the first direction.

[0233] The third bridging region 40 divides the drift region 28 extending in the second direction on the first surface. The third bridging region 40 connects, via a p-type silicon carbide region, the body region 30 and the anode region 34 that are adjacent to each other and are separated from each other with the n-type drift region 28 therebetween.

[0234] The first cross-linking region 36, the second cross-linking region 38, and the third cross-linking region 40 are, for example, arranged side by side in a first direction.

[0235] The distance in the second direction between two adjacent third bridging regions 40 is, for example, smaller than the width in the first direction of the transistor region 101. The distance in the second direction between two adjacent third bridging regions 40 is, for example, not less than 10 μm and not more than 200 μm.

[0236] The width of the third cross-linked region 40 in the second direction is, for example, smaller than the distance between two adjacent second portions 28b. The distance between two adjacent second portions 28b is, for example, 3 μm or more and 30 μm or less. The width of the third cross-linked region 40 in the second direction is, for example, 1 μm or more and 10 μm or less.

[0237] The third bridging region 40 contains, for example, aluminum (Al) as a p-type impurity. The p-type impurity concentration of the third bridging region 40 is, for example, 1×10 16 cm -3 More than 1×10 21 cm -3 The p-type impurity concentration of the third bridging region 40 is, for example, substantially the same as the p-type impurity concentration of the body region 30 and the anode region 34. The p-type impurity concentration of the third bridging region 40 is, for example, substantially the same as the p-type impurity concentration of the first bridging region 36. The p-type impurity concentration of the third bridging region 40 is, for example, substantially the same as the p-type impurity concentration of the second bridging region 38.

[0238] The depth of the third bridging region 40 is, for example, 0.3 μm or more and 1.0 μm or less. The depth of the third bridging region 40 is, for example, substantially the same as the depth of the body region 30 and the anode region 34. The depth of the third bridging region 40 is, for example, substantially the same as the depth of the first bridging region 36. The depth of the third bridging region 40 is, for example, substantially the same as the depth of the second bridging region 38.

[0239] Although FIG. 31 illustrates an example in which two third cross-linking regions 40 are arranged in the second direction, three or more third cross-linking regions 40 may be arranged.

[0240] The occupancy rate per unit area of ​​the anode region 34 projected onto the first surface P1 is greater than the occupancy rate per unit area of ​​the body region 30 projected onto the first surface P1. In other words, in a region of a given size, the occupancy rate of the anode region 34 projected onto the first surface P1 is greater than the occupancy rate of the body region 30 projected onto the first surface P1. That is, the occupancy rate of the pn junction diode in the diode region 102 is greater than the occupancy rate of the pn junction diode in the transistor region 101.

[0241] The occupancy rate per unit area of ​​the anode region 34 projected onto the first surface P1 is, for example, 1.2 times or more and 3 times or less than the occupancy rate per unit area of ​​the body region 30 projected onto the first surface P1.

[0242] The unit area is not particularly limited as long as it is a size that allows comparison of the average occupancy rate of the body region 30 in the transistor region 101 and the average occupancy rate of the anode region 34 in the diode region 102. The unit area is, for example, 30 μm×30 μm=900 μm 2 It is.

[0243] In addition, the contact area per unit area between the source electrode 12 and the anode region 34 in the diode region 102 is larger than the contact area per unit area between the source electrode 12 and the body region 30 in the transistor region 101. That is, the contact resistance per unit area between the source electrode 12 and the anode region 34 in the diode region 102 is smaller than the contact resistance per unit area between the source electrode 12 and the body region 30 in the transistor region 101.

[0244] In the MOSFET 200 of the second embodiment, similarly to the MOSFET 100 of the first embodiment, the MOSFET 200 includes a p-type first bridging region 36 (fourth silicon carbide region), a p-type second bridging region 38 (sixth silicon carbide region), and a p-type third bridging region 40 (seventh silicon carbide region), so that the p-type body region 30 and the p-type anode region 34 extending in the second direction are connected by the p-type region in the first direction. The first bridging region 36, the second bridging region 38, and the third bridging region 40 connecting the body region 30 and the anode region 34 promote the movement of holes in the first direction, so that the start of operation of the pn junction diodes provided in the diode region 102 and the transistor region 101 and the rise of the forward current after the start of operation can be made uniform within the chip.

[0245] According to the MOSFET 200 of the second embodiment, the variation in the surge current flowing through the MOSFET can be suppressed within the chip, and therefore, according to the MOSFET 200 of the second embodiment, the surge current resistance is improved.

[0246] In the MOSFET 200 of the second embodiment, the depth of the p-type first bridging region 36 (fourth silicon carbide region) can be made deeper than the depth of the p-type body region 30 (second silicon carbide region). Also, the depth of the p-type second bridging region 38 (sixth silicon carbide region) can be made deeper than the depth of the p-type anode region 34 (fifth silicon carbide region).

[0247] In the MOSFET 200 of the second embodiment, the p-type impurity concentration of the p-type first bridging region 36 (fourth silicon carbide region) can be made higher than the p-type impurity concentration of the p-type body region 30 (second silicon carbide region). The p-type impurity concentration of the p-type second bridging region 38 (sixth silicon carbide region) can be made higher than the p-type impurity concentration of the p-type anode region 34 (fifth silicon carbide region).

[0248] In the MOSFET 200 of the second embodiment, the multiple first bridging regions 36 do not necessarily have to be aligned along the first direction. Similarly, the multiple second bridging regions 38 do not necessarily have to be aligned along the first direction. In addition, the first bridging region 36, the second bridging region 38, and the third bridging region 40 do not necessarily have to be arranged side by side in the first direction.

[0249] As described above, according to the second embodiment, it is possible to provide a semiconductor device with improved surge current resistance.

[0250] In the first and second embodiments, the crystal structure of SiC is 4H-SiC, but the present invention can be applied to devices using SiC with other crystal structures such as 6H-SiC, 3C-SiC, etc. Also, a plane other than the (0001) plane can be applied to the surface of the silicon carbide layer 10.

[0251] In the first and second embodiments, aluminum (Al) is exemplified as the p-type impurity, but boron (B) can also be used. In addition, nitrogen (N) and phosphorus (P) are exemplified as the n-type impurity, but arsenic (As), antimony (Sb), etc. can also be used.

[0252] Although some embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. For example, components of one embodiment may be replaced or changed with components of another embodiment. These embodiments and their modifications are included in the scope and spirit of the invention, and are included in the scope of the invention and its equivalents described in the claims. [Explanation of symbols]

[0253] 10 Silicon carbide layer 12 source electrode (first electrode) 14 Drain electrode (second electrode) 16 Gate insulating layer 18 Gate electrode 28 drift region (first silicon carbide region) 28a First Part 28b Second Part 30 Body region (second silicon carbide region) 32 source region (third silicon carbide region) 34 anode region (fifth silicon carbide region) 36 First bridge region (fourth silicon carbide region) 38 Second bridge region (sixth silicon carbide region) 40 third bridge region (seventh silicon carbide region) 100 MOSFET (semiconductor device) 101 Transistor Area 102 Diode Region P1 First Side P2 Second Side

Claims

1. a plurality of transistor regions and a plurality of diode regions arranged alternately in a first direction; The transistor region is A silicon carbide layer having a first surface and a second surface opposite to the first surface, a first silicon carbide region of n-type contacting the first surface, extending in a second direction perpendicular to the first direction, and having a plurality of first portions arranged in the first direction; a plurality of p-type second silicon carbide regions provided between the first silicon carbide region and the first surface, extending in the second direction and arranged in the first direction; an n-type third silicon carbide region provided between the second silicon carbide region and the first surface; a plurality of p-type fourth silicon carbide regions provided between the first silicon carbide region and the first surface, arranged in the second direction, and connecting two adjacent second silicon carbide regions; a silicon carbide layer comprising: a first electrode in contact with the first portion, the second silicon carbide region, the third silicon carbide region, and the fourth silicon carbide region; a second electrode in contact with the second surface; a plurality of gate electrodes extending in the second direction and arranged in the first direction, the gate electrodes facing the second silicon carbide region; a gate insulating layer provided between the gate electrode and the second silicon carbide region; Including, The diode region is the first silicon carbide region of n-type having a plurality of second portions in contact with the first surface and extending in the second direction; a plurality of p-type fifth silicon carbide regions provided between the first silicon carbide region and the first surface, extending in the second direction and arranged in the first direction; a plurality of p-type sixth silicon carbide regions provided between the first silicon carbide region and the first surface, arranged in the second direction, and connecting two adjacent fifth silicon carbide regions; The silicon carbide layer comprising: the first electrode in contact with the second portion, the fifth silicon carbide region, and the sixth silicon carbide region; the second electrode; the silicon carbide layer further includes a plurality of p-type seventh silicon carbide regions provided between the first silicon carbide region and the first surface, arranged in the second direction, and connecting adjacent ones of the second silicon carbide region and the fifth silicon carbide region.

2. 2 . The semiconductor device according to claim 1 , wherein an occupancy rate per unit area of ​​said fifth silicon carbide region projected onto said first surface is greater than an occupancy rate per unit area of ​​said second silicon carbide region projected onto said first surface.

3. 3 . The semiconductor device according to claim 2 , wherein the contact area per unit area between the first electrode and the fifth silicon carbide region is larger than the contact area per unit area between the first electrode and the second silicon carbide region.

4. The semiconductor device according to claim 1 , wherein a width of said sixth silicon carbide region in said second direction is smaller than a width of said fifth silicon carbide region in said first direction.

5. 2 . The semiconductor device according to claim 1 , wherein a distance between two adjacent said fourth silicon carbide regions in said second direction is smaller than a width of said transistor region in said first direction.

6. the fourth silicon carbide region extends in the first direction, the fourth silicon carbide region intersecting the second silicon carbide region; the sixth silicon carbide region extends in the first direction, the sixth silicon carbide region intersects with the fifth silicon carbide region, The semiconductor device according to claim 1 , wherein said fourth silicon carbide region, said sixth silicon carbide region, and said seventh silicon carbide region are continuous in said first direction.

7. a depth of the fourth silicon carbide region is greater than a depth of the second silicon carbide region; The semiconductor device according to claim 1 , wherein a depth of said sixth silicon carbide region is greater than a depth of said fifth silicon carbide region.

8. a p-type impurity concentration of the fourth silicon carbide region is higher than a p-type impurity concentration of the second silicon carbide region; 2 . The semiconductor device according to claim 1 , wherein a p-type impurity concentration of said sixth silicon carbide region is higher than a p-type impurity concentration of said fifth silicon carbide region.

9. 2. The semiconductor device according to claim 1 , wherein a second distance in the first direction between two adjacent second portions with the fifth silicon carbide region therebetween is equal to a first distance in the first direction between two adjacent first portions with the second silicon carbide region therebetween.

10. 2. The semiconductor device according to claim 1, wherein the width of said transistor region in said first direction is larger than the width of said diode region in said first direction.

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