Method for manufacturing substrate

Abstract

To reduce the number of photomasks used.SOLUTION: A method for manufacturing a substrate 21 includes: patterning a first conductive film F1 to provide a first conductive part 15A; depositing a first insulating film F2 on the first conductive film F1 and patterning a second conductive film F4 deposited on the first insulating film F2 to provide a second conductive part 15B; depositing a second insulating film F5 on the second conductive film F4 and exposing and developing a third insulating film F6 deposited on the second insulating film F5 to provide first and second openings F6B and F6C; etching the first and second insulating films F2 and F5 through the third insulating film F6 to provide a third opening F5B in the second insulating film F5, a fourth opening F2A in the first insulating film F2 and a fifth opening F5C in a first interlayer insulating film F5; connecting a first part 30A of a third conductive part 30 provided by patterning a third conductive film F7 deposited on the third insulating film F6 to the first conductive part 15A through the first, third and fourth openings F6B, F5B and F2A; and connecting a second part 30B of the third conductive part 30 to the second conductive part 15B through the second and fifth openings F6C and F5C.SELECTED DRAWING: Figure 13C

Description

[Technical field]

[0001] The technology disclosed in this specification relates to a method for manufacturing a substrate. [Background technology]

[0002] Conventionally, the method described in Patent Document 1 below is known as an example of a manufacturing method for a substrate constituting a liquid crystal display device. Patent Document 1 discloses an active matrix substrate as the substrate. The active matrix substrate has a plurality of pixel regions, at least one of which includes a pixel TFT, a pixel electrode, a first circuit TFT, and a drive circuit wiring connected to the first circuit TFT, the pixel TFT and the first circuit TFT are oxide semiconductor TFTs, the pixel electrode is formed from an upper transparent conductive film, the drive circuit wiring includes a transparent wiring portion formed from a lower transparent conductive film located closer to the substrate 1 than the upper transparent conductive film, and at least one of the source electrode and the drain electrode of the first circuit TFT is formed from the lower transparent conductive film. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] International Publication No. 2018 / 043426 Summary of the Invention [Problem to be solved by the invention]

[0004] In the active matrix substrate described in the above-mentioned Patent Document 1, the second wiring connected to the source electrode of the first circuit TFT is connected to the gate bus line through an opening in the gate insulating layer. Therefore, when manufacturing the active matrix substrate, a dedicated photomask is required for patterning the gate insulating layer in order to provide an opening in the gate insulating layer. This poses the problem of a large number of photomasks being used.

[0005] The technology described in this specification was developed based on the above circumstances, and aims to reduce the number of photomasks used. [Means for solving the problem]

[0006] (1) A method for manufacturing a substrate according to the technology described in this specification includes forming a first conductive film on a base portion, patterning the first conductive film to provide a first conductive portion, forming a first insulating film on the first conductive film, forming a second conductive film on the first insulating film, patterning the second conductive film to provide a second conductive portion at a position that does not overlap with the first conductive portion, forming a second insulating film on the second conductive film, forming a third insulating film made of a photosensitive material on the second insulating film, exposing the third insulating film using a photomask and then developing it, thereby providing a first opening in the third insulating film at a position that overlaps with the first conductive portion and providing a second opening in the third insulating film at a position that overlaps with the second conductive portion, and forming a first insulating film and a second insulating film with a first insulating film and a second insulating film with a second insulating film and a second insulating film with a second insulating film and a first insulating film and a second insulating film with a second insulating film and a second insulating film and a first insulating film and a second insulating film and a second insulating film and a second insulating film and a first insulating film and a second insulating film and a second insulating film and a second insulating film and a second insulating film and a first insulating film and a second insulating film and a second insulating film and a second insulating film and a second insulating film and a second insulating film and a third ... By etching a film, a third opening is provided in the second insulating film at a position overlapping with the first opening, a fourth opening is provided in the first insulating film at a position overlapping with the first opening and the third opening, and a fifth opening is provided in the second insulating film at a position overlapping with the second opening; a third conductive film is deposited on the third insulating film; the third conductive film is patterned to provide a third conductive portion at a position overlapping with both the first conductive portion and the second conductive portion; a first portion of the third conductive portion that overlaps with the first conductive portion is connected to the first conductive portion through the first opening, the third opening, and the fourth opening; and a second portion of the third conductive portion that overlaps with the second conductive portion is connected to the second conductive portion through the second opening and the fifth opening.

[0007] (2) In addition to the above (1), the method for manufacturing the substrate may include patterning the second conductive film to provide a fourth conductive portion at a position that does not overlap any of the first conductive portion, the second conductive portion, and the third conductive portion, exposing the third insulating film using the photomask and then developing it to provide a sixth opening in the third insulating film at a position that overlaps with the fourth conductive portion, etching the second insulating film through the third insulating film to provide a seventh opening in the second insulating film at a position that overlaps with the sixth opening, patterning the third conductive film to provide a fifth conductive portion at a position that overlaps with the fourth conductive portion, connecting the fifth conductive portion to the fourth conductive portion through the sixth opening and the seventh opening, forming a fourth insulating film on the third conductive film, patterning the fourth insulating film to provide an eighth opening at the position that overlaps with the fifth conductive portion, forming a fourth conductive film on the fourth insulating film, patterning the fourth conductive film to provide a sixth conductive portion at a position that overlaps with the fifth conductive portion, and connecting the sixth conductive portion to the fifth conductive portion through the eighth opening.

[0008] (3) In addition to the above (1) or (2), the method for manufacturing the substrate further includes the steps of: patterning the first conductive film to provide a seventh conductive portion at a position not overlapping any of the first conductive portion, the second conductive portion, and the third conductive portion; exposing the third insulating film using the photomask and then developing the third insulating film to provide a ninth opening at a position overlapping the seventh conductive portion in the third insulating film; etching the first insulating film and the second insulating film through the third insulating film to provide a tenth opening at a position overlapping the ninth opening in the second insulating film; It is also possible to provide an eleventh opening at a position overlapping with the tenth opening, pattern the third conductive film to provide an eighth conductive portion at a position overlapping with the seventh conductive portion, connect the eighth conductive portion to the seventh conductive portion through the ninth opening, the tenth opening and the eleventh opening, form a fourth insulating film on the third conductive film, pattern the fourth insulating film to provide a twelfth opening at a position overlapping with the eighth conductive portion, form a fourth conductive film on the fourth insulating film, pattern the fourth conductive film to provide a ninth conductive portion at a position overlapping with the eighth conductive portion, and connect the ninth conductive portion to the eighth conductive portion through the twelfth opening.

[0009] (4) In addition to any one of (1) to (3), the method for manufacturing the substrate further includes patterning the second conductive film to provide a tenth conductive portion at a position not overlapping any of the first conductive portion, the second conductive portion, and the third conductive portion, exposing the third insulating film using the photomask and then developing the third insulating film to provide a thirteenth opening at a position overlapping the tenth conductive portion in the third insulating film, etching the second insulating film through the third insulating film to provide a fourteenth opening at a position overlapping the thirteenth opening in the second insulating film, It is also possible to pattern a conductive film to provide an 11th conductive portion at a position overlapping with the 10th conductive portion, connect the 11th conductive portion to the 10th conductive portion through the 13th opening and the 14th opening, form a fourth insulating film on the third conductive film, pattern the fourth insulating film to provide a 15th opening at a position overlapping with the 11th conductive portion, form a fourth conductive film on the fourth insulating film, pattern the fourth conductive film to provide a 12th conductive portion at a position overlapping with the 11th conductive portion, and connect the 12th conductive portion to the 11th conductive portion through the 15th opening. Effect of the Invention

[0010] According to the technique described in this specification, the number of photomasks used can be reduced. [Brief description of the drawings]

[0011] [Figure 1] FIG. 1 is a plan view of a liquid crystal panel and the like that constitute a liquid crystal display device according to a first embodiment; [Diagram 2] 1 is a schematic cross-sectional view of a liquid crystal panel according to a first embodiment of the present invention; [Diagram 3] FIG. 1 is a plan view of a display area of ​​an array substrate constituting a liquid crystal panel according to a first embodiment; [Figure 4] 1 is a cross-sectional view of the TFT and its surroundings on an array substrate according to a first embodiment; [Diagram 5] FIG. 2 is a plan view showing a connection portion between a first wiring portion and a second wiring portion that configure a first lead-out wiring in the array substrate according to the first embodiment; [Figure 6]6 is a cross-sectional view of the array substrate according to the first embodiment taken along line vi-vi in ​​FIG. 5 . [Figure 7] 1 is a plan view of the vicinity of a terminal (driver mounting area) on an array substrate according to a first embodiment; [Figure 8] 8 is a cross-sectional view of the array substrate according to the first embodiment taken along line viii-vii of FIG. 7 . [Figure 9A] FIG. 5 is a cross-sectional view similar to FIG. 4, illustrating a state in which a first metal film is patterned in a first step included in a manufacturing method of an array substrate according to the first embodiment; [Figure 9B] FIG. 5 is a cross-sectional view similar to FIG. 4, illustrating a state in which the semiconductor film is patterned in a third step included in the manufacturing method of the array substrate according to the first embodiment. [Figure 9C] FIG. 5 is a cross-sectional view similar to FIG. 4, illustrating a state in which the second metal film is patterned in a fourth step included in the manufacturing method of the array substrate according to the first embodiment; [Figure 10A] FIG. 7 is a cross-sectional view similar to FIG. 6, illustrating a state in which a first metal film is patterned in a first step included in the manufacturing method of the array substrate according to the first embodiment; [Figure 10B] FIG. 7 is a cross-sectional view similar to FIG. 6, illustrating a state in which the semiconductor film is patterned in a third step included in the manufacturing method of the array substrate according to the first embodiment. [Figure 10C] FIG. 7 is a cross-sectional view similar to FIG. 6, illustrating a state in which the second metal film is patterned in a fourth step included in the manufacturing method of the array substrate according to the first embodiment; [Figure 11A] FIG. 9 is a cross-sectional view similar to FIG. 8, illustrating a state in which a first metal film is patterned in a first step included in a manufacturing method of an array substrate according to the first embodiment; [Figure 11B] FIG. 9 is a cross-sectional view similar to FIG. 8, illustrating a state in which the semiconductor film is patterned in a third step included in the method for manufacturing the array substrate according to the first embodiment; [Figure 11C] 9 is a cross-sectional view similar to FIG. 8 , illustrating a state in which the second metal film is patterned in a fourth step included in the manufacturing method of the array substrate according to the first embodiment; [Figure 12A]FIG. 5 is a cross-sectional view similar to FIG. 4, illustrating a state in which the planarization film is exposed to light through a photomask in a sixth step included in the method for manufacturing the array substrate according to the first embodiment. [Figure 12B] FIG. 5 is a cross-sectional view similar to FIG. 4, illustrating a state in which the planarization film is developed in a sixth step included in the method for manufacturing the array substrate according to the first embodiment. [Figure 12C] FIG. 5 is a cross-sectional view similar to FIG. 4, illustrating a state in which the first interlayer insulating film is etched through the planarizing film in a seventh step included in the method for manufacturing the array substrate according to the first embodiment; [Figure 13A] FIG. 7 is a cross-sectional view similar to FIG. 6, illustrating a state in which the planarization film is exposed to light through a photomask in a sixth step included in the method for manufacturing the array substrate according to the first embodiment. [Figure 13B] FIG. 7 is a cross-sectional view similar to FIG. 6, illustrating a state in which the planarization film is developed in a sixth step included in the manufacturing method of the array substrate according to the first embodiment. [Figure 13C] FIG. 7 is a cross-sectional view similar to FIG. 6, illustrating a state in which the gate insulating film and the first interlayer insulating film are etched through the planarizing film in a seventh step included in the method for manufacturing the array substrate according to the first embodiment. [Figure 14A] FIG. 9 is a cross-sectional view similar to FIG. 8 , illustrating a state in which the planarization film is exposed through a photomask in a sixth step included in the method for manufacturing the array substrate according to the first embodiment. [Figure 14B] FIG. 9 is a cross-sectional view similar to FIG. 8 , illustrating a state in which the planarization film is developed in a sixth step included in the method for manufacturing the array substrate according to the first embodiment. [Figure 14C] FIG. 9 is a cross-sectional view similar to FIG. 8 , illustrating a state in which the gate insulating film and the first interlayer insulating film are etched through the planarizing film in a seventh step included in the method for manufacturing the array substrate according to the first embodiment. [Figure 15A] FIG. 5 is a cross-sectional view similar to FIG. 4, illustrating a state in which the third metal film is patterned in an eighth step included in the manufacturing method of the array substrate according to the first embodiment; [Figure 15B] FIG. 5 is a cross-sectional view similar to FIG. 4, illustrating a state in which the first transparent electrode film is patterned in a ninth step included in the manufacturing method of the array substrate according to the first embodiment. [Figure 15C]FIG. 5 is a cross-sectional view similar to FIG. 4, illustrating a state in which the second interlayer insulating film is patterned in a tenth step included in the method for manufacturing the array substrate according to the first embodiment; [Figure 15D] FIG. 5 is a cross-sectional view similar to FIG. 4, illustrating a state in which the second transparent electrode film is patterned in an eleventh step included in the manufacturing method of the array substrate according to the first embodiment; [Figure 16A] FIG. 7 is a cross-sectional view similar to FIG. 6, illustrating a state in which the third metal film is patterned in an eighth step included in the method for manufacturing the array substrate according to the first embodiment; [Figure 16B] FIG. 7 is a cross-sectional view similar to FIG. 6, illustrating a state in which the first transparent electrode film is patterned in a ninth step included in the manufacturing method of the array substrate according to the first embodiment. [Figure 16C] FIG. 7 is a cross-sectional view similar to FIG. 6, illustrating a state in which the second interlayer insulating film is patterned in a tenth step included in the method for manufacturing the array substrate according to the first embodiment; [Figure 16D] 7 is a cross-sectional view similar to FIG. 6 showing a state in which the second transparent electrode film is patterned in an eleventh step included in the manufacturing method of the array substrate according to the first embodiment; [Figure 17A] FIG. 9 is a cross-sectional view similar to FIG. 8, illustrating a state in which the third metal film is patterned in an eighth step included in the manufacturing method of the array substrate according to the first embodiment; [Figure 17B] 9 is a cross-sectional view similar to FIG. 8 showing a state in which the first transparent electrode film is patterned in a ninth step included in the manufacturing method of the array substrate according to the first embodiment; [Figure 17C] 9 is a cross-sectional view similar to FIG. 8 , illustrating a state in which the second interlayer insulating film is patterned in a tenth step included in the method for manufacturing the array substrate according to the first embodiment; [Figure 17D] 9 is a cross-sectional view similar to FIG. 8 , illustrating a state in which the second transparent electrode film is patterned in an eleventh step included in the method for manufacturing the array substrate according to the first embodiment; DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0012] <Embodiment 1> The first embodiment will be described with reference to Fig. 1 to Fig. 17C. A liquid crystal panel (display device, display panel) 11 provided in a liquid crystal display device 10 will be illustrated. Note that the X-axis, Y-axis, and Z-axis are shown in a part of each drawing, and each axis direction is drawn to be the direction shown in each drawing. Also, the up-down direction is based on Fig. 2, Fig. 4, Fig. 6, Fig. 8, Fig. 9A to Fig. 17D, and the upper side of each drawing is the front side and the lower side of each drawing is the back side.

[0013] 1, a liquid crystal display device 10 includes at least a horizontally elongated rectangular liquid crystal panel 11 capable of displaying an image, and a backlight device (illumination device) that is an external light source that irradiates the liquid crystal panel 11 with light to be used for display. The short side direction of this liquid crystal panel 11 coincides with the Y-axis direction, the long side direction with the X-axis direction, and the plate thickness direction with the Z-axis direction. The backlight device is disposed on the rear side (back surface side) of the liquid crystal panel 11, and includes, for example, a light source (e.g., an LED) that emits white light, and an optical member that converts the light from the light source into planar light by applying an optical effect.

[0014] As shown in FIG. 1, the central portion of the display surface of the liquid crystal panel 11 is a display area AA (the area surrounded by a dashed line in FIG. 1) where an image is displayed. In contrast, the outer peripheral portion of a rectangular frame (picture frame) surrounding the display area AA on the display surface of the liquid crystal panel 11 is a non-display area NAA where no image is displayed. The liquid crystal panel 11 is formed by bonding a pair of substrates 20, 21. The front side (front side) of the pair of substrates 20, 21 is the counter substrate 20, and the back side (rear side) is the array substrate (substrate) 21. Both the counter substrate 20 and the array substrate 21 are formed by laminating various films on the inner side of a glass substrate. A polarizing plate is attached to the outer side of each of the substrates 20, 21.

[0015] 1, the short side dimension of the counter substrate 20 is shorter than the short side dimension of the array substrate 21. The counter substrate 20 is attached to the array substrate 21 in such a manner that one end in the short side direction (Y-axis direction) is aligned with the array substrate 21. Therefore, the other end in the short side direction of the array substrate 21 is an exposed portion 21A that protrudes laterally and is exposed relative to the counter substrate 20. The entire exposed portion 21A is a non-display area NAA, and a driver (signal supply unit) 12 and a flexible substrate 13 for supplying various signals are mounted thereon.

[0016] The driver 12 is an LSI chip having a driving circuit therein, and processes various signals transmitted by the flexible substrate 13. The driver 12 is mounted on the exposed portion 21A of the array substrate 21 by COG (Chip On Glass). The driver 12 is connected to a terminal 16 (see FIG. 7) provided in the mounting area of ​​the driver 12 in the exposed portion 21A via an anisotropic conductive film. The flexible substrate 13 is configured by forming a number of wiring patterns (not shown) on a base material made of a synthetic resin material (e.g., polyimide resin, etc.) having insulating properties and flexibility, and one end side is connected to the exposed portion 21A of the array substrate 21, and the other end side is connected to an external control substrate (signal supply source). Various signals supplied from the control substrate are transmitted to the liquid crystal panel 11 via the flexible substrate 13.

[0017] As shown in FIG. 1, in the non-display area NAA of the array substrate 21, a pair of gate circuit units 14 are provided so as to sandwich the display area AA from both sides in the X-axis direction. The gate circuit units 14 are provided monolithically on the array substrate 21 to supply scanning signals to gate wirings 26 described later. In the non-display area NAA of the array substrate 21, in an area between the display area AA and the driver 12 in the Y-axis direction, a plurality of lead-out wirings 15 are provided, which are led out from the source wirings 27 described later to the non-display area NAA. The lead-out wirings 15 are connected to the ends of the source wirings 27 on the driver 12 side and to terminals 16 (see FIG. 7) provided in the mounting area of ​​the driver 12, and transmit signals output from the driver 12 to the source wirings 27. The plurality of lead-out wirings 15 are routed so as to spread out in a fan shape from the driver 12 side toward the display area AA side.

[0018] 2, the liquid crystal panel 11 has a liquid crystal layer (medium layer) 22 that contains liquid crystal molecules, which are a substance that fills the internal space between the pair of substrates 20, 21 and whose optical properties change when an electric field is applied. The liquid crystal layer 22 is sealed by a seal portion 17 that surrounds the internal space between the pair of substrates 20, 21. The seal portion 17 is disposed in the non-display area NAA and is formed in a square frame shape (endless ring shape) so as to surround the entire internal space between both substrates 20, 21.

[0019] As shown in Fig. 3, in the display area AA on the inner surface side of the array substrate 21 facing the counter substrate 20, TFTs (switching elements, thin film transistors) 23 and pixel electrodes (sixth conductive portions) 24 are provided. The TFTs 23 and pixel electrodes 24 are arranged in a matrix shape (row and column shape) with a gap between them along the X-axis direction and the Y-axis direction. A plurality of gate wirings (scanning wirings) 26 and source wirings (image wirings, data wirings) 27 are arranged around the TFTs 23 and pixel electrodes 24, each of which is perpendicular (intersecting) to each other. The gate wirings 26 extend along the X-axis direction, and a plurality of source wirings 27 are arranged with a gap between them along the Y-axis direction. The source wirings 27 extend along the Y-axis direction, and a plurality of source wirings 27 are arranged with a gap between them along the X-axis direction. The gate wiring 26 is connected to the gate electrode 23A of the TFT 23, the source wiring 27 is connected to the source electrode 23B of the TFT 23, and the pixel electrode 24 is connected to the drain electrode (fourth conductive portion) 23C of the TFT 23 via an intermediate electrode (fifth conductive portion) 29 (see FIG. 4). When the TFT 23 is driven based on a scanning signal transmitted to the gate wiring 26, it is possible to charge the pixel electrode 24 to a potential based on an image signal transmitted to the source wiring 27. The pixel electrode 24 has a vertically long rectangular shape in plan view. A plurality of slits 24A are formed in the pixel electrode 24.

[0020] In addition, in the display area AA of the counter substrate 20, a plurality of color filters are provided at positions facing each pixel electrode 24 on the array substrate 21 side. The color filters are made of three colors, R (red), G (green), and B (blue), repeatedly arranged in a predetermined order, and together with the pixel electrodes 24, form pixels of each color (red pixels, green pixels, and blue pixels). The three pixels, red pixels, green pixels, and blue pixels, form a display pixel capable of displaying a color of a predetermined gradation. In addition, a light-shielding portion (black matrix) is formed between each color filter to prevent color mixing.

[0021] As shown in FIG. 4, a common electrode 25 is provided in the display area AA on the inner surface side of the array substrate 21. The common electrode 25 is formed in a generally solid shape so as to extend at least over the entire display area AA, and is arranged so as to overlap all the pixel electrodes 24 on the lower layer side. A common potential signal is supplied to the common electrode 25 by a common wiring 28, and the common electrode 25 is thereby maintained at a common potential (reference potential). When the pixel electrode 24 is charged to a potential based on an image signal transmitted to the source wiring 27 in response to the driving of the TFT 23, a potential difference is generated between the pixel electrode 24 and the common electrode 25. Then, a fringe electric field (oblique electric field) including a component along the plate surface of the array substrate 21 and a component in the normal direction to the plate surface of the array substrate 21 is generated between the common electrode 25 and the opening edge of the slit 24A in the pixel electrode 24. Therefore, by utilizing this fringe electric field, the orientation state of the liquid crystal molecules contained in the liquid crystal layer 22 can be controlled, and a predetermined display is performed based on the orientation state of the liquid crystal molecules. That is, the liquid crystal panel 11 according to this embodiment operates in a FFS (Fringe Field Switching) mode.

[0022] As shown in Fig. 3, a common wiring 28 connected to the common electrode 25 is provided in the display area AA on the inner surface side of the array substrate 21. A common potential signal is supplied to the common wiring 28 by the driver 12 or the flexible substrate 13 (see Fig. 1). The common wiring 28 is arranged so as to overlap with the gate wiring 26 and the source wiring 27, and forms a substantially lattice shape in a plan view. The common wiring 28 is laid out over almost the entire display area AA, thereby making it possible to reduce the resistance distribution of the common electrode 25.

[0023] Here, various films laminated on the glass substrate (base portion) 21GS of the array substrate 21 will be described in detail with reference to Fig. 4. As shown in Fig. 4, on the glass substrate 21GS of the array substrate 21, at least a first metal film (first conductive film) F1, a gate insulating film (first insulating film) F2, a semiconductor film F3, a second metal film (second conductive film) F4, a first interlayer insulating film (second insulating film) F5, a planarizing film (third insulating film) F6, a third metal film (third conductive film) F7, a first transparent electrode film (fifth conductive film) F8, a second interlayer insulating film (fourth insulating film) F9, a second transparent electrode film (fourth conductive film) F10, and an alignment film are laminated in this order from the lower layer side (glass substrate 21GS side). Of these, the first metal film F1 is shown in Figures 9A, 10A and 11A, the semiconductor film F3 is shown in Figures 9B, 10B and 11B, the second metal film F4 is shown in Figures 9C, 10C and 11C, the third metal film F7 is shown in Figures 15A, 16A and 17A, the first transparent electrode film F8 is shown in Figures 15B, 16B and 17B, and the second transparent electrode film F10 is shown in Figures 15D, 16D and 17D.

[0024] The first metal film F1, the second metal film F4, and the third metal film F7 are each a single layer film made of one type of metal material selected from copper, titanium, aluminum, molybdenum, tungsten, etc., or a laminated film or alloy made of different types of metal materials, and are conductive. The semiconductor film F3 is made of a thin film using a semiconductor material such as an oxide semiconductor or amorphous silicon. The gate insulating film F2, the first interlayer insulating film F5, and the second interlayer insulating film F9 are made of silicon nitride (SiN x ), silicon oxide (SiO 2 ). The planarization film F6 is made of an organic material such as PMMA (acrylic resin) having photosensitivity. The first transparent electrode film F8 and the second transparent electrode film F10 are made of a transparent electrode material (e.g., ITO (Indium Tin Oxide) or IZO (Indium Zinc Oxide)) and are conductive. The alignment film is made of an alignment film material such as polyimide, and is formed in a solid shape so as to extend at least over the entire display area AA. An alignment film similar to that of the array substrate 21 is also provided on the innermost surface of the counter substrate 20.

[0025] The relationship between each film formed on the array substrate 21 and the structures (TFT 23, pixel electrode 24, common electrode 25, common wiring 28, and intermediate electrode 29) provided in the display area AA of the array substrate 21 will be described in detail. First, as shown in FIG. 4, the TFT 23 has a gate electrode 23A, a source electrode 23B, a drain electrode 23C, and a semiconductor portion 23D. The gate electrode 23A is made of a first metal film F1. The gate wiring 26 is made of a part of the first metal film F1 that is different from the gate electrode 23A and is connected to the gate electrode 23A. The semiconductor portion 23D is made of a semiconductor film F3 and is superimposed on the upper layer side of the gate electrode 23A via a gate insulating film F2. The source electrode 23B and the drain electrode 23C are both made of a second metal film F4 and are directly laminated on the semiconductor portion 23D. The source electrode 23B is connected to a part of the semiconductor portion 23D (the end on the left side in FIG. 4). The drain electrode 23C is connected to a part of the semiconductor portion 23D (the end on the right side in FIG. 4) at a position spaced apart from the source electrode 23B in the X-axis direction. The source wiring 27 is made of a part of the second metal film F4 separate from the source electrode 23B and the drain electrode 23C, and is connected to the source electrode 23B.

[0026] As shown in FIG. 4, the common wiring 28 is made of a third metal film F7. The common electrode 25 is made of a first transparent electrode film F8. The common electrode 25 is directly laminated on the common wiring 28 and is connected to almost the entire area of ​​the common wiring 28. The intermediate electrode 29 is made of a part of the third metal film F7 that is separate from the common wiring 28. The intermediate electrode 29 is disposed on the upper layer side of the drain electrode 23C, overlapping with the first interlayer insulating film F5 and the planarizing film F6. A first pixel contact hole (seventh opening) F5A is opened and provided at a position of the first interlayer insulating film F5 overlapping with both the intermediate electrode 29 and the drain electrode 23C. A second pixel contact hole (sixth opening) F6A is opened and provided at a position of the planarizing film F6 overlapping with both the intermediate electrode 29 and the drain electrode 23C. The intermediate electrode 29 and the drain electrode 23C are connected through a first pixel contact hole F5A and a second pixel contact hole F6A.

[0027] As shown in FIG. 4, the pixel electrode 24 is made of a second transparent electrode film F10. A part of the pixel electrode 24 is arranged to overlap the upper layer side of the intermediate electrode 29 via a second interlayer insulating film F9. A third pixel contact hole (eighth opening) F9A is opened and provided in the second interlayer insulating film F9 at a position where the second interlayer insulating film F9 overlaps with both the pixel electrode 24 and the intermediate electrode 29. The pixel electrode 24 and the intermediate electrode 29 are connected through the third pixel contact hole F9A. In this way, the drain electrode 23C and the pixel electrode 24 are connected through the intermediate electrode 29 located in the middle.

[0028] Next, the relationship between each film formed on the array substrate 21 and the structures (the lead-out wiring 15, the terminal 16, and the wiring connection portion 30) provided in the non-display area NAA of the array substrate 21 will be described in detail. First, the lead-out wiring 15 will be described. As shown in FIG. 1, the lead-out wiring 15 includes two types of lead-out wiring, a first lead-out wiring 15α and a second lead-out wiring 15β. In the following, when the lead-out wirings 15 are to be distinguished from one another, the subscript α is added to the symbol of the "first lead-out wiring" and the subscript β is added to the symbol of the "second lead-out wiring". When the lead-out wirings 15 are to be collectively referred to without distinction, the subscript is not added to the symbol. Among them, the second lead-out wiring 15β is made up of a portion of the second metal film F4 that is separate from the source electrode 23B, the drain electrode 23C, and the source wiring 27 over its entire length, and is connected to the end of the source wiring 27 to be connected. On the other hand, the first lead wiring 15α includes a portion made of the first metal film F1 (first wiring section 15A described later) and a portion made of the second metal film F4 (second wiring section 15B described later), which are connected by a wiring connection section (third conductive section) 30. The first lead wiring 15α and the second lead wiring 15β are arranged in multiples so as to be alternately arranged in the X-axis direction. As a result, even if the portion made of the first metal film F1 of the first lead wiring 15α and the second lead wiring 15β made of the second metal film F4 are adjacent to each other in the X-axis direction, the gate insulating film F2 (see FIG. 6) is interposed between them to prevent short-circuiting. This allows the arrangement pitch of the multiple lead wirings 15 to be narrowed, which is suitable for narrowing the frame and increasing the definition of the liquid crystal panel 11.

[0029] In detail, the first wiring part (first conductive part) 15A, which is a part on the terminal 16 side of the first lead wiring 15α, is composed of a part of the first metal film F1 that is different from the gate electrode 23A and the gate wiring 26, as shown in FIG. 5 and FIG. 6. The first wiring part 15A includes a part of the first lead wiring 15α that is connected to the terminal 16, as well as a part that extends in a diagonal direction with respect to the X-axis direction and the Y-axis direction (see FIG. 1). The end of the first wiring part 15A on the opposite side to the terminal 16 side is a first widened part (first contact part) 15A1 that is wider than the other part (main part). The second wiring part (second conductive part) 15B, which is a part on the source wiring 27 side of the first lead wiring 15α, is composed of a part of the second metal film F4 that is different from the source electrode 23B, the drain electrode 23C, and the source wiring 27, and is connected to the end of the source wiring 27 to be connected. The end of the second wiring portion 15B opposite to the source wiring 27 side is a second widened portion (second contact portion) 15B1 that is wider than the other portions. The first wiring portion 15A and the second wiring portion 15B are arranged so as not to overlap each other, specifically, the first widened portion 15A1 and the second widened portion 15B1 are arranged so as to be spaced apart in the Y-axis direction. The wiring connection portion 30 is made of a portion of the third metal film F7 that is separate from the common wiring 28 and the intermediate electrode 29. The wiring connection portion 30 extends along the Y-axis direction and is arranged across the first widened portion 15A1 of the first wiring portion 15A and the second widened portion 15B1 of the second wiring portion 15B.

[0030] 6, the wiring connection part 30 has a first overlapping part (first part) 30A arranged on the upper layer side overlapping the first widened part 15A1 of the first wiring part 15A via the gate insulating film F2, the first interlayer insulating film F5, and the planarizing film F6. A first wiring contact hole (fourth opening) F2A is opened and provided in the gate insulating film F2 at a position overlapping both the first overlapping part 30A of the wiring connection part 30 and the first widened part 15A1 of the first wiring part 15A. A second wiring contact hole (third opening) F5B is opened and provided in the first interlayer insulating film F5 at a position overlapping both the first overlapping part 30A of the wiring connection part 30 and the first widened part 15A1 of the first wiring part 15A. A third wiring contact hole (first opening) F6B is opened and provided at a position of the planarization film F6 overlapping both the first overlapping portion 30A of the wiring connection portion 30 and the first widened portion 15A1 of the first wiring portion 15A. The first overlapping portion 30A of the wiring connection portion 30 and the first widened portion 15A1 of the first wiring portion 15A are connected through the first wiring contact hole F2A, the second wiring contact hole F5B, and the third wiring contact hole F6B.

[0031] 6, the wiring connection part 30 has a second overlapping part (second part) 30B arranged on the upper layer side overlapping the second widened part 15B1 of the second wiring part 15B via the first interlayer insulating film F5 and the planarizing film F6. A fourth wiring contact hole (fifth opening) F5C is opened and provided in the first interlayer insulating film F5 at a position where the first interlayer insulating film F5 overlaps with both the second overlapping part 30B of the wiring connection part 30 and the second widened part 15B1 of the second wiring part 15B. A fifth wiring contact hole (second opening) F6C is opened and provided in the planarizing film F6 at a position where the first interlayer insulating film F5 overlaps with both the second overlapping part 30B of the wiring connection part 30 and the second widened part 15B1 of the second wiring part 15B. The second overlapping portion 30B of the wiring connection portion 30 and the second widened portion 15B1 of the second wiring portion 15B are connected through the fourth wiring contact hole F5C and the fifth wiring contact hole F6C. In this manner, the first wiring portion 15A and the second wiring portion 15B are connected through the wiring connection portion 30 located in the uppermost layer.

[0032] Next, the terminals 16 will be described. As shown in FIG. 7, a plurality of terminals 16 are arranged in a line in the mounting area of ​​the driver 12 in the exposed portion 21A of the array substrate 21. The terminals 16 are connected to bumps provided on the driver 12 via an anisotropic conductive film. The plurality of terminals 16 include a plurality of input terminals 31 for inputting signals to the driver 12 and output terminals 32 for receiving signals output from the driver 12. The input terminals 31 and the output terminals 32 each have a vertically elongated rectangular shape in plan view, and are arranged with their long sides parallel to the Y-axis direction and their short sides parallel to the X-axis direction. The input terminals 31 are located on the side farther from the display area AA (the side closer to the flexible substrate 13) in the mounting area of ​​the driver 12. The plurality of input terminals 31 are arranged in a line at intervals along the X-axis direction. The output terminals 32 are located on the side closer to the display area AA (the side farther from the flexible substrate 13) in the mounting area of ​​the driver 12. The multiple output terminals 32 are linearly arranged at intervals along the X-axis direction to form a single row. The signals output from the driver 12 to the output terminals 32 include at least an image signal. The signals output from the driver 12 to the output terminals 32 may include, in addition to the image signal, a scanning signal, a common potential signal of a common potential, a ground potential signal of a ground potential, and the like.

[0033] As shown in FIG. 7, the output terminals 32 each include a first terminal 32α connected to an end of the first lead-out wiring 15α and a second terminal 32β connected to an end of the second lead-out wiring 15β. In the following description, when the output terminals 32 are to be distinguished from one another, the subscript α is added to the symbol of the "first output terminal" and the subscript β is added to the symbol of the "second output terminal." When the output terminals 32 are to be collectively referred to without distinction, the subscript is not added to the symbol. The second terminal 32β is connected to an end of the second lead-out wiring 15β opposite to the end connected to the source wiring 27. On the other hand, the first terminal 32α is connected to an end of the first wiring portion 15A constituting the first lead-out wiring 15α opposite to the end connected to the wiring connection portion 30. The first terminals 32α and the second terminals 32β are arranged alternately and repeatedly in the X-axis direction, similar to the lead-out wiring 15.

[0034] As shown in FIG. 8, the output terminal 32 has a laminated structure in which a plurality of electrodes 33-36, 37-40 are laminated and connected to each other. Specifically, the first terminal 32α is composed of a first electrode (seventh conductive portion) 33, a second electrode (eighth conductive portion) 34, a third electrode (thirteenth conductive portion) 35, and a fourth electrode (ninth conductive portion) 36, in that order from the lower layer side. The first electrode 33 is composed of a portion of the first metal film F1 that is separate from the gate electrode 23A, the gate wiring 26, and the first wiring portion 15A. The first electrode 33 is connected to an end of the first wiring portion 15A that constitutes the first lead wiring 15α to be connected. The second electrode 34 is composed of a portion of the third metal film F7 that is separate from the common wiring 28, the intermediate electrode 29, and the wiring connection portion 30. The second electrode 34 is arranged to overlap the first electrode 33 on the upper layer side via the gate insulating film F2, the first interlayer insulating film F5, and the planarizing film F6. The third electrode 35 is a part of the first transparent electrode film F8 that is separate from the common electrode 25. The third electrode 35 is laminated on the upper layer side in a manner that makes direct contact with the second electrode 34 without an insulating film therebetween, and is connected to the second electrode 34. The fourth electrode 36 is a part of the second transparent electrode film F10 that is separate from the pixel electrode 24. The fourth electrode 36 is superimposed on the upper layer side of the third electrode 35 via the second interlayer insulating film F9. In this way, the first terminal 32α has a four-layer structure in which the number of laminated electrodes 33 to 36 is four.

[0035] As shown in FIG. 8, a first terminal contact hole (11th opening) F2B is provided at a position of the gate insulating film F2 overlapping both the first electrode 33 and the second electrode 34. A second terminal contact hole (10th opening) F5D is provided at a position of the first interlayer insulating film F5 overlapping both the first electrode 33 and the second electrode 34. A third terminal contact hole (9th opening) F6D is provided at a position of the planarizing film F6 overlapping both the first electrode 33 and the second electrode 34. The first electrode 33 and the second electrode 34 are connected through the first terminal contact hole F2B, the second terminal contact hole F5D, and the third terminal contact hole F6D. A fourth terminal contact hole (12th opening) F9B is provided at a position of the second interlayer insulating film F9 overlapping both the third electrode 35 and the fourth electrode 36. The third electrode 35 and the fourth electrode 36 are connected through the fourth terminal contact hole F9B. In this manner, the four electrodes 33 to 36 constituting the first terminal 32α are connected to each other and have the same potential.

[0036] As shown in FIG. 8, the second terminal 32β is composed of a fifth electrode (tenth conductive portion) 37, a sixth electrode (eleventh conductive portion) 38, a seventh electrode (fourteenth conductive portion) 39, and an eighth electrode (twelfth conductive portion) 40, in that order from the bottom. The fifth electrode 37 is composed of a portion of the second metal film F4 that is separate from the source electrode 23B, the drain electrode 23C, the source wiring 27, and the second wiring portion 15B. The fifth electrode 37 is connected to an end of the second lead wiring 15β to be connected. The sixth electrode 38 is composed of a portion of the third metal film F7 that is separate from the common wiring 28, the intermediate electrode 29, the wiring connection portion 30, and the second electrode 34. The sixth electrode 38 is disposed on the upper layer side superimposed on the fifth electrode 37 via the first interlayer insulating film F5 and the planarization film F6. The seventh electrode 39 is composed of a portion of the first transparent electrode film F8 that is separate from the common electrode 25 and the third electrode 35. The seventh electrode 39 is laminated on the upper layer side in a manner of directly contacting the sixth electrode 38 without an insulating film therebetween, and is connected to the sixth electrode 38. The eighth electrode 40 is formed of a part of the second transparent electrode film F10 that is separate from the pixel electrode 24 and the fourth electrode 36. The eighth electrode 40 is disposed on the upper layer side superimposed on the seventh electrode 39 via the second interlayer insulating film F9. In this way, the second terminal 32β has a four-layer structure in which the number of laminated electrodes 37 to 40 is four. That is, the second terminal 32β has a laminated structure in which the number of laminated layers is the same as that of the first terminal 32α, and the height (thickness) from the main surface of the glass substrate 21GS is approximately the same as that of the first terminal 32α. This stabilizes the posture of the driver 12 mounted on the first terminal 32α and the second terminal 32β via an anisotropic conductive film, and improves the connection reliability between the first terminal 32α and the second terminal 32β and the bumps on the driver 12 side.

[0037] As shown in FIG. 8, a fifth terminal contact hole (14th opening) F5E is provided at a position of the first interlayer insulating film F5 overlapping both the fifth electrode 37 and the sixth electrode 38. A sixth terminal contact hole (13th opening) F6E is provided at a position of the planarizing film F6 overlapping both the fifth electrode 37 and the sixth electrode 38. The fifth electrode 37 and the sixth electrode 38 are connected through the fifth terminal contact hole F5E and the sixth terminal contact hole F6E. A seventh terminal contact hole (15th opening) F9C is provided at a position of the second interlayer insulating film F9 overlapping both the seventh electrode 39 and the eighth electrode 40. The seventh electrode 39 and the eighth electrode 40 are connected through the seventh terminal contact hole F9C. In this way, the four electrodes 37 to 40 constituting the second terminal 32β are connected to each other and have the same potential.

[0038] The liquid crystal panel 11 according to this embodiment has the above-mentioned structure, and its manufacturing method will be described below. The manufacturing method of the liquid crystal panel 11 includes a counter substrate manufacturing process (CF substrate manufacturing process) for manufacturing the counter substrate 20, an array substrate manufacturing process (substrate manufacturing process) for manufacturing the array substrate 21, and a bonding process for bonding the manufactured counter substrate 20 and array substrate 21 together. Of these processes, the array substrate manufacturing process will be described below.

[0039] The array substrate manufacturing process includes a first step of forming a first metal film F1 and patterning it to form each structure (gate wiring 26, gate electrode 23A, etc.), a second step of forming a gate insulating film F2, a third step of forming a semiconductor film F3 and patterning it to form each structure (semiconductor portion 23D, etc.), a fourth step of forming a second metal film F4 and patterning it to form each structure (source wiring 27, source electrode 23B, drain electrode 23C, etc.), a fifth step of forming a first interlayer insulating film F5, and a fifth step of forming a planarizing film F6 and patterning it. The method includes at least a sixth step of etching the gate insulating film F2 and the first interlayer insulating film F5, an eighth step of depositing and patterning a third metal film F7 to form each structure (such as the common wiring 28 and the intermediate electrode 29), a ninth step of depositing and patterning a first transparent electrode film F8 to form each structure (such as the common electrode 25), a tenth step of depositing and patterning a second interlayer insulating film F9, and an eleventh step of depositing and patterning a second transparent electrode film F10 to form each structure (such as the pixel electrode 24).

[0040] The term "patterning" refers to the processing of a film based on a general photolithography method. Specifically, a photoresist film is formed on the film to be processed, the photoresist film is exposed to light by an exposure device through a photomask having a predetermined opening pattern, the photoresist film is developed, and etching is performed through the developed photoresist film, thereby processing the film to be processed, i.e., patterning is performed.

[0041] In the first step, a first metal film F1 is formed on the glass substrate 21GS of the array substrate 21, as shown by the two-dot chain lines in FIGS. 9A, 10A, and 11A. The formed first metal film F1 is patterned by the general photolithography method described above. When the first metal film F1 is patterned, a gate electrode 23A and a gate wiring 26 (see FIG. 3) are provided in a portion of the first metal film F1 that is arranged in the display area AA, as shown in FIG. 9A. A first wiring portion 15A that constitutes a first lead wiring 15α is provided in a portion of the first metal film F1 that is arranged in the non-display area NAA, as shown in FIG. 10A, and a first electrode 33 that constitutes a first terminal 32α is provided in a portion of the first metal film F1 that is arranged in the non-display area NAA, as shown in FIG. 11A.

[0042] In the second step, a gate insulating film F2 is formed on the first metal film F1 (see FIGS. 9B, 10B, and 11B). Then, in the third step, a semiconductor film F3 is formed on the gate insulating film F2 as shown by the two-dot chain lines in FIGS. 9B, 10B, and 11B. The formed semiconductor film F3 is patterned by a general photolithography method. When the semiconductor film F3 is patterned, a semiconductor section 23D is provided in a portion of the semiconductor film F3 that is disposed in the display area AA as shown in FIGS. 9B, 10B, and 11B. A semiconductor section of a switching element (such as a TFT) included in the gate circuit unit 14 is provided in a portion of the semiconductor film F3 that is disposed in the non-display area NAA.

[0043] In the fourth step, a second metal film F4 is formed on the semiconductor film F3 as shown by the two-dot chain lines in FIGS. 9C, 10C, and 11C. The formed second metal film F4 is patterned by a general photolithography method. When the second metal film F4 is patterned, the source electrode 23B, the drain electrode 23C, and the source wiring 27 (see FIG. 3) are provided in the portion of the second metal film F4 that is arranged in the display area AA as shown in FIG. 9C. The second wiring portion 15B and the second lead wiring 15β (see FIG. 7) that constitute the first lead wiring 15α are provided in the portion of the second metal film F4 that is arranged in the non-display area NAA as shown in FIG. 10C, and the fifth electrode 37 that constitutes the second terminal 32β is provided as shown in FIG. 11C.

[0044] In the fifth step, a first interlayer insulating film F5 is formed on the second metal film F4 (see FIG. 12A, FIG. 13A, and FIG. 14A). Subsequently, in the sixth step, as shown in FIG. 12A, FIG. 13A, and FIG. 14A, a planarizing film F6 is formed on the first interlayer insulating film F5. After that, the planarizing film F6 is exposed to light using an exposure device and a photomask PM. The planarizing film F6 is made of an organic material having positive photosensitivity. Here, the photomask PM will be described. The photomask PM includes a transparent base material PM1 having sufficiently high light transmittance, and a light-shielding film PM2 formed on the main surface of the base material PM1. The light-shielding film PM2 blocks exposure light from a light source of the exposure device, and has a partial opening PM3. In the photomask PM, the formation range of the light-shielding film PM2 is a light-shielding region that blocks light, and the formation range of the opening PM3 (the non-formation range of the light-shielding film PM2) is a light-transmitting region that transmits light.

[0045] In the sixth step, when the exposure light emitted from the light source of the exposure device is irradiated onto the planarization film F6 through the photomask PM having the above-mentioned configuration, the area of ​​the planarization film F6 overlapping with the light-shielding film PM2 is not exposed, and the area of ​​the planarization film F6 overlapping with the opening PM3 is selectively exposed. When development is performed following the exposure, as shown in FIG. 12B, FIG. 13B, and FIG. 14B, the exposed portion of the positive type planarization film F6 is removed because it is dissolved by the developer at a high speed, that is, the dissolution rate is high. On the other hand, the dissolution rate of the non-exposed portion is slow, so that it remains. The developed planarization film F6 is baked. In the above manner, the planarization film F6 is patterned. As a result, the second pixel contact hole F6A is provided in the portion of the planarization film F6 that is arranged in the display area AA, as shown in FIG. 12B. In the portion of the planarization film F6 arranged in the non-display area NAA, a third wiring contact hole F6B and a fifth wiring contact hole F6C are provided, as shown in FIG. 13B, and a third terminal contact hole F6D and a sixth terminal contact hole F6E are provided, as shown in FIG. 14B.

[0046] In the seventh step following the sixth step, the gate insulating film F2 and the first interlayer insulating film F5 are etched using the planarization film F6 patterned in the sixth step as a mask. When the etching is performed, the portions of the first interlayer insulating film F5 that overlap with the contact holes F6A to F6E of the planarization film F6 are selectively removed as shown in Figs. 12C, 13C, and 14C. As a result, the first pixel contact hole F5A is provided in the portion of the first interlayer insulating film F5 that is disposed in the display area AA as shown in Fig. 12C. The first pixel contact hole F5A is connected to the second pixel contact hole F6A. The drain electrode 23C is exposed to the outside above through the first pixel contact hole F5A and the second pixel contact hole F6A. In the portion of the first interlayer insulating film F5 disposed in the non-display area NAA, as shown in FIG. 13C, a second wiring contact hole F5B and a fourth wiring contact hole F5C are provided, and as shown in FIG. 14C, a second terminal contact hole F5D and a fifth terminal contact hole F5E are provided. As shown in FIG. 13C, the second wiring contact hole F5B communicates with the third wiring contact hole F6B. The fourth wiring contact hole F5C communicates with the fifth wiring contact hole F6C. The second wiring portion 15B is exposed to the upper outside through the fourth wiring contact hole F5C and the fifth wiring contact hole F6C. As shown in FIG. 14C, the second terminal contact hole F5D communicates with the third terminal contact hole F6D. The fifth terminal contact hole F5E communicates with the sixth terminal contact hole F6E. The fifth electrode 37 is exposed to the upper outside through the fifth terminal contact hole F5E and the sixth terminal contact hole F6E.

[0047] When etching is further performed, the gate insulating film F2 has a portion that overlaps with each of the contact holes F6A to F6E of the planarization film F6 and does not overlap with each structure (the drain electrode 23C, the second wiring portion 15B, and the fifth electrode 37) made of the second metal film F4, and is selectively removed. As a result, the first wiring contact hole F2A is provided in the portion of the gate insulating film F2 arranged in the non-display area NAA as shown in FIG. 13C, and the first terminal contact hole F2B is provided as shown in FIG. 14C. The first wiring contact hole F2A communicates with the second wiring contact hole F5B and the third wiring contact hole F6B as shown in FIG. 13C. The first wiring portion 15A is exposed to the upper outside through the first wiring contact hole F2A, the second wiring contact hole F5B, and the third wiring contact hole F6B. The first terminal contact hole F2B communicates with the second terminal contact hole F5D and the third terminal contact hole F6D as shown in FIG. 14C. The first electrode 33 is exposed to the outside above through the first terminal contact hole F2B, the second terminal contact hole F5D, and the third terminal contact hole F6D.

[0048] As described above, in the seventh step, as shown in FIG. 13C, the second wiring contact hole F5B, the first wiring contact hole F2A, and the fourth wiring contact hole F5C provided in the gate insulating film F2 and the first interlayer insulating film F5 are provided by locally etching the gate insulating film F2 and the first interlayer insulating film F5 through the first wiring contact hole F2A and the fourth wiring contact hole F5C of the planarizing film F6. That is, the planarizing film F6 in which the first wiring contact hole F2A and the fourth wiring contact hole F5C are provided is used as a mask to provide the second wiring contact hole F5B, the first wiring contact hole F2A, and the fourth wiring contact hole F5C in the gate insulating film F2 and the first interlayer insulating film F5, so that a dedicated photomask for patterning the gate insulating film F2 and the first interlayer insulating film F5 is not required. This makes it possible to reduce the number of photomasks used.

[0049] 12C, in the seventh step, the first pixel contact hole F5A in the first interlayer insulating film F5 is provided by locally etching the first interlayer insulating film F5 through the second pixel contact hole F6A in the planarizing film F6. In other words, the planarizing film F6 in which the second pixel contact hole F6A is provided is used as a mask to provide the first pixel contact hole F5A in the first interlayer insulating film F5, so that a dedicated photomask for patterning the first interlayer insulating film F5 is not required. This makes it possible to reduce the number of photomasks used.

[0050] 14C, in the seventh step, the second terminal contact hole F5D and the first terminal contact hole F2B provided in the gate insulating film F2 and the first interlayer insulating film F5 are provided by locally etching the gate insulating film F2 and the first interlayer insulating film F5 through the third terminal contact hole F6D in the planarizing film F6. In other words, the planarizing film F6 in which the third terminal contact hole F6D is provided is used as a mask to provide the second terminal contact hole F5D and the first terminal contact hole F2B in the gate insulating film F2 and the first interlayer insulating film F5, so that a dedicated photomask for patterning the gate insulating film F2 and the first interlayer insulating film F5 is not required. This makes it possible to reduce the number of photomasks used.

[0051] 14C, in the seventh step, the fifth terminal contact hole F5E in the first interlayer insulating film F5 is provided by locally etching the first interlayer insulating film F5 through the sixth terminal contact hole F6E in the planarizing film F6. In other words, the fourth terminal contact hole F9B is provided in the first interlayer insulating film F5 using the planarizing film F6 in which the sixth terminal contact hole F6E is provided as a mask, so that a dedicated photomask for patterning the first interlayer insulating film F5 is not required. This makes it possible to reduce the number of photomasks used.

[0052] In the eighth step, a third metal film F7 is formed on the planarization film F6. The formed third metal film F7 is patterned by a general photolithography method. When the third metal film F7 is patterned, a common wiring 28 and an intermediate electrode 29 are provided in a portion of the third metal film F7 that is disposed in the display area AA, as shown in FIG. 15A. Among them, the intermediate electrode 29 is connected to the drain electrode 23C through the first pixel contact hole F5A and the second pixel contact hole F6A that communicate with each other. A wiring connection portion 30 is provided in a portion of the third metal film F7 that is disposed in the non-display area NAA, as shown in FIG. 16A, and a second electrode 34 that constitutes the first terminal 32α and a sixth electrode 38 that constitutes the second terminal 32β are provided in a portion of the third metal film F7 that is disposed in the non-display area NAA, as shown in FIG. 17A. As shown in FIG. 16A, a part of the wiring connection part 30 is connected to the first wiring part 15A through the first wiring contact hole F2A, the second wiring contact hole F5B, and the third wiring contact hole F6B, and another part is connected to the second wiring part 15B through the fourth wiring contact hole F5C and the fifth wiring contact hole F6C. This allows the first wiring part 15A and the second wiring part 15B to be connected by the wiring connection part 30. As shown in FIG. 17A, the second electrode 34 is connected to the first electrode 33 through the first terminal contact hole F2B, the second terminal contact hole F5D, and the third terminal contact hole F6D. The sixth electrode 38 is connected to the fifth electrode 37 through the fifth terminal contact hole F5E and the sixth terminal contact hole F6E.

[0053] In the ninth step, the first transparent electrode film F8 is formed on the third metal film F7. The formed first transparent electrode film F8 is patterned by a general photolithography method. When the first transparent electrode film F8 is patterned, a common electrode 25 is provided on a portion of the first transparent electrode film F8 that is arranged in the display area AA, as shown in FIG. 15B. The common electrode 25 is connected to the common wiring 28 by directly contacting the common wiring 28. As shown in FIG. 17B, a third electrode 35 constituting the first terminal 32α and a seventh electrode 39 constituting the second terminal 32β are provided on a portion of the first transparent electrode film F8 that is arranged in the non-display area NAA. The third electrode 35 is connected to the second electrode 34 by directly contacting the second electrode 34. The seventh electrode 39 is connected to the sixth electrode 38 by directly contacting the sixth electrode 38.

[0054] In the tenth step, the second interlayer insulating film F9 is formed on the first transparent electrode film F8. The formed second interlayer insulating film F9 is patterned by a general photolithography method. When the second interlayer insulating film F9 is patterned, a third pixel contact hole F9A is provided in a portion of the second interlayer insulating film F9 that is disposed in the display area AA, as shown in FIG. 15C. The intermediate electrode 29 is exposed to the upper outside through the third pixel contact hole F9A. A fourth terminal contact hole F9B and a seventh terminal contact hole F9C are provided in a portion of the second interlayer insulating film F9 that is disposed in the non-display area NAA, as shown in FIG. 17C. The third electrode 35 is exposed to the upper outside through the fourth terminal contact hole F9B. The seventh electrode 39 is exposed to the upper outside through the fourth terminal contact hole F9B.

[0055] In the eleventh step, the second transparent electrode film F10 is formed on the second interlayer insulating film F9. The formed second transparent electrode film F10 is patterned by a general photolithography method. When the second transparent electrode film F10 is patterned, a pixel electrode 24 is provided in a portion of the second transparent electrode film F10 that is disposed in the display area AA, as shown in FIG. 15D. The pixel electrode 24 is connected to the intermediate electrode 29 through the third pixel contact hole F9A. A fourth electrode 36 constituting the first terminal 32α and an eighth electrode 40 constituting the second terminal 32β are provided in a portion of the second transparent electrode film F10 that is disposed in the non-display area NAA, as shown in FIG. 17D. The fourth electrode 36 is connected to the third electrode 35 through the fourth terminal contact hole F9B, as shown in FIG. 17D. The eighth electrode 40 is connected to the seventh electrode 39 through the seventh terminal contact hole F9C.

[0056] As described above, in this embodiment, a photomask is required in each of the first, third, fourth, sixth, eighth, ninth, tenth, and eleventh steps included in the array substrate manufacturing process, resulting in eight photomasks being used. Conventionally, a photomask was required in at least the second step in addition to the eight steps described above, resulting in nine photomasks being used. Compared to the conventional method, this embodiment can reduce the number of photomasks used by at least one.

[0057] As described above, the method for manufacturing the array substrate (substrate) 21 of this embodiment includes forming a first metal film (first conductive film) F1 on a glass substrate (base portion) 21GS, patterning the first metal film F1 to provide a first wiring portion (first conductive portion) 15A, forming a gate insulating film (first insulating film) F2 on the first metal film F1, forming a second metal film (second conductive film) F4 on the gate insulating film F2, patterning the second metal film F4 to provide a second wiring portion (second conductive portion) 15B at a position not overlapping with the first wiring portion 15A, and forming a first interlayer insulating film (second insulating film) F2 on the second metal film F4. A gate insulating film F2 and a first interlayer insulating film F5 are formed, a planarization film (third insulating film) F6 made of a photosensitive material is formed on the first interlayer insulating film F5, and the planarization film F6 is exposed using a photomask PM and then developed, thereby providing a third wiring contact hole (first opening) F6B at a position where the planarization film F6 overlaps with the first wiring portion 15A, and providing a fifth wiring contact hole (second opening) F6C at a position where the planarization film F6 overlaps with the second wiring portion 15B, and etching the gate insulating film F2 and the first interlayer insulating film F5 through the planarization film F6. A second wiring contact hole (third opening) F5B is provided at a position overlapping with the third wiring contact hole F6B, a first wiring contact hole (fourth opening) F2A is provided at a position overlapping with the third wiring contact hole F6B and the second wiring contact hole F5B in the gate insulating film F2, and a fourth wiring contact hole (fifth opening) F5C is provided at a position overlapping with the fifth wiring contact hole F6C in the first interlayer insulating film F5. A third metal film (third conductive film) F7 is formed on the planarizing film F6, and the third metal film F7 is patterned to form a first wiring contact hole (fifth opening) F5A. A wiring connection portion (third conductive portion) 30 is provided at a position overlapping both the wiring portion 15A and the second wiring portion 15B, and a first overlapping portion (first portion) 30A of the wiring connection portion 30 overlapping with the first wiring portion 15A is connected to the first wiring portion 15A through the third wiring contact hole F6B, the second wiring contact hole F5B and the first wiring contact hole F2A, and a second overlapping portion (second portion) 30B of the wiring connection portion 30 overlapping with the second wiring portion 15B is connected to the second wiring portion 15B through the fifth wiring contact hole F6C and the fourth wiring contact hole F5C.

[0058] The first wiring portion 15A made of the first metal film F1 is connected to the first overlapping portion 30A of the wiring connection portion 30 made of the third metal film F7 through the third wiring contact hole F6B, the second wiring contact hole F5B, and the first wiring contact hole F2A of the gate insulating film F2, the first interlayer insulating film F5, and the planarizing film F6. The second overlapping portion 30B of the wiring connection portion 30 is connected to the second wiring portion 15B made of the second metal film F4 through the fifth wiring contact hole F6C and the fourth wiring contact hole F5C of the first interlayer insulating film F5 and the planarizing film F6. The second wiring contact hole F5B, the first wiring contact hole F2A, and the fourth wiring contact hole F5C provided in the gate insulating film F2 and the first interlayer insulating film F5 are provided by locally etching the gate insulating film F2 and the first interlayer insulating film F5 through the first wiring contact hole F2A and the fourth wiring contact hole F5C of the planarizing film F6. In other words, the planarization film F6 in which the first wiring contact hole F2A and the fourth wiring contact hole F5C are provided is used as a mask to provide the second wiring contact hole F5B, the first wiring contact hole F2A, and the fourth wiring contact hole F5C in the gate insulating film F2 and the first interlayer insulating film F5, eliminating the need for a dedicated photomask for patterning the gate insulating film F2 and the first interlayer insulating film F5, thereby reducing the number of photomasks used.

[0059] In addition, the second metal film F4 is patterned to provide a drain electrode (fourth conductive portion) 23C at a position that does not overlap any of the first wiring portion 15A, the second wiring portion 15B, and the wiring connection portion 30, and the planarization film F6 is exposed using a photomask PM and then developed to provide a second pixel contact hole (sixth opening) F6A at a position that overlaps with the drain electrode 23C in the planarization film F6, and the first interlayer insulating film F5 is etched via the planarization film F6 to provide a first pixel contact hole (seventh opening) F5A at a position that overlaps with the second pixel contact hole F6A in the first interlayer insulating film F5, and the third metal film F7 is patterned to provide a second pixel contact hole (seventh opening) F5A at a position that overlaps with the drain electrode 23C in the first interlayer insulating film F5. an intermediate electrode (fifth conductive portion) 29 is provided in the drain electrode 23C position, the intermediate electrode 29 is connected to the drain electrode 23C through the second pixel contact hole F6A and the first pixel contact hole F5A, a second interlayer insulating film (fourth insulating film) F9 is formed on the third metal film F7, the second interlayer insulating film F9 is patterned to provide a third pixel contact hole (eighth opening) F9A at a position overlapping with the intermediate electrode 29, a second transparent electrode film (fourth conductive film) F10 is formed on the second interlayer insulating film F9, the second transparent electrode film F10 is patterned to provide a pixel electrode (sixth conductive portion) 24 at a position overlapping with the intermediate electrode 29, and the pixel electrode 24 is connected to the intermediate electrode 29 through the third pixel contact hole F9A.

[0060] The drain electrode 23C made of the second metal film F4 is connected to the intermediate electrode 29 made of the third metal film F7 through the second pixel contact hole F6A and the first pixel contact hole F5A in the first interlayer insulating film F5 and the planarizing film F6. The pixel electrode 24 made of the second transparent electrode film F10 is connected to the intermediate electrode 29 through the third pixel contact hole F9A in the second interlayer insulating film F9. Therefore, the drain electrode 23C and the pixel electrode 24 are connected through the intermediate electrode 29 located in the middle. The first pixel contact hole F5A provided in the first interlayer insulating film F5 is provided by locally etching the first interlayer insulating film F5 through the second pixel contact hole F6A in the planarizing film F6. In other words, the planarizing film F6 in which the second pixel contact hole F6A is provided is used as a mask to provide the first pixel contact hole F5A in the first interlayer insulating film F5, so that a dedicated photomask for patterning the first interlayer insulating film F5 is not required. This makes it possible to reduce the number of photomasks used.

[0061] Moreover, the first metal film F1 is patterned to provide a first electrode (seventh conductive portion) 33 at a position not overlapping any of the first wiring portion 15A, the second wiring portion 15B, and the wiring connection portion 30, and the planarization film F6 is exposed using a photomask PM and then developed to provide a third terminal contact hole (ninth opening) F6D at a position overlapping with the first electrode 33 in the planarization film F6, and the gate insulating film F2 and the first interlayer insulating film F5 are etched via the planarization film F6 to provide a second terminal contact hole (tenth opening) F5D at a position overlapping with the third terminal contact hole F6D in the first interlayer insulating film F5, and a first terminal contact hole (tenth opening) F5D at a position overlapping with the third terminal contact hole F6D and the second terminal contact hole F5D in the gate insulating film F2. a third terminal contact hole F6D, a second terminal contact hole F5D, and a first terminal contact hole F2B; a second interlayer insulating film F9 is formed on the third metal film F7; the second interlayer insulating film F9 is patterned to provide a fourth terminal contact hole (twelfth opening) F9B at a position overlapping with the second electrode 34; a second transparent electrode film F10 is formed on the second interlayer insulating film F9; the second transparent electrode film F10 is patterned to provide a fourth electrode (ninth conductive portion) 36 at a position overlapping with the second electrode 34; and the fourth electrode 36 is connected to the second electrode 34 through the fourth terminal contact hole F9B.

[0062] A second electrode 34 made of a third metal film F7 is connected to the first electrode 33 made of the first metal film F1 through the third terminal contact hole F6D, the second terminal contact hole F5D, and the first terminal contact hole F2B of the gate insulating film F2, the first interlayer insulating film F5, and the planarizing film F6. A fourth electrode 36 made of a second transparent electrode film F10 is connected to the second electrode 34 through the fourth terminal contact hole F9B of the second interlayer insulating film F9. Therefore, the first electrode 33 and the fourth electrode 36 are connected through the second electrode 34 located in the middle. The second terminal contact hole F5D and the first terminal contact hole F2B provided in the gate insulating film F2 and the first interlayer insulating film F5 are provided by locally etching the gate insulating film F2 and the first interlayer insulating film F5 through the third terminal contact hole F6D of the planarizing film F6. In other words, the planarization film F6 in which the third terminal contact hole F6D is provided is used as a mask to provide the second terminal contact hole F5D and the first terminal contact hole F2B in the gate insulating film F2 and the first interlayer insulating film F5, eliminating the need for a dedicated photomask for patterning the gate insulating film F2 and the first interlayer insulating film F5, thereby reducing the number of photomasks used.

[0063] In addition, the second metal film F4 is patterned to provide a fifth electrode (tenth conductive portion) 37 at a position not overlapping any of the first wiring portion 15A, the second wiring portion 15B, and the wiring connection portion 30, and the planarization film F6 is exposed using a photomask PM and then developed to provide a sixth terminal contact hole (thirteenth opening) F6E at a position overlapping with the fifth electrode 37 in the planarization film F6, and the first interlayer insulating film F5 is etched via the planarization film F6 to provide a fifth terminal contact hole (fourteenth opening) F5E at a position overlapping with the sixth terminal contact hole F6E in the first interlayer insulating film F5, and the third metal film F7 is patterned to provide a fifth electrode (tenth conductive portion) 37 at a position overlapping with the fifth electrode 37 in the planarization film F6. a sixth electrode (eleventh conductive portion) 38 is provided at a position where it overlaps with the sixth electrode 38, the sixth electrode 38 is connected to the fifth electrode 37 through the sixth terminal contact hole F6E and the fifth terminal contact hole F5E, a second interlayer insulating film F9 is formed on the third metal film F7, the second interlayer insulating film F9 is patterned to provide a seventh terminal contact hole (fifteenth opening) F9C at a position where it overlaps with the sixth electrode 38, a second transparent electrode film F10 is formed on the second interlayer insulating film F9, the second transparent electrode film F10 is patterned to provide an eighth electrode (twelfth conductive portion) 40 at a position where it overlaps with the sixth electrode 38, and the eighth electrode 40 is connected to the sixth electrode 38 through the seventh terminal contact hole F9C.

[0064] A sixth electrode 38 made of the third metal film F7 is connected to the fifth electrode 37 made of the second metal film F4 through the sixth terminal contact hole F6E and the fifth terminal contact hole F5E in the first interlayer insulating film F5 and the planarizing film F6. An eighth electrode 40 made of the second transparent electrode film F10 is connected to the sixth electrode 38 through the seventh terminal contact hole F9C in the second interlayer insulating film F9. Therefore, the fifth electrode 37 and the eighth electrode 40 are connected through the sixth electrode 38 located in the middle. The fifth terminal contact hole F5E provided in the first interlayer insulating film F5 is provided by locally etching the first interlayer insulating film F5 through the sixth terminal contact hole F6E in the planarizing film F6. In other words, the fourth terminal contact hole F9B is provided in the first interlayer insulating film F5 using the planarizing film F6 in which the sixth terminal contact hole F6E is provided as a mask, so that a dedicated photomask for patterning the first interlayer insulating film F5 is not required. This makes it possible to reduce the number of photomasks used.

[0065] <Other embodiments> The technology disclosed in this specification is not limited to the embodiments described above and illustrated in the drawings, and the following embodiments, for example, are also included in the technical scope.

[0066] (1) All of the plurality of lead-out wirings 15 may be second lead-out wirings 15β, and all of the plurality of output terminals 32 may be first terminals 32α. In this case, in order to connect the second lead-out wiring 15β made of the second metal film F4 to the first electrode 33 made of the first metal film F1 constituting the first terminal 32α, a connection structure shown in Fig. 6 (a structure in which the second lead-out wiring 15β and the first electrode 33 are connected by a connection portion (third conductive portion) made of the third metal film F7 like the wiring connection portion 30) may be adopted.

[0067] (2) All of the plurality of lead-out wirings 15 may be first lead-out wirings 15α, and all of the plurality of output terminals 32 may be second terminals 32β. In this case, in order to connect the first wiring portion 15A made of the first metal film F1 of the first lead-out wirings 15α to the fifth electrode 37 made of the second metal film F4 constituting the second terminal 32β, a connection structure shown in Fig. 6 (a structure in which the first wiring portion 15A and the fifth electrode 37 are connected by a connection portion (third conductive portion) made of the third metal film F7 like the wiring connection portion 30) may be adopted.

[0068] (3) The connection structure shown in FIG. 6 (a structure in which the first conductive portion and the second conductive portion are connected by the third conductive portion) can also be applied to structures other than the lead-out wiring 15 (for example, wiring and electrodes that constitute the gate circuit portion 14).

[0069] (4) All of the plurality of lead-out wirings 15 may be second lead-out wirings 15β, and all of the plurality of output terminals 32 may be second terminals 32β. In this case, the second lead-out wiring 15β made of the second metal film F4 may be directly connected to the fifth electrode 37 made of the second metal film F4, which constitutes the second terminal 32β.

[0070] (5) All of the plurality of lead-out wirings 15 may be the first lead-out wirings 15α, and all of the plurality of output terminals 32 may be the first terminals 32α. In this case, the first wiring portion 15A made of the first metal film F1 of the first lead-out wirings 15α may be directly connected to the first electrode 33 made of the first metal film F1 constituting the first terminal 32α.

[0071] (6) The first terminal 32α does not have to include the third electrode 35. In that case, the fourth electrode 36 is directly connected to the second electrode 34 through a fourth terminal contact hole F9B in the second interlayer insulating film F9.

[0072] (7) The second terminal 32β does not have to include the seventh electrode 39. In that case, the eighth electrode 40 is directly connected to the sixth electrode 38 through the seventh terminal contact hole F9C in the second interlayer insulating film F9.

[0073] (8) The cross-sectional configuration of the input terminal 31 may be the same as that of the first terminal 32α, or may be the same as that of the second terminal 32β. In this way, the input terminal 31 and the output terminal 32 each have a four-layer structure, and the height from the main surface of the glass substrate 21GS is approximately the same. This stabilizes the posture of the driver 12 mounted on the input terminal 31 and the output terminal 32β via an anisotropic conductive film, and improves the connection reliability between the input terminal 31 and the output terminal 32β and the bumps on the driver 12 side.

[0074] (9) The multiple output terminals 32 may be arranged in a staggered pattern in a plan view in the mounting area of ​​the driver 12.

[0075] (10) An insulating film (third interlayer insulating film) may be interposed between the third metal film F7 and the first transparent electrode film F8. In this case, a plurality of touch wirings (position detection wirings) made of the third metal film F7 may be provided instead of the common wiring 28, and the common electrode 25 made of the first transparent electrode film F8 may be divided into a plurality of touch electrodes (position detection electrodes), and each touch wiring may be individually connected to each touch electrode. To connect the touch electrode and the touch wiring, a contact hole (opening) may be formed in the insulating film interposed between the third metal film F7 and the first transparent electrode film F8. By adopting the above configuration, a touch panel function (position detection function) can be added to the liquid crystal panel 11.

[0076] (11) As described above in (10), when an insulating film is interposed between the third metal film F7 and the first transparent electrode film F8, it is also possible to form the pixel electrode 24 using the first transparent electrode film F8 and the common electrode 25 using the second transparent electrode film F10.

[0077] (12) The planarizing film F6 may be made of an organic material having negative photosensitivity.

[0078] (13) The gate circuit section 14 may be omitted.

[0079] (14) The display mode of the liquid crystal panel 11 may be VA mode, IPS mode, or the like other than FFS mode.

[0080] (15) The semiconductor film F3 may be a silicon thin film (polycrystalline silicon thin film).

[0081] (16) The base portion may be other than the glass substrate 21GS. For example, when the array substrate 21 includes a resin substrate, the resin substrate becomes the base portion. Also, as in (15) above, when the semiconductor film F3 is a silicon thin film, an insulating film or the like arranged above the semiconductor film F3 becomes the base portion.

[0082] (17) The liquid crystal panel 11 may be of a reflective or semi-transmissive type other than a transmissive type.

[0083] (18) A display panel other than the liquid crystal panel 11 (such as an organic electroluminescence (EL) display panel) may be used. [Explanation of symbols]

[0084] 15A...first wiring portion (first conductive portion), 15B...second wiring portion (second conductive portion), 21...array substrate (substrate), 21GS...glass substrate (base portion), 23C...drain electrode (fourth conductive portion), 24...pixel electrode (sixth conductive portion), 29...intermediate electrode (fifth conductive portion), 30...wiring connection portion (third conductive portion), 30A...first overlapping portion (first portion), 30B...second overlapping portion (second portion), 33...first electrode (seventh conductive portion), 34...second electrode (eighth conductive portion) ), 36...fourth electrode (ninth conductive portion), 37...fifth electrode (tenth conductive portion), 38...sixth electrode (eleventh conductive portion), 40...eighth electrode (twelfth conductive portion), F1...first metal film (first conductive film), F2...gate insulating film (first insulating film), F2A...first wiring contact hole (fourth opening), F2B...first terminal contact hole (eleventh opening), F4...second metal film (second conductive film), F5...first interlayer insulating film (second insulating film), F5A...first pixel Contact hole (7th opening), F5B...second wiring contact hole (3rd opening), F5C...fourth wiring contact hole (5th opening), F5D...second terminal contact hole (10th opening), F5E...fifth terminal contact hole (14th opening), F6...planarization film (3rd insulating film), F6A...second pixel contact hole (6th opening), F6B...third wiring contact hole (1st opening), F6C...fifth wiring contact hole (2nd opening), F6D...3rd terminal contact hole (9th opening), F6E...6th terminal contact hole (13th opening), F7...3rd metal film (3rd conductive film), F9...2nd interlayer insulating film (4th insulating film), F9A...3rd pixel contact hole (8th opening), F9B...4th terminal contact hole (12th opening), F9C...7th terminal contact hole (15th opening), F10...2nd transparent electrode film (4th conductive film), PM...photomask

Claims

1. forming a first conductive film on the base portion and patterning the first conductive film to provide a first conductive portion; forming a first insulating film on the first conductive film; forming a second conductive film on the first insulating film, and patterning the second conductive film to provide a second conductive portion at a position not overlapping the first conductive portion; forming a second insulating film on the second conductive film; forming a third insulating film made of a photosensitive material on the second insulating film, exposing the third insulating film using a photomask and developing the third insulating film, thereby providing a first opening at a position where the third insulating film overlaps the first conductive portion and providing a second opening at a position where the third insulating film overlaps the second conductive portion; by etching the first insulating film and the second insulating film through the third insulating film, a third opening is provided in the second insulating film at a position overlapping with the first opening, a fourth opening is provided in the first insulating film at a position overlapping with the first opening and the third opening, and a fifth opening is provided in the second insulating film at a position overlapping with the second opening; A method for manufacturing a substrate, comprising the steps of: depositing a third conductive film on the third insulating film; patterning the third conductive film to provide a third conductive portion at a position overlapping both the first conductive portion and the second conductive portion; connecting a first portion of the third conductive portion that overlaps with the first conductive portion to the first conductive portion through the first opening, the third opening, and the fourth opening; and connecting a second portion of the third conductive portion that overlaps with the second conductive portion to the second conductive portion through the second opening and the fifth opening.

2. patterning the second conductive film to provide a fourth conductive portion at a position not overlapping any of the first conductive portion, the second conductive portion, and the third conductive portion; exposing the third insulating film using the photomask and developing the third insulating film to form a sixth opening at a position overlapping the fourth conductive portion in the third insulating film; forming a seventh opening in the second insulating film at a position overlapping with the sixth opening by etching the second insulating film through the third insulating film; patterning the third conductive film to provide a fifth conductive portion at a position overlapping the fourth conductive portion; connecting the fifth conductive portion to the fourth conductive portion through the sixth opening and the seventh opening; forming a fourth insulating film on the third conductive film, and patterning the fourth insulating film to provide an eighth opening at a position overlapping the fifth conductive portion; 2. A method for manufacturing a substrate as described in claim 1, further comprising the steps of: depositing a fourth conductive film on the fourth insulating film; patterning the fourth conductive film to provide a sixth conductive portion at a position overlapping the fifth conductive portion; and connecting the sixth conductive portion to the fifth conductive portion through the eighth opening.

3. patterning the first conductive film to provide a seventh conductive portion at a position not overlapping any of the first conductive portion, the second conductive portion, and the third conductive portion; by exposing the third insulating film using the photomask and then developing the third insulating film, a ninth opening is provided at a position of the third insulating film overlapping the seventh conductive portion; by etching the first insulating film and the second insulating film through the third insulating film, a tenth opening is provided in the second insulating film at a position overlapping with the ninth opening, and an eleventh opening is provided in the first insulating film at a position overlapping with the ninth opening and the tenth opening; patterning the third conductive film to provide an eighth conductive portion at a position overlapping the seventh conductive portion; connecting the eighth conductive portion to the seventh conductive portion through the ninth opening, the tenth opening, and the eleventh opening; forming a fourth insulating film on the third conductive film, and patterning the fourth insulating film to provide a twelfth opening at a position overlapping the eighth conductive portion; 3. A method for manufacturing a substrate according to claim 1 or claim 2, further comprising the steps of: depositing a fourth conductive film on the fourth insulating film; patterning the fourth conductive film to provide a ninth conductive portion at a position overlapping the eighth conductive portion; and connecting the ninth conductive portion to the eighth conductive portion through the twelfth opening.

4. patterning the second conductive film to provide a tenth conductive portion at a position not overlapping any of the first conductive portion, the second conductive portion, and the third conductive portion; exposing the third insulating film using the photomask and then developing the third insulating film to form a thirteenth opening at a position of the third insulating film overlapping the tenth conductive portion; a fourth opening is formed in the second insulating film at a position overlapping with the third opening by etching the second insulating film through the third insulating film; patterning the third conductive film to provide an eleventh conductive portion at a position overlapping the tenth conductive portion; and connecting the eleventh conductive portion to the tenth conductive portion through the thirteenth opening and the fourteenth opening; forming a fourth insulating film on the third conductive film, and patterning the fourth insulating film to provide a fifteenth opening at a position overlapping the eleventh conductive portion; 3. A method for manufacturing a substrate according to claim 1 or claim 2, further comprising the steps of: depositing a fourth conductive film on the fourth insulating film; patterning the fourth conductive film to provide a twelfth conductive portion at a position overlapping the eleventh conductive portion; and connecting the twelfth conductive portion to the eleventh conductive portion through the fifteenth opening.

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