Semiconductor device and method for manufacturing semiconductor device

Abstract

To provide a semiconductor device capable of multiplying the number of carriers generated by a photoelectric effect from a light injected from a back surface.SOLUTION: A semiconductor device 11 comprises an embedded insulation layer 25 and a semiconductor region 27. A first region 29 of the semiconductor region 27, a second region 31 of the semiconductor region 27, and the embedded insulation layer 25 are disposed along a first shaft Ax1, and the first region 29 contains a first conductive type semiconductor 26. The second region 31 contains an avalanche photodiode region 32 disposed between the first region 29 and the embedded insulation layer 25. Each avalanche photodiode region 32 contains a first conductive type well region 33, a first conductive type first addition region 35, and a second conductive type high concentration region 37. The well region 33 is extended along a reference surface REF crossing the first shaft Ax1. The first addition region 35 and the high concentration region 37 are disposed along the reference surface REF, and between the well region 33 and the embedded insulation layer 25.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a semiconductor device and a method for fabricating a semiconductor device. [Background technology]

[0002] Patent Document 1 discloses a back-illuminated avalanche photodiode (APD) array. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2011-211070 A Summary of the Invention [Problem to be solved by the invention]

[0004] In Patent Document 1, a sensor semiconductor chip of an avalanche photodiode array and a separate control semiconductor chip (a control large scale integrated circuit) including a readout circuit are assembled into an assembly using a bonding technique such as bumping.

[0005] Assembly by bonding is complicated because it requires additional steps such as alignment of two semiconductor chips and a bump process. Assembly using bump technology may also be an obstacle to miniaturization of the sensor semiconductor chip. Such an assembly includes additional connection electrodes such as bump electrodes, which may cause operation delays and increased power consumption due to additional parasitic capacitance.

[0006] An object of the present invention is to provide a semiconductor device that enables multiplication of carriers generated by the photoelectric effect from light (photons) incident from the rear surface, and a method for manufacturing such a semiconductor device. [Means for solving the problem]

[0007] A semiconductor device according to a first aspect of the present invention comprises an insulating layer including a buried insulating layer in a support, and a semiconductor region provided in the support and including a first region and a second region, the first region of the semiconductor region, the second region of the semiconductor region, and the buried insulating layer are arranged along a first axis, the first region of the semiconductor region includes a semiconductor of a first conductivity type, and the second region of the semiconductor region includes avalanche photodiode regions arranged in an array between the first region of the semiconductor region and the buried insulating layer, each of the avalanche photodiode regions includes a well region of the first conductivity type, a first doped region of the first conductivity type, and a high concentration region of a second conductivity type, the well region extends along a reference plane intersecting the first axis in each of the avalanche photodiode regions, and the first doped region and the high concentration region are , the high concentration region is disposed along the reference surface, the high concentration region forms a junction with the well region, the first doped region reaches the well region and is electrically connected to each other, the first doped region and the high concentration region are disposed between the well region and the buried insulating layer, a dopant concentration of the high concentration region is greater than a dopant concentration of the well region, the second conductivity type is different from the first conductivity type, each of the avalanche photodiode regions further includes a second doped region of the second conductivity type, the first doped region, the second doped region, and the high concentration region are disposed along the reference surface between the well region and the buried insulating layer, the second doped region is located between the first doped region and the high concentration region, a dopant concentration of the second doped region is less than a dopant concentration of the high concentration region, and a dopant concentration of the second doped region is greater than a dopant concentration of the well region.

[0008] A method of fabricating a semiconductor device according to a second aspect of the present invention relates to a method of fabricating a semiconductor device having a plurality of avalanche photodiode regions, the method comprising: preparing a substrate including a semiconductor region including a first region and a second region, and a buried insulating layer provided on the semiconductor region, and forming a well region of a first conductivity type, a high concentration region of a second conductivity type, and a first doped region of the first conductivity type in the second region of the substrate in each of the avalanche photodiode regions, the first region of the semiconductor region, the second region of the semiconductor region, and the buried insulating layer being arranged along a first axis, the first region of the semiconductor region including a semiconductor of a first conductivity type, and the first doped region of the first conductivity type. the region and the high concentration region are arranged along a reference plane that intersects the first axis, the well region extends along the reference plane, the high concentration region and the first doped region are arranged along the reference plane between the well region and the buried insulating layer, the high concentration region and the first doped region are spaced apart from each other, a dopant concentration of the first doped region is greater than a dopant concentration of a semiconductor of the first conductivity type, a dopant concentration of the high concentration region is greater than a dopant concentration of the well region, and the second conductivity type is different from the first conductivity type. Effect of the Invention

[0009] According to the first and second aspects, a semiconductor device that enables multiplication of carriers generated by the photoelectric effect from light (photons) incident from the back surface, and a method for manufacturing such a semiconductor device can be provided. [Brief description of the drawings]

[0010] [Figure 1] FIG. 1 is a plan view showing the front surface of a semiconductor device according to the present embodiment. [Diagram 2] FIG. 2 is a plan view showing an exemplary pixel structure of the semiconductor device according to the present embodiment. [Diagram 3] FIG. 3 is a cross-sectional view taken along line III-III shown in FIG. [Figure 4]FIG. 4 is a diagram showing a depletion layer in the semiconductor device according to the present embodiment. [Diagram 5] FIG. 5 is a diagram illustrating one arrangement of adjacent avalanche photodiode regions. [Figure 6] FIG. 6 is a diagram showing another arrangement of adjacent avalanche photodiode regions. [Figure 7] FIG. 7 is a diagram showing a step in a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 8] FIG. 8 is a diagram showing a step in a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 9] FIG. 9 is a diagram showing a step in a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 10] FIG. 10 is a diagram showing a step in a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 11] FIG. 11 is a diagram showing a step in a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 12] FIG. 12 is a diagram showing a step in a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 13] FIG. 13 is a diagram showing a step in a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 14] FIG. 14 is a diagram showing a step in a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 15] FIG. 15 is a diagram showing a step in a method for manufacturing a semiconductor device according to an embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011] Hereinafter, each embodiment for carrying out the present invention will be described with reference to the drawings. In the following description, the same or similar parts are designated by the same or similar reference numerals, and duplicated description will be omitted.

[0012] FIG. 1 is a plan view showing a front surface of a semiconductor device according to the present embodiment. The semiconductor device 11 includes a plurality of pixels 13 and a peripheral circuit 15 configured to control these pixels 13. The peripheral circuit 15 is connected to the array of pixels 13 via a selection line that enables selection and non-selection of the pixels 13 and a signal line that reads pixel data from the pixels 13 so that imaging using the pixels 13 and reading out of signals from the pixels 13 can be controlled. Each of the pixels 13 includes an avalanche photodiode (APD). The semiconductor device 11 can constitute, for example, a silicon photon multiplier. The pixels 13 and the peripheral circuit 15 can be surrounded by a guard ring 14.

[0013] The semiconductor device 11 performs operations such as resetting the pixels 13, capturing an image using the pixels 13, and reading data from the pixels 13. The reset operation resets the accumulated charge in each pixel 13. The imaging operation accumulates carriers (one of a pair of charges generated by the photoelectric effect) from photons incident on the imaging area of ​​the semiconductor device 11 in an array of pixels 13. The data reading operation sequentially extracts the amount of charge accumulated in the pixels 13 during imaging in the form of an electrical signal to the peripheral circuit 15. For these operations, the peripheral circuit 15 can include signal processing circuits such as a selection circuit for the pixels 13, a circuit for holding a signal from the pixels 13, and an AD conversion circuit for the signal holding circuit.

[0014] Fig. 2 is a plan view showing an exemplary pixel structure of a semiconductor device according to the present embodiment, and Fig. 3 is a cross-sectional view taken along line III-III shown in Fig. 2.

[0015] 2 and 3, the semiconductor device 11 includes a support 23, and the pixel 13 is disposed within the support 23. Specifically, FIGS. 2 and 3 show one pixel section. The pixel 13 amplifies carriers 20 generated by the photoelectric effect from light LIN incident from a back surface 27b of the semiconductor region 27. The back surface 27b of the semiconductor region 27 is located opposite to a front surface 27c of the semiconductor region 27.

[0016] The semiconductor device 11 includes a buried insulating layer 25 in a support 23 and a semiconductor region 27 in the support 23. The semiconductor region 27 includes a first region 29 and a second region 31. The semiconductor region 27 may include silicon, and the buried insulating layer 25 may include an inorganic compound including a compound of silicon and oxygen, nitrogen, or fluorine. According to this semiconductor device 11, the support 23 including the buried insulating layer 25 and the semiconductor region 27 is derived from an SOI wafer.

[0017] The first region 29, the second region 31, and the buried insulating layer 25 are arranged along a first axis Ax1. The second region 31 is provided between the first region 29 and the buried insulating layer 25. The first region 29 includes a first conductive type semiconductor (hereinafter, referred to as a "first conductive type semiconductor 26"). The second region 31 may include the first conductive type semiconductor 26 in a portion thereof. The first conductive type may be, for example, a p-type. The second conductive type used in the subsequent description may be, for example, an n-type.

[0018] The first conductivity type semiconductor 26 may be the base semiconductor in the wafer used in production, for example an SOI wafer, and has a low dopant concentration to enable the formation of p-type and n-type regions of the semiconductor device 11 as described subsequently.

[0019] The second region 31 includes a plurality of avalanche photodiode regions 32 that physically correspond to the pixels 13, and the avalanche photodiode regions 32 are arranged between the first region 29 and the buried insulating layer 25. This arrangement can be, for example, a one-dimensional or two-dimensional array-like arrangement. The avalanche photodiode regions 32 can convert light (or photons) incident from the rear surface of the substrate into an electrical signal by using avalanche breakdown, for example.

[0020] Each of the avalanche photodiode regions 32 includes a well region 33 of a first conductivity type, a first dopant-doped region of the first conductivity type (hereinafter referred to as a "first doped region 35"), and a high-concentration region 37 of a second conductivity type. The well region 33 extends along a reference plane REF intersecting the first axis Ax1. The first doped region 35 and the high-concentration region 37 are disposed along the reference plane REF. The first doped region 35 and the high-concentration region 37 are disposed between the well region 33 and the buried insulating layer 25.

[0021] A dopant concentration N37 (not shown) of the high concentration region 37 is greater than a dopant concentration P33 (not shown) of the well region 33. The dopant concentration P33 of the well region 33 is greater than a dopant concentration P26 (not shown) of the first conductivity type semiconductor 26.

[0022] According to the semiconductor device 11, the well region 33 of the first conductivity type extends along the reference surface REF in the avalanche photodiode region 32. The first doped region 35 of the first conductivity type can supply power to the well region 33.

[0023] The well region 33 extending along the reference plane REF reaches the high concentration region 37 located between the well region 33 and the buried insulating layer 25, and the well region 33 and the high concentration region 37 form a pn junction JAB1. Specifically, the upper side 33d of the well region 33 and the bottom surface 37d of the high concentration region 37 form a pn junction JAB1. A depletion layer is generated in this pn junction JAB1 by a voltage applied between the high concentration region 37 and the well region 33. The dopant concentration P33 of the well region 33 is greater than the dopant concentration P26 of the first conductive type semiconductor 26, and the dopant concentration N37 of the high concentration region 37 is greater than the dopant concentration P33 of the well region 33. For this reason, the depletion layer does not spread much in the direction from the high concentration region 37 to the first region 29 of the semiconductor region 27. The thin depletion layer creates a high electric field within the depletion layer leading to avalanche breakdown in response to the injection of carriers 20 into the depletion layer from the first region 29 of the semiconductor region 27. The first area of ​​the pn junction JAB1 capable of generating a high electric field is associated with the area of ​​the bottom surface 37d of the high concentration region 37.

[0024] Each of the avalanche photodiode regions 32 may further include a second dopant doped region of a second conductivity type (hereinafter, "second doped region 39"). The first doped region 35, the second doped region 39, and the high concentration region 37 are arranged along a reference plane REF. The first doped region 35 and the second doped region 39 are spaced apart from each other. The second doped region 39 is adjacent to the high concentration region 37 and mutually doped.

[0025] The first doped region 35, the high concentration region 37, and the second doped region 39 are disposed between the well region 33 and the buried insulating layer 25. A dopant concentration N39 (not shown) of the second doped region 39 is lower than a dopant concentration N37 of the high concentration region 37. The dopant concentration N39 of the second doped region 39 is higher than a dopant concentration P26 of the first conductivity type semiconductor 26.

[0026] According to the semiconductor device 11, the well region 33 extends along the reference plane REF to the outside of the bottom surface 37d of the high concentration region 37 and reaches the second doped region 39, and the well region 33 and the second doped region 39 form a pn junction JAB2. Specifically, the pn junction JAB2 is formed by the upper side 33d of the well region 33 and the bottom surface 39d of the second doped region 39. A voltage is applied to the semiconductor device 11 such that an avalanche breakdown occurs in the pn junction JAB2. Due to the expansion of the area of ​​the pn junction, the second area of ​​the pn junction JAB2 capable of generating a high electric field is added to the first area of ​​the pn junction JAB1 capable of generating a high electric field, and the total area of ​​these junctions becomes larger than the area of ​​the bottom surface 37d of the high concentration region 37.

[0027] The well region 33 extending along the reference plane REF reaches the second doped region 39 and the high concentration region 37 located between the well region 33 and the buried insulating layer 25, and the well region 33, the second doped region 39 and the high concentration region 37 form a pn junction.

[0028] By providing the second doped region 39 between the high concentration region 37 and the first doped region 35, it is possible to prevent the side surface of the high concentration region 37 from forming a pn junction including a junction with the high concentration semiconductor region. This makes it easier for avalanche breakdown to occur at the bottom surface of the high concentration region 37 and the second doped region 39 around it. In addition, by separating the second doped region 39 from the first doped region 35, it is possible to prevent the second doped region 39 from forming a pn junction directly with the first doped region 35.

[0029] Each of the avalanche photodiode regions 32 may further include a lightly doped region 41 of the first conductivity type located between the well region 33 and the heavily doped region 37 .

[0030] The first doped region 35, the low concentration region 41, the second doped region 39, and the high concentration region 37 are arranged along a reference plane REF. A dopant concentration P41 (not shown) of the low concentration region 41 is lower than a dopant concentration N35 (not shown) of the first doped region 35, and the dopant concentration P41 of the low concentration region 41 is lower than a dopant concentration N39 of the second doped region 39.

[0031] According to the semiconductor device 11, the generation of a high electric field is prevented by disposing the low concentration region 41 between the first doped region 35 and the second doped region 39. The low concentration region 41 may include the first conductivity type semiconductor 26, for example.

[0032] Each of the avalanche photodiode regions 32 can further include a first conductive type first high concentration region 43 surrounded by the first doped region 35. According to the semiconductor device 11, the resistance of the power supply path to the well region 33 can be reduced, and a potential can be reliably applied to the positions of the pn junctions in the high concentration region 37 and the second doped region 39.

[0033] The first doped region 35 and the second doped region 39 are provided between the first high concentration region 43 and the high concentration region 37. The dopant concentration P43 of the first high concentration region 43 is greater than the dopant concentrations P33, P35, and P43 of the well region 33, the first doped region 35, and the second doped region 39.

[0034] Exemplary Relationships for Dopant Concentrations P26 <P33<N37 P26 <P35<N37 P26 <N39<P43 P41 <P33<P43 P26≦P41 <N35 P33 <N35<N39 P41 <N39 P41 <P35<P43

[0035] 2, there is shown an exemplary arrangement of second doped region 35, highly doped region 37, first doped region 35, and first highly doped region 43 at interface 30 (or reference plane REF) between buried insulating layer 25 and semiconductor region 27. Well region 33 is shown in dashed line and is approximately the same size as the perimeter of first doped region 35.

[0036] The second doped region 39 can extend along the interface 30 (or the reference plane REF) so as to surround the high concentration region 37. In the semiconductor device 11, when the second doped region 39 surrounds the high concentration region 37, the pn junction area can be increased, and current concentration can be avoided during avalanche breakdown.

[0037] The low concentration region 41 can extend along the interface 30 (or the reference plane REF) so as to surround the high concentration region 37. In the semiconductor device 11, when the low concentration region 41 surrounds the high concentration region 37, the generation of avalanche breakdown can be avoided over the sides of the high concentration region 37.

[0038] The first doped region 35 can extend along the interface 30 (or the reference plane REF) so as to surround the high concentration region 37. In the semiconductor device 11, when the first doped region 35 surrounds the high concentration region 37, the current path is expanded, and current concentration during avalanche breakdown can be avoided.

[0039] 3, the semiconductor device 11 may, if desired, further comprise an overlying structure 28 located on the buried insulating layer 25. The overlying structure 28 may include an overlying insulating layer, such as a silicon-based inorganic compound film comprising, for example, silicon oxide or silicon nitride.

[0040] The semiconductor device 11 may further include a first electrode 45 and a second electrode 47. According to this semiconductor device 11, the first electrode 45 and the second electrode 47 are located on the buried insulating layer 25 of the insulating layer 22. Specifically, the first electrode 45 is electrically connected to the high concentration region 37 through the opening 22b of the buried insulating layer 25. The second electrode 47 is electrically connected to the first high concentration region 43 through the opening 22c of the buried insulating layer 25. A covering structure 28 covers the first electrode 45 and the second electrode 47. In addition, the covering structure 28 may include one or more wiring layers that transmit an electrical signal from one of the first electrode 45 and the second electrode 47 to the peripheral circuit 15.

[0041] The semiconductor device 11 may further include an element region 57 and a circuit element 58 located on the buried insulating layer 25. The element region 57 and the circuit element 58 are covered by a covering structure .

[0042] The element region 57 can include a quench resistor provided for each element, for example, an avalanche photodiode, connected to the avalanche photodiode region 32. The quench resistor has one end and the other end, and the one end is connected to either the high concentration region 37 or the first high concentration region 43 of the avalanche photodiode region 32 via an electrode, and the other end is connected to a power supply line via another electrode.

[0043] According to the semiconductor device 11, the processing circuit and the avalanche photodiode in the avalanche photodiode region 32 are integrated on a common support. One or more circuit elements 58 for the processing circuit are connected to the avalanche photodiode region 32 and can include a resistor, such as a quench resistor, a capacitor, and a transistor. Specifically, the quench resistor and the avalanche photodiode are integrated on a common support 23. The quench resistor can include a polysilicon resistor. Also, one end of the quench resistor can be connected to, for example, the cathode of the avalanche photodiode, and the other end of the quench resistor is connected to a power supply line, and the current of the avalanche breakdown flows to the avalanche photodiode via the power supply line and the quench resistor.

[0044] The circuit element 58 may include an element connected to the avalanche photodiode region 32, for example, a processing circuit ("15" in FIG. 1) provided for each avalanche photodiode. The processing circuit is connected to the other (for example, an anode) of the high concentration region 37 or the first high concentration region 43 of the avalanche photodiode region 32 via an electrode, and receives an electrical signal from the avalanche photodiode region 32. Specifically, the processing circuit is provided for each avalanche photodiode, and can perform electrical processing such as amplifying, holding, and / or selecting the electrical signal from the avalanche photodiode region 32.

[0045] 4 is a diagram showing a depletion layer in a semiconductor device according to this embodiment. The two-dot chain line in FIG. 4 indicates the spread of the depletion layer from the high concentration region 37 of the semiconductor device 11. The depletion layer spreads to the second doped region 39 located on the side of the high concentration region 37. On the other hand, at the junction between the lower surface of the high concentration region 37 and the well region 33, the depletion layer hardly spreads to the high concentration region 37, but spreads to the well region 33. The dopant concentration and thickness of the well region 33 are related to the characteristics of the avalanche breakdown.

[0046] The semiconductor device 11 may include a protective film provided on the rear surface 27b of the semiconductor region 27 (the rear surface 23b of the support 23) if necessary.

[0047] 1 and 2, a coordinate system CS is depicted. Pixels 13 are arranged in the directions of the X-axis and Y-axis of the coordinate system CS. Referring to FIG. 2, two types of arrangement pitches of the pixels 13 are shown. The first pitch is indicated by PX1 and PY1. The second pitch is indicated by PX2 and PY2.

[0048] 5 and 6 are diagrams showing exemplary arrangements of adjacent avalanche photodiode regions. In Fig. 5 and Fig. 6, dashed lines indicate boundaries between pixels 13.

[0049] Referring to FIG. 5, four pixels 13 are arranged according to a first pitch (PX1 and PY1). The avalanche photodiode region 32 may include a first avalanche photodiode region 32b, a second avalanche photodiode region 32c, a third avalanche photodiode region 32d, and a second avalanche photodiode region 32e. The first avalanche photodiode region 32b, the second avalanche photodiode region 32c, the third avalanche photodiode region 32d, and the second avalanche photodiode region 32e are adjacent to each other in the X-axis direction or the Y-axis direction of the coordinate system CS shown in FIG. 1. Each of the avalanche photodiode regions (32b, 32c, 32d, 32e) may be arranged in an array such that the periphery of the first doped region 35 of the remaining avalanche photodiode regions (32b, 32c, 32d, 32e) is shared with each other.

[0050] 6, four pixels 13 are arranged according to a first pitch (PX2 and PY2). The avalanche photodiode region 32 includes a fifth avalanche photodiode region 32f, a sixth avalanche photodiode region 32g, a seventh avalanche photodiode region 32h, and a sixth avalanche photodiode region 32i. The fifth avalanche photodiode region 32f, the sixth avalanche photodiode region 32g, the seventh avalanche photodiode region 32h, and the sixth avalanche photodiode region 32i are adjacent to each other in the X-axis direction or the Y-axis direction of the coordinate system CS shown in FIG. 1. The fifth avalanche photodiode region 32f, the sixth avalanche photodiode region 32g, the seventh avalanche photodiode region 32h and the sixth avalanche photodiode region 32i can be arranged in an array such that the first doped region 35 of each avalanche photodiode region (32f, 32g, 32h, 32i) is spaced apart from the first doped region 35 of the other avalanche photodiode regions (32f, 32g, 32h, 32i). A well region 33 can be provided for each avalanche photodiode region 32, or a single well region 33 can be provided for the entire array of avalanche photodiode regions 32.

[0051] Subsequently, a description will be given of the main steps in the method of manufacturing the semiconductor device 11. Where possible, already used reference numerals will be used in the subsequent description.

[0052] FIG. 7 shows a step in a method of manufacturing the semiconductor device 11.

[0053] First, a wafer 61 to be used in the manufacturing process is prepared. The wafer 61 can be, for example, a silicon-on-insulator (SOI) substrate. The wafer 61 can include a semiconductor region 27 including a first region 29 and a second region 31, a buried insulating layer 25 provided on the semiconductor region 27, and a semiconductor layer 24 provided on the buried insulating layer 25. The wafer 61 is sometimes referred to as a "substrate" in the art.

[0054] In the wafer 61, the well region 33, the first doped region 35, the second doped region 39, the high concentration region 37, and the first high concentration region 43 are formed. These can be formed by, for example, photolithography and ion implantation. Although there is no limitation on the order of formation, the well region 33 formed at a deep position is formed first.

[0055] The formation of the well region 33 will be described with reference to Fig. 7. In this embodiment, a first conductivity type dopant, for example, boron, is ion-implanted into the entire surface of the wafer 61. If necessary, a heat treatment can be performed after the ion implantation, and the dopant formed by the ion implantation can be activated by the heat treatment.

[0056] An area deeper than the deepest part of the well region 33 is referred to as a first region 31. An area between the first region 31 and the buried insulating layer 25 is referred to as a second region 31. The well region 33 extends along the boundary between the first region 31 and the second region 31. The first conductivity type semiconductor 26 is left between the well region 33 and the buried insulating layer 25.

[0057] FIG. 8 illustrates a step in a method of manufacturing the semiconductor device 11.

[0058] Next, in this embodiment, the first doped region 35 is formed. The formation of the first doped region 35 will be described with reference to FIG. 8. In this embodiment, a mask 62 is formed by photolithography. The mask 62 has an opening 62b. When a first conductive type dopant, for example, boron, is ion-implanted into the entire surface of the wafer 61, ions are implanted into the wafer 61 from the opening 62b. The ion implantation energy and dose of the first doped region 35 are adjusted so that the first doped region 35 reaches the well region 33. If necessary, a heat treatment can be performed after the ion implantation, and the dopant formed by the ion implantation can be activated by this heat treatment.

[0059] After ion implantation, the mask 62 is removed.

[0060] FIG. 9 illustrates a step in a method of manufacturing the semiconductor device 11.

[0061] Next, in this embodiment, the second doped region 39 is formed. The formation of the second doped region 39 will be described with reference to FIG. 9. In this embodiment, a mask 64 is formed by photolithography. The mask 64 has an opening 64b. When a second conductive type dopant, for example, phosphorus, is ion-implanted into the entire surface of the wafer 61, ions are implanted into the wafer 61 from the opening 64b. The ion implantation energy and dose of the second doped region 39 are adjusted so that the second doped region 39 reaches the well region 33. If necessary, a heat treatment can be performed after the ion implantation, and the dopant formed by the ion implantation can be activated by this heat treatment.

[0062] After ion implantation, the mask 64 is removed.

[0063] FIG. 10 illustrates a step in a method of manufacturing a semiconductor device 11.

[0064] Next, in this embodiment, the high concentration region 37 is formed. The formation of the high concentration region 37 will be described with reference to FIG. 10. In this embodiment, a mask 66 is formed by photolithography. The mask 66 has an opening 66b. When a second conductive type dopant, for example, phosphorus, is ion-implanted into the entire surface of the wafer 61, ions are implanted into the wafer 61 from the opening 66b. The ion implantation energy and dose of the high concentration region 37 are adjusted so that the high concentration region 37 reaches the well region 33. If necessary, a heat treatment can be performed after the ion implantation, and the dopant formed by the ion implantation can be activated by this heat treatment.

[0065] After ion implantation, the mask 66 is removed.

[0066] FIG. 11 shows a step in a method of manufacturing a semiconductor device 11.

[0067] Next, in this embodiment, the first high concentration region 43 is formed. The formation of the first high concentration region 43 will be described with reference to FIG. 11. In this embodiment, a mask 68 is formed by photolithography. The mask 68 has an opening 68b. When a first conductive type dopant, for example, boron, is ion-implanted into the entire surface of the wafer 61, ions are implanted into the wafer 61 from the opening 68b. The ion implantation energy and dose of the first high concentration region 43 are adjusted so that the first high concentration region 43 reaches the well region 33. If necessary, a heat treatment can be performed after the ion implantation, and the dopant formed by the ion implantation can be activated by this heat treatment.

[0068] After ion implantation, the mask 68 is removed.

[0069] In this embodiment, the low concentration region 41 is provided by the original first conductivity type semiconductor 26 of the semiconductor region 27. However, if necessary, a desired dopant concentration can be provided in the low concentration region 41 by photolithography and ion implantation.

[0070] 12 shows a step in a method for manufacturing the semiconductor device 11. In each of the avalanche photodiode regions 32 of the wafer 61, circuit elements are formed in one or more semiconductor regions (57, 58) of the semiconductor layer 24 on the buried insulating layer 25. This formation can be performed using processes related to the manufacture of CMOS semiconductor devices, such as photolithography, etching, oxidation, and thin film growth. Specifically, the element region 57 can include a quench resistor, and the circuit element 58 can include a circuit element for a processing circuit.

[0071] FIG. 13 shows a step in the method of manufacturing the semiconductor device 11. After forming the circuit elements 58, a metallization process is performed. In each of the avalanche photodiode regions 32 of the wafer 61, a first electrode 45 and a second electrode 47 are formed. A mask is formed by photolithography. The mask has openings in areas where electrical connections are to be made. The mask is used to form respective openings (25b, 25c) in the buried insulating layer 25 by etching. These openings (25b, 25c) penetrate the buried insulating layer 25 to the semiconductor region 27, specifically the respective high concentration regions (37, 43). After forming the openings (25b, 25c), a metallization process is performed to form the first electrode 45 and the second electrode 47.

[0072] Specifically, the first electrode 45 is electrically connected to the high concentration region 37 through the opening 25b. The second electrode 47 is electrically connected to the first high concentration region 43 through the opening 25c. The metal layer of the first electrode 45 and / or the metal layer of the second electrode 47 can be connected to a circuit element in the semiconductor region (57, 58).

[0073] 14 shows a step in a method of manufacturing the semiconductor device 11. After the first electrode 45 and the second electrode 47 are formed, an overlying structure 28 is formed covering the first electrode 45 and the second electrode 47. The overlying structure 28 is deposited over the buried insulating layer 25 and the circuit elements 58 over the entire wafer 61. This deposition may include silicon oxide, for example, by chemical vapor deposition. An insulating region 63 includes the buried insulating layer 25 and the overlying structure 28.

[0074] The cladding structure 28 may include a wiring structure having one or more metal layers and insulating layers between the metal layers. The wiring structure may connect the photodiodes in each of the avalanche photodiode regions 32 to peripheral circuitry and / or to processing circuitry for each avalanche photodiode region 32.

[0075] 15 shows a step in the method of manufacturing the semiconductor device 11. After the covering structure 28 is formed, the back surface of the wafer 61 is polished or ground to obtain a device product (an array of semiconductor devices 11) having a desired substrate thickness.

[0076] The semiconductor region 27 may be provided with a thickness of, for example, about 1000 micrometers in the exemplary semiconductor device 11. The peaks of the dopant concentrations of the high concentration region 37 and the first high concentration region 43 are located at a distance of, for example, about 0.5 micrometers in the direction from the interface 30 toward the back surface 27b of the semiconductor region 27.

[0077] According to this manufacturing method, a semiconductor device 11 as shown in FIG. 1 is manufactured. In the semiconductor device 11, in the avalanche photodiode region 32, a well region 33 of a first conductivity type extends along a reference plane REF intersecting with the first axis Ax1. A first doped region 35 of a first conductivity type can feed power to the well region 33. The well region 33 extends along the reference plane REF to reach a second doped region 39 and a high concentration region 37 located between the well region 33 and the buried insulating layer 25. The second doped region 39 and the high concentration region 37 form pn junctions JAB1 and JAB2 with the well region 33, respectively. In these pn junctions JAB1 and JAB2, a depletion layer is generated by application of a voltage between the second doped region 39 and the high concentration region 37 and the well region 33. Since the dopant concentration N37 of the high concentration region 37 is greater than the dopant concentration P33 of the well region 33, the depletion layer does not spread very far in the direction from the high concentration region 37 to the first region 31 of the semiconductor region 27. The thin depletion layer generates a high electric field within the depletion layer, leading to avalanche breakdown in response to the injection of carriers 20 from the first region 29 of the semiconductor region 27 into the depletion layer. The pn junction area capable of generating a high electric field is related to the area of ​​the bottom surface 37d of the high concentration region 37 and the bottom surface 39d of the second doped region 39.

[0078] According to the present embodiment, a semiconductor device that enables multiplication by avalanche breakdown of carriers generated by the photoelectric effect from light (photons) incident from the back surface, and a method for manufacturing such a semiconductor device can be provided.

[0079] The above embodiment further discloses the following supplementary notes.

[0080] (Appendix 1) a support including an insulating layer and a semiconductor region provided in the support and including a first region and a second region, the first region of the semiconductor region, the second region of the semiconductor region, and the buried insulating layer being arranged along a first axis, the first region of the semiconductor region including a semiconductor of a first conductivity type, the second region of the semiconductor region including avalanche photodiode regions arranged in an array between the first region of the semiconductor region and the buried insulating layer, each of the avalanche photodiode regions including a well region of the first conductivity type, a first doped region of the first conductivity type, and a high concentration region of a second conductivity type, the well region extending along a reference plane intersecting the first axis in each of the avalanche photodiode regions, and the first doped region and the high concentration region being arranged along the reference plane in each of the avalanche photodiode regions. a high concentration region and a high concentration region, the high concentration region forming a junction with the well region, the first doped region reaching the well region and electrically connected to each other, the first doped region and the high concentration region being disposed between the well region and the buried insulating layer, a dopant concentration of the high concentration region being higher than a dopant concentration of the well region, the second conductivity type being different from the first conductivity type, each of the avalanche photodiode regions further including a second doped region of the second conductivity type, the first doped region, the second doped region, and the high concentration region being disposed along the reference plane between the well region and the buried insulating layer, the second doped region being located between the first doped region and the high concentration region, a dopant concentration of the second doped region being lower than a dopant concentration of the high concentration region, and a dopant concentration of the second doped region being higher than a dopant concentration of the well region.

[0081] (Appendix 2) 2. The semiconductor device according to claim 1, wherein each of the avalanche photodiode regions further includes a low concentration region of the first conductivity type located between the buried insulating layer and the high concentration region, the first doped region, the low concentration region, the second doped region, and the high concentration region are arranged along the reference plane, and a dopant concentration of the low concentration region is lower than the dopant concentration of the first doped region, and the dopant concentration of the low concentration region is lower than the dopant concentration of the second doped region.

[0082] (Appendix 3) 3. The semiconductor device according to claim 2, wherein the low concentration region extends along an interface between the buried insulating layer and the semiconductor region so as to surround the high concentration region and the second doped region.

[0083] (Appendix 4) 4. The semiconductor device according to claim 1, wherein the second doped region extends so as to surround the high concentration region along the interface between the buried insulating layer and the semiconductor region.

[0084] (Appendix 5) 5. The semiconductor device according to claim 1, wherein each of the avalanche photodiode regions further includes a first high concentration region of the first conductivity type surrounded by the first doped region, the first doped region and the second doped region are provided between the first high concentration region and the high concentration region, and a dopant concentration of the first high concentration region is greater than a dopant concentration of the well region.

[0085] (Appendix 6) 6. The semiconductor device of claim 5, further comprising: a first electrode electrically connected to the high concentration region and located on the buried insulating layer; and a second electrode electrically connected to the first high concentration region and located on the buried insulating layer.

[0086] (Appendix 7) 7. The semiconductor device according to any one of Appendix 1 to Appendix 6, wherein the avalanche photodiode region includes a first avalanche photodiode region and a second avalanche photodiode region, and the first avalanche photodiode region and the second avalanche photodiode region are arranged in an array such that the first doped region of the first avalanche photodiode region and the second avalanche photodiode region are shared by each other.

[0087] (Appendix 8) 7. The semiconductor device according to any one of Appendix 1 to Appendix 6, wherein the avalanche photodiode region includes a first avalanche photodiode region and a second avalanche photodiode region, and the first avalanche photodiode region and the second avalanche photodiode region are arranged in an array such that the first doped region of the first avalanche photodiode region is spaced apart from the first doped region of the second avalanche photodiode region.

[0088] (Appendix 9) preparing a substrate including a semiconductor region including a first region and a second region, and a buried insulating layer provided on the semiconductor region; and forming a well region of a first conductivity type, a high concentration region of a second conductivity type, and a first doped region of the first conductivity type in the second region of the substrate in each of the avalanche photodiode regions, wherein the first region of the semiconductor region, the second region of the semiconductor region, and the buried insulating layer are arranged along a first axis, the first region of the semiconductor region includes a semiconductor of a first conductivity type, and the first doped region and the high concentration region are disposed along a first axis. a well region extending along the reference plane, the highly doped region and the first doped region being disposed along the reference plane between the well region and the buried insulating layer, the highly doped region and the first doped region being spaced apart from one another, a dopant concentration of the first doped region being greater than a dopant concentration of a semiconductor of the first conductivity type, a dopant concentration of the highly doped region being greater than a dopant concentration of the well region, and the second conductivity type being different from the first conductivity type.

[0089] (Appendix 10) 10. The method of claim 9, further comprising forming a second doped region of the first conductivity type in the second region of the substrate for each avalanche photodiode region, wherein the second doped region is spaced apart from the first doped region, the second doped region is located between the first doped region and the high concentration region, the second doped region is spaced apart from the high concentration region, and a dopant concentration of the second doped region is greater than a dopant concentration of the well region.

[0090] (Appendix 11) 11. The method of claim 10, further comprising forming a first high concentration region of the first conductivity type in the second region for each of the avalanche photodiode regions, the first high concentration region being surrounded by the first doped region, the first doped region and the second doped region being provided between the first high concentration region and the high concentration region, and a dopant concentration of the first high concentration region being greater than a dopant concentration of the well region.

[0091] The present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the spirit and scope of the present invention, all of which are included in the technical concept of the present invention. [Explanation of symbols]

[0092] REFERENCE SIGNS LIST 11 semiconductor device, 13 pixel, 15 peripheral circuit, 22 insulating layer, 23 support, 24 semiconductor layer, 25 buried insulating layer, 26 conductive semiconductor, 27 semiconductor region, 28 covering structure, 29 first region, 30 interface, 31 second region, 32 avalanche photodiode region, 33 well region, 35...first doped region, 37...high concentration region, 39...second doped region, 41...low concentration region, 43...first high concentration region, 45, 47...electrode, 57...element region, 5 8...Circuit element, 61...Wafer, 62, 64, 66, 68...Mask, 25b, 25c, 62b, 64b, 66b, 68b...Aperture, Ax1...Axis, REF...Reference plane

Claims

1. an insulating layer including a buried insulating layer within the support; a semiconductor region provided within the support and including a first region and a second region; Equipped with the first region of the semiconductor region, the second region of the semiconductor region, and the buried insulating layer are disposed along a first axis; the first region of the semiconductor region includes a semiconductor of a first conductivity type; the second region of the semiconductor region includes avalanche photodiode regions arranged in an array between the first region of the semiconductor region and the buried insulating layer; Each of the avalanche photodiode regions includes a well region of the first conductivity type, a first doped region of the first conductivity type, and a high concentration region of a second conductivity type; the well region extends along a reference plane intersecting the first axis in each of the avalanche photodiode regions; the first doped region and the high concentration region are disposed along the reference plane in each of the avalanche photodiode regions; the high concentration region forms a junction with the well region, the first doped region reaches the well region and is electrically connected to the well region; the first doped region and the high concentration region are disposed between the well region and the buried insulating layer; a dopant concentration of the high concentration region is greater than a dopant concentration of the well region; The second conductivity type is different from the first conductivity type, Each of the avalanche photodiode regions further includes a second doped region of the second conductivity type, the first doped region, the second doped region, and the high concentration region are disposed along the reference plane between the well region and the buried insulating layer; the second doped region is located between the first doped region and the high concentration region, the dopant concentration of the second doped region is less than the dopant concentration of the high concentration region; The dopant concentration of the second doped region is greater than the dopant concentration of the well region. Semiconductor device.

2. Each of the avalanche photodiode regions further includes a low concentration region of the first conductivity type located between the buried insulating layer and the high concentration region, the first doped region, the low concentration region, the second doped region, and the high concentration region are arranged along the reference plane; a dopant concentration in the low concentration region is lower than the dopant concentration in the first doped region; The dopant concentration of the low concentration region is lower than the dopant concentration of the second doped region.

2. The semiconductor device according to claim 1.

3. the low concentration region extends along an interface between the buried insulating layer and the semiconductor region so as to surround the high concentration region and the second doped region; 3. The semiconductor device according to claim 2.

4. the second doped region extends along the interface between the buried insulating layer and the semiconductor region so as to surround the high concentration region; 4. The semiconductor device according to claim 3.

5. Each of the avalanche photodiode regions further includes a first high concentration region of the first conductivity type surrounded by the first doped region, the first doped region and the second doped region are provided between the first high concentration region and the high concentration region, The dopant concentration of the first high concentration region is greater than the dopant concentration of the well region.

5. The semiconductor device according to claim 4.

6. a first electrode electrically connected to the high concentration region and located on the buried insulating layer; a second electrode electrically connected to the first high concentration region and located on the buried insulating layer; Further comprising:

6. The semiconductor device according to claim 5.

7. the avalanche photodiode region includes a first avalanche photodiode region and a second avalanche photodiode region; the first avalanche photodiode region and the second avalanche photodiode region are arranged in an array such that the first doped region of the first avalanche photodiode region and the second avalanche photodiode region are shared by each other.

2. The semiconductor device according to claim 1.

8. the avalanche photodiode region includes a first avalanche photodiode region and a second avalanche photodiode region; the first avalanche photodiode region and the second avalanche photodiode region are arranged in an array such that the first doped region of the first avalanche photodiode region is spaced apart from the first doped region of the second avalanche photodiode region.

2. The semiconductor device according to claim 1.

9. 1. A method of fabricating a semiconductor device having a plurality of avalanche photodiode regions, comprising the steps of: providing a substrate including a semiconductor region including a first region and a second region, and a buried insulating layer disposed over the semiconductor region; forming a well region of a first conductivity type, a high concentration region of a second conductivity type, and a first doped region of the first conductivity type in the second region of the substrate in each of the avalanche photodiode regions; Equipped with the first region of the semiconductor region, the second region of the semiconductor region, and the buried insulating layer are disposed along a first axis; the first region of the semiconductor region includes a semiconductor of a first conductivity type; the first doped region and the high concentration region are disposed along a reference plane intersecting the first axis, The well region extends along the reference surface, the high concentration region and the first doped region are disposed along the reference plane between the well region and the buried insulating layer; The high concentration region and the first added region are spaced apart from each other, a dopant concentration of the first doped region is greater than a dopant concentration of the first conductive type semiconductor; a dopant concentration of the high concentration region is greater than a dopant concentration of the well region; The second conductivity type is different from the first conductivity type. A method for fabricating a semiconductor device.

10. forming a second doped region of the first conductivity type in the second region of the substrate for each of the avalanche photodiode regions; the second doping region is spaced from the first doping region, the second doped region is located between the first doped region and the high concentration region, The dopant concentration of the second doped region is greater than the dopant concentration of the well region. A method for fabricating a semiconductor device according to claim 9.

11. forming a first high concentration region of the first conductivity type in the second region for each of the avalanche photodiode regions; the first high concentration region is surrounded by the first doped region, the first doped region and the second doped region are provided between the first high concentration region and the high concentration region, The dopant concentration of the first high concentration region is greater than the dopant concentration of the well region. A method for fabricating a semiconductor device according to claim 10.

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