Method for forming ohmic contact on high-power electrical diode

Abstract

To provide a method for forming an ohmic contact electrically connecting to implanted regions of a merged-PN Schottky (MPS) diode.SOLUTION: A method of forming an ohmic contact on a MPS diode 200 includes: depositing a first metallic layer (anode terminal 226) on a top surface of a semiconductor drift layer 224 having an electrical contact point (implanted well 230), the first metallic layer being highly reflective with regard to laser light; depositing a second metallic layer on portions of the first metallic layer aligned with the electrical contact point, the second metallic layer being selected to absorb the laser light; and exposing the first and the second metallic layers to the laser light in a laser annealing process, the second metallic layer being substantially increased in temperature due to the laser light. The increase in temperature of the second metallic layer forms the ohmic contact 232 between the electrical contact point and the first metallic layer.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] FIELD OF THE DISCLOSURE Embodiments of the present disclosure relate generally to creating ohmic contacts on high power electrical diodes, and more particularly, to creating ohmic contacts that electrically connect to an implanted region of a Merged PN Schottky (MPS) diode. [Background technology]

[0002] Many semiconductor components, such as MOSFETs, diodes, Schottky devices, and other transistors, require contacts to be formed between the semiconductor component and a metal. To improve the efficiency of the semiconductor component, an ohmic contact is most commonly formed. An ohmic contact refers to a type of low resistance electrical contact between a metal and a semiconductor material, and exhibits linear behavior over a wide range of voltages and currents. An ohmic contact allows for the efficient transfer of electrical current between the metal and semiconductor components.

[0003] One particular application utilizing ohmic contacts is the Merged PN Schottky (MPS) diode. Applicant has identified many technical challenges and difficulties associated with forming ohmic contacts between semiconductors and metals. Through applied effort, ingenuity, and innovation, Applicant has solved the problems associated with forming ohmic contacts on high power electrical diodes, which are described in detail below. Summary of the Invention

[0004] Various embodiments are directed to an exemplary method of forming an ohmic contact on a semiconductor component, such as a high power electrical diode. According to some embodiments of the present disclosure, an exemplary method is provided. In some embodiments, the exemplary method includes depositing a first metal layer on a top surface of a semiconductor drift layer including an electrical contact, the first metal layer reflecting laser light. The method further includes depositing a second metal layer on a portion of the first metal layer, the second metal layer being aligned with the electrical contact, and the second metal layer absorbing the laser light. The method further includes exposing the first metal layer and the second metal layer to laser light in a laser annealing process, the second metal layer being substantially elevated in temperature by the laser light. In some embodiments, the elevated temperature forms an ohmic contact between the electrical contact and the first metal layer.

[0005] In some embodiments, the semiconductor component is a merged PN Schottky diode.

[0006] In some embodiments, the electrical contact is an implanted well in the top surface of the semiconductor drift layer.

[0007] In some embodiments, a portion of the second metal layer is disposed on an upper surface of the first metal layer directly opposite the implantation well.

[0008] In some embodiments, the first reflectance of the first metal layer is greater than the second reflectance of the second metal layer.

[0009] In some embodiments, the injection well comprises a p-type semiconductor and the semiconductor drift layer comprises an n-type semiconductor.

[0010] In some embodiments, the ohmic contact forms electrical contact with the implantation well.

[0011] In some embodiments, the method may further include removing the second metal layer and depositing a front metal over the ohmic contact.

[0012] In some embodiments, the front metal is the anode of the semiconductor component.

[0013] In some embodiments, the method may further include removing the front metal from all areas except the semiconductor component areas on and immediately surrounding the ohmic contacts.

[0014] In some embodiments, the method may further include depositing a passivation layer over and around the front metal, and etching an access channel through the passivation layer to the front metal.

[0015] In some embodiments, the method may further include depositing a dielectric layer on the top surface of the semiconductor drift layer and on the ohmic contact, removing the dielectric layer immediately above the top surface of the semiconductor drift layer of the semiconductor component such that the ohmic contact is exposed, and depositing a front metal on the ohmic contact and the dielectric layer.

[0016] In some embodiments, the method may further include removing the front metal from all areas except the semiconductor component areas on and immediately surrounding the ohmic contacts.

[0017] In some embodiments, the method may further include depositing a passivation layer on and immediately surrounding a surface of the front metal, and etching an access channel through the passivation layer to the front metal.

[0018] In some embodiments, the method may further include creating a rear ohmic contact on an opposing surface of the passivation layer, the rear metal being in electrical contact with the rear ohmic contact.

[0019] In some embodiments, the rear ohmic contact is the cathode of the semiconductor component.

[0020] In some embodiments, the semiconductor drift layer is formed by a process of epitaxial growth on a semiconductor substrate.

[0021] In some embodiments, both the semiconductor substrate and the semiconductor drift layer comprise silicon carbide.

[0022] In some embodiments, the first metal layer comprises aluminum.

[0023] In some embodiments, the second metal layer comprises titanium. [Brief description of the drawings]

[0024] Reference will now be made to the accompanying drawings, in which components shown in the figures may or may not be present in a particular embodiment described herein. Some embodiments may include fewer (or more) components than shown in the figures in accordance with exemplary embodiments of the present disclosure. [Figure 1A] 1A-1D illustrate an exemplary conventional process for creating ohmic contacts on semiconductor components. [Figure 1B] 1A-1D illustrate an exemplary conventional process for creating ohmic contacts on semiconductor components. [Figure 1C] 1A-1D illustrate an exemplary conventional process for creating ohmic contacts on semiconductor components. [Figure 1D] 1A-1D illustrate an exemplary conventional process for creating ohmic contacts on semiconductor components. [Figure 1E] 1A-1D illustrate an exemplary conventional process for creating ohmic contacts on semiconductor components. [Figure 1F] 1A-1D illustrate an exemplary conventional process for creating ohmic contacts on semiconductor components. [Figure 1G] 1A-1D illustrate an exemplary conventional process for creating ohmic contacts on semiconductor components. [Diagram 2]FIG. 1 is a cross-sectional view of an example merged PN Schottky (MPS) diode in accordance with one or more embodiments of the present disclosure. [Diagram 3] 1 is a flowchart illustrating an exemplary process for forming an ohmic contact on an electrical diode in accordance with one or more embodiments of the present disclosure. [Figure 4] 1 shows a flowchart illustrating an example process for forming an ohmic contact on an electrical diode having a field plate edge termination in accordance with one or more embodiments of the present disclosure. [Figure 5A] 1A-1D are cross-sectional views of an example process for manufacturing an MPS diode with a field plate edge termination having one or more ohmic contacts formed in accordance with one or more embodiments of the present disclosure. [Figure 5B] 1A-1D are cross-sectional views of an example process for manufacturing an MPS diode with a field plate edge termination having one or more ohmic contacts formed in accordance with one or more embodiments of the present disclosure. [Figure 5C] 1A-1D are cross-sectional views of an example process for manufacturing an MPS diode with a field plate edge termination having one or more ohmic contacts formed in accordance with one or more embodiments of the present disclosure. [Figure 5D] 1A-1D are cross-sectional views of an example process for manufacturing an MPS diode with a field plate edge termination having one or more ohmic contacts formed in accordance with one or more embodiments of the present disclosure. [Figure 5E] 1A-1D are cross-sectional views of an example process for manufacturing an MPS diode with a field plate edge termination having one or more ohmic contacts formed in accordance with one or more embodiments of the present disclosure. [Figure 5F] 1A-1D are cross-sectional views of an example process for manufacturing an MPS diode with a field plate edge termination having one or more ohmic contacts formed in accordance with one or more embodiments of the present disclosure. [Figure 5G]1A-1D are cross-sectional views of an example process for manufacturing an MPS diode with a field plate edge termination having one or more ohmic contacts formed in accordance with one or more embodiments of the present disclosure. [Figure 5H] 1A-1D are cross-sectional views of an example process for manufacturing an MPS diode with a field plate edge termination having one or more ohmic contacts formed in accordance with one or more embodiments of the present disclosure. [Figure 5I] 1A-1D are cross-sectional views of an example process for manufacturing an MPS diode with a field plate edge termination having one or more ohmic contacts formed in accordance with one or more embodiments of the present disclosure. [Figure 5J] 1A-1D are cross-sectional views of an example process for manufacturing an MPS diode with a field plate edge termination having one or more ohmic contacts formed in accordance with one or more embodiments of the present disclosure. [Figure 5K] 1A-1D are cross-sectional views of an example process for manufacturing an MPS diode with a field plate edge termination having one or more ohmic contacts formed in accordance with one or more embodiments of the present disclosure. [Figure 5L] 1A-1D are cross-sectional views of an example process for manufacturing an MPS diode with a field plate edge termination having one or more ohmic contacts formed in accordance with one or more embodiments of the present disclosure. [Figure 5M] 1A-1D are cross-sectional views of an example process for manufacturing an MPS diode with a field plate edge termination having one or more ohmic contacts formed in accordance with one or more embodiments of the present disclosure. [Figure 5N] 1A-1D are cross-sectional views of an example process for manufacturing an MPS diode with a field plate edge termination having one or more ohmic contacts formed in accordance with one or more embodiments of the present disclosure. [Figure 5O]1A-1D are cross-sectional views of an example process for manufacturing an MPS diode with a field plate edge termination having one or more ohmic contacts formed in accordance with one or more embodiments of the present disclosure. [Figure 5P] 1A-1D are cross-sectional views of an example process for manufacturing an MPS diode with a field plate edge termination having one or more ohmic contacts formed in accordance with one or more embodiments of the present disclosure. [Figure 5Q] 1A-1D are cross-sectional views of an example process for manufacturing an MPS diode with a field plate edge termination having one or more ohmic contacts formed in accordance with one or more embodiments of the present disclosure. [Figure 5R] 1A-1D are cross-sectional views of an example process for manufacturing an MPS diode with a field plate edge termination having one or more ohmic contacts formed in accordance with one or more embodiments of the present disclosure. [Figure 5S] 1A-1D are cross-sectional views of an example process for manufacturing an MPS diode with a field plate edge termination having one or more ohmic contacts formed in accordance with one or more embodiments of the present disclosure. [Figure 5T] 1A-1D are cross-sectional views of an example process for manufacturing an MPS diode with a field plate edge termination having one or more ohmic contacts formed in accordance with one or more embodiments of the present disclosure. [Figure 5U] 1A-1D are cross-sectional views of an example process for manufacturing an MPS diode with a field plate edge termination having one or more ohmic contacts formed in accordance with one or more embodiments of the present disclosure. [Figure 6] 1 shows a flowchart illustrating an example process for forming an ohmic contact on an electrical diode without a field plate edge termination in accordance with one or more embodiments of the present disclosure. [Figure 7A]1A-1D are cross-sectional views of an example process for manufacturing an MPS diode without a field plate edge termination having one or more ohmic contacts formed in accordance with one or more embodiments of the present disclosure. [Figure 7B] 1A-1D are cross-sectional views of an example process for manufacturing an MPS diode without a field plate edge termination having one or more ohmic contacts formed in accordance with one or more embodiments of the present disclosure. [Figure 7C] 1A-1D are cross-sectional views of an example process for manufacturing an MPS diode without a field plate edge termination having one or more ohmic contacts formed in accordance with one or more embodiments of the present disclosure. [Figure 7D] 1A-1D are cross-sectional views of an example process for manufacturing an MPS diode without a field plate edge termination having one or more ohmic contacts formed in accordance with one or more embodiments of the present disclosure. [Figure 7E] 1A-1D are cross-sectional views of an example process for manufacturing an MPS diode without a field plate edge termination having one or more ohmic contacts formed in accordance with one or more embodiments of the present disclosure. [Figure 7F] 1A-1D are cross-sectional views of an example process for manufacturing an MPS diode without a field plate edge termination having one or more ohmic contacts formed in accordance with one or more embodiments of the present disclosure. [Figure 7G] 1A-1D are cross-sectional views of an example process for manufacturing an MPS diode without a field plate edge termination having one or more ohmic contacts formed in accordance with one or more embodiments of the present disclosure. [Figure 7H] 1A-1D are cross-sectional views of an example process for manufacturing an MPS diode without a field plate edge termination having one or more ohmic contacts formed in accordance with one or more embodiments of the present disclosure. [Figure 7I]1A-1C are cross-sectional views of an example process for manufacturing an MPS diode without a field plate edge termination having one or more ohmic contacts formed in accordance with one or more embodiments of the present disclosure. [Figure 7J] 1A-1C are cross-sectional views of an example process for manufacturing an MPS diode without a field plate edge termination having one or more ohmic contacts formed in accordance with one or more embodiments of the present disclosure. [Figure 7K] 1A-1C are cross-sectional views of an example process for manufacturing an MPS diode without a field plate edge termination having one or more ohmic contacts formed in accordance with one or more embodiments of the present disclosure. [Figure 7L] 1A-1C are cross-sectional views of an example process for manufacturing an MPS diode without a field plate edge termination having one or more ohmic contacts formed in accordance with one or more embodiments of the present disclosure. [Figure 7M] 1A-1C are cross-sectional views of an example process for manufacturing an MPS diode without a field plate edge termination having one or more ohmic contacts formed in accordance with one or more embodiments of the present disclosure. [Figure 7N] 1A-1C are cross-sectional views of an example process for manufacturing an MPS diode without a field plate edge termination having one or more ohmic contacts formed in accordance with one or more embodiments of the present disclosure. [Figure 7O] 1A-1C are cross-sectional views of an example process for manufacturing an MPS diode without a field plate edge termination having one or more ohmic contacts formed in accordance with one or more embodiments of the present disclosure. [Figure 7P] 1A-1C are cross-sectional views of an example process for manufacturing an MPS diode without a field plate edge termination having one or more ohmic contacts formed in accordance with one or more embodiments of the present disclosure. [Figure 7Q]1A-1D are cross-sectional views of an example process for manufacturing an MPS diode without a field plate edge termination having one or more ohmic contacts formed in accordance with one or more embodiments of the present disclosure. [Figure 7R] 1A-1D are cross-sectional views of an example process for manufacturing an MPS diode without a field plate edge termination having one or more ohmic contacts formed in accordance with one or more embodiments of the present disclosure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0025] Exemplary embodiments are described more fully below with reference to the accompanying drawings, in which some, but not all, embodiments of the invention of the present disclosure are shown. However, embodiments of the present disclosure may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will satisfy applicable legal requirements. Like numbers refer to like elements throughout.

[0026] As used herein, terms such as "front," "rear," "behind," "top," "vertical," "horizontal," "upper," "lower," "above," "below," and the like are used for illustrative purposes in the examples provided below to describe the relative location of particular components or portions of components with respect to the local reference frame of an electrical diode using any global reference frame.

[0027] In some examples, a Cartesian (three-axis) reference system is provided. Generally, the positive y direction corresponds to "up," "above," or "on top," unless otherwise noted. Conversely, the negative y direction corresponds to "down," "below," "under," or "beneath."

[0028] Various exemplary embodiments address technical problems associated with forming ohmic contacts on electrical components. As will be appreciated by those skilled in the art to which this disclosure pertains, there are numerous exemplary scenarios in which ohmic contacts may be formed on electrical components.

[0029] Many semiconductor components, such as MOSFETs, power diodes, Schottky diodes, and other transistors, require contacts to be formed between the semiconductor component and a metal. To improve the efficiency of the component, an ohmic contact is most commonly formed. An ohmic contact refers to a type of low-resistance electrical contact between a metal and a semiconductor material, and exhibits linear behavior over a wide range of voltages and currents. An ohmic contact allows for efficient transmission of electrical current between the metal and semiconductor components.

[0030] One particular application that utilizes ohmic contacts is the Merged PN Schottky (MPS) diode. The MPS diode includes one or more isolated implanted regions (or doped wells) implanted into the Schottky device drift layer. Typically, the implanted regions are of a different conductivity type (e.g., p-type) than the drift layer (e.g., n-type) of the MPS diode. The implanted regions result in PN-type junctions interspersed within the Schottky diode. The result is a diode that has the advantages of both Schottky diodes and PN junction diodes. Some of the advantages may include lower leakage current, improved surge current capability at high power, and improved performance at high frequencies. For improved performance, ohmic contacts may be formed at the junctions between the front contact metal and each of the doped wells of the MPS diode. The placement and efficiency of these ohmic contacts play an important role in the overall efficiency of the semiconductor component.

[0031] 1A-1G, an exemplary conventional process 100 for creating ohmic contacts is shown. As shown in FIG. 1A, the exemplary conventional process 100 includes disposing a dielectric 106 on a top surface of a drift layer 102 of a semiconductor component 116, the drift layer 102 including a number of electrical contacts 104 (e.g., doped wells of an MPS diode) to which electrical connections may be made.

[0032] As shown in Figure 1B, a mask 108 is placed on top of the dielectric 106 and aligned with the electrical contacts 104 of the underlying semiconductor component 116. Aligning the mask 108 allows the dielectric 106 directly above the electrical contacts 104 of the semiconductor component 116 to be removed, as shown in Figure 1C.

[0033] As shown in FIG. 1D , an additional layer of dielectric 106 material is disposed on the surface of the semiconductor component 116 such that a thin layer of dielectric covers the exposed portions of the drift layer 102 and the electrical contacts 104 that define the semiconductor component 116, while a thicker layer of dielectric 106 covers the surrounding surfaces.

[0034] 1E, a mask 110 is deposited on the surface of the dielectric 106, with openings in the mask 110 aligned with the electrical contacts 104 underlying the dielectric 106 layer. The mask 110 allows the dielectric 106 to be etched such that the electrical contacts 104 are exposed.

[0035] As shown in FIG. 1F, the mask 110 is removed, a contact metal 112 (e.g., nickel) is deposited over the entire surface of the dielectric 106, and an annealing process is performed to form an ohmic contact. The annealing process generally involves heating the semiconductor component 116 to an annealing temperature of 1000° C. or higher. It is necessary to heat the semiconductor component 116 to a high annealing temperature to enable a reaction between the contact metal 112 and the electrical contact 104. Heating the semiconductor component 116 to an annealing temperature may promote the formation of a silicide between the doped silicon electrical contact 104 and the contact metal 112 at the electrical contact 104. However, a high annealing temperature may cause the contact metal 112 to react with other parts of the semiconductor component 116, making the removal of the contact metal 112 difficult, and even damaging the layers underlying the semiconductor component 116.

[0036] As shown in Figure 1G, the contact metal 112 is removed from the semiconductor component 116 everywhere except directly over the electrical contacts 104. As further shown in Figure 1G, the formation of a silicide results in an ohmic contact 114 in electrical contact with each of the electrical contacts 104. Removal of the contact metal 112 from the surface of the semiconductor component 116 can be particularly complicated. Moreover, removal of the contact metal 112 can adversely affect layers underlying the semiconductor component 116.

[0037] The conventional process 100 shown in FIGS. 1A-1G may have several drawbacks. For example, the formation of ohmic contacts requires annealing temperatures of 1000° C. or more. Such high temperatures may damage the underlying structures of the semiconductor components. In addition, the metal layer (e.g., nickel) used to react with the electrical contacts and promote silicide growth must be removed from everywhere that is not in direct contact with the electrical contacts. The process for removing the metal layer may be complicated. Furthermore, these reactions may extend beyond the limits of the electrical contacts to other areas of the semiconductor components. The extension of ohmic contacts into the semiconductor components may adversely affect the performance of the semiconductor components. This extension of ohmic contacts becomes even more problematic as the size of the features of the semiconductor components continues to shrink.

[0038] Various exemplary embodiments described herein utilize various techniques to create ohmic contacts to semiconductor components, such as MPS diodes. For example, in some embodiments, a first metal is deposited on a surface of the semiconductor component having one or more electrical contacts. The first metal can be selected based on the first metal's ability to reflect light emitted from a laser. In general, the more reflective the first metal is, the less the first metal will heat up when struck by laser light.

[0039] A second metal may also be deposited on the surface of the first metal. In some embodiments, the second metal may be patterned based on the desired location for the ohmic contact. For example, the second metal may be placed in a location aligned with the underlying electrical contact. The second metal may be selected based on the absorption characteristics of the second metal. In general, the more light from the laser that the second metal absorbs, the hotter the second metal becomes. By strategically patterning the second metal only in the desired location for the ohmic contact, the second metal, and portions of the underlying first metal, will increase in temperature significantly only in the desired location for the ohmic contact. The localized temperature increase can promote a reaction between the second metal, the first metal, and the underlying semiconductor contact to form a silicide at the contact point, creating an ohmic contact to the underlying electrical contact.

[0040] As a result of the exemplary embodiments and examples described herein, the complexity of ohmic contact formation, particularly on MPS diodes, can be significantly reduced. In addition, the exemplary embodiments described herein can limit the expansion of ohmic contacts outside of the desired electrical contact. Limiting the expansion of ohmic contacts can result in higher performance semiconductor components. In addition, limiting the expansion of ohmic contacts can allow ohmic contacts to be formed on semiconductor components having electrical contacts that are smaller in size and separated by smaller distances.

[0041] 2, an exemplary merged PN Schottky (MPS) diode 200 is provided. As shown in FIG. 2, the exemplary MPS diode 200 includes a substrate 220 having a top surface 220a and a bottom surface 220b opposite the top surface 220a. As further shown in FIG. 2, the exemplary MPS diode 200 includes a semiconductor drift layer 224 on the top surface 220a of the substrate 220, the semiconductor drift layer 224 further including a top surface 224a opposite the substrate 220. The MPS diode 200 of FIG. 2 further includes an anode terminal 226 disposed on the top surface 224a of the semiconductor drift layer 224, the anode terminal 226 forming a Schottky diode 234 with the top surface 224a of the semiconductor drift layer 224. As further shown in FIG. 2, the MPS diode 200 includes a plurality of junction barrier elements 228 at a junction between the top surface 224a of the semiconductor drift layer 224 and the anode terminal 226. Each junction barrier element 228 comprises an implanted well 230 implanted in the top surface 224a of the semiconducting drift layer 224 and an ohmic contact 232 that forms an electrical connection between the anode terminal 226 and the implanted well 230. The illustrated MPS diode 200 further includes a cathode terminal 222 adjacent the bottom surface 220b of the substrate 220, opposite the semiconducting drift layer 224.

[0042] As shown in FIG. 2, the exemplary MPS diode 200 includes a substrate 220. The substrate (e.g., wafer) 220 may be any semiconductor material that serves as a base layer for a semiconductor component (e.g., MPS diode 200). The substrate 220 may include silicon, germanium, gallium arsenide, gallium nitride, silicon carbide (SiC), or other similar semiconductor materials. The substrate 220 may serve as a base layer for epitaxial growth of additional semiconductor materials. Epitaxial growth may be used to grow additional crystalline layers, such as a semiconductor drift layer 224, on the substrate 220.

[0043] In some embodiments, the substrate 220 may include SiC. SiC may offer many advantages in high power applications. For example, SiC-based semiconductor components may dissipate heat more efficiently, be more tolerant to higher frequencies, have lower reverse leakage currents and power losses, be more stable over a wide temperature range, have lower electromagnetic emissions, and offer other related advantages.

[0044] In some embodiments, the substrate 220 may be doped with a first dopant type to produce a semiconductor having a particular conductivity type. A dopant may be any impurity intentionally added to a semiconductor to modify the conductivity of the semiconductor. Adding a dopant with extra valence electrons to the substrate 220 produces a semiconductor with n-type doping, or an n-doped semiconductor. Dopants with extra valence electrons may include phosphorus, arsenic, antimony, etc. Adding a dopant to a substrate 220 that is deficient in valence electrons produces a semiconductor with p-type doping, or a p-doped semiconductor. Dopants that are deficient in valence electrons may include boron, aluminum, gallium, etc. As shown in FIG. 2, the substrate 220 of the exemplary MPS diode 200 is an n-type semiconductor substrate 220.

[0045] In some embodiments, the substrate 220 may include a doping concentration. The doping concentration may refer to the number of impurities introduced into the semiconductor substrate 220 structure relative to the number of intrinsic semiconductor atoms. A high doping concentration means that more impurities are introduced into the semiconductor substrate 220 relative to the number of intrinsic semiconductor atoms. In some embodiments, the doping concentration of the substrate 220 may be higher than the doping concentration of the semiconductor drift layer 224.

[0046] As further shown in FIG. 2, the exemplary MPS diode 200 includes a semiconductor drift layer 224. The semiconductor drift layer 224 may be any semiconductor material configured to allow current flow from the anode terminal 226 to the cathode terminal 222 as a result of majority carrier drift. The semiconductor drift layer 224 allows current flow from the anode terminal 226 to the cathode terminal 222 when a barrier voltage of the MPS diode 200 is exceeded. Additionally, the semiconductor drift layer blocks or limits current flow in the reverse direction, e.g., from the cathode terminal 222 to the anode terminal. As shown in FIG. 2, the semiconductor drift layer 224 is of the same dopant type as the substrate 220, e.g., an n-type semiconductor. As further shown in FIG. 2, the semiconductor drift layer 224 can have a different doping concentration than the substrate 220. For example, the semiconductor drift layer 224 can have a lower doping concentration than the substrate 220.

[0047] 2, the exemplary MPS diode 200 includes an anode terminal 226. The anode terminal 226 may be any conductive material (e.g., a front metal) through which current enters the MPS diode 200 or, equivalently, through which electrons exit the MPS diode 200. In some embodiments, the anode terminal 226 may include a metal or combination of metals, such as molybdenum, platinum, chromium, tungsten, nickel, or other similar conductive materials. In some embodiments, the anode terminal 226 may be disposed on a junction barrier element 228 and may provide a conductive path from an external power source to an implantation well 230 of the MPS diode 200.

[0048] As shown in FIG. 2, the anode terminal 226 can provide a metal contact to the top surface 224a of the semiconductor drift layer 224. The portion of the semiconductor drift layer 224 that contacts the anode terminal 226 can form a Schottky diode 234. The Schottky diode 234 can be any semiconductor diode formed by a junction between a semiconductor and a metal. In general, the Schottky diode 234 has a low forward voltage and a very fast switching operation. Thus, the Schottky diode 234 is less likely to overheat at high voltages, can transmit current with greater efficiency, and can operate well at high frequencies.

[0049] 2, the exemplary MPS diode 200 further includes a cathode terminal 222. The cathode terminal 222 may be any conductive material (e.g., a backside metal) through which current exits the MPS diode 200, or equivalently, through which electrons enter the MPS diode 200. In some embodiments, the cathode terminal 222 may include a metal or combination of metals, such as molybdenum, platinum, chromium, tungsten, nickel, or other similar conductive materials. In some embodiments, the cathode terminal 222 may be disposed below the substrate 220, adjacent to the bottom surface 220b of the substrate.

[0050] As further shown in FIG. 2, the MPS diode 200 includes a junction barrier element 228. The junction barrier element 228 may be any portion of the top surface 224a of the semiconductor drift layer 224 that is modified or doped such that a PN junction is formed between the junction barrier element 228 and the semiconductor drift layer 224. In some embodiments, the junction barrier element 228 may include an implantation well 230 (e.g., an electrical contact). The implantation well 230 may include a region of the top surface 224a of the semiconductor drift layer 224 that is doped with a doping agent having an opposite conductivity type to the semiconductor drift layer 224. As shown in FIG. 2, the semiconductor drift layer 224 is an n-type doped semiconductor and the implantation well 230 is a p-type doped semiconductor. In some embodiments, the implantation well 230 may be doped with a higher concentration of doping than the surrounding semiconductor drift layer 224.

[0051] As further shown in FIG. 2, the junction barrier element 228 includes an ohmic contact 232 between the anode terminal 226 and an implantation well 230 of the junction barrier element 228. The ohmic contact 232 may be any electrical contact between a metal and a semiconductor that has low contact resistance and linear current-voltage (IV) behavior. The ohmic contact 232 may be formed by performing an annealing process on the surfaces of the anode terminal 226 and the implantation well 230. The annealing may produce a silicide that forms an alloy between the semiconductor (e.g., implantation well 230) and the metal (e.g., anode terminal 226) at the junction, which may lower the barrier height.

[0052] 3, an exemplary process 300 is provided for forming an ohmic contact (e.g., ohmic contact 114, 232) on a semiconductor component (e.g., semiconductor component 116, MPS diode 200). In block 302, a first metal layer is deposited on a top surface of a semiconductor drift layer (e.g., semiconductor drift layer 224) including an electrical contact (e.g., implantation well 230), the first metal layer exhibiting high reflectivity (e.g., first reflectivity) properties and low absorption to laser light used in a laser annealing process compared to the reflectivity properties of a second metal layer.

[0053] As described herein, the first metal layer includes any conductive material configured to form an ohmic contact with a semiconductor drift layer of an underlying semiconductor component, and is configured to be highly reflective to laser light directed at the first metal layer during a laser annealing process.

[0054] For example, as shown in the embodiments illustrated in Figures 5A-5U and 7A-7R, the first metal layer can include aluminum. In some embodiments, the first metal layer can include an aluminum compound, such as silicon-doped aluminum, aluminum silicide, or other similar compounds. Aluminum is a highly reflective material, especially with respect to laser light, such as ultraviolet (UV) lasers. By reflecting the laser light, the temperature of the first metal layer does not increase substantially as much as a less highly reflective material.

[0055] In some embodiments, the first metal layer may be deposited on the surface of the semiconductor component using physical vapor deposition, chemical vapor deposition, evaporation, sputtering deposition, or another similar process. In some embodiments, the first metal layer may cover the entire surface of the semiconductor component, including electrical contacts, such as implanted wells in the MPS diode, and other portions of exposed silicon, for example, in the semiconductor drift layer. The first metal layer may form ohmic contacts with underlying highly doped electrical contacts through an annealing or heating process. In such a process, a reaction between the first metal layer and the electrical contacts may be induced, for example, the formation of a silicide may be induced through an annealing or heating process.

[0056] If the temperature of the first metal layer increases at other portions of the exposed silicon, such as the semiconductor drift layer, undesirable reactions may occur between the first metal layer and the underlying semiconductor components. Therefore, as described with reference to the embodiments herein, it is desirable to avoid reactions between the first metal layer and other portions of the exposed silicon.

[0057] In block 304, a second metal layer is deposited on portions of the first metal layer, the second metal layer aligned with the electrical contacts, the second metal layer absorbing laser light. The second metal layer is selected in part based on its high absorption characteristics or low reflectivity (e.g., the second reflectivity) when exposed to laser light, particularly laser light commonly used in annealing. The second metal layer that absorbs laser light will experience a more substantial temperature increase compared to a more reflective material such as the first metal layer. Although shown as titanium in the exemplary embodiments of Figures 5A-5U and 7A-7R, the second metal layer can include any material that has a higher absorption rate than the first metal layer that can enable localized heating of the first metal layer in portions that are in direct contact with the second metal layer.

[0058] In some embodiments, the second metal layer may be deposited on a portion of the first metal layer. For example, the second metal layer may be aligned with one or more electrical contacts. The semiconductor component may include an electrical contact, such as an implanted well, configured to receive electrical contact via an ohmic contact. The portion of the second metal layer aligned with the electrical contact underlying the first metal layer may allow an ohmic contact to be formed between the first metal layer and the electrical contact during a laser annealing process.

[0059] In block 306, the first metal layer and the second metal layer are exposed to laser light in a laser annealing process, where the second metal layer is increased in temperature by the laser light, and the increased temperature forms an ohmic contact between the electrical contact and the first metal layer. By positioning a portion of the second metal layer on the first metal layer such that the portion of the second metal layer is aligned with the electrical contact underlying the first metal layer, the second metal layer may allow an ohmic contact to be localized to the electrical contact during the laser annealing process. When a surface of the semiconductor component (including the first metal layer and the portion of the first metal layer covered by the second metal layer) is exposed to laser light during the laser annealing process, the portion of the second metal layer absorbs the laser light and increases in temperature. The increased temperature of the second metal layer also increases the portion of the first metal layer between the second metal layer and the underlying electrical contact, allowing it to react with the underlying electrical contact. Ohmic contacts are formed between the second metal layer, the first metal layer, and the underlying electrical contacts.

[0060] Due to the reflective properties of the first metal layer, the portions of the first metal layer that are not in contact with the second metal layer do not increase in temperature as significantly as the portions of the first metal layer that are in contact with the second metal layer, and therefore the first metal layer does not react with the exposed portions of the underlying semiconductor drift layer, and as a result, ohmic contact is limited to the portions of the first metal layer that are underneath the second metal layer.

[0061] Referring now to FIG. 4, an exemplary process 400 for fabricating a power diode utilizing a field plate edge termination structure according to one or more embodiments of the present disclosure is provided. In block 402, the first metal layer is removed. In some embodiments, ohmic contacts may be formed between portions of the second metal layer, the underlying first metal layer, and the underlying electrical contacts, as described in connection with FIG. 3. The first metal layer may be removed by wet etching, dry etching, or another similar process for removing a metal layer on a semiconductor. In some embodiments, the ohmic contacts may be protected using a masking process. In some embodiments, an etching process may be utilized such that the ohmic contacts remain while other portions of the first metal layer are removed.

[0062] At block 404, a dielectric layer is deposited on the top surface of the semiconductor drift layer and the ohmic contact. The dielectric layer may be any insulating material configured to electrically insulate portions of the semiconductor component. The dielectric layer may be formed on the semiconductor component by thermal oxidation, deposition, or another similar process. In some embodiments, the dielectric layer may include silicon oxide, silicon nitride, or another similar insulator. In some embodiments, the dielectric may be deposited or grown on the entire surface of the semiconductor component.

[0063] In block 406, the dielectric layer immediately above the top surface of the semiconductor drift layer of the semiconductor component is removed, thereby exposing the ohmic contact. In some embodiments, the semiconductor component may include a transmission region where electrical contact is made with the anode terminal and where current transmission may occur. For example, in an MPS diode (e.g., MPS diode 200), the transmission region may include a junction barrier element (e.g., junction barrier element 228) and a contact region between the anode terminal (e.g., anode terminal 226) and the semiconductor drift layer (e.g., semiconductor drift layer 224) that form one or more Schottky diodes (e.g., Schottky diode 234). The deposited or grown dielectric layer may be removed such that the transmission region of the semiconductor component is exposed. In some embodiments, the dielectric layer may be removed by masking and etching or other similar processes.

[0064] At block 408, a front metal is deposited on the ohmic contacts and the dielectric layer. As described in connection with FIG. 2, the front metal (e.g., anode terminal 226) may be any conductive material through which current enters the semiconductor component, or equivalently through which electrons exit the semiconductor component. In some embodiments, the front metal may include a combination of multiple layers of metals, such as molybdenum, platinum, chromium, tungsten, titanium, nickel, etc. In some embodiments, the front metal may be deposited over the surface of the semiconductor component using physical vapor deposition, chemical vapor deposition, evaporation, sputtering deposition, or another similar process. The front metal covers the surface of the transmission region and is in electrical contact with the exposed semiconductor drift layer and the ohmic contact.

[0065] In block 410, the front metal is removed from all areas except the electrical diode area on and immediately surrounding the ohmic contacts. In some embodiments, the front metal remains such that the front metal provides electrical contact to the top surface of the semiconductor component, e.g., the exposed semiconductor drift layer and the ohmic contacts. Additionally, the front metal may overlap a portion of the dielectric layer.

[0066] At block 412, a passivation layer is deposited on the surface and immediately surrounding the front metal. The passivation layer may include any material configured to cover the semiconductor component and protect the semiconductor from corrosion, chemical reactivity, and electrical contact. The passivation layer may be formed by thermal oxidation or other similar processes. In some embodiments, the passivation layer may cover the entire surface of the semiconductor component.

[0067] At block 414, an access channel is etched through the passivation layer to the front metal. The access channel may be etched using a mask and a wet or dry etching process. The access channel may be any path, corridor, wire, or opening that allows access to the conductive front metal from outside the passivation layer.

[0068] 5A-5U, an exemplary process 500 for forming an ohmic contact on an exemplary MPS diode is illustrated. The illustrated exemplary process 500 of FIGS. 5A-5U further includes a process for forming a field plate edge termination structure. In FIG. 5A, one or more heavily doped regions (e.g., implantation wells 530) are formed in a surface of a semiconductor drift layer 524 (e.g., semiconductor drift layer 224) of a semiconductor component 568. As shown in FIG. 5A, the heavily doped regions form the implantation wells 530. As described in connection with FIG. 1, the implantation wells 530 may include a region of the top surface 524a of the semiconductor drift layer 524 that is doped with a p-type doping opposite the n-type doping of the semiconductor drift layer 224. Furthermore, in some embodiments, the implantation wells 530 may be doped at a higher concentration than the surrounding semiconductor drift layer 524. The semiconductor drift layer 524 may be formed by an epitaxial growth process on a substrate 520. Substrate 520 is comprised of an n-type semiconductor, as is semiconductor drift layer 524. In some embodiments, substrate 520 may be more highly doped than semiconductor drift layer 524. In some embodiments, both substrate 520 and semiconductor drift layer 524 may include silicon carbide, which may be particularly beneficial in high power and / or high frequency devices.

[0069] The implanted well 530 can be formed by a process of ion implantation 552, as shown in FIG. 5A. The implanted well 530 is defined by a mask 550 that blocks implantation of ions outside the implanted well 530, and a guard ring that forms the periphery of the semiconductor component 568. The implanted well 530 forms a PN junction diode with the semiconductor drift layer 524. In an MPS diode, the implanted well 530 can relieve some of the stress on the diode under high power. The implanted well 530 can carry some of the current through the diode when the power is high. Without the implanted well 530, a pure Schottky diode would be overstressed and could go into thermal runaway. Thus, the implanted well 530 allows the MPS diode to obtain some of the advantages of both Schottky and PN diodes.

[0070] 5B, the mask 550 is removed from the top surface 524a of the semiconductor drift layer 524.

[0071] 5C, the semiconductor component 568 undergoes an annealing process to activate the dopants in the implanted wells 530 in the semiconductor drift layer 524. The annealing process may include exposing the semiconductor component 568 to high temperatures and allowing the semiconductor component 568 to slowly cool. Such an annealing process may fix the implanted ions into lattice sites of the semiconductor drift layer 524 structure. In some embodiments, damage from ion implantation may be repaired during this process.

[0072] As shown in FIG. 5D, an aluminum layer (e.g., a first metal layer) 554 is deposited on the semiconductor component 568. The aluminum layer 554 may be deposited on the top surface 524a of the semiconductor drift layer 524 by a process such as physical vapor deposition, chemical vapor deposition, evaporation, sputtering deposition, or other similar processes. As described herein, aluminum may be selected as the first metal layer because it reflects laser light. Thus, there is no significant increase in temperature to the aluminum layer 554 when exposed to laser light in the annealing process. Due to the reflectivity of aluminum, the underlying component is protected during the laser annealing process. Additionally, the aluminum may be reacted with the underlying implanted well 530 to create an ohmic contact (e.g., ohmic contact 532 as shown in FIG. 5I).

[0073] 5E, a titanium layer 556 is deposited on the top surface 554a of the aluminum layer 554. The titanium layer 556 may be deposited on the top surface 554a of the aluminum layer 554 by a process such as physical vapor deposition, chemical vapor deposition, evaporation, sputtering deposition, or other similar processes. As described herein, titanium may be selected as the second metal layer based at least in part on titanium's absorption of laser light. Due to titanium's absorption of laser light when exposed to the laser light source, the titanium layer 556 increases in temperature when exposed to the laser light source.

[0074] As shown in Figure 5F, a mask 558 is deposited on an upper surface 556a of titanium layer 556. Mask 558 protects the portions of titanium layer 556 below mask 558 from being removed during an etch or another process utilized to remove titanium layer 556. Mask 558 is aligned with implantation wells 530 below aluminum layer 554, as shown in Figure 5F.

[0075] As shown in FIG. 5G, titanium layer 556 of semiconductor component 568 is removed from the surface of semiconductor component 568 except where titanium layer 556 is protected by mask 558.

[0076] As shown in Figure 5H, mask 558 is removed from semiconductor component 568, leaving only the portions of titanium layer 556 protected by mask 558 on the surface of aluminum layer 554. The remaining portions of titanium layer 556 are aligned with implanted wells 530 implanted in semiconductor drift layer 524 below aluminum layer 554, as shown in Figure 5h.

[0077] As shown in FIG. 5I, a laser 562 directs laser light 564 across a surface of a semiconductor component 568 in a laser annealing process. The laser annealing process can be utilized to heat portions of the semiconductor component 568 configured to absorb the laser light 564 (e.g., portions of the titanium layer 556). By generating laser light 564 having a wavelength that is absorbed by the titanium layer 556 but reflected by the aluminum layer 554, a temperature increase occurs in the remaining portions of the titanium layer 556 and portions of the underlying aluminum layer 554 that are in contact with the titanium layer 556. However, portions of the aluminum layer 554 that are not in contact with the titanium layer 556 reflect the laser light 564 and do not experience a substantial temperature increase. In some embodiments, a laser 562 emitting ultraviolet (UV) laser light 564 is utilized to perform the laser annealing process. In such embodiments, the wavelength of the UV laser light 564 may be between 290 nanometers and 370 nanometers. Preferably, it is between 300 nanometers and 360 nanometers, and more preferably between 310 nanometers and 350 nanometers. In some embodiments, the titanium layer 556 may become increasingly reflective of the laser light 564 as the wavelength moves beyond 370 nanometers. The increase in reflectivity may mean that less laser light 564 is absorbed by the titanium layer 556, and the titanium layer 564 does not reach a sufficient temperature to facilitate the formation of the ohmic contact 532.

[0078] The increase in temperature of the titanium layer 556 and portions of the underlying aluminum layer 554 allows a reaction to occur between the titanium layer 556, the aluminum layer 554, and the implantation well 530. This reaction forms an ohmic contact 532 between the titanium of the titanium layer 556, the aluminum of the aluminum layer 554, and the implantation well 530 in the semiconductor drift layer 524. Such a titanium / aluminum ohmic contact is one of the best known ohmic contacts for p-type or n-type implantation regions. Because the increase in temperature is localized based on the location of the portions of the titanium layer 556, the portions of the aluminum layer 554 that do not experience a substantial increase in temperature do not react with the underlying semiconductor.

[0079] As shown in FIG. 5J, the aluminum layer 554 is removed from the surface of the semiconductor component 568, leaving the ohmic contact 532 formed by the titanium layer 556 and the underlying aluminum layer 554 intact over the implantation well 530.

[0080] As shown in FIG. 5K, a dielectric layer 566 is formed on the top surface 524a of the semiconductor drift layer 524, including the ohmic contact 532, by thermal oxidation, deposition, or other similar process.

[0081] As shown in Figure 5L, a mask 558 is placed over the dielectric layer 566 such that the portion of the dielectric layer 566 directly above the semiconductor component 568, including the ohmic contact 532, is exposed. As shown in Figure 5L, the mask 558 is aligned with the p-type doped guard ring and shows the peripheral extent of the semiconductor component 568.

[0082] As shown in Figure 5M, the dielectric layer 566 is removed directly above the semiconductor component 568 including the ohmic contact 532. As shown in Figure 5M, the dielectric layer 566 remains over the outer semiconductor portion of the semiconductor component 568, as indicated by the p-type doped guard ring. At least a portion of the dielectric layer 566 overlaps the guard ring at the outer extent of the semiconductor component 568. The dielectric layer 566 at the edge of the semiconductor component 568 at least partially forms a field plate edge termination structure with the front metal 526, as shown in Figure 5O.

[0083] Mask 558 is removed from the surface of dielectric layer 566, as shown in FIG. 5N.

[0084] As shown in FIG. 5O, a front metal 526 (e.g., anode terminal 226) is deposited on a surface of the semiconductor component 568. As described in connection with FIG. 2, the front metal 526 may be any conductive material through which current enters the semiconductor component 568 or, equivalently, through which electrons exit the semiconductor component 568. In some embodiments, the front metal 526 may include a metal or combination of metals, such as molybdenum, platinum, chromium, tungsten, nickel, or other similar conductive materials. As shown in FIG. 5O, the front metal 526 is disposed on an ohmic contact 532 and provides a conductive path from an external power source to the implantation well 530 of the semiconductor component 568. The front metal 526 further creates a Schottky junction 570 between the front metal 526 and the semiconductor drift layer 524.

[0085] As shown in Figure 5P, a mask 560 is deposited on the surface of the front metal 526. The mask 560 defines the outer dimensions of the front metal relative to the semiconductor components 568. As shown in Figure 5P, the mask 560 overlies at least a portion of the dielectric layer 566 below the front metal 526.

[0086] As shown in FIG. 5Q, the portions of the front metal 526 that are not protected by the mask 560 are removed from the surface of the dielectric layer 566. As further shown in FIG. 5Q, the mask 560 is removed from the surface of the front metal 526. As shown, the front metal 526 at least partially overlaps the dielectric layer 566. The front metal 526 forms a field plate edge termination structure with the dielectric layer 566 that defines the periphery of the semiconductor component 568. In some embodiments, the field plate edge termination structure can create high resistance regions and reduce electric field concentration near the edges of the semiconductor component 568. Reducing the electric field concentration near the edges of the semiconductor component 568 can reduce stress on portions of the semiconductor component 568.

[0087] As shown in FIG. 5R, a passivation layer 576 is deposited over the surface of the semiconductor component 568, including the front metal 526 and portions of the exposed dielectric layer 566.

[0088] 4, the passivation layer 576 may include any material configured to coat the semiconductor components 568 to protect them from corrosion, chemical reactivity, and electrical contact. The passivation layer 576 may be formed by thermal oxidation or another similar process.

[0089] 5S, a mask 578 is placed on the surface of the passivation layer 576. The mask 578 is aligned with the surface of the front metal 526 to define a path through the passivation layer 576 to the surface of the front metal 526.

[0090] 5T, an access channel 572 is etched through the passivation layer 576 to the front metal 526. The access channel 572 provides an opening through the passivation layer 576 allowing access to the conductive front metal 526 from outside the passivation layer 576.

[0091] As shown in Figure 5U, the mask 578 is removed from the surface of the passivation layer 576. As further shown in Figure 5U, a rear ohmic contact 574 is formed on the bottom surface of the substrate 520. In addition, rear metal 522 (e.g., cathode termination 222) is disposed on the surface of the rear ohmic contact 574.

[0092] The resulting semiconductor component 568 is an MPS diode with field plate edge termination, as shown in FIG. 5U.

[0093] 6, an exemplary process 600 for fabricating a power diode without a field plate edge termination structure is provided in accordance with one or more embodiments of the present disclosure. In block 602, the first metal layer is removed. As described in connection with block 402 of FIG. 4, ohmic contacts may be formed between portions of the second metal layer and the underlying first metal layer and an underlying electrical contact. The first metal layer may be removed by wet etching, dry etching, or another similar process for removing a metal layer on a semiconductor.

[0094] At block 604, a front metal is deposited on the ohmic contacts. As described in connection with FIG. 2, the front metal (e.g., anode terminal 226) may be any conductive material through which current enters the semiconductor component or equivalently through which electrons exit the semiconductor component. In some embodiments, the front metal may include a combination of metals in multiple layers, such as molybdenum, platinum, chromium, tungsten, nickel, titanium, etc. As further shown in process 600, the front metal is deposited on the entire surface of the semiconductor. The front metal may be deposited using physical vapor deposition, chemical vapor deposition, evaporation, sputtering deposition, or another similar process. The front metal covers the surface of the transmission region and forms electrical contact with the exposed semiconductor drift layer and ohmic contacts, as well as other semiconductor regions outside the semiconductor component.

[0095] At block 606, the front metal is removed from all areas except the semiconductor component areas on and immediately surrounding the ohmic contacts. In some embodiments, the front metal remains such that the front metal provides electrical contact to the top surfaces of the semiconductor components, e.g., the exposed semiconductor drift layer and the ohmic contacts. However, the front metal is removed beyond the extent of the semiconductor components.

[0096] At block 608, a passivation layer is deposited on and around the front metal. The passivation layer may include any material configured to cover the semiconductor component and protect the semiconductor from corrosion, chemical reactivity, and electrical contact. The passivation layer may be formed by thermal oxidation or other similar processes. In some embodiments, the passivation layer may cover the entire surface of the semiconductor component.

[0097] At block 610, an access channel is etched through the passivation layer to the front metal. The access channel may be etched using a mask and a wet or dry etching process. The access channel may be any path, corridor, wire, or opening that allows access to the conductive front metal from outside the passivation layer.

[0098] 7A-7R, an exemplary process 700 for forming an ohmic contact on an exemplary MPS diode is illustrated. The illustrated exemplary process 700 of FIGS. 7A-7R illustrates a process for creating an MPS diode without forming a field plate edge termination structure. In FIG. 7A, one or more heavily doped regions (e.g., implantation well 730) are formed in a surface of a semiconductor drift layer 724 (e.g., semiconductor drift layer 224, 524) of a semiconductor component 768. As shown in FIG. 7A, the heavily doped regions form the implantation well 730. As described in connection with FIG. 1, the implantation well 730 may include a region of the top surface 724a of the semiconductor drift layer 724 that is doped with a p-type doping opposite the n-type doping of the semiconductor drift layer 724. Furthermore, in some embodiments, the implantation well 730 may be doped at a higher concentration than the surrounding semiconductor drift layer 724. The semiconductor drift layer 724 may be formed by an epitaxial growth process on a substrate 720. Substrate 720 is comprised of an n-type semiconductor, as is semiconductor drift layer 724. In some embodiments, substrate 720 may be more highly doped than semiconductor drift layer 724. In some embodiments, both substrate 720 and semiconductor drift layer 724 may include silicon carbide, which may be particularly beneficial in high power and / or high frequency devices.

[0099] The implanted well 730 can be formed by a process of ion implantation 752, as shown in FIG. 7A. The implanted well 730 is defined by a mask 750 that blocks implantation of ions outside the implanted well 730, and a guard ring that forms the periphery of the semiconductor component 768. The implanted well 730 forms a PN junction diode with the semiconductor drift layer 724. In an MPS diode, the implanted well 730 can relieve some of the stress on the diode under high power. The implanted well 730 can carry some of the current through the diode when the power is high. Without the implanted well 730, a pure Schottky diode would be overstressed and could go into thermal runaway. Thus, the implanted well 730 allows the MPS diode to obtain some of the advantages of both Schottky and PN diodes.

[0100] 7B, the mask 750 is removed from the top surface 724a of the semiconductor drift layer 724.

[0101] 7C, the semiconductor component 768 undergoes an annealing process to fix the implanted well 730 in the semiconductor drift layer 724. The annealing process may include exposing the semiconductor component 768 to a high temperature and allowing the semiconductor component 768 to slowly cool. Such an annealing process may fix the implanted ions within the structure of the semiconductor drift layer 724.

[0102] As shown in FIG. 7D, an aluminum layer (e.g., a first metal layer) 754 is deposited on the semiconductor component 768. The aluminum layer 754 may be deposited on the top surface 724a of the semiconductor drift layer 724 by a process such as physical vapor deposition, chemical vapor deposition, evaporation, sputtering deposition, or other similar processes. As described herein, aluminum may be selected as the first metal layer because it reflects laser light. Thus, there is no significant increase in temperature to the aluminum layer 754 when exposed to laser light in the annealing process. Due to the reflectivity of aluminum, the underlying component is protected during the laser annealing process. Additionally, the aluminum may be reacted with the underlying implanted well 730 to create an ohmic contact (e.g., ohmic contact 732 as shown in FIG. 7I).

[0103] As shown in FIG. 7E, a titanium layer 756 is deposited on the top surface 754a of the aluminum layer 754. The titanium layer 756 may be deposited on the top surface 754a of the aluminum layer 754 by a process such as physical vapor deposition, chemical vapor deposition, evaporation, sputtering deposition, or other similar processes. As described herein, titanium may be selected as the second metal layer based at least in part on titanium's absorption of laser light. Due to titanium's absorption of laser light when exposed to the laser light source, the titanium layer 756 increases in temperature when exposed to the laser light source.

[0104] As shown in Figure 7F, a mask 758 is deposited on an upper surface 756a of titanium layer 756. Mask 758 protects the portions of titanium layer 756 below mask 758 from being removed during an etch or another process utilized to remove titanium layer 756. Mask 758 is aligned with implantation wells 730 below aluminum layer 754, as shown in Figure 7F.

[0105] As shown in FIG. 7G, titanium layer 756 of semiconductor component 768 is removed from the surface of semiconductor component 768 except where titanium layer 756 is protected by mask 758.

[0106] As shown in Figure 7H, mask 758 is removed from semiconductor component 768, leaving only the portions of titanium layer 756 protected by mask 758 on the surface of aluminum layer 754. The remaining portions of titanium layer 756 are aligned with implanted wells 730 implanted in semiconductor drift layer 724 below aluminum layer 754, as shown in Figure 7H.

[0107] As shown in Figure 7I, a laser 762 directs laser light 764 across a surface of a semiconductor component 768 in a laser annealing process. The laser annealing process can be used to heat the portions of the semiconductor component 768 that are configured to absorb the laser light 764 (e.g., portions of the titanium layer 756). By generating laser light 764 having a wavelength that is absorbed by the titanium layer 756 but reflected by the aluminum layer 754, a temperature increase occurs in the remainder of the titanium layer 756 and in the portions of the underlying aluminum layer 754 that are in contact with the titanium layer 756. However, the portions of the aluminum layer 754 that are not in contact with the titanium layer 756 reflect the laser light 764 and do not experience a substantial increase in temperature.

[0108] The increase in temperature of the underlying portions of titanium layer 756 and aluminum layer 754 allows a reaction to occur between titanium layer 756, aluminum layer 754, and implantation well 730. This reaction forms an ohmic contact 732 between the titanium of titanium layer 756, the aluminum of aluminum layer 754, and implantation well 730 in semiconductor drift layer 724. Such a titanium / aluminum ohmic contact is one of the best known ohmic contacts for p-type or n-type implantation regions. Because the increase in temperature is localized based on the location of the portion of titanium layer 756, the portion of aluminum layer 754 that does not experience a substantial increase in temperature does not react with the underlying semiconductor.

[0109] As shown in FIG. 7J, the aluminum layer 754 is removed from the surface of the semiconductor component 768, leaving the ohmic contact 732 formed by the titanium layer 756 and the underlying aluminum layer 754 intact over the implantation well 730.

[0110] As shown in FIG. 7K, a front metal 726 (e.g., anode terminal 226) is deposited on a surface of the semiconductor component 768. As described in connection with FIG. 2, the front metal 726 may be any conductive material through which current enters the semiconductor component 568 or, equivalently, through which electrons exit the semiconductor component 768. In some embodiments, the front metal 726 may include a metal or combination of metals, such as molybdenum, platinum, chromium, tungsten, nickel, or other similar conductive materials. As shown in FIG. 7K, the front metal 726 is disposed on an ohmic contact 732 and provides a conductive path from an external power source to the implantation well 730 of the semiconductor component 768. The front metal 726 further forms a Schottky diode 770 between the front metal 726 and the semiconductor drift layer 724.

[0111] As shown in Figure 7L, a mask 760 is deposited on the surface of the front metal 726. The mask 760 defines the outer dimensions of the front metal relative to the semiconductor components 768. As shown in Figure 7L, the mask 760 overlaps at least a portion of a guard ring that establishes a perimeter of the semiconductor components 768 below the front metal 726.

[0112] As shown in Figure 7M, the portions of the front metal 726 that are not protected by the mask 760 are removed from the surface of the semiconductor component 768. As further shown in Figure 7M, the front metal 726 at least partially overlaps a guard ring that defines the periphery of the semiconductor component 768. The front metal 726 provides a contact for a Schottky diode 770 between the front metal 726 and the exposed portion of the semiconductor drift layer 724. The front metal 726 also provides an electrical connection to a PN junction diode between the implantation well 730 and the semiconductor drift layer 724.

[0113] The mask 760 is removed from the surface of the front metal 726, as shown in FIG. 7N.

[0114] As shown in Figure 7O, a passivation layer 776 is deposited over the surface of the semiconductor component 768, including the exposed portions of the front metal 726 and the semiconductor drift layer 724, as well as any other exposed surfaces. As described in connection with Figure 4, the passivation layer 776 may include any material configured to coat the semiconductor component 768 to protect it from corrosion, chemical reactivity, and electrical contact. The passivation layer 776 may be formed by thermal oxidation or another similar process.

[0115] 7P, a mask 778 is placed on the surface of the passivation layer 776. The mask 778 is aligned with the surface of the front metal 726 so as to define a path through the passivation layer 776 to the surface of the front metal 726.

[0116] 7Q, an access channel 772 is etched through the passivation layer 776 to the front metal 726. The access channel 772 provides an opening through the passivation layer 776 allowing access to the conductive front metal 726 from outside the passivation layer 776.

[0117] As shown in Figure 7R, the mask 778 is removed from the surface of the passivation layer 776. As further shown in Figure 7R, a rear ohmic contact 774 is formed on the bottom surface of the substrate 720. In addition, rear metal 722 (e.g., cathode termination 222) is disposed on the surface of the rear ohmic contact 774.

[0118] The resulting semiconductor component 768 is an MPS diode without a field plate edge termination, as shown in FIG. 7R.

[0119] Although this detailed description has described several embodiments of the present invention, the appended claims cover other embodiments of the present invention that differ from the described embodiments, according to various modifications and improvements. For example, those skilled in the art will recognize that such principles may be applied to any semiconductor device that benefits from precise placement of ohmic contacts, such as any semiconductor device that utilizes a merged PN Schottky diode or other PN diode that utilizes ohmic contacts.

[0120] Within the appended claims, no claim is intended to be construed under 35 U.S.C. 112, paragraph 6, unless the specific terms "means for" or "step for" are used in a given claim.

[0121] Use of broader terms such as "comprises," "includes," and "having" should be understood to provide support for narrower terms such as "consisting of," "consisting essentially of," and "comprised substantially of." Use of terms such as "optionally," "may," "might," "possibly," and the like with respect to any element of an embodiment means that the element is not required, or that the element is alternatively required, with both alternatives being within the scope of the embodiment(s). Also, references to examples are provided merely for illustrative purposes and are not intended to be exclusive.

Claims

1. 1. A method for forming an ohmic contact on a semiconductor component, comprising: depositing a first metal layer on a top surface of the semiconductor drift layer including the electrical contacts, the first metal layer reflecting laser light; depositing a second metal layer over portions of the first metal layer, the second metal layer aligned with the electrical contacts, the second metal layer absorbing the laser light; exposing the first metal layer and the second metal layer to the laser light in a laser annealing process, wherein the second metal layer is substantially elevated in temperature by the laser light; Including, The method of claim 1, wherein the increase in temperature forms the ohmic contact between the electrical contact and the first metal layer.

2. The method of claim 1 , wherein the semiconductor component is a merged PN Schottky diode.

3. The method of claim 2 , wherein the electrical contact is an implanted well in the top surface of the semiconductor drift layer.

4. The method of claim 3 , wherein said portion of said second metal layer is disposed on an upper surface of said first metal layer directly opposite said implantation well.

5. The method of claim 4 , wherein a first reflectance of the first metal layer is greater than a second reflectance of the second metal layer.

6. The method of claim 4 , wherein the implantation well comprises a p-type semiconductor and the semiconductor drift layer comprises an n-type semiconductor.

7. The method of claim 4 , wherein the ohmic contact forms electrical contact with the implantation well.

8. removing the second metal layer; The method of claim 1 further comprising depositing a front metal over the ohmic contact.

9. The method of claim 8 , wherein the front metal is an anode of the semiconductor component.

10. 9. The method of claim 8, further comprising removing the front metal from all areas except for semiconductor component areas on and immediately surrounding the ohmic contacts.

11. depositing a passivation layer over and around the front metal; The method of claim 10 further comprising: etching an access channel through the passivation layer to the front metal.

12. depositing a dielectric layer over the top surface of the semiconductor drift layer and the ohmic contact; removing the dielectric layer immediately above the top surface of the semiconductor drift layer of the semiconductor component such that the ohmic contact is exposed; The method of claim 8 further comprising depositing a front metal over the ohmic contact and the dielectric layer.

13. The method of claim 12 further comprising removing the front metal from all areas except for semiconductor component areas over and immediately surrounding the ohmic contacts.

14. depositing a passivation layer on and immediately surrounding the surface of the front metal; The method of claim 13 further comprising: etching an access channel through the passivation layer to the front metal.

15. forming a rear ohmic contact on the surface opposite the passivation layer; The method of claim 14 , wherein a backside metal is in electrical contact with the backside ohmic contact.

16. The method of claim 15 , wherein the rear ohmic contact is a cathode of the semiconductor component.

17. The method of claim 1 , wherein the semiconductor drift layer is formed by a process of epitaxial growth on a semiconductor substrate.

18. The method of claim 17 , wherein both the semiconductor substrate and the semiconductor drift layer comprise silicon carbide.

19. The method of claim 1 , wherein the first metal layer comprises aluminum.

20. The method of claim 1 , wherein the second metal layer comprises titanium.

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